1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright (c) 2016 - 2018 Cavium Inc. 3 * All rights reserved. 4 * www.cavium.com 5 */ 6 7 /**************************************************************************** 8 * 9 * Name: mcp_public.h 10 * 11 * Description: MCP public data 12 * 13 * Created: 13/01/2013 yanivr 14 * 15 ****************************************************************************/ 16 17 #ifndef MCP_PUBLIC_H 18 #define MCP_PUBLIC_H 19 20 #define VF_MAX_STATIC 192 /* In case of AH */ 21 #define VF_BITMAP_SIZE_IN_DWORDS (VF_MAX_STATIC / 32) 22 #define VF_BITMAP_SIZE_IN_BYTES (VF_BITMAP_SIZE_IN_DWORDS * sizeof(u32)) 23 24 /* Extended array size to support for 240 VFs 8 dwords */ 25 #define EXT_VF_MAX_STATIC 240 26 #define EXT_VF_BITMAP_SIZE_IN_DWORDS (((EXT_VF_MAX_STATIC - 1) / 32) + 1) 27 #define EXT_VF_BITMAP_SIZE_IN_BYTES (EXT_VF_BITMAP_SIZE_IN_DWORDS * \ 28 sizeof(u32)) 29 #define ADDED_VF_BITMAP_SIZE 2 30 31 #define MCP_GLOB_PATH_MAX 2 32 #define MCP_PORT_MAX 2 /* Global */ 33 #define MCP_GLOB_PORT_MAX 4 /* Global */ 34 #define MCP_GLOB_FUNC_MAX 16 /* Global */ 35 36 typedef u32 offsize_t; /* In DWORDS !!! */ 37 /* Offset from the beginning of the MCP scratchpad */ 38 #define OFFSIZE_OFFSET_OFFSET 0 39 #define OFFSIZE_OFFSET_MASK 0x0000ffff 40 /* Size of specific element (not the whole array if any) */ 41 #define OFFSIZE_SIZE_OFFSET 16 42 #define OFFSIZE_SIZE_MASK 0xffff0000 43 44 /* SECTION_OFFSET is calculating the offset in bytes out of offsize */ 45 #define SECTION_OFFSET(_offsize) \ 46 ((((_offsize & OFFSIZE_OFFSET_MASK) >> OFFSIZE_OFFSET_OFFSET) << 2)) 47 48 /* SECTION_SIZE is calculating the size in bytes out of offsize */ 49 #define SECTION_SIZE(_offsize) \ 50 (((_offsize & OFFSIZE_SIZE_MASK) >> OFFSIZE_SIZE_OFFSET) << 2) 51 52 /* SECTION_ADDR returns the GRC addr of a section, given offsize and index 53 * within section 54 */ 55 #define SECTION_ADDR(_offsize, idx) \ 56 (MCP_REG_SCRATCH + \ 57 SECTION_OFFSET(_offsize) + (SECTION_SIZE(_offsize) * idx)) 58 59 /* SECTION_OFFSIZE_ADDR returns the GRC addr to the offsize address. Use 60 * offsetof, since the OFFSETUP collide with the firmware definition 61 */ 62 #define SECTION_OFFSIZE_ADDR(_pub_base, _section) \ 63 (_pub_base + offsetof(struct mcp_public_data, sections[_section])) 64 /* PHY configuration */ 65 struct eth_phy_cfg { 66 /* 0 = autoneg, 1000/10000/20000/25000/40000/50000/100000 */ 67 u32 speed; 68 #define RTE_ETH_SPEED_AUTONEG 0 69 #define RTE_ETH_SPEED_SMARTLINQ 0x8 /* deprecated - use link_modes field instead */ 70 71 u32 pause; /* bitmask */ 72 #define ETH_PAUSE_NONE 0x0 73 #define ETH_PAUSE_AUTONEG 0x1 74 #define ETH_PAUSE_RX 0x2 75 #define ETH_PAUSE_TX 0x4 76 77 u32 adv_speed; /* Default should be the speed_cap_mask */ 78 u32 loopback_mode; 79 #define ETH_LOOPBACK_NONE (0) 80 /* Serdes loopback. In AH, it refers to Near End */ 81 #define ETH_LOOPBACK_INT_PHY (1) 82 #define ETH_LOOPBACK_EXT_PHY (2) /* External PHY Loopback */ 83 /* External Loopback (Require loopback plug) */ 84 #define ETH_LOOPBACK_EXT (3) 85 #define ETH_LOOPBACK_MAC (4) /* MAC Loopback - not supported */ 86 #define ETH_LOOPBACK_CNIG_AH_ONLY_0123 (5) /* Port to itself */ 87 #define ETH_LOOPBACK_CNIG_AH_ONLY_2301 (6) /* Port to Port */ 88 #define ETH_LOOPBACK_PCS_AH_ONLY (7) /* PCS loopback (TX to RX) */ 89 /* Loop RX packet from PCS to TX */ 90 #define ETH_LOOPBACK_REVERSE_MAC_AH_ONLY (8) 91 /* Remote Serdes Loopback (RX to TX) */ 92 #define ETH_LOOPBACK_INT_PHY_FEA_AH_ONLY (9) 93 94 u32 eee_cfg; 95 /* EEE is enabled (configuration). Refer to eee_status->active for negotiated 96 * status 97 */ 98 #define EEE_CFG_EEE_ENABLED (1 << 0) 99 #define EEE_CFG_TX_LPI (1 << 1) 100 #define EEE_CFG_ADV_SPEED_1G (1 << 2) 101 #define EEE_CFG_ADV_SPEED_10G (1 << 3) 102 #define EEE_TX_TIMER_USEC_MASK (0xfffffff0) 103 #define EEE_TX_TIMER_USEC_OFFSET 4 104 #define EEE_TX_TIMER_USEC_BALANCED_TIME (0xa00) 105 #define EEE_TX_TIMER_USEC_AGGRESSIVE_TIME (0x100) 106 #define EEE_TX_TIMER_USEC_LATENCY_TIME (0x6000) 107 108 u32 link_modes; /* Additional link modes */ 109 #define LINK_MODE_SMARTLINQ_ENABLE 0x1 /* XXX Deprecate */ 110 }; 111 112 struct port_mf_cfg { 113 u32 dynamic_cfg; /* device control channel */ 114 #define PORT_MF_CFG_OV_TAG_MASK 0x0000ffff 115 #define PORT_MF_CFG_OV_TAG_OFFSET 0 116 #define PORT_MF_CFG_OV_TAG_DEFAULT PORT_MF_CFG_OV_TAG_MASK 117 118 u32 reserved[1]; 119 }; 120 121 /* DO NOT add new fields in the middle 122 * MUST be synced with struct pmm_stats_map 123 */ 124 struct eth_stats { 125 u64 r64; /* 0x00 (Offset 0x00 ) RX 64-byte frame counter*/ 126 u64 r127; /* 0x01 (Offset 0x08 ) RX 65 to 127 byte frame counter*/ 127 u64 r255; /* 0x02 (Offset 0x10 ) RX 128 to 255 byte frame counter*/ 128 u64 r511; /* 0x03 (Offset 0x18 ) RX 256 to 511 byte frame counter*/ 129 u64 r1023; /* 0x04 (Offset 0x20 ) RX 512 to 1023 byte frame counter*/ 130 /* 0x05 (Offset 0x28 ) RX 1024 to 1518 byte frame counter */ 131 u64 r1518; 132 union { 133 struct { /* bb */ 134 /* 0x06 (Offset 0x30 ) RX 1519 to 1522 byte VLAN-tagged frame counter */ 135 u64 r1522; 136 /* 0x07 (Offset 0x38 ) RX 1519 to 2047 byte frame counter*/ 137 u64 r2047; 138 /* 0x08 (Offset 0x40 ) RX 2048 to 4095 byte frame counter*/ 139 u64 r4095; 140 /* 0x09 (Offset 0x48 ) RX 4096 to 9216 byte frame counter*/ 141 u64 r9216; 142 /* 0x0A (Offset 0x50 ) RX 9217 to 16383 byte frame counter */ 143 u64 r16383; 144 } bb0; 145 struct { /* ah */ 146 u64 unused1; 147 /* 0x07 (Offset 0x38 ) RX 1519 to max byte frame counter*/ 148 u64 r1519_to_max; 149 u64 unused2; 150 u64 unused3; 151 u64 unused4; 152 } ah0; 153 } u0; 154 u64 rfcs; /* 0x0F (Offset 0x58 ) RX FCS error frame counter*/ 155 u64 rxcf; /* 0x10 (Offset 0x60 ) RX control frame counter*/ 156 u64 rxpf; /* 0x11 (Offset 0x68 ) RX pause frame counter*/ 157 u64 rxpp; /* 0x12 (Offset 0x70 ) RX PFC frame counter*/ 158 u64 raln; /* 0x16 (Offset 0x78 ) RX alignment error counter*/ 159 u64 rfcr; /* 0x19 (Offset 0x80 ) RX false carrier counter */ 160 u64 rovr; /* 0x1A (Offset 0x88 ) RX oversized frame counter*/ 161 u64 rjbr; /* 0x1B (Offset 0x90 ) RX jabber frame counter */ 162 u64 rund; /* 0x34 (Offset 0x98 ) RX undersized frame counter */ 163 u64 rfrg; /* 0x35 (Offset 0xa0 ) RX fragment counter */ 164 u64 t64; /* 0x40 (Offset 0xa8 ) TX 64-byte frame counter */ 165 u64 t127; /* 0x41 (Offset 0xb0 ) TX 65 to 127 byte frame counter */ 166 u64 t255; /* 0x42 (Offset 0xb8 ) TX 128 to 255 byte frame counter*/ 167 u64 t511; /* 0x43 (Offset 0xc0 ) TX 256 to 511 byte frame counter*/ 168 u64 t1023; /* 0x44 (Offset 0xc8 ) TX 512 to 1023 byte frame counter*/ 169 /* 0x45 (Offset 0xd0 ) TX 1024 to 1518 byte frame counter */ 170 u64 t1518; 171 union { 172 struct { /* bb */ 173 /* 0x47 (Offset 0xd8 ) TX 1519 to 2047 byte frame counter */ 174 u64 t2047; 175 /* 0x48 (Offset 0xe0 ) TX 2048 to 4095 byte frame counter */ 176 u64 t4095; 177 /* 0x49 (Offset 0xe8 ) TX 4096 to 9216 byte frame counter */ 178 u64 t9216; 179 /* 0x4A (Offset 0xf0 ) TX 9217 to 16383 byte frame counter */ 180 u64 t16383; 181 } bb1; 182 struct { /* ah */ 183 /* 0x47 (Offset 0xd8 ) TX 1519 to max byte frame counter */ 184 u64 t1519_to_max; 185 u64 unused6; 186 u64 unused7; 187 u64 unused8; 188 } ah1; 189 } u1; 190 u64 txpf; /* 0x50 (Offset 0xf8 ) TX pause frame counter */ 191 u64 txpp; /* 0x51 (Offset 0x100) TX PFC frame counter */ 192 /* 0x6C (Offset 0x108) Transmit Logical Type LLFC message counter */ 193 union { 194 struct { /* bb */ 195 /* 0x6C (Offset 0x108) Transmit Logical Type LLFC message counter */ 196 u64 tlpiec; 197 /* 0x6E (Offset 0x110) Transmit Total Collision Counter */ 198 u64 tncl; 199 } bb2; 200 struct { /* ah */ 201 u64 unused9; 202 u64 unused10; 203 } ah2; 204 } u2; 205 u64 rbyte; /* 0x3d (Offset 0x118) RX byte counter */ 206 u64 rxuca; /* 0x0c (Offset 0x120) RX UC frame counter */ 207 u64 rxmca; /* 0x0d (Offset 0x128) RX MC frame counter */ 208 u64 rxbca; /* 0x0e (Offset 0x130) RX BC frame counter */ 209 /* 0x22 (Offset 0x138) RX good frame (good CRC, not oversized, no ERROR) */ 210 u64 rxpok; 211 u64 tbyte; /* 0x6f (Offset 0x140) TX byte counter */ 212 u64 txuca; /* 0x4d (Offset 0x148) TX UC frame counter */ 213 u64 txmca; /* 0x4e (Offset 0x150) TX MC frame counter */ 214 u64 txbca; /* 0x4f (Offset 0x158) TX BC frame counter */ 215 u64 txcf; /* 0x54 (Offset 0x160) TX control frame counter */ 216 /* HSI - Cannot add more stats to this struct. If needed, then need to open new 217 * struct 218 */ 219 220 }; 221 222 struct brb_stats { 223 u64 brb_truncate[8]; 224 u64 brb_discard[8]; 225 }; 226 227 struct port_stats { 228 struct brb_stats brb; 229 struct eth_stats eth; 230 }; 231 232 /*----+------------------------------------------------------------------------ 233 * C | Number and | Ports in| Ports in|2 PHY-s |# of ports|# of engines 234 * h | rate of | team #1 | team #2 |are used|per path | (paths) 235 * i | physical | | | | | enabled 236 * p | ports | | | | | 237 *====+============+=========+=========+========+==========+=================== 238 * BB | 1x100G | This is special mode, where there are actually 2 HW func 239 * BB | 2x10/20Gbps| 0,1 | NA | No | 1 | 1 240 * BB | 2x40 Gbps | 0,1 | NA | Yes | 1 | 1 241 * BB | 2x50Gbps | 0,1 | NA | No | 1 | 1 242 * BB | 4x10Gbps | 0,2 | 1,3 | No | 1/2 | 1,2 (2 is optional) 243 * BB | 4x10Gbps | 0,1 | 2,3 | No | 1/2 | 1,2 (2 is optional) 244 * BB | 4x10Gbps | 0,3 | 1,2 | No | 1/2 | 1,2 (2 is optional) 245 * BB | 4x10Gbps | 0,1,2,3 | NA | No | 1 | 1 246 * AH | 2x10/20Gbps| 0,1 | NA | NA | 1 | NA 247 * AH | 4x10Gbps | 0,1 | 2,3 | NA | 2 | NA 248 * AH | 4x10Gbps | 0,2 | 1,3 | NA | 2 | NA 249 * AH | 4x10Gbps | 0,3 | 1,2 | NA | 2 | NA 250 * AH | 4x10Gbps | 0,1,2,3 | NA | NA | 1 | NA 251 *====+============+=========+=========+========+==========+=================== 252 */ 253 254 #define CMT_TEAM0 0 255 #define CMT_TEAM1 1 256 #define CMT_TEAM_MAX 2 257 258 struct couple_mode_teaming { 259 u8 port_cmt[MCP_GLOB_PORT_MAX]; 260 #define PORT_CMT_IN_TEAM (1 << 0) 261 262 #define PORT_CMT_PORT_ROLE (1 << 1) 263 #define PORT_CMT_PORT_INACTIVE (0 << 1) 264 #define PORT_CMT_PORT_ACTIVE (1 << 1) 265 266 #define PORT_CMT_TEAM_MASK (1 << 2) 267 #define PORT_CMT_TEAM0 (0 << 2) 268 #define PORT_CMT_TEAM1 (1 << 2) 269 }; 270 271 /************************************** 272 * LLDP and DCBX HSI structures 273 **************************************/ 274 #define LLDP_CHASSIS_ID_STAT_LEN 4 275 #define LLDP_PORT_ID_STAT_LEN 4 276 #define DCBX_MAX_APP_PROTOCOL 32 277 #define MAX_SYSTEM_LLDP_TLV_DATA 32 /* In dwords. 128 in bytes*/ 278 #define MAX_TLV_BUFFER 128 /* In dwords. 512 in bytes*/ 279 typedef enum _lldp_agent_e { 280 LLDP_NEAREST_BRIDGE = 0, 281 LLDP_NEAREST_NON_TPMR_BRIDGE, 282 LLDP_NEAREST_CUSTOMER_BRIDGE, 283 LLDP_MAX_LLDP_AGENTS 284 } lldp_agent_e; 285 286 struct lldp_config_params_s { 287 u32 config; 288 #define LLDP_CONFIG_TX_INTERVAL_MASK 0x000000ff 289 #define LLDP_CONFIG_TX_INTERVAL_OFFSET 0 290 #define LLDP_CONFIG_HOLD_MASK 0x00000f00 291 #define LLDP_CONFIG_HOLD_OFFSET 8 292 #define LLDP_CONFIG_MAX_CREDIT_MASK 0x0000f000 293 #define LLDP_CONFIG_MAX_CREDIT_OFFSET 12 294 #define LLDP_CONFIG_ENABLE_RX_MASK 0x40000000 295 #define LLDP_CONFIG_ENABLE_RX_OFFSET 30 296 #define LLDP_CONFIG_ENABLE_TX_MASK 0x80000000 297 #define LLDP_CONFIG_ENABLE_TX_OFFSET 31 298 /* Holds local Chassis ID TLV header, subtype and 9B of payload. 299 * If firtst byte is 0, then we will use default chassis ID 300 */ 301 u32 local_chassis_id[LLDP_CHASSIS_ID_STAT_LEN]; 302 /* Holds local Port ID TLV header, subtype and 9B of payload. 303 * If firtst byte is 0, then we will use default port ID 304 */ 305 u32 local_port_id[LLDP_PORT_ID_STAT_LEN]; 306 }; 307 308 struct lldp_status_params_s { 309 u32 prefix_seq_num; 310 u32 status; /* TBD */ 311 /* Holds remote Chassis ID TLV header, subtype and 9B of payload. */ 312 u32 peer_chassis_id[LLDP_CHASSIS_ID_STAT_LEN]; 313 /* Holds remote Port ID TLV header, subtype and 9B of payload. */ 314 u32 peer_port_id[LLDP_PORT_ID_STAT_LEN]; 315 u32 suffix_seq_num; 316 }; 317 318 struct dcbx_ets_feature { 319 u32 flags; 320 #define DCBX_ETS_ENABLED_MASK 0x00000001 321 #define DCBX_ETS_ENABLED_OFFSET 0 322 #define DCBX_ETS_WILLING_MASK 0x00000002 323 #define DCBX_ETS_WILLING_OFFSET 1 324 #define DCBX_ETS_ERROR_MASK 0x00000004 325 #define DCBX_ETS_ERROR_OFFSET 2 326 #define DCBX_ETS_CBS_MASK 0x00000008 327 #define DCBX_ETS_CBS_OFFSET 3 328 #define DCBX_ETS_MAX_TCS_MASK 0x000000f0 329 #define DCBX_ETS_MAX_TCS_OFFSET 4 330 #define DCBX_OOO_TC_MASK 0x00000f00 331 #define DCBX_OOO_TC_OFFSET 8 332 /* Entries in tc table are orginized that the left most is pri 0, right most is 333 * prio 7 334 */ 335 336 u32 pri_tc_tbl[1]; 337 /* Fixed TCP OOO TC usage is deprecated and used only for driver backward 338 * compatibility 339 */ 340 #define DCBX_TCP_OOO_TC (4) 341 #define DCBX_TCP_OOO_K2_4PORT_TC (3) 342 343 #define NIG_ETS_ISCSI_OOO_CLIENT_OFFSET (DCBX_TCP_OOO_TC + 1) 344 #define DCBX_CEE_STRICT_PRIORITY 0xf 345 /* Entries in tc table are orginized that the left most is pri 0, right most is 346 * prio 7 347 */ 348 349 u32 tc_bw_tbl[2]; 350 /* Entries in tc table are orginized that the left most is pri 0, right most is 351 * prio 7 352 */ 353 354 u32 tc_tsa_tbl[2]; 355 #define DCBX_ETS_TSA_STRICT 0 356 #define DCBX_ETS_TSA_CBS 1 357 #define DCBX_ETS_TSA_ETS 2 358 }; 359 360 struct dcbx_app_priority_entry { 361 u32 entry; 362 #define DCBX_APP_PRI_MAP_MASK 0x000000ff 363 #define DCBX_APP_PRI_MAP_OFFSET 0 364 #define DCBX_APP_PRI_0 0x01 365 #define DCBX_APP_PRI_1 0x02 366 #define DCBX_APP_PRI_2 0x04 367 #define DCBX_APP_PRI_3 0x08 368 #define DCBX_APP_PRI_4 0x10 369 #define DCBX_APP_PRI_5 0x20 370 #define DCBX_APP_PRI_6 0x40 371 #define DCBX_APP_PRI_7 0x80 372 #define DCBX_APP_SF_MASK 0x00000300 373 #define DCBX_APP_SF_OFFSET 8 374 #define DCBX_APP_SF_ETHTYPE 0 375 #define DCBX_APP_SF_PORT 1 376 #define DCBX_APP_SF_IEEE_MASK 0x0000f000 377 #define DCBX_APP_SF_IEEE_OFFSET 12 378 #define DCBX_APP_SF_IEEE_RESERVED 0 379 #define DCBX_APP_SF_IEEE_ETHTYPE 1 380 #define DCBX_APP_SF_IEEE_TCP_PORT 2 381 #define DCBX_APP_SF_IEEE_UDP_PORT 3 382 #define DCBX_APP_SF_IEEE_TCP_UDP_PORT 4 383 384 #define DCBX_APP_PROTOCOL_ID_MASK 0xffff0000 385 #define DCBX_APP_PROTOCOL_ID_OFFSET 16 386 }; 387 388 389 /* FW structure in BE */ 390 struct dcbx_app_priority_feature { 391 u32 flags; 392 #define DCBX_APP_ENABLED_MASK 0x00000001 393 #define DCBX_APP_ENABLED_OFFSET 0 394 #define DCBX_APP_WILLING_MASK 0x00000002 395 #define DCBX_APP_WILLING_OFFSET 1 396 #define DCBX_APP_ERROR_MASK 0x00000004 397 #define DCBX_APP_ERROR_OFFSET 2 398 /* Not in use 399 #define DCBX_APP_DEFAULT_PRI_MASK 0x00000f00 400 #define DCBX_APP_DEFAULT_PRI_OFFSET 8 401 */ 402 #define DCBX_APP_MAX_TCS_MASK 0x0000f000 403 #define DCBX_APP_MAX_TCS_OFFSET 12 404 #define DCBX_APP_NUM_ENTRIES_MASK 0x00ff0000 405 #define DCBX_APP_NUM_ENTRIES_OFFSET 16 406 struct dcbx_app_priority_entry app_pri_tbl[DCBX_MAX_APP_PROTOCOL]; 407 }; 408 409 /* FW structure in BE */ 410 struct dcbx_features { 411 /* PG feature */ 412 struct dcbx_ets_feature ets; 413 /* PFC feature */ 414 u32 pfc; 415 #define DCBX_PFC_PRI_EN_BITMAP_MASK 0x000000ff 416 #define DCBX_PFC_PRI_EN_BITMAP_OFFSET 0 417 #define DCBX_PFC_PRI_EN_BITMAP_PRI_0 0x01 418 #define DCBX_PFC_PRI_EN_BITMAP_PRI_1 0x02 419 #define DCBX_PFC_PRI_EN_BITMAP_PRI_2 0x04 420 #define DCBX_PFC_PRI_EN_BITMAP_PRI_3 0x08 421 #define DCBX_PFC_PRI_EN_BITMAP_PRI_4 0x10 422 #define DCBX_PFC_PRI_EN_BITMAP_PRI_5 0x20 423 #define DCBX_PFC_PRI_EN_BITMAP_PRI_6 0x40 424 #define DCBX_PFC_PRI_EN_BITMAP_PRI_7 0x80 425 426 #define DCBX_PFC_FLAGS_MASK 0x0000ff00 427 #define DCBX_PFC_FLAGS_OFFSET 8 428 #define DCBX_PFC_CAPS_MASK 0x00000f00 429 #define DCBX_PFC_CAPS_OFFSET 8 430 #define DCBX_PFC_MBC_MASK 0x00004000 431 #define DCBX_PFC_MBC_OFFSET 14 432 #define DCBX_PFC_WILLING_MASK 0x00008000 433 #define DCBX_PFC_WILLING_OFFSET 15 434 #define DCBX_PFC_ENABLED_MASK 0x00010000 435 #define DCBX_PFC_ENABLED_OFFSET 16 436 #define DCBX_PFC_ERROR_MASK 0x00020000 437 #define DCBX_PFC_ERROR_OFFSET 17 438 439 /* APP feature */ 440 struct dcbx_app_priority_feature app; 441 }; 442 443 struct dcbx_local_params { 444 u32 config; 445 #define DCBX_CONFIG_VERSION_MASK 0x00000007 446 #define DCBX_CONFIG_VERSION_OFFSET 0 447 #define DCBX_CONFIG_VERSION_DISABLED 0 448 #define DCBX_CONFIG_VERSION_IEEE 1 449 #define DCBX_CONFIG_VERSION_CEE 2 450 #define DCBX_CONFIG_VERSION_DYNAMIC \ 451 (DCBX_CONFIG_VERSION_IEEE | DCBX_CONFIG_VERSION_CEE) 452 #define DCBX_CONFIG_VERSION_STATIC 4 453 454 u32 flags; 455 struct dcbx_features features; 456 }; 457 458 struct dcbx_mib { 459 u32 prefix_seq_num; 460 u32 flags; 461 /* 462 #define DCBX_CONFIG_VERSION_MASK 0x00000007 463 #define DCBX_CONFIG_VERSION_OFFSET 0 464 #define DCBX_CONFIG_VERSION_DISABLED 0 465 #define DCBX_CONFIG_VERSION_IEEE 1 466 #define DCBX_CONFIG_VERSION_CEE 2 467 #define DCBX_CONFIG_VERSION_STATIC 4 468 */ 469 struct dcbx_features features; 470 u32 suffix_seq_num; 471 }; 472 473 struct lldp_system_tlvs_buffer_s { 474 u32 flags; 475 #define LLDP_SYSTEM_TLV_VALID_MASK 0x1 476 #define LLDP_SYSTEM_TLV_VALID_OFFSET 0 477 /* This bit defines if system TLVs are instead of mandatory TLVS or in 478 * addition to them. Set 1 for replacing mandatory TLVs 479 */ 480 #define LLDP_SYSTEM_TLV_MANDATORY_MASK 0x2 481 #define LLDP_SYSTEM_TLV_MANDATORY_OFFSET 1 482 #define LLDP_SYSTEM_TLV_LENGTH_MASK 0xffff0000 483 #define LLDP_SYSTEM_TLV_LENGTH_OFFSET 16 484 u32 data[MAX_SYSTEM_LLDP_TLV_DATA]; 485 }; 486 487 /* Since this struct is written by MFW and read by driver need to add 488 * sequence guards (as in case of DCBX MIB) 489 */ 490 struct lldp_received_tlvs_s { 491 u32 prefix_seq_num; 492 u32 length; 493 u32 tlvs_buffer[MAX_TLV_BUFFER]; 494 u32 suffix_seq_num; 495 }; 496 497 struct dcb_dscp_map { 498 u32 flags; 499 #define DCB_DSCP_ENABLE_MASK 0x1 500 #define DCB_DSCP_ENABLE_OFFSET 0 501 #define DCB_DSCP_ENABLE 1 502 u32 dscp_pri_map[8]; 503 }; 504 505 /************************************** 506 * Attributes commands 507 **************************************/ 508 509 enum _attribute_commands_e { 510 ATTRIBUTE_CMD_READ = 0, 511 ATTRIBUTE_CMD_WRITE, 512 ATTRIBUTE_CMD_READ_CLEAR, 513 ATTRIBUTE_CMD_CLEAR, 514 ATTRIBUTE_NUM_OF_COMMANDS 515 }; 516 517 /**************************************/ 518 /* */ 519 /* P U B L I C G L O B A L */ 520 /* */ 521 /**************************************/ 522 struct public_global { 523 u32 max_path; /* 32bit is wasty, but this will be used often */ 524 /* (Global) 32bit is wasty, but this will be used often */ 525 u32 max_ports; 526 #define MODE_1P 1 /* TBD - NEED TO THINK OF A BETTER NAME */ 527 #define MODE_2P 2 528 #define MODE_3P 3 529 #define MODE_4P 4 530 u32 debug_mb_offset; 531 u32 phymod_dbg_mb_offset; 532 struct couple_mode_teaming cmt; 533 /* Temperature in Celcius (-255C / +255C), measured every second. */ 534 s32 internal_temperature; 535 u32 mfw_ver; 536 u32 running_bundle_id; 537 s32 external_temperature; 538 u32 mdump_reason; 539 #define MDUMP_REASON_INTERNAL_ERROR (1 << 0) 540 #define MDUMP_REASON_EXTERNAL_TRIGGER (1 << 1) 541 #define MDUMP_REASON_DUMP_AGED (1 << 2) 542 u32 ext_phy_upgrade_fw; 543 #define EXT_PHY_FW_UPGRADE_STATUS_MASK (0x0000ffff) 544 #define EXT_PHY_FW_UPGRADE_STATUS_OFFSET (0) 545 #define EXT_PHY_FW_UPGRADE_STATUS_IN_PROGRESS (1) 546 #define EXT_PHY_FW_UPGRADE_STATUS_FAILED (2) 547 #define EXT_PHY_FW_UPGRADE_STATUS_SUCCESS (3) 548 #define EXT_PHY_FW_UPGRADE_TYPE_MASK (0xffff0000) 549 #define EXT_PHY_FW_UPGRADE_TYPE_OFFSET (16) 550 }; 551 552 /**************************************/ 553 /* */ 554 /* P U B L I C P A T H */ 555 /* */ 556 /**************************************/ 557 558 /**************************************************************************** 559 * Shared Memory 2 Region * 560 ****************************************************************************/ 561 /* The fw_flr_ack is actually built in the following way: */ 562 /* 8 bit: PF ack */ 563 /* 128 bit: VF ack */ 564 /* 8 bit: ios_dis_ack */ 565 /* In order to maintain endianity in the mailbox hsi, we want to keep using */ 566 /* u32. The fw must have the VF right after the PF since this is how it */ 567 /* access arrays(it expects always the VF to reside after the PF, and that */ 568 /* makes the calculation much easier for it. ) */ 569 /* In order to answer both limitations, and keep the struct small, the code */ 570 /* will abuse the structure defined here to achieve the actual partition */ 571 /* above */ 572 /****************************************************************************/ 573 struct fw_flr_mb { 574 u32 aggint; 575 u32 opgen_addr; 576 u32 accum_ack; /* 0..15:PF, 16..207:VF, 256..271:IOV_DIS */ 577 #define ACCUM_ACK_PF_BASE 0 578 #define ACCUM_ACK_PF_SHIFT 0 579 580 #define ACCUM_ACK_VF_BASE 8 581 #define ACCUM_ACK_VF_SHIFT 3 582 583 #define ACCUM_ACK_IOV_DIS_BASE 256 584 #define ACCUM_ACK_IOV_DIS_SHIFT 8 585 586 }; 587 588 struct public_path { 589 struct fw_flr_mb flr_mb; 590 /* 591 * mcp_vf_disabled is set by the MCP to indicate the driver about VFs 592 * which were disabled/flred 593 */ 594 u32 mcp_vf_disabled[VF_MAX_STATIC / 32]; /* 0x003c */ 595 596 /* Reset on mcp reset, and incremented for eveny process kill event. */ 597 u32 process_kill; 598 #define PROCESS_KILL_COUNTER_MASK 0x0000ffff 599 #define PROCESS_KILL_COUNTER_OFFSET 0 600 #define PROCESS_KILL_GLOB_AEU_BIT_MASK 0xffff0000 601 #define PROCESS_KILL_GLOB_AEU_BIT_OFFSET 16 602 #define GLOBAL_AEU_BIT(aeu_reg_id, aeu_bit) (aeu_reg_id * 32 + aeu_bit) 603 /*Added to support E5 240 VFs*/ 604 u32 mcp_vf_disabled2[ADDED_VF_BITMAP_SIZE]; 605 }; 606 607 /**************************************/ 608 /* */ 609 /* P U B L I C P O R T */ 610 /* */ 611 /**************************************/ 612 #define FC_NPIV_WWPN_SIZE 8 613 #define FC_NPIV_WWNN_SIZE 8 614 struct dci_npiv_settings { 615 u8 npiv_wwpn[FC_NPIV_WWPN_SIZE]; 616 u8 npiv_wwnn[FC_NPIV_WWNN_SIZE]; 617 }; 618 619 struct dci_fc_npiv_cfg { 620 /* hdr used internally by the MFW */ 621 u32 hdr; 622 u32 num_of_npiv; 623 }; 624 625 #define MAX_NUMBER_NPIV 64 626 struct dci_fc_npiv_tbl { 627 struct dci_fc_npiv_cfg fc_npiv_cfg; 628 struct dci_npiv_settings settings[MAX_NUMBER_NPIV]; 629 }; 630 631 /**************************************************************************** 632 * Driver <-> FW Mailbox * 633 ****************************************************************************/ 634 635 struct public_port { 636 u32 validity_map; /* 0x0 (4*2 = 0x8) */ 637 638 /* validity bits */ 639 #define MCP_VALIDITY_PCI_CFG 0x00100000 640 #define MCP_VALIDITY_MB 0x00200000 641 #define MCP_VALIDITY_DEV_INFO 0x00400000 642 #define MCP_VALIDITY_RESERVED 0x00000007 643 644 /* One licensing bit should be set */ 645 /* yaniv - tbd ? license */ 646 #define MCP_VALIDITY_LIC_KEY_IN_EFFECT_MASK 0x00000038 647 #define MCP_VALIDITY_LIC_MANUF_KEY_IN_EFFECT 0x00000008 648 #define MCP_VALIDITY_LIC_UPGRADE_KEY_IN_EFFECT 0x00000010 649 #define MCP_VALIDITY_LIC_NO_KEY_IN_EFFECT 0x00000020 650 651 /* Active MFW */ 652 #define MCP_VALIDITY_ACTIVE_MFW_UNKNOWN 0x00000000 653 #define MCP_VALIDITY_ACTIVE_MFW_MASK 0x000001c0 654 #define MCP_VALIDITY_ACTIVE_MFW_NCSI 0x00000040 655 #define MCP_VALIDITY_ACTIVE_MFW_NONE 0x000001c0 656 657 u32 link_status; 658 #define LINK_STATUS_LINK_UP 0x00000001 659 #define LINK_STATUS_SPEED_AND_DUPLEX_MASK 0x0000001e 660 #define LINK_STATUS_SPEED_AND_DUPLEX_1000THD (1 << 1) 661 #define LINK_STATUS_SPEED_AND_DUPLEX_1000TFD (2 << 1) 662 #define LINK_STATUS_SPEED_AND_DUPLEX_10G (3 << 1) 663 #define LINK_STATUS_SPEED_AND_DUPLEX_20G (4 << 1) 664 #define LINK_STATUS_SPEED_AND_DUPLEX_40G (5 << 1) 665 #define LINK_STATUS_SPEED_AND_DUPLEX_50G (6 << 1) 666 #define LINK_STATUS_SPEED_AND_DUPLEX_100G (7 << 1) 667 #define LINK_STATUS_SPEED_AND_DUPLEX_25G (8 << 1) 668 #define LINK_STATUS_AUTO_NEGOTIATE_ENABLED 0x00000020 669 #define LINK_STATUS_AUTO_NEGOTIATE_COMPLETE 0x00000040 670 #define LINK_STATUS_PARALLEL_DETECTION_USED 0x00000080 671 #define LINK_STATUS_PFC_ENABLED 0x00000100 672 #define LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE 0x00000200 673 #define LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE 0x00000400 674 #define LINK_STATUS_LINK_PARTNER_10G_CAPABLE 0x00000800 675 #define LINK_STATUS_LINK_PARTNER_20G_CAPABLE 0x00001000 676 #define LINK_STATUS_LINK_PARTNER_40G_CAPABLE 0x00002000 677 #define LINK_STATUS_LINK_PARTNER_50G_CAPABLE 0x00004000 678 #define LINK_STATUS_LINK_PARTNER_100G_CAPABLE 0x00008000 679 #define LINK_STATUS_LINK_PARTNER_25G_CAPABLE 0x00010000 680 #define LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK 0x000C0000 681 #define LINK_STATUS_LINK_PARTNER_NOT_PAUSE_CAPABLE (0 << 18) 682 #define LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE (1 << 18) 683 #define LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE (2 << 18) 684 #define LINK_STATUS_LINK_PARTNER_BOTH_PAUSE (3 << 18) 685 #define LINK_STATUS_SFP_TX_FAULT 0x00100000 686 #define LINK_STATUS_TX_FLOW_CONTROL_ENABLED 0x00200000 687 #define LINK_STATUS_RX_FLOW_CONTROL_ENABLED 0x00400000 688 #define LINK_STATUS_RX_SIGNAL_PRESENT 0x00800000 689 #define LINK_STATUS_MAC_LOCAL_FAULT 0x01000000 690 #define LINK_STATUS_MAC_REMOTE_FAULT 0x02000000 691 #define LINK_STATUS_UNSUPPORTED_SPD_REQ 0x04000000 692 #define LINK_STATUS_FEC_MODE_MASK 0x38000000 693 #define LINK_STATUS_FEC_MODE_NONE (0 << 27) 694 #define LINK_STATUS_FEC_MODE_FIRECODE_CL74 (1 << 27) 695 #define LINK_STATUS_FEC_MODE_RS_CL91 (2 << 27) 696 #define LINK_STATUS_EXT_PHY_LINK_UP 0x40000000 697 698 u32 link_status1; 699 u32 ext_phy_fw_version; 700 /* Points to struct eth_phy_cfg (For READ-ONLY) */ 701 u32 drv_phy_cfg_addr; 702 703 u32 port_stx; 704 705 u32 stat_nig_timer; 706 707 struct port_mf_cfg port_mf_config; 708 struct port_stats stats; 709 710 u32 media_type; 711 #define MEDIA_UNSPECIFIED 0x0 712 #define MEDIA_SFPP_10G_FIBER 0x1 /* Use MEDIA_MODULE_FIBER instead */ 713 #define MEDIA_XFP_FIBER 0x2 /* Use MEDIA_MODULE_FIBER instead */ 714 #define MEDIA_DA_TWINAX 0x3 715 #define MEDIA_BASE_T 0x4 716 #define MEDIA_SFP_1G_FIBER 0x5 /* Use MEDIA_MODULE_FIBER instead */ 717 #define MEDIA_MODULE_FIBER 0x6 718 #define MEDIA_KR 0xf0 719 #define MEDIA_NOT_PRESENT 0xff 720 721 u32 lfa_status; 722 #define LFA_LINK_FLAP_REASON_OFFSET 0 723 #define LFA_LINK_FLAP_REASON_MASK 0x000000ff 724 #define LFA_NO_REASON (0 << 0) 725 #define LFA_LINK_DOWN (1 << 0) 726 #define LFA_FORCE_INIT (1 << 1) 727 #define LFA_LOOPBACK_MISMATCH (1 << 2) 728 #define LFA_SPEED_MISMATCH (1 << 3) 729 #define LFA_FLOW_CTRL_MISMATCH (1 << 4) 730 #define LFA_ADV_SPEED_MISMATCH (1 << 5) 731 #define LFA_EEE_MISMATCH (1 << 6) 732 #define LFA_LINK_MODES_MISMATCH (1 << 7) 733 #define LINK_FLAP_AVOIDANCE_COUNT_OFFSET 8 734 #define LINK_FLAP_AVOIDANCE_COUNT_MASK 0x0000ff00 735 #define LINK_FLAP_COUNT_OFFSET 16 736 #define LINK_FLAP_COUNT_MASK 0x00ff0000 737 738 u32 link_change_count; 739 740 /* LLDP params */ 741 /* offset: 536 bytes? */ 742 struct lldp_config_params_s lldp_config_params[LLDP_MAX_LLDP_AGENTS]; 743 struct lldp_status_params_s lldp_status_params[LLDP_MAX_LLDP_AGENTS]; 744 struct lldp_system_tlvs_buffer_s system_lldp_tlvs_buf; 745 746 /* DCBX related MIB */ 747 struct dcbx_local_params local_admin_dcbx_mib; 748 struct dcbx_mib remote_dcbx_mib; 749 struct dcbx_mib operational_dcbx_mib; 750 751 /* FC_NPIV table offset & size in NVRAM value of 0 means not present */ 752 753 u32 fc_npiv_nvram_tbl_addr; 754 u32 fc_npiv_nvram_tbl_size; 755 u32 transceiver_data; 756 #define ETH_TRANSCEIVER_STATE_MASK 0x000000FF 757 #define ETH_TRANSCEIVER_STATE_OFFSET 0x00000000 758 #define ETH_TRANSCEIVER_STATE_UNPLUGGED 0x00000000 759 #define ETH_TRANSCEIVER_STATE_PRESENT 0x00000001 760 #define ETH_TRANSCEIVER_STATE_VALID 0x00000003 761 #define ETH_TRANSCEIVER_STATE_UPDATING 0x00000008 762 #define ETH_TRANSCEIVER_TYPE_MASK 0x0000FF00 763 #define ETH_TRANSCEIVER_TYPE_OFFSET 0x00000008 764 #define ETH_TRANSCEIVER_TYPE_NONE 0x00000000 765 #define ETH_TRANSCEIVER_TYPE_UNKNOWN 0x000000FF 766 /* 1G Passive copper cable */ 767 #define ETH_TRANSCEIVER_TYPE_1G_PCC 0x01 768 /* 1G Active copper cable */ 769 #define ETH_TRANSCEIVER_TYPE_1G_ACC 0x02 770 #define ETH_TRANSCEIVER_TYPE_1G_LX 0x03 771 #define ETH_TRANSCEIVER_TYPE_1G_SX 0x04 772 #define ETH_TRANSCEIVER_TYPE_10G_SR 0x05 773 #define ETH_TRANSCEIVER_TYPE_10G_LR 0x06 774 #define ETH_TRANSCEIVER_TYPE_10G_LRM 0x07 775 #define ETH_TRANSCEIVER_TYPE_10G_ER 0x08 776 /* 10G Passive copper cable */ 777 #define ETH_TRANSCEIVER_TYPE_10G_PCC 0x09 778 /* 10G Active copper cable */ 779 #define ETH_TRANSCEIVER_TYPE_10G_ACC 0x0a 780 #define ETH_TRANSCEIVER_TYPE_XLPPI 0x0b 781 #define ETH_TRANSCEIVER_TYPE_40G_LR4 0x0c 782 #define ETH_TRANSCEIVER_TYPE_40G_SR4 0x0d 783 #define ETH_TRANSCEIVER_TYPE_40G_CR4 0x0e 784 /* Active optical cable */ 785 #define ETH_TRANSCEIVER_TYPE_100G_AOC 0x0f 786 #define ETH_TRANSCEIVER_TYPE_100G_SR4 0x10 787 #define ETH_TRANSCEIVER_TYPE_100G_LR4 0x11 788 #define ETH_TRANSCEIVER_TYPE_100G_ER4 0x12 789 /* Active copper cable */ 790 #define ETH_TRANSCEIVER_TYPE_100G_ACC 0x13 791 #define ETH_TRANSCEIVER_TYPE_100G_CR4 0x14 792 #define ETH_TRANSCEIVER_TYPE_4x10G_SR 0x15 793 /* 25G Passive copper cable - short */ 794 #define ETH_TRANSCEIVER_TYPE_25G_CA_N 0x16 795 /* 25G Active copper cable - short */ 796 #define ETH_TRANSCEIVER_TYPE_25G_ACC_S 0x17 797 /* 25G Passive copper cable - medium */ 798 #define ETH_TRANSCEIVER_TYPE_25G_CA_S 0x18 799 /* 25G Active copper cable - medium */ 800 #define ETH_TRANSCEIVER_TYPE_25G_ACC_M 0x19 801 /* 25G Passive copper cable - long */ 802 #define ETH_TRANSCEIVER_TYPE_25G_CA_L 0x1a 803 /* 25G Active copper cable - long */ 804 #define ETH_TRANSCEIVER_TYPE_25G_ACC_L 0x1b 805 #define ETH_TRANSCEIVER_TYPE_25G_SR 0x1c 806 #define ETH_TRANSCEIVER_TYPE_25G_LR 0x1d 807 #define ETH_TRANSCEIVER_TYPE_25G_AOC 0x1e 808 809 #define ETH_TRANSCEIVER_TYPE_4x10G 0x1f 810 #define ETH_TRANSCEIVER_TYPE_4x25G_CR 0x20 811 #define ETH_TRANSCEIVER_TYPE_1000BASET 0x21 812 #define ETH_TRANSCEIVER_TYPE_10G_BASET 0x22 813 #define ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_40G_SR 0x30 814 #define ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_40G_CR 0x31 815 #define ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_40G_LR 0x32 816 #define ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_SR 0x33 817 #define ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_CR 0x34 818 #define ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_LR 0x35 819 #define ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_AOC 0x36 820 u32 wol_info; 821 u32 wol_pkt_len; 822 u32 wol_pkt_details; 823 struct dcb_dscp_map dcb_dscp_map; 824 825 u32 eee_status; 826 /* Set when EEE negotiation is complete. */ 827 #define EEE_ACTIVE_BIT (1 << 0) 828 829 /* Shows the Local Device EEE capabilities */ 830 #define EEE_LD_ADV_STATUS_MASK 0x000000f0 831 #define EEE_LD_ADV_STATUS_OFFSET 4 832 #define EEE_1G_ADV (1 << 1) 833 #define EEE_10G_ADV (1 << 2) 834 /* Same values as in EEE_LD_ADV, but for Link Parter */ 835 #define EEE_LP_ADV_STATUS_MASK 0x00000f00 836 #define EEE_LP_ADV_STATUS_OFFSET 8 837 838 /* Supported speeds for EEE */ 839 #define EEE_SUPPORTED_SPEED_MASK 0x0000f000 840 #define EEE_SUPPORTED_SPEED_OFFSET 12 841 #define EEE_1G_SUPPORTED (1 << 1) 842 #define EEE_10G_SUPPORTED (1 << 2) 843 844 u32 eee_remote; /* Used for EEE in LLDP */ 845 #define EEE_REMOTE_TW_TX_MASK 0x0000ffff 846 #define EEE_REMOTE_TW_TX_OFFSET 0 847 #define EEE_REMOTE_TW_RX_MASK 0xffff0000 848 #define EEE_REMOTE_TW_RX_OFFSET 16 849 850 u32 module_info; 851 #define ETH_TRANSCEIVER_MONITORING_TYPE_MASK 0x000000FF 852 #define ETH_TRANSCEIVER_MONITORING_TYPE_OFFSET 0 853 #define ETH_TRANSCEIVER_ADDR_CHNG_REQUIRED (1 << 2) 854 #define ETH_TRANSCEIVER_RCV_PWR_MEASURE_TYPE (1 << 3) 855 #define ETH_TRANSCEIVER_EXTERNALLY_CALIBRATED (1 << 4) 856 #define ETH_TRANSCEIVER_INTERNALLY_CALIBRATED (1 << 5) 857 #define ETH_TRANSCEIVER_HAS_DIAGNOSTIC (1 << 6) 858 #define ETH_TRANSCEIVER_IDENT_MASK 0x0000ff00 859 #define ETH_TRANSCEIVER_IDENT_OFFSET 8 860 861 u32 oem_cfg_port; 862 #define OEM_CFG_CHANNEL_TYPE_MASK 0x00000003 863 #define OEM_CFG_CHANNEL_TYPE_OFFSET 0 864 #define OEM_CFG_CHANNEL_TYPE_VLAN_PARTITION 0x1 865 #define OEM_CFG_CHANNEL_TYPE_STAGGED 0x2 866 867 #define OEM_CFG_SCHED_TYPE_MASK 0x0000000C 868 #define OEM_CFG_SCHED_TYPE_OFFSET 2 869 #define OEM_CFG_SCHED_TYPE_ETS 0x1 870 #define OEM_CFG_SCHED_TYPE_VNIC_BW 0x2 871 872 struct lldp_received_tlvs_s lldp_received_tlvs[LLDP_MAX_LLDP_AGENTS]; 873 u32 system_lldp_tlvs_buf2[MAX_SYSTEM_LLDP_TLV_DATA]; 874 }; 875 876 /**************************************/ 877 /* */ 878 /* P U B L I C F U N C */ 879 /* */ 880 /**************************************/ 881 882 struct public_func { 883 u32 iscsi_boot_signature; 884 u32 iscsi_boot_block_offset; 885 886 /* MTU size per funciton is needed for the OV feature */ 887 u32 mtu_size; 888 /* 9 entires for the C2S PCP map for each inner VLAN PCP + 1 default */ 889 890 /* For PCP values 0-3 use the map lower */ 891 /* 0xFF000000 - PCP 0, 0x00FF0000 - PCP 1, 892 * 0x0000FF00 - PCP 2, 0x000000FF PCP 3 893 */ 894 u32 c2s_pcp_map_lower; 895 /* For PCP values 4-7 use the map upper */ 896 /* 0xFF000000 - PCP 4, 0x00FF0000 - PCP 5, 897 * 0x0000FF00 - PCP 6, 0x000000FF PCP 7 898 */ 899 u32 c2s_pcp_map_upper; 900 901 /* For PCP default value get the MSB byte of the map default */ 902 u32 c2s_pcp_map_default; 903 904 u32 reserved[4]; 905 906 /* replace old mf_cfg */ 907 u32 config; 908 /* E/R/I/D */ 909 /* function 0 of each port cannot be hidden */ 910 #define FUNC_MF_CFG_FUNC_HIDE 0x00000001 911 #define FUNC_MF_CFG_PAUSE_ON_HOST_RING 0x00000002 912 #define FUNC_MF_CFG_PAUSE_ON_HOST_RING_OFFSET 0x00000001 913 914 915 #define FUNC_MF_CFG_PROTOCOL_MASK 0x000000f0 916 #define FUNC_MF_CFG_PROTOCOL_OFFSET 4 917 #define FUNC_MF_CFG_PROTOCOL_ETHERNET 0x00000000 918 #define FUNC_MF_CFG_PROTOCOL_ISCSI 0x00000010 919 #define FUNC_MF_CFG_PROTOCOL_FCOE 0x00000020 920 #define FUNC_MF_CFG_PROTOCOL_ROCE 0x00000030 921 #define FUNC_MF_CFG_PROTOCOL_MAX 0x00000030 922 923 /* MINBW, MAXBW */ 924 /* value range - 0..100, increments in 1 % */ 925 #define FUNC_MF_CFG_MIN_BW_MASK 0x0000ff00 926 #define FUNC_MF_CFG_MIN_BW_OFFSET 8 927 #define FUNC_MF_CFG_MIN_BW_DEFAULT 0x00000000 928 #define FUNC_MF_CFG_MAX_BW_MASK 0x00ff0000 929 #define FUNC_MF_CFG_MAX_BW_OFFSET 16 930 #define FUNC_MF_CFG_MAX_BW_DEFAULT 0x00640000 931 932 u32 status; 933 #define FUNC_STATUS_VIRTUAL_LINK_UP 0x00000001 934 #define FUNC_STATUS_LOGICAL_LINK_UP 0x00000002 935 #define FUNC_STATUS_FORCED_LINK 0x00000004 936 937 u32 mac_upper; /* MAC */ 938 #define FUNC_MF_CFG_UPPERMAC_MASK 0x0000ffff 939 #define FUNC_MF_CFG_UPPERMAC_OFFSET 0 940 #define FUNC_MF_CFG_UPPERMAC_DEFAULT FUNC_MF_CFG_UPPERMAC_MASK 941 u32 mac_lower; 942 #define FUNC_MF_CFG_LOWERMAC_DEFAULT 0xffffffff 943 944 u32 fcoe_wwn_port_name_upper; 945 u32 fcoe_wwn_port_name_lower; 946 947 u32 fcoe_wwn_node_name_upper; 948 u32 fcoe_wwn_node_name_lower; 949 950 u32 ovlan_stag; /* tags */ 951 #define FUNC_MF_CFG_OV_STAG_MASK 0x0000ffff 952 #define FUNC_MF_CFG_OV_STAG_OFFSET 0 953 #define FUNC_MF_CFG_OV_STAG_DEFAULT FUNC_MF_CFG_OV_STAG_MASK 954 955 u32 pf_allocation; /* vf per pf */ 956 957 u32 preserve_data; /* Will be used bt CCM */ 958 959 u32 driver_last_activity_ts; 960 961 /* 962 * drv_ack_vf_disabled is set by the PF driver to ack handled disabled 963 * VFs 964 */ 965 u32 drv_ack_vf_disabled[VF_MAX_STATIC / 32]; /* 0x0044 */ 966 967 u32 drv_id; 968 #define DRV_ID_PDA_COMP_VER_MASK 0x0000ffff 969 #define DRV_ID_PDA_COMP_VER_OFFSET 0 970 971 #define LOAD_REQ_HSI_VERSION 2 972 #define DRV_ID_MCP_HSI_VER_MASK 0x00ff0000 973 #define DRV_ID_MCP_HSI_VER_OFFSET 16 974 #define DRV_ID_MCP_HSI_VER_CURRENT (LOAD_REQ_HSI_VERSION << \ 975 DRV_ID_MCP_HSI_VER_OFFSET) 976 977 #define DRV_ID_DRV_TYPE_MASK 0x7f000000 978 #define DRV_ID_DRV_TYPE_OFFSET 24 979 #define DRV_ID_DRV_TYPE_UNKNOWN (0 << DRV_ID_DRV_TYPE_OFFSET) 980 #define DRV_ID_DRV_TYPE_LINUX (1 << DRV_ID_DRV_TYPE_OFFSET) 981 #define DRV_ID_DRV_TYPE_WINDOWS (2 << DRV_ID_DRV_TYPE_OFFSET) 982 #define DRV_ID_DRV_TYPE_DIAG (3 << DRV_ID_DRV_TYPE_OFFSET) 983 #define DRV_ID_DRV_TYPE_PREBOOT (4 << DRV_ID_DRV_TYPE_OFFSET) 984 #define DRV_ID_DRV_TYPE_SOLARIS (5 << DRV_ID_DRV_TYPE_OFFSET) 985 #define DRV_ID_DRV_TYPE_VMWARE (6 << DRV_ID_DRV_TYPE_OFFSET) 986 #define DRV_ID_DRV_TYPE_FREEBSD (7 << DRV_ID_DRV_TYPE_OFFSET) 987 #define DRV_ID_DRV_TYPE_AIX (8 << DRV_ID_DRV_TYPE_OFFSET) 988 989 #define DRV_ID_DRV_INIT_HW_MASK 0x80000000 990 #define DRV_ID_DRV_INIT_HW_OFFSET 31 991 #define DRV_ID_DRV_INIT_HW_FLAG (1 << DRV_ID_DRV_INIT_HW_OFFSET) 992 993 u32 oem_cfg_func; 994 #define OEM_CFG_FUNC_TC_MASK 0x0000000F 995 #define OEM_CFG_FUNC_TC_OFFSET 0 996 #define OEM_CFG_FUNC_TC_0 0x0 997 #define OEM_CFG_FUNC_TC_1 0x1 998 #define OEM_CFG_FUNC_TC_2 0x2 999 #define OEM_CFG_FUNC_TC_3 0x3 1000 #define OEM_CFG_FUNC_TC_4 0x4 1001 #define OEM_CFG_FUNC_TC_5 0x5 1002 #define OEM_CFG_FUNC_TC_6 0x6 1003 #define OEM_CFG_FUNC_TC_7 0x7 1004 1005 #define OEM_CFG_FUNC_HOST_PRI_CTRL_MASK 0x00000030 1006 #define OEM_CFG_FUNC_HOST_PRI_CTRL_OFFSET 4 1007 #define OEM_CFG_FUNC_HOST_PRI_CTRL_VNIC 0x1 1008 #define OEM_CFG_FUNC_HOST_PRI_CTRL_OS 0x2 1009 }; 1010 1011 /**************************************/ 1012 /* */ 1013 /* P U B L I C M B */ 1014 /* */ 1015 /**************************************/ 1016 /* This is the only section that the driver can write to, and each */ 1017 /* Basically each driver request to set feature parameters, 1018 * will be done using a different command, which will be linked 1019 * to a specific data structure from the union below. 1020 * For huge strucuture, the common blank structure should be used. 1021 */ 1022 1023 struct mcp_mac { 1024 u32 mac_upper; /* Upper 16 bits are always zeroes */ 1025 u32 mac_lower; 1026 }; 1027 1028 struct mcp_val64 { 1029 u32 lo; 1030 u32 hi; 1031 }; 1032 1033 struct mcp_file_att { 1034 u32 nvm_start_addr; 1035 u32 len; 1036 }; 1037 1038 struct bist_nvm_image_att { 1039 u32 return_code; 1040 u32 image_type; /* Image type */ 1041 u32 nvm_start_addr; /* NVM address of the image */ 1042 u32 len; /* Include CRC */ 1043 }; 1044 1045 #define MCP_DRV_VER_STR_SIZE 16 1046 #define MCP_DRV_VER_STR_SIZE_DWORD (MCP_DRV_VER_STR_SIZE / sizeof(u32)) 1047 #define MCP_DRV_NVM_BUF_LEN 32 1048 struct drv_version_stc { 1049 u32 version; 1050 u8 name[MCP_DRV_VER_STR_SIZE - 4]; 1051 }; 1052 1053 /* statistics for ncsi */ 1054 struct lan_stats_stc { 1055 u64 ucast_rx_pkts; 1056 u64 ucast_tx_pkts; 1057 u32 fcs_err; 1058 u32 rserved; 1059 }; 1060 1061 struct fcoe_stats_stc { 1062 u64 rx_pkts; 1063 u64 tx_pkts; 1064 u32 fcs_err; 1065 u32 login_failure; 1066 }; 1067 1068 struct iscsi_stats_stc { 1069 u64 rx_pdus; 1070 u64 tx_pdus; 1071 u64 rx_bytes; 1072 u64 tx_bytes; 1073 }; 1074 1075 struct rdma_stats_stc { 1076 u64 rx_pkts; 1077 u64 tx_pkts; 1078 u64 rx_bytes; 1079 u64 tx_bytes; 1080 }; 1081 1082 struct ocbb_data_stc { 1083 u32 ocbb_host_addr; 1084 u32 ocsd_host_addr; 1085 u32 ocsd_req_update_interval; 1086 }; 1087 1088 #define MAX_NUM_OF_SENSORS 7 1089 #define MFW_SENSOR_LOCATION_INTERNAL 1 1090 #define MFW_SENSOR_LOCATION_EXTERNAL 2 1091 #define MFW_SENSOR_LOCATION_SFP 3 1092 1093 #define SENSOR_LOCATION_OFFSET 0 1094 #define SENSOR_LOCATION_MASK 0x000000ff 1095 #define THRESHOLD_HIGH_OFFSET 8 1096 #define THRESHOLD_HIGH_MASK 0x0000ff00 1097 #define CRITICAL_TEMPERATURE_OFFSET 16 1098 #define CRITICAL_TEMPERATURE_MASK 0x00ff0000 1099 #define CURRENT_TEMP_OFFSET 24 1100 #define CURRENT_TEMP_MASK 0xff000000 1101 struct temperature_status_stc { 1102 u32 num_of_sensors; 1103 u32 sensor[MAX_NUM_OF_SENSORS]; 1104 }; 1105 1106 /* crash dump configuration header */ 1107 struct mdump_config_stc { 1108 u32 version; 1109 u32 config; 1110 u32 epoc; 1111 u32 num_of_logs; 1112 u32 valid_logs; 1113 }; 1114 1115 enum resource_id_enum { 1116 RESOURCE_NUM_SB_E = 0, 1117 RESOURCE_NUM_L2_QUEUE_E = 1, 1118 RESOURCE_NUM_VPORT_E = 2, 1119 RESOURCE_NUM_VMQ_E = 3, 1120 /* Not a real resource!! it's a factor used to calculate others */ 1121 RESOURCE_FACTOR_NUM_RSS_PF_E = 4, 1122 /* Not a real resource!! it's a factor used to calculate others */ 1123 RESOURCE_FACTOR_RSS_PER_VF_E = 5, 1124 RESOURCE_NUM_RL_E = 6, 1125 RESOURCE_NUM_PQ_E = 7, 1126 RESOURCE_NUM_VF_E = 8, 1127 RESOURCE_VFC_FILTER_E = 9, 1128 RESOURCE_ILT_E = 10, 1129 RESOURCE_CQS_E = 11, 1130 RESOURCE_GFT_PROFILES_E = 12, 1131 RESOURCE_NUM_TC_E = 13, 1132 RESOURCE_NUM_RSS_ENGINES_E = 14, 1133 RESOURCE_LL2_QUEUE_E = 15, 1134 RESOURCE_RDMA_STATS_QUEUE_E = 16, 1135 RESOURCE_BDQ_E = 17, 1136 RESOURCE_MAX_NUM, 1137 RESOURCE_NUM_INVALID = 0xFFFFFFFF 1138 }; 1139 1140 /* Resource ID is to be filled by the driver in the MB request 1141 * Size, offset & flags to be filled by the MFW in the MB response 1142 */ 1143 struct resource_info { 1144 enum resource_id_enum res_id; 1145 u32 size; /* number of allocated resources */ 1146 u32 offset; /* Offset of the 1st resource */ 1147 u32 vf_size; 1148 u32 vf_offset; 1149 u32 flags; 1150 #define RESOURCE_ELEMENT_STRICT (1 << 0) 1151 }; 1152 1153 #define DRV_ROLE_NONE 0 1154 #define DRV_ROLE_PREBOOT 1 1155 #define DRV_ROLE_OS 2 1156 #define DRV_ROLE_KDUMP 3 1157 1158 struct load_req_stc { 1159 u32 drv_ver_0; 1160 u32 drv_ver_1; 1161 u32 fw_ver; 1162 u32 misc0; 1163 #define LOAD_REQ_ROLE_MASK 0x000000FF 1164 #define LOAD_REQ_ROLE_OFFSET 0 1165 #define LOAD_REQ_LOCK_TO_MASK 0x0000FF00 1166 #define LOAD_REQ_LOCK_TO_OFFSET 8 1167 #define LOAD_REQ_LOCK_TO_DEFAULT 0 1168 #define LOAD_REQ_LOCK_TO_NONE 255 1169 #define LOAD_REQ_FORCE_MASK 0x000F0000 1170 #define LOAD_REQ_FORCE_OFFSET 16 1171 #define LOAD_REQ_FORCE_NONE 0 1172 #define LOAD_REQ_FORCE_PF 1 1173 #define LOAD_REQ_FORCE_ALL 2 1174 #define LOAD_REQ_FLAGS0_MASK 0x00F00000 1175 #define LOAD_REQ_FLAGS0_OFFSET 20 1176 #define LOAD_REQ_FLAGS0_AVOID_RESET (0x1 << 0) 1177 }; 1178 1179 struct load_rsp_stc { 1180 u32 drv_ver_0; 1181 u32 drv_ver_1; 1182 u32 fw_ver; 1183 u32 misc0; 1184 #define LOAD_RSP_ROLE_MASK 0x000000FF 1185 #define LOAD_RSP_ROLE_OFFSET 0 1186 #define LOAD_RSP_HSI_MASK 0x0000FF00 1187 #define LOAD_RSP_HSI_OFFSET 8 1188 #define LOAD_RSP_FLAGS0_MASK 0x000F0000 1189 #define LOAD_RSP_FLAGS0_OFFSET 16 1190 #define LOAD_RSP_FLAGS0_DRV_EXISTS (0x1 << 0) 1191 }; 1192 1193 struct mdump_retain_data_stc { 1194 u32 valid; 1195 u32 epoch; 1196 u32 pf; 1197 u32 status; 1198 }; 1199 1200 struct attribute_cmd_write_stc { 1201 u32 val; 1202 u32 mask; 1203 u32 offset; 1204 }; 1205 1206 union drv_union_data { 1207 struct mcp_mac wol_mac; /* UNLOAD_DONE */ 1208 1209 /* This configuration should be set by the driver for the LINK_SET command. */ 1210 1211 struct eth_phy_cfg drv_phy_cfg; 1212 1213 struct mcp_val64 val64; /* For PHY / AVS commands */ 1214 1215 u8 raw_data[MCP_DRV_NVM_BUF_LEN]; 1216 1217 struct mcp_file_att file_att; 1218 1219 u32 ack_vf_disabled[VF_MAX_STATIC / 32]; 1220 1221 struct drv_version_stc drv_version; 1222 1223 struct lan_stats_stc lan_stats; 1224 struct fcoe_stats_stc fcoe_stats; 1225 struct iscsi_stats_stc iscsi_stats; 1226 struct rdma_stats_stc rdma_stats; 1227 struct ocbb_data_stc ocbb_info; 1228 struct temperature_status_stc temp_info; 1229 struct resource_info resource; 1230 struct bist_nvm_image_att nvm_image_att; 1231 struct mdump_config_stc mdump_config; 1232 u32 dword; 1233 1234 struct load_req_stc load_req; 1235 struct load_rsp_stc load_rsp; 1236 struct mdump_retain_data_stc mdump_retain; 1237 struct attribute_cmd_write_stc attribute_cmd_write; 1238 /* ... */ 1239 }; 1240 1241 struct public_drv_mb { 1242 u32 drv_mb_header; 1243 #define DRV_MSG_CODE_MASK 0xffff0000 1244 #define DRV_MSG_CODE_LOAD_REQ 0x10000000 1245 #define DRV_MSG_CODE_LOAD_DONE 0x11000000 1246 #define DRV_MSG_CODE_INIT_HW 0x12000000 1247 #define DRV_MSG_CODE_CANCEL_LOAD_REQ 0x13000000 1248 #define DRV_MSG_CODE_UNLOAD_REQ 0x20000000 1249 #define DRV_MSG_CODE_UNLOAD_DONE 0x21000000 1250 #define DRV_MSG_CODE_INIT_PHY 0x22000000 1251 /* Params - FORCE - Reinitialize the link regardless of LFA */ 1252 /* - DONT_CARE - Don't flap the link if up */ 1253 #define DRV_MSG_CODE_LINK_RESET 0x23000000 1254 1255 #define DRV_MSG_CODE_SET_LLDP 0x24000000 1256 #define DRV_MSG_CODE_REGISTER_LLDP_TLVS_RX 0x24100000 1257 #define DRV_MSG_CODE_SET_DCBX 0x25000000 1258 /* OneView feature driver HSI*/ 1259 #define DRV_MSG_CODE_OV_UPDATE_CURR_CFG 0x26000000 1260 #define DRV_MSG_CODE_OV_UPDATE_BUS_NUM 0x27000000 1261 #define DRV_MSG_CODE_OV_UPDATE_BOOT_PROGRESS 0x28000000 1262 #define DRV_MSG_CODE_OV_UPDATE_STORM_FW_VER 0x29000000 1263 #define DRV_MSG_CODE_NIG_DRAIN 0x30000000 1264 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE 0x31000000 1265 #define DRV_MSG_CODE_BW_UPDATE_ACK 0x32000000 1266 #define DRV_MSG_CODE_OV_UPDATE_MTU 0x33000000 1267 /* DRV_MB Param: driver version supp, FW_MB param: MFW version supp, 1268 * data: struct resource_info 1269 */ 1270 #define DRV_MSG_GET_RESOURCE_ALLOC_MSG 0x34000000 1271 #define DRV_MSG_SET_RESOURCE_VALUE_MSG 0x35000000 1272 #define DRV_MSG_CODE_OV_UPDATE_WOL 0x38000000 1273 #define DRV_MSG_CODE_OV_UPDATE_ESWITCH_MODE 0x39000000 1274 #define DRV_MSG_CODE_S_TAG_UPDATE_ACK 0x3b000000 1275 #define DRV_MSG_CODE_OEM_UPDATE_FCOE_CVID 0x3c000000 1276 #define DRV_MSG_CODE_OEM_UPDATE_FCOE_FABRIC_NAME 0x3d000000 1277 #define DRV_MSG_CODE_OEM_UPDATE_BOOT_CFG 0x3e000000 1278 #define DRV_MSG_CODE_OEM_RESET_TO_DEFAULT 0x3f000000 1279 #define DRV_MSG_CODE_OV_GET_CURR_CFG 0x40000000 1280 #define DRV_MSG_CODE_GET_OEM_UPDATES 0x41000000 1281 /* params [31:8] - reserved, [7:0] - bitmap */ 1282 #define DRV_MSG_CODE_GET_PPFID_BITMAP 0x43000000 1283 1284 /* Param: [0:15] Option ID, [16] - All, [17] - Init, [18] - Commit, 1285 * [19] - Free 1286 */ 1287 #define DRV_MSG_CODE_GET_NVM_CFG_OPTION 0x003e0000 1288 /* Param: [0:15] Option ID, [17] - Init, [18] , [19] - Free */ 1289 #define DRV_MSG_CODE_SET_NVM_CFG_OPTION 0x003f0000 1290 /*deprecated don't use*/ 1291 #define DRV_MSG_CODE_INITIATE_FLR_DEPRECATED 0x02000000 1292 #define DRV_MSG_CODE_INITIATE_PF_FLR 0x02010000 1293 #define DRV_MSG_CODE_INITIATE_VF_FLR 0x02020000 1294 #define DRV_MSG_CODE_VF_DISABLED_DONE 0xc0000000 1295 #define DRV_MSG_CODE_CFG_VF_MSIX 0xc0010000 1296 #define DRV_MSG_CODE_CFG_PF_VFS_MSIX 0xc0020000 1297 /* Param is either DRV_MB_PARAM_NVM_PUT_FILE_BEGIN_MFW/IMAGE */ 1298 #define DRV_MSG_CODE_NVM_PUT_FILE_BEGIN 0x00010000 1299 /* Param should be set to the transaction size (up to 64 bytes) */ 1300 #define DRV_MSG_CODE_NVM_PUT_FILE_DATA 0x00020000 1301 /* MFW will place the file offset and len in file_att struct */ 1302 #define DRV_MSG_CODE_NVM_GET_FILE_ATT 0x00030000 1303 /* Read 32bytes of nvram data. Param is [0:23] ??? Offset [24:31] - 1304 * ??? Len in Bytes 1305 */ 1306 #define DRV_MSG_CODE_NVM_READ_NVRAM 0x00050000 1307 /* Writes up to 32Bytes to nvram. Param is [0:23] ??? Offset [24:31] 1308 * ??? Len in Bytes. In case this address is in the range of secured file in 1309 * secured mode, the operation will fail 1310 */ 1311 #define DRV_MSG_CODE_NVM_WRITE_NVRAM 0x00060000 1312 /* Delete a file from nvram. Param is image_type. */ 1313 #define DRV_MSG_CODE_NVM_DEL_FILE 0x00080000 1314 /* Reset MCP when no NVM operation is going on, and no drivers are loaded. 1315 * In case operation succeed, MCP will not ack back. 1316 */ 1317 #define DRV_MSG_CODE_MCP_RESET 0x00090000 1318 /* Temporary command to set secure mode, where the param is 0 (None secure) / 1319 * 1 (Secure) / 2 (Full-Secure) 1320 */ 1321 #define DRV_MSG_CODE_SET_SECURE_MODE 0x000a0000 1322 /* Param: [0:15] - Address, [16:18] - lane# (0/1/2/3 - for single lane, 1323 * 4/5 - for dual lanes, 6 - for all lanes, [28] - PMD reg, [29] - select port, 1324 * [30:31] - port 1325 */ 1326 #define DRV_MSG_CODE_PHY_RAW_READ 0x000b0000 1327 /* Param: [0:15] - Address, [16:18] - lane# (0/1/2/3 - for single lane, 1328 * 4/5 - for dual lanes, 6 - for all lanes, [28] - PMD reg, [29] - select port, 1329 * [30:31] - port 1330 */ 1331 #define DRV_MSG_CODE_PHY_RAW_WRITE 0x000c0000 1332 /* Param: [0:15] - Address, [30:31] - port */ 1333 #define DRV_MSG_CODE_PHY_CORE_READ 0x000d0000 1334 /* Param: [0:15] - Address, [30:31] - port */ 1335 #define DRV_MSG_CODE_PHY_CORE_WRITE 0x000e0000 1336 /* Param: [0:3] - version, [4:15] - name (null terminated) */ 1337 #define DRV_MSG_CODE_SET_VERSION 0x000f0000 1338 #define DRV_MSG_CODE_MCP_RESET_FORCE 0x000f04ce 1339 /* Halts the MCP. To resume MCP, user will need to use 1340 * MCP_REG_CPU_STATE/MCP_REG_CPU_MODE registers. 1341 */ 1342 #define DRV_MSG_CODE_MCP_HALT 0x00100000 1343 /* Set virtual mac address, params [31:6] - reserved, [5:4] - type, 1344 * [3:0] - func, drv_data[7:0] - MAC/WWNN/WWPN 1345 */ 1346 #define DRV_MSG_CODE_SET_VMAC 0x00110000 1347 /* Set virtual mac address, params [31:6] - reserved, [5:4] - type, 1348 * [3:0] - func, drv_data[7:0] - MAC/WWNN/WWPN 1349 */ 1350 #define DRV_MSG_CODE_GET_VMAC 0x00120000 1351 #define DRV_MSG_CODE_VMAC_TYPE_OFFSET 4 1352 #define DRV_MSG_CODE_VMAC_TYPE_MASK 0x30 1353 #define DRV_MSG_CODE_VMAC_TYPE_MAC 1 1354 #define DRV_MSG_CODE_VMAC_TYPE_WWNN 2 1355 #define DRV_MSG_CODE_VMAC_TYPE_WWPN 3 1356 /* Get statistics from pf, params [31:4] - reserved, [3:0] - stats type */ 1357 #define DRV_MSG_CODE_GET_STATS 0x00130000 1358 #define DRV_MSG_CODE_STATS_TYPE_LAN 1 1359 #define DRV_MSG_CODE_STATS_TYPE_FCOE 2 1360 #define DRV_MSG_CODE_STATS_TYPE_ISCSI 3 1361 #define DRV_MSG_CODE_STATS_TYPE_RDMA 4 1362 /* Host shall provide buffer and size for MFW */ 1363 #define DRV_MSG_CODE_PMD_DIAG_DUMP 0x00140000 1364 /* Host shall provide buffer and size for MFW */ 1365 #define DRV_MSG_CODE_PMD_DIAG_EYE 0x00150000 1366 /* Param: [0:1] - Port, [2:7] - read size, [8:15] - I2C address, 1367 * [16:31] - offset 1368 */ 1369 #define DRV_MSG_CODE_TRANSCEIVER_READ 0x00160000 1370 /* Param: [0:1] - Port, [2:7] - write size, [8:15] - I2C address, 1371 * [16:31] - offset 1372 */ 1373 #define DRV_MSG_CODE_TRANSCEIVER_WRITE 0x00170000 1374 /* indicate OCBB related information */ 1375 #define DRV_MSG_CODE_OCBB_DATA 0x00180000 1376 /* Set function BW, params[15:8] - min, params[7:0] - max */ 1377 #define DRV_MSG_CODE_SET_BW 0x00190000 1378 #define BW_MAX_MASK 0x000000ff 1379 #define BW_MAX_OFFSET 0 1380 #define BW_MIN_MASK 0x0000ff00 1381 #define BW_MIN_OFFSET 8 1382 1383 /* When param is set to 1, all parities will be masked(disabled). When params 1384 * are set to 0, parities will be unmasked again. 1385 */ 1386 #define DRV_MSG_CODE_MASK_PARITIES 0x001a0000 1387 /* param[0] - Simulate fan failure, param[1] - simulate over temp. */ 1388 #define DRV_MSG_CODE_INDUCE_FAILURE 0x001b0000 1389 #define DRV_MSG_FAN_FAILURE_TYPE (1 << 0) 1390 #define DRV_MSG_TEMPERATURE_FAILURE_TYPE (1 << 1) 1391 /* Param: [0:15] - gpio number */ 1392 #define DRV_MSG_CODE_GPIO_READ 0x001c0000 1393 /* Param: [0:15] - gpio number, [16:31] - gpio value */ 1394 #define DRV_MSG_CODE_GPIO_WRITE 0x001d0000 1395 /* Param: [0:7] - test enum, [8:15] - image index, [16:31] - reserved */ 1396 #define DRV_MSG_CODE_BIST_TEST 0x001e0000 1397 #define DRV_MSG_CODE_GET_TEMPERATURE 0x001f0000 1398 1399 /* Set LED mode params :0 operational, 1 LED turn ON, 2 LED turn OFF */ 1400 #define DRV_MSG_CODE_SET_LED_MODE 0x00200000 1401 /* drv_data[7:0] - EPOC in seconds, drv_data[15:8] - 1402 * driver version (MAJ MIN BUILD SUB) 1403 */ 1404 #define DRV_MSG_CODE_TIMESTAMP 0x00210000 1405 /* This is an empty mailbox just return OK*/ 1406 #define DRV_MSG_CODE_EMPTY_MB 0x00220000 1407 1408 /* Param[0:4] - resource number (0-31), Param[5:7] - opcode, 1409 * param[15:8] - age 1410 */ 1411 #define DRV_MSG_CODE_RESOURCE_CMD 0x00230000 1412 1413 #define RESOURCE_CMD_REQ_RESC_MASK 0x0000001F 1414 #define RESOURCE_CMD_REQ_RESC_OFFSET 0 1415 #define RESOURCE_CMD_REQ_OPCODE_MASK 0x000000E0 1416 #define RESOURCE_CMD_REQ_OPCODE_OFFSET 5 1417 /* request resource ownership with default aging */ 1418 #define RESOURCE_OPCODE_REQ 1 1419 /* request resource ownership without aging */ 1420 #define RESOURCE_OPCODE_REQ_WO_AGING 2 1421 /* request resource ownership with specific aging timer (in seconds) */ 1422 #define RESOURCE_OPCODE_REQ_W_AGING 3 1423 #define RESOURCE_OPCODE_RELEASE 4 /* release resource */ 1424 /* force resource release */ 1425 #define RESOURCE_OPCODE_FORCE_RELEASE 5 1426 #define RESOURCE_CMD_REQ_AGE_MASK 0x0000FF00 1427 #define RESOURCE_CMD_REQ_AGE_OFFSET 8 1428 1429 #define RESOURCE_CMD_RSP_OWNER_MASK 0x000000FF 1430 #define RESOURCE_CMD_RSP_OWNER_OFFSET 0 1431 #define RESOURCE_CMD_RSP_OPCODE_MASK 0x00000700 1432 #define RESOURCE_CMD_RSP_OPCODE_OFFSET 8 1433 /* resource is free and granted to requester */ 1434 #define RESOURCE_OPCODE_GNT 1 1435 /* resource is busy, param[7:0] indicates owner as follow 0-15 = PF0-15, 1436 * 16 = MFW, 17 = diag over serial 1437 */ 1438 #define RESOURCE_OPCODE_BUSY 2 1439 /* indicate release request was acknowledged */ 1440 #define RESOURCE_OPCODE_RELEASED 3 1441 /* indicate release request was previously received by other owner */ 1442 #define RESOURCE_OPCODE_RELEASED_PREVIOUS 4 1443 /* indicate wrong owner during release */ 1444 #define RESOURCE_OPCODE_WRONG_OWNER 5 1445 #define RESOURCE_OPCODE_UNKNOWN_CMD 255 1446 1447 /* dedicate resource 0 for dump */ 1448 #define RESOURCE_DUMP 0 1449 1450 #define DRV_MSG_CODE_GET_MBA_VERSION 0x00240000 /* Get MBA version */ 1451 /* Send crash dump commands with param[3:0] - opcode */ 1452 #define DRV_MSG_CODE_MDUMP_CMD 0x00250000 1453 #define MDUMP_DRV_PARAM_OPCODE_MASK 0x0000000f 1454 /* acknowledge reception of error indication */ 1455 #define DRV_MSG_CODE_MDUMP_ACK 0x01 1456 /* set epoc and personality as follow: drv_data[3:0] - epoch, 1457 * drv_data[7:4] - personality 1458 */ 1459 #define DRV_MSG_CODE_MDUMP_SET_VALUES 0x02 1460 /* trigger crash dump procedure */ 1461 #define DRV_MSG_CODE_MDUMP_TRIGGER 0x03 1462 /* Request valid logs and config words */ 1463 #define DRV_MSG_CODE_MDUMP_GET_CONFIG 0x04 1464 /* Set triggers mask. drv_mb_param should indicate (bitwise) which 1465 * trigger enabled 1466 */ 1467 #define DRV_MSG_CODE_MDUMP_SET_ENABLE 0x05 1468 /* Clear all logs */ 1469 #define DRV_MSG_CODE_MDUMP_CLEAR_LOGS 0x06 1470 #define DRV_MSG_CODE_MDUMP_GET_RETAIN 0x07 /* Get retained data */ 1471 #define DRV_MSG_CODE_MDUMP_CLR_RETAIN 0x08 /* Clear retain data */ 1472 #define DRV_MSG_CODE_MEM_ECC_EVENTS 0x00260000 /* Param: None */ 1473 /* Param: [0:15] - gpio number */ 1474 #define DRV_MSG_CODE_GPIO_INFO 0x00270000 1475 /* Value will be placed in union */ 1476 #define DRV_MSG_CODE_EXT_PHY_READ 0x00280000 1477 /* Value should be placed in union */ 1478 #define DRV_MSG_CODE_EXT_PHY_WRITE 0x00290000 1479 #define DRV_MB_PARAM_ADDR_OFFSET 0 1480 #define DRV_MB_PARAM_ADDR_MASK 0x0000FFFF 1481 #define DRV_MB_PARAM_DEVAD_OFFSET 16 1482 #define DRV_MB_PARAM_DEVAD_MASK 0x001F0000 1483 #define DRV_MB_PARAM_PORT_OFFSET 21 1484 #define DRV_MB_PARAM_PORT_MASK 0x00600000 1485 #define DRV_MSG_CODE_EXT_PHY_FW_UPGRADE 0x002a0000 1486 1487 #define DRV_MSG_CODE_GET_TLV_DONE 0x002f0000 /* Param: None */ 1488 /* Param: Set DRV_MB_PARAM_FEATURE_SUPPORT_* */ 1489 #define DRV_MSG_CODE_FEATURE_SUPPORT 0x00300000 1490 /* return FW_MB_PARAM_FEATURE_SUPPORT_* */ 1491 #define DRV_MSG_CODE_GET_MFW_FEATURE_SUPPORT 0x00310000 1492 #define DRV_MSG_CODE_READ_WOL_REG 0X00320000 1493 #define DRV_MSG_CODE_WRITE_WOL_REG 0X00330000 1494 #define DRV_MSG_CODE_GET_WOL_BUFFER 0X00340000 1495 /* Param: [0:23] Attribute key, [24:31] Attribute sub command */ 1496 #define DRV_MSG_CODE_ATTRIBUTE 0x00350000 1497 1498 /* Param: Password len. Union: Plain Password */ 1499 #define DRV_MSG_CODE_ENCRYPT_PASSWORD 0x00360000 1500 #define DRV_MSG_CODE_GET_ENGINE_CONFIG 0x00370000 /* Param: None */ 1501 1502 #define DRV_MSG_SEQ_NUMBER_MASK 0x0000ffff 1503 1504 u32 drv_mb_param; 1505 /* UNLOAD_REQ params */ 1506 #define DRV_MB_PARAM_UNLOAD_WOL_UNKNOWN 0x00000000 1507 #define DRV_MB_PARAM_UNLOAD_WOL_MCP 0x00000001 1508 #define DRV_MB_PARAM_UNLOAD_WOL_DISABLED 0x00000002 1509 #define DRV_MB_PARAM_UNLOAD_WOL_ENABLED 0x00000003 1510 1511 /* UNLOAD_DONE_params */ 1512 #define DRV_MB_PARAM_UNLOAD_NON_D3_POWER 0x00000001 1513 1514 /* INIT_PHY params */ 1515 #define DRV_MB_PARAM_INIT_PHY_FORCE 0x00000001 1516 #define DRV_MB_PARAM_INIT_PHY_DONT_CARE 0x00000002 1517 1518 /* LLDP / DCBX params*/ 1519 /* To be used with SET_LLDP command */ 1520 #define DRV_MB_PARAM_LLDP_SEND_MASK 0x00000001 1521 #define DRV_MB_PARAM_LLDP_SEND_OFFSET 0 1522 /* To be used with SET_LLDP and REGISTER_LLDP_TLVS_RX commands */ 1523 #define DRV_MB_PARAM_LLDP_AGENT_MASK 0x00000006 1524 #define DRV_MB_PARAM_LLDP_AGENT_OFFSET 1 1525 /* To be used with REGISTER_LLDP_TLVS_RX command */ 1526 #define DRV_MB_PARAM_LLDP_TLV_RX_VALID_MASK 0x00000001 1527 #define DRV_MB_PARAM_LLDP_TLV_RX_VALID_OFFSET 0 1528 #define DRV_MB_PARAM_LLDP_TLV_RX_TYPE_MASK 0x000007f0 1529 #define DRV_MB_PARAM_LLDP_TLV_RX_TYPE_OFFSET 4 1530 /* To be used with SET_DCBX command */ 1531 #define DRV_MB_PARAM_DCBX_NOTIFY_MASK 0x00000008 1532 #define DRV_MB_PARAM_DCBX_NOTIFY_OFFSET 3 1533 1534 #define DRV_MB_PARAM_NIG_DRAIN_PERIOD_MS_MASK 0x000000FF 1535 #define DRV_MB_PARAM_NIG_DRAIN_PERIOD_MS_OFFSET 0 1536 1537 #define DRV_MB_PARAM_NVM_PUT_FILE_BEGIN_MFW 0x1 1538 #define DRV_MB_PARAM_NVM_PUT_FILE_BEGIN_IMAGE 0x2 1539 1540 #define DRV_MB_PARAM_NVM_OFFSET_OFFSET 0 1541 #define DRV_MB_PARAM_NVM_OFFSET_MASK 0x00FFFFFF 1542 #define DRV_MB_PARAM_NVM_LEN_OFFSET 24 1543 #define DRV_MB_PARAM_NVM_LEN_MASK 0xFF000000 1544 1545 #define DRV_MB_PARAM_PHY_ADDR_OFFSET 0 1546 #define DRV_MB_PARAM_PHY_ADDR_MASK 0x1FF0FFFF 1547 #define DRV_MB_PARAM_PHY_LANE_OFFSET 16 1548 #define DRV_MB_PARAM_PHY_LANE_MASK 0x000F0000 1549 #define DRV_MB_PARAM_PHY_SELECT_PORT_OFFSET 29 1550 #define DRV_MB_PARAM_PHY_SELECT_PORT_MASK 0x20000000 1551 #define DRV_MB_PARAM_PHY_PORT_OFFSET 30 1552 #define DRV_MB_PARAM_PHY_PORT_MASK 0xc0000000 1553 1554 #define DRV_MB_PARAM_PHYMOD_LANE_OFFSET 0 1555 #define DRV_MB_PARAM_PHYMOD_LANE_MASK 0x000000FF 1556 #define DRV_MB_PARAM_PHYMOD_SIZE_OFFSET 8 1557 #define DRV_MB_PARAM_PHYMOD_SIZE_MASK 0x000FFF00 1558 /* configure vf MSIX params BB */ 1559 #define DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_OFFSET 0 1560 #define DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_MASK 0x000000FF 1561 #define DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_OFFSET 8 1562 #define DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_MASK 0x0000FF00 1563 /* configure vf MSIX for PF params AH*/ 1564 #define DRV_MB_PARAM_CFG_PF_VFS_MSIX_SB_NUM_OFFSET 0 1565 #define DRV_MB_PARAM_CFG_PF_VFS_MSIX_SB_NUM_MASK 0x000000FF 1566 1567 /* OneView configuration parametres */ 1568 #define DRV_MB_PARAM_OV_CURR_CFG_OFFSET 0 1569 #define DRV_MB_PARAM_OV_CURR_CFG_MASK 0x0000000F 1570 #define DRV_MB_PARAM_OV_CURR_CFG_NONE 0 1571 #define DRV_MB_PARAM_OV_CURR_CFG_OS 1 1572 #define DRV_MB_PARAM_OV_CURR_CFG_VENDOR_SPEC 2 1573 #define DRV_MB_PARAM_OV_CURR_CFG_OTHER 3 1574 #define DRV_MB_PARAM_OV_CURR_CFG_VC_CLP 4 1575 #define DRV_MB_PARAM_OV_CURR_CFG_CNU 5 1576 #define DRV_MB_PARAM_OV_CURR_CFG_DCI 6 1577 #define DRV_MB_PARAM_OV_CURR_CFG_HII 7 1578 1579 #define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_OFFSET 0 1580 #define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_MASK 0x000000FF 1581 #define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_NONE (1 << 0) 1582 #define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_ISCSI_IP_ACQUIRED (1 << 1) 1583 #define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_FCOE_FABRIC_LOGIN_SUCCESS (1 << 1) 1584 #define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_TRARGET_FOUND (1 << 2) 1585 #define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_ISCSI_CHAP_SUCCESS (1 << 3) 1586 #define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_FCOE_LUN_FOUND (1 << 3) 1587 #define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_LOGGED_INTO_TGT (1 << 4) 1588 #define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_IMG_DOWNLOADED (1 << 5) 1589 #define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_OS_HANDOFF (1 << 6) 1590 #define DRV_MB_PARAM_OV_UPDATE_BOOT_COMPLETED 0 1591 1592 #define DRV_MB_PARAM_OV_PCI_BUS_NUM_OFFSET 0 1593 #define DRV_MB_PARAM_OV_PCI_BUS_NUM_MASK 0x000000FF 1594 1595 #define DRV_MB_PARAM_OV_STORM_FW_VER_OFFSET 0 1596 #define DRV_MB_PARAM_OV_STORM_FW_VER_MASK 0xFFFFFFFF 1597 #define DRV_MB_PARAM_OV_STORM_FW_VER_MAJOR_MASK 0xFF000000 1598 #define DRV_MB_PARAM_OV_STORM_FW_VER_MINOR_MASK 0x00FF0000 1599 #define DRV_MB_PARAM_OV_STORM_FW_VER_BUILD_MASK 0x0000FF00 1600 #define DRV_MB_PARAM_OV_STORM_FW_VER_DROP_MASK 0x000000FF 1601 1602 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_OFFSET 0 1603 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_MASK 0xF 1604 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_UNKNOWN 0x1 1605 /* Not Installed*/ 1606 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_NOT_LOADED 0x2 1607 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_LOADING 0x3 1608 /* installed but disabled by user/admin/OS */ 1609 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_DISABLED 0x4 1610 /* installed and active */ 1611 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_ACTIVE 0x5 1612 1613 #define DRV_MB_PARAM_OV_MTU_SIZE_OFFSET 0 1614 #define DRV_MB_PARAM_OV_MTU_SIZE_MASK 0xFFFFFFFF 1615 1616 #define DRV_MB_PARAM_ESWITCH_MODE_MASK (DRV_MB_PARAM_ESWITCH_MODE_NONE | \ 1617 DRV_MB_PARAM_ESWITCH_MODE_VEB | \ 1618 DRV_MB_PARAM_ESWITCH_MODE_VEPA) 1619 #define DRV_MB_PARAM_ESWITCH_MODE_NONE 0x0 1620 #define DRV_MB_PARAM_ESWITCH_MODE_VEB 0x1 1621 #define DRV_MB_PARAM_ESWITCH_MODE_VEPA 0x2 1622 1623 #define DRV_MB_PARAM_DUMMY_OEM_UPDATES_MASK 0x1 1624 #define DRV_MB_PARAM_DUMMY_OEM_UPDATES_OFFSET 0 1625 1626 #define DRV_MB_PARAM_SET_LED_MODE_OPER 0x0 1627 #define DRV_MB_PARAM_SET_LED_MODE_ON 0x1 1628 #define DRV_MB_PARAM_SET_LED_MODE_OFF 0x2 1629 #define DRV_MB_PARAM_SET_LED1_MODE_ON 0x3 1630 #define DRV_MB_PARAM_SET_LED2_MODE_ON 0x4 1631 #define DRV_MB_PARAM_SET_ACT_LED_MODE_ON 0x6 1632 1633 #define DRV_MB_PARAM_TRANSCEIVER_PORT_OFFSET 0 1634 #define DRV_MB_PARAM_TRANSCEIVER_PORT_MASK 0x00000003 1635 #define DRV_MB_PARAM_TRANSCEIVER_SIZE_OFFSET 2 1636 #define DRV_MB_PARAM_TRANSCEIVER_SIZE_MASK 0x000000FC 1637 #define DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_OFFSET 8 1638 #define DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_MASK 0x0000FF00 1639 #define DRV_MB_PARAM_TRANSCEIVER_OFFSET_OFFSET 16 1640 #define DRV_MB_PARAM_TRANSCEIVER_OFFSET_MASK 0xFFFF0000 1641 1642 #define DRV_MB_PARAM_GPIO_NUMBER_OFFSET 0 1643 #define DRV_MB_PARAM_GPIO_NUMBER_MASK 0x0000FFFF 1644 #define DRV_MB_PARAM_GPIO_VALUE_OFFSET 16 1645 #define DRV_MB_PARAM_GPIO_VALUE_MASK 0xFFFF0000 1646 #define DRV_MB_PARAM_GPIO_DIRECTION_OFFSET 16 1647 #define DRV_MB_PARAM_GPIO_DIRECTION_MASK 0x00FF0000 1648 #define DRV_MB_PARAM_GPIO_CTRL_OFFSET 24 1649 #define DRV_MB_PARAM_GPIO_CTRL_MASK 0xFF000000 1650 1651 /* Resource Allocation params - Driver version support*/ 1652 #define DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_MASK 0xFFFF0000 1653 #define DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_OFFSET 16 1654 #define DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_MASK 0x0000FFFF 1655 #define DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_OFFSET 0 1656 1657 #define DRV_MB_PARAM_BIST_UNKNOWN_TEST 0 1658 #define DRV_MB_PARAM_BIST_REGISTER_TEST 1 1659 #define DRV_MB_PARAM_BIST_CLOCK_TEST 2 1660 #define DRV_MB_PARAM_BIST_NVM_TEST_NUM_IMAGES 3 1661 #define DRV_MB_PARAM_BIST_NVM_TEST_IMAGE_BY_INDEX 4 1662 1663 #define DRV_MB_PARAM_BIST_RC_UNKNOWN 0 1664 #define DRV_MB_PARAM_BIST_RC_PASSED 1 1665 #define DRV_MB_PARAM_BIST_RC_FAILED 2 1666 #define DRV_MB_PARAM_BIST_RC_INVALID_PARAMETER 3 1667 1668 #define DRV_MB_PARAM_BIST_TEST_INDEX_OFFSET 0 1669 #define DRV_MB_PARAM_BIST_TEST_INDEX_MASK 0x000000FF 1670 #define DRV_MB_PARAM_BIST_TEST_IMAGE_INDEX_OFFSET 8 1671 #define DRV_MB_PARAM_BIST_TEST_IMAGE_INDEX_MASK 0x0000FF00 1672 1673 #define DRV_MB_PARAM_FEATURE_SUPPORT_PORT_MASK 0x0000FFFF 1674 #define DRV_MB_PARAM_FEATURE_SUPPORT_PORT_OFFSET 0 1675 /* driver supports SmartLinQ parameter */ 1676 #define DRV_MB_PARAM_FEATURE_SUPPORT_PORT_SMARTLINQ 0x00000001 1677 /* driver supports EEE parameter */ 1678 #define DRV_MB_PARAM_FEATURE_SUPPORT_PORT_EEE 0x00000002 1679 #define DRV_MB_PARAM_FEATURE_SUPPORT_FUNC_MASK 0xFFFF0000 1680 #define DRV_MB_PARAM_FEATURE_SUPPORT_FUNC_OFFSET 16 1681 /* driver supports virtual link parameter */ 1682 #define DRV_MB_PARAM_FEATURE_SUPPORT_FUNC_VLINK 0x00010000 1683 /* Driver attributes params */ 1684 #define DRV_MB_PARAM_ATTRIBUTE_KEY_OFFSET 0 1685 #define DRV_MB_PARAM_ATTRIBUTE_KEY_MASK 0x00FFFFFF 1686 #define DRV_MB_PARAM_ATTRIBUTE_CMD_OFFSET 24 1687 #define DRV_MB_PARAM_ATTRIBUTE_CMD_MASK 0xFF000000 1688 1689 #define DRV_MB_PARAM_NVM_CFG_OPTION_ID_OFFSET 0 1690 /* Option# */ 1691 #define DRV_MB_PARAM_NVM_CFG_OPTION_ID_MASK 0x0000FFFF 1692 #define DRV_MB_PARAM_NVM_CFG_OPTION_ALL_OFFSET 16 1693 /* (Only for Set) Applies option<92>s value to all entities (port/func) 1694 * depending on the option type 1695 */ 1696 #define DRV_MB_PARAM_NVM_CFG_OPTION_ALL_MASK 0x00010000 1697 #define DRV_MB_PARAM_NVM_CFG_OPTION_INIT_OFFSET 17 1698 /* When set, and state is IDLE, MFW will allocate resources and load 1699 * configuration from NVM 1700 */ 1701 #define DRV_MB_PARAM_NVM_CFG_OPTION_INIT_MASK 0x00020000 1702 #define DRV_MB_PARAM_NVM_CFG_OPTION_COMMIT_OFFSET 18 1703 /* (Only for Set) - When set submit changed nvm_cfg1 to flash */ 1704 #define DRV_MB_PARAM_NVM_CFG_OPTION_COMMIT_MASK 0x00040000 1705 #define DRV_MB_PARAM_NVM_CFG_OPTION_FREE_OFFSET 19 1706 /* Free - When set, free allocated resources, and return to IDLE state. */ 1707 #define DRV_MB_PARAM_NVM_CFG_OPTION_FREE_MASK 0x00080000 1708 #define SINGLE_NVM_WR_OP(optionId) \ 1709 ((((optionId) & DRV_MB_PARAM_NVM_CFG_OPTION_ID_MASK) << \ 1710 DRV_MB_PARAM_NVM_CFG_OPTION_ID_OFFSET) | \ 1711 (DRV_MB_PARAM_NVM_CFG_OPTION_INIT_MASK | \ 1712 DRV_MB_PARAM_NVM_CFG_OPTION_COMMIT_MASK | \ 1713 DRV_MB_PARAM_NVM_CFG_OPTION_FREE_MASK)) 1714 u32 fw_mb_header; 1715 #define FW_MSG_CODE_UNSUPPORTED 0x00000000 1716 #define FW_MSG_CODE_DRV_LOAD_ENGINE 0x10100000 1717 #define FW_MSG_CODE_DRV_LOAD_PORT 0x10110000 1718 #define FW_MSG_CODE_DRV_LOAD_FUNCTION 0x10120000 1719 #define FW_MSG_CODE_DRV_LOAD_REFUSED_PDA 0x10200000 1720 #define FW_MSG_CODE_DRV_LOAD_REFUSED_HSI_1 0x10210000 1721 #define FW_MSG_CODE_DRV_LOAD_REFUSED_DIAG 0x10220000 1722 #define FW_MSG_CODE_DRV_LOAD_REFUSED_HSI 0x10230000 1723 #define FW_MSG_CODE_DRV_LOAD_REFUSED_REQUIRES_FORCE 0x10300000 1724 #define FW_MSG_CODE_DRV_LOAD_REFUSED_REJECT 0x10310000 1725 #define FW_MSG_CODE_DRV_LOAD_DONE 0x11100000 1726 #define FW_MSG_CODE_DRV_UNLOAD_ENGINE 0x20110000 1727 #define FW_MSG_CODE_DRV_UNLOAD_PORT 0x20120000 1728 #define FW_MSG_CODE_DRV_UNLOAD_FUNCTION 0x20130000 1729 #define FW_MSG_CODE_DRV_UNLOAD_DONE 0x21100000 1730 #define FW_MSG_CODE_INIT_PHY_DONE 0x21200000 1731 #define FW_MSG_CODE_INIT_PHY_ERR_INVALID_ARGS 0x21300000 1732 #define FW_MSG_CODE_LINK_RESET_DONE 0x23000000 1733 #define FW_MSG_CODE_SET_LLDP_DONE 0x24000000 1734 #define FW_MSG_CODE_SET_LLDP_UNSUPPORTED_AGENT 0x24010000 1735 #define FW_MSG_CODE_REGISTER_LLDP_TLVS_RX_DONE 0x24100000 1736 #define FW_MSG_CODE_SET_DCBX_DONE 0x25000000 1737 #define FW_MSG_CODE_UPDATE_CURR_CFG_DONE 0x26000000 1738 #define FW_MSG_CODE_UPDATE_BUS_NUM_DONE 0x27000000 1739 #define FW_MSG_CODE_UPDATE_BOOT_PROGRESS_DONE 0x28000000 1740 #define FW_MSG_CODE_UPDATE_STORM_FW_VER_DONE 0x29000000 1741 #define FW_MSG_CODE_UPDATE_DRIVER_STATE_DONE 0x31000000 1742 #define FW_MSG_CODE_DRV_MSG_CODE_BW_UPDATE_DONE 0x32000000 1743 #define FW_MSG_CODE_DRV_MSG_CODE_MTU_SIZE_DONE 0x33000000 1744 #define FW_MSG_CODE_RESOURCE_ALLOC_OK 0x34000000 1745 #define FW_MSG_CODE_RESOURCE_ALLOC_UNKNOWN 0x35000000 1746 #define FW_MSG_CODE_RESOURCE_ALLOC_DEPRECATED 0x36000000 1747 #define FW_MSG_CODE_RESOURCE_ALLOC_GEN_ERR 0x37000000 1748 #define FW_MSG_CODE_GET_OEM_UPDATES_DONE 0x41000000 1749 1750 #define FW_MSG_CODE_NIG_DRAIN_DONE 0x30000000 1751 #define FW_MSG_CODE_VF_DISABLED_DONE 0xb0000000 1752 #define FW_MSG_CODE_DRV_CFG_VF_MSIX_DONE 0xb0010000 1753 #define FW_MSG_CODE_INITIATE_VF_FLR_OK 0xb0030000 1754 #define FW_MSG_CODE_ERR_RESOURCE_TEMPORARY_UNAVAILABLE 0x008b0000 1755 #define FW_MSG_CODE_ERR_RESOURCE_ALREADY_ALLOCATED 0x008c0000 1756 #define FW_MSG_CODE_ERR_RESOURCE_NOT_ALLOCATED 0x008d0000 1757 #define FW_MSG_CODE_ERR_NON_USER_OPTION 0x008e0000 1758 #define FW_MSG_CODE_ERR_UNKNOWN_OPTION 0x008f0000 1759 #define FW_MSG_CODE_WAIT 0x00900000 1760 #define FW_MSG_CODE_FLR_ACK 0x02000000 1761 #define FW_MSG_CODE_FLR_NACK 0x02100000 1762 #define FW_MSG_CODE_SET_DRIVER_DONE 0x02200000 1763 #define FW_MSG_CODE_SET_VMAC_SUCCESS 0x02300000 1764 #define FW_MSG_CODE_SET_VMAC_FAIL 0x02400000 1765 1766 #define FW_MSG_CODE_NVM_OK 0x00010000 1767 #define FW_MSG_CODE_NVM_INVALID_MODE 0x00020000 1768 #define FW_MSG_CODE_NVM_PREV_CMD_WAS_NOT_FINISHED 0x00030000 1769 #define FW_MSG_CODE_NVM_FAILED_TO_ALLOCATE_PAGE 0x00040000 1770 #define FW_MSG_CODE_NVM_INVALID_DIR_FOUND 0x00050000 1771 #define FW_MSG_CODE_NVM_PAGE_NOT_FOUND 0x00060000 1772 #define FW_MSG_CODE_NVM_FAILED_PARSING_BNDLE_HEADER 0x00070000 1773 #define FW_MSG_CODE_NVM_FAILED_PARSING_IMAGE_HEADER 0x00080000 1774 #define FW_MSG_CODE_NVM_PARSING_OUT_OF_SYNC 0x00090000 1775 #define FW_MSG_CODE_NVM_FAILED_UPDATING_DIR 0x000a0000 1776 #define FW_MSG_CODE_NVM_FAILED_TO_FREE_PAGE 0x000b0000 1777 #define FW_MSG_CODE_NVM_FILE_NOT_FOUND 0x000c0000 1778 #define FW_MSG_CODE_NVM_OPERATION_FAILED 0x000d0000 1779 #define FW_MSG_CODE_NVM_FAILED_UNALIGNED 0x000e0000 1780 #define FW_MSG_CODE_NVM_BAD_OFFSET 0x000f0000 1781 #define FW_MSG_CODE_NVM_BAD_SIGNATURE 0x00100000 1782 #define FW_MSG_CODE_NVM_FILE_READ_ONLY 0x00200000 1783 #define FW_MSG_CODE_NVM_UNKNOWN_FILE 0x00300000 1784 #define FW_MSG_CODE_NVM_PUT_FILE_FINISH_OK 0x00400000 1785 /* MFW reject "mcp reset" command if one of the drivers is up */ 1786 #define FW_MSG_CODE_MCP_RESET_REJECT 0x00600000 1787 #define FW_MSG_CODE_NVM_FAILED_CALC_HASH 0x00310000 1788 #define FW_MSG_CODE_NVM_PUBLIC_KEY_MISSING 0x00320000 1789 #define FW_MSG_CODE_NVM_INVALID_PUBLIC_KEY 0x00330000 1790 1791 #define FW_MSG_CODE_PHY_OK 0x00110000 1792 #define FW_MSG_CODE_PHY_ERROR 0x00120000 1793 #define FW_MSG_CODE_SET_SECURE_MODE_ERROR 0x00130000 1794 #define FW_MSG_CODE_SET_SECURE_MODE_OK 0x00140000 1795 #define FW_MSG_MODE_PHY_PRIVILEGE_ERROR 0x00150000 1796 #define FW_MSG_CODE_OK 0x00160000 1797 #define FW_MSG_CODE_ERROR 0x00170000 1798 #define FW_MSG_CODE_LED_MODE_INVALID 0x00170000 1799 #define FW_MSG_CODE_PHY_DIAG_OK 0x00160000 1800 #define FW_MSG_CODE_PHY_DIAG_ERROR 0x00170000 1801 #define FW_MSG_CODE_INIT_HW_FAILED_TO_ALLOCATE_PAGE 0x00040000 1802 #define FW_MSG_CODE_INIT_HW_FAILED_BAD_STATE 0x00170000 1803 #define FW_MSG_CODE_INIT_HW_FAILED_TO_SET_WINDOW 0x000d0000 1804 #define FW_MSG_CODE_INIT_HW_FAILED_NO_IMAGE 0x000c0000 1805 #define FW_MSG_CODE_INIT_HW_FAILED_VERSION_MISMATCH 0x00100000 1806 #define FW_MSG_CODE_TRANSCEIVER_DIAG_OK 0x00160000 1807 #define FW_MSG_CODE_TRANSCEIVER_DIAG_ERROR 0x00170000 1808 #define FW_MSG_CODE_TRANSCEIVER_NOT_PRESENT 0x00020000 1809 #define FW_MSG_CODE_TRANSCEIVER_BAD_BUFFER_SIZE 0x000f0000 1810 #define FW_MSG_CODE_GPIO_OK 0x00160000 1811 #define FW_MSG_CODE_GPIO_DIRECTION_ERR 0x00170000 1812 #define FW_MSG_CODE_GPIO_CTRL_ERR 0x00020000 1813 #define FW_MSG_CODE_GPIO_INVALID 0x000f0000 1814 #define FW_MSG_CODE_GPIO_INVALID_VALUE 0x00050000 1815 #define FW_MSG_CODE_BIST_TEST_INVALID 0x000f0000 1816 #define FW_MSG_CODE_EXTPHY_INVALID_IMAGE_HEADER 0x00700000 1817 #define FW_MSG_CODE_EXTPHY_INVALID_PHY_TYPE 0x00710000 1818 #define FW_MSG_CODE_EXTPHY_OPERATION_FAILED 0x00720000 1819 #define FW_MSG_CODE_EXTPHY_NO_PHY_DETECTED 0x00730000 1820 #define FW_MSG_CODE_RECOVERY_MODE 0x00740000 1821 1822 /* mdump related response codes */ 1823 #define FW_MSG_CODE_MDUMP_NO_IMAGE_FOUND 0x00010000 1824 #define FW_MSG_CODE_MDUMP_ALLOC_FAILED 0x00020000 1825 #define FW_MSG_CODE_MDUMP_INVALID_CMD 0x00030000 1826 #define FW_MSG_CODE_MDUMP_IN_PROGRESS 0x00040000 1827 #define FW_MSG_CODE_MDUMP_WRITE_FAILED 0x00050000 1828 1829 1830 #define FW_MSG_CODE_DRV_CFG_PF_VFS_MSIX_DONE 0x00870000 1831 #define FW_MSG_CODE_DRV_CFG_PF_VFS_MSIX_BAD_ASIC 0x00880000 1832 1833 #define FW_MSG_CODE_WOL_READ_WRITE_OK 0x00820000 1834 #define FW_MSG_CODE_WOL_READ_WRITE_INVALID_VAL 0x00830000 1835 #define FW_MSG_CODE_WOL_READ_WRITE_INVALID_ADDR 0x00840000 1836 #define FW_MSG_CODE_WOL_READ_BUFFER_OK 0x00850000 1837 #define FW_MSG_CODE_WOL_READ_BUFFER_INVALID_VAL 0x00860000 1838 1839 #define FW_MSG_CODE_ATTRIBUTE_INVALID_KEY 0x00020000 1840 #define FW_MSG_CODE_ATTRIBUTE_INVALID_CMD 0x00030000 1841 1842 #define FW_MSG_SEQ_NUMBER_MASK 0x0000ffff 1843 #define FW_MSG_SEQ_NUMBER_OFFSET 0 1844 #define FW_MSG_CODE_MASK 0xffff0000 1845 #define FW_MSG_CODE_OFFSET 16 1846 u32 fw_mb_param; 1847 /* Resource Allocation params - MFW version support */ 1848 #define FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_MASK 0xFFFF0000 1849 #define FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_OFFSET 16 1850 #define FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_MASK 0x0000FFFF 1851 #define FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_OFFSET 0 1852 1853 /* get MFW feature support response */ 1854 /* MFW supports SmartLinQ */ 1855 #define FW_MB_PARAM_FEATURE_SUPPORT_SMARTLINQ 0x00000001 1856 /* MFW supports EEE */ 1857 #define FW_MB_PARAM_FEATURE_SUPPORT_EEE 0x00000002 1858 /* MFW supports DRV_LOAD Timeout */ 1859 #define FW_MB_PARAM_FEATURE_SUPPORT_DRV_LOAD_TO 0x00000004 1860 /* MFW support complete IGU cleanup upon FLR */ 1861 #define FW_MB_PARAM_FEATURE_SUPPORT_IGU_CLEANUP 0x00000080 1862 /* MFW supports virtual link */ 1863 #define FW_MB_PARAM_FEATURE_SUPPORT_VLINK 0x00010000 1864 1865 #define FW_MB_PARAM_LOAD_DONE_DID_EFUSE_ERROR (1 << 0) 1866 1867 #define FW_MB_PARAM_OEM_UPDATE_MASK 0xFF 1868 #define FW_MB_PARAM_OEM_UPDATE_OFFSET 0 1869 #define FW_MB_PARAM_OEM_UPDATE_BW 0x01 1870 #define FW_MB_PARAM_OEM_UPDATE_S_TAG 0x02 1871 #define FW_MB_PARAM_OEM_UPDATE_CFG 0x04 1872 1873 #define FW_MB_PARAM_ENG_CFG_FIR_AFFIN_VALID_MASK 0x00000001 1874 #define FW_MB_PARAM_ENG_CFG_FIR_AFFIN_VALID_OFFSET 0 1875 #define FW_MB_PARAM_ENG_CFG_FIR_AFFIN_VALUE_MASK 0x00000002 1876 #define FW_MB_PARAM_ENG_CFG_FIR_AFFIN_VALUE_OFFSET 1 1877 #define FW_MB_PARAM_ENG_CFG_L2_AFFIN_VALID_MASK 0x00000004 1878 #define FW_MB_PARAM_ENG_CFG_L2_AFFIN_VALID_OFFSET 2 1879 #define FW_MB_PARAM_ENG_CFG_L2_AFFIN_VALUE_MASK 0x00000008 1880 #define FW_MB_PARAM_ENG_CFG_L2_AFFIN_VALUE_OFFSET 3 1881 1882 #define FW_MB_PARAM_PPFID_BITMAP_MASK 0xFF 1883 #define FW_MB_PARAM_PPFID_BITMAP_OFFSET 0 1884 1885 u32 drv_pulse_mb; 1886 #define DRV_PULSE_SEQ_MASK 0x00007fff 1887 #define DRV_PULSE_SYSTEM_TIME_MASK 0xffff0000 1888 /* 1889 * The system time is in the format of 1890 * (year-2001)*12*32 + month*32 + day. 1891 */ 1892 #define DRV_PULSE_ALWAYS_ALIVE 0x00008000 1893 /* 1894 * Indicate to the firmware not to go into the 1895 * OS-absent when it is not getting driver pulse. 1896 * This is used for debugging as well for PXE(MBA). 1897 */ 1898 1899 u32 mcp_pulse_mb; 1900 #define MCP_PULSE_SEQ_MASK 0x00007fff 1901 #define MCP_PULSE_ALWAYS_ALIVE 0x00008000 1902 /* Indicates to the driver not to assert due to lack 1903 * of MCP response 1904 */ 1905 #define MCP_EVENT_MASK 0xffff0000 1906 #define MCP_EVENT_OTHER_DRIVER_RESET_REQ 0x00010000 1907 1908 /* The union data is used by the driver to pass parameters to the scratchpad. */ 1909 1910 union drv_union_data union_data; 1911 1912 }; 1913 1914 /* MFW - DRV MB */ 1915 /********************************************************************** 1916 * Description 1917 * Incremental Aggregative 1918 * 8-bit MFW counter per message 1919 * 8-bit ack-counter per message 1920 * Capabilities 1921 * Provides up to 256 aggregative message per type 1922 * Provides 4 message types in dword 1923 * Message type pointers to byte offset 1924 * Backward Compatibility by using sizeof for the counters. 1925 * No lock requires for 32bit messages 1926 * Limitations: 1927 * In case of messages greater than 32bit, a dedicated mechanism(e.g lock) 1928 * is required to prevent data corruption. 1929 **********************************************************************/ 1930 enum MFW_DRV_MSG_TYPE { 1931 MFW_DRV_MSG_LINK_CHANGE, 1932 MFW_DRV_MSG_FLR_FW_ACK_FAILED, 1933 MFW_DRV_MSG_VF_DISABLED, 1934 MFW_DRV_MSG_LLDP_DATA_UPDATED, 1935 MFW_DRV_MSG_DCBX_REMOTE_MIB_UPDATED, 1936 MFW_DRV_MSG_DCBX_OPERATIONAL_MIB_UPDATED, 1937 MFW_DRV_MSG_ERROR_RECOVERY, 1938 MFW_DRV_MSG_BW_UPDATE, 1939 MFW_DRV_MSG_S_TAG_UPDATE, 1940 MFW_DRV_MSG_GET_LAN_STATS, 1941 MFW_DRV_MSG_GET_FCOE_STATS, 1942 MFW_DRV_MSG_GET_ISCSI_STATS, 1943 MFW_DRV_MSG_GET_RDMA_STATS, 1944 MFW_DRV_MSG_FAILURE_DETECTED, 1945 MFW_DRV_MSG_TRANSCEIVER_STATE_CHANGE, 1946 MFW_DRV_MSG_CRITICAL_ERROR_OCCURRED, 1947 MFW_DRV_MSG_EEE_NEGOTIATION_COMPLETE, 1948 MFW_DRV_MSG_GET_TLV_REQ, 1949 MFW_DRV_MSG_OEM_CFG_UPDATE, 1950 MFW_DRV_MSG_LLDP_RECEIVED_TLVS_UPDATED, 1951 MFW_DRV_MSG_MAX 1952 }; 1953 1954 #define MFW_DRV_MSG_MAX_DWORDS(msgs) (((msgs - 1) >> 2) + 1) 1955 #define MFW_DRV_MSG_DWORD(msg_id) (msg_id >> 2) 1956 #define MFW_DRV_MSG_OFFSET(msg_id) ((msg_id & 0x3) << 3) 1957 #define MFW_DRV_MSG_MASK(msg_id) (0xff << MFW_DRV_MSG_OFFSET(msg_id)) 1958 1959 #ifdef BIG_ENDIAN /* Like MFW */ 1960 #define DRV_ACK_MSG(msg_p, msg_id) \ 1961 ((u8)((u8 *)msg_p)[msg_id]++;) 1962 #else 1963 #define DRV_ACK_MSG(msg_p, msg_id) \ 1964 ((u8)((u8 *)msg_p)[((msg_id & ~3) | ((~msg_id) & 3))]++;) 1965 #endif 1966 1967 #define MFW_DRV_UPDATE(shmem_func, msg_id) \ 1968 ((u8)((u8 *)(MFW_MB_P(shmem_func)->msg))[msg_id]++;) 1969 1970 struct public_mfw_mb { 1971 u32 sup_msgs; /* Assigend with MFW_DRV_MSG_MAX */ 1972 /* Incremented by the MFW */ 1973 u32 msg[MFW_DRV_MSG_MAX_DWORDS(MFW_DRV_MSG_MAX)]; 1974 /* Incremented by the driver */ 1975 u32 ack[MFW_DRV_MSG_MAX_DWORDS(MFW_DRV_MSG_MAX)]; 1976 }; 1977 1978 /**************************************/ 1979 /* */ 1980 /* P U B L I C D A T A */ 1981 /* */ 1982 /**************************************/ 1983 enum public_sections { 1984 PUBLIC_DRV_MB, /* Points to the first drv_mb of path0 */ 1985 PUBLIC_MFW_MB, /* Points to the first mfw_mb of path0 */ 1986 PUBLIC_GLOBAL, 1987 PUBLIC_PATH, 1988 PUBLIC_PORT, 1989 PUBLIC_FUNC, 1990 PUBLIC_MAX_SECTIONS 1991 }; 1992 1993 struct drv_ver_info_stc { 1994 u32 ver; 1995 u8 name[32]; 1996 }; 1997 1998 /* Runtime data needs about 1/2K. We use 2K to be on the safe side. 1999 * Please make sure data does not exceed this size. 2000 */ 2001 #define NUM_RUNTIME_DWORDS 16 2002 struct drv_init_hw_stc { 2003 u32 init_hw_bitmask[NUM_RUNTIME_DWORDS]; 2004 u32 init_hw_data[NUM_RUNTIME_DWORDS * 32]; 2005 }; 2006 2007 struct mcp_public_data { 2008 /* The sections fields is an array */ 2009 u32 num_sections; 2010 offsize_t sections[PUBLIC_MAX_SECTIONS]; 2011 struct public_drv_mb drv_mb[MCP_GLOB_FUNC_MAX]; 2012 struct public_mfw_mb mfw_mb[MCP_GLOB_FUNC_MAX]; 2013 struct public_global global; 2014 struct public_path path[MCP_GLOB_PATH_MAX]; 2015 struct public_port port[MCP_GLOB_PORT_MAX]; 2016 struct public_func func[MCP_GLOB_FUNC_MAX]; 2017 }; 2018 2019 #define I2C_TRANSCEIVER_ADDR 0xa0 2020 #define MAX_I2C_TRANSACTION_SIZE 16 2021 #define MAX_I2C_TRANSCEIVER_PAGE_SIZE 256 2022 2023 #endif /* MCP_PUBLIC_H */ 2024