1 /* 2 * Copyright (c) 2016 QLogic Corporation. 3 * All rights reserved. 4 * www.qlogic.com 5 * 6 * See LICENSE.qede_pmd for copyright and licensing details. 7 */ 8 9 /**************************************************************************** 10 * 11 * Name: mcp_public.h 12 * 13 * Description: MCP public data 14 * 15 * Created: 13/01/2013 yanivr 16 * 17 ****************************************************************************/ 18 19 #ifndef MCP_PUBLIC_H 20 #define MCP_PUBLIC_H 21 22 #define VF_MAX_STATIC 192 /* In case of AH */ 23 24 #define MCP_GLOB_PATH_MAX 2 25 #define MCP_PORT_MAX 2 /* Global */ 26 #define MCP_GLOB_PORT_MAX 4 /* Global */ 27 #define MCP_GLOB_FUNC_MAX 16 /* Global */ 28 29 typedef u32 offsize_t; /* In DWORDS !!! */ 30 /* Offset from the beginning of the MCP scratchpad */ 31 #define OFFSIZE_OFFSET_SHIFT 0 32 #define OFFSIZE_OFFSET_MASK 0x0000ffff 33 /* Size of specific element (not the whole array if any) */ 34 #define OFFSIZE_SIZE_SHIFT 16 35 #define OFFSIZE_SIZE_MASK 0xffff0000 36 37 /* SECTION_OFFSET is calculating the offset in bytes out of offsize */ 38 #define SECTION_OFFSET(_offsize) \ 39 ((((_offsize & OFFSIZE_OFFSET_MASK) >> OFFSIZE_OFFSET_SHIFT) << 2)) 40 41 /* SECTION_SIZE is calculating the size in bytes out of offsize */ 42 #define SECTION_SIZE(_offsize) \ 43 (((_offsize & OFFSIZE_SIZE_MASK) >> OFFSIZE_SIZE_SHIFT) << 2) 44 45 /* SECTION_ADDR returns the GRC addr of a section, given offsize and index 46 * within section 47 */ 48 #define SECTION_ADDR(_offsize, idx) \ 49 (MCP_REG_SCRATCH + \ 50 SECTION_OFFSET(_offsize) + (SECTION_SIZE(_offsize) * idx)) 51 52 /* SECTION_OFFSIZE_ADDR returns the GRC addr to the offsize address. Use 53 * offsetof, since the OFFSETUP collide with the firmware definition 54 */ 55 #define SECTION_OFFSIZE_ADDR(_pub_base, _section) \ 56 (_pub_base + offsetof(struct mcp_public_data, sections[_section])) 57 /* PHY configuration */ 58 struct eth_phy_cfg { 59 /* 0 = autoneg, 1000/10000/20000/25000/40000/50000/100000 */ 60 u32 speed; 61 #define ETH_SPEED_AUTONEG 0 62 #define ETH_SPEED_SMARTLINQ 0x8 63 64 u32 pause; /* bitmask */ 65 #define ETH_PAUSE_NONE 0x0 66 #define ETH_PAUSE_AUTONEG 0x1 67 #define ETH_PAUSE_RX 0x2 68 #define ETH_PAUSE_TX 0x4 69 70 u32 adv_speed; /* Default should be the speed_cap_mask */ 71 u32 loopback_mode; 72 #define ETH_LOOPBACK_NONE (0) 73 /* Serdes loopback. In AH, it refers to Near End */ 74 #define ETH_LOOPBACK_INT_PHY (1) 75 #define ETH_LOOPBACK_EXT_PHY (2) /* External PHY Loopback */ 76 /* External Loopback (Require loopback plug) */ 77 #define ETH_LOOPBACK_EXT (3) 78 #define ETH_LOOPBACK_MAC (4) /* MAC Loopback - not supported */ 79 #define ETH_LOOPBACK_CNIG_AH_ONLY_0123 (5) /* Port to itself */ 80 #define ETH_LOOPBACK_CNIG_AH_ONLY_2301 (6) /* Port to Port */ 81 #define ETH_LOOPBACK_PCS_AH_ONLY (7) /* PCS loopback (TX to RX) */ 82 /* Loop RX packet from PCS to TX */ 83 #define ETH_LOOPBACK_REVERSE_MAC_AH_ONLY (8) 84 /* Remote Serdes Loopback (RX to TX) */ 85 #define ETH_LOOPBACK_INT_PHY_FEA_AH_ONLY (9) 86 87 /* features */ 88 u32 feature_config_flags; 89 #define ETH_EEE_MODE_ADV_LPI (1 << 0) 90 }; 91 92 struct port_mf_cfg { 93 u32 dynamic_cfg; /* device control channel */ 94 #define PORT_MF_CFG_OV_TAG_MASK 0x0000ffff 95 #define PORT_MF_CFG_OV_TAG_SHIFT 0 96 #define PORT_MF_CFG_OV_TAG_DEFAULT PORT_MF_CFG_OV_TAG_MASK 97 98 u32 reserved[1]; 99 }; 100 101 /* DO NOT add new fields in the middle 102 * MUST be synced with struct pmm_stats_map 103 */ 104 struct eth_stats { 105 u64 r64; /* 0x00 (Offset 0x00 ) RX 64-byte frame counter*/ 106 u64 r127; /* 0x01 (Offset 0x08 ) RX 65 to 127 byte frame counter*/ 107 u64 r255; /* 0x02 (Offset 0x10 ) RX 128 to 255 byte frame counter*/ 108 u64 r511; /* 0x03 (Offset 0x18 ) RX 256 to 511 byte frame counter*/ 109 u64 r1023; /* 0x04 (Offset 0x20 ) RX 512 to 1023 byte frame counter*/ 110 /* 0x05 (Offset 0x28 ) RX 1024 to 1518 byte frame counter */ 111 u64 r1518; 112 /* 0x06 (Offset 0x30 ) RX 1519 to 1522 byte VLAN-tagged frame counter */ 113 u64 r1522; 114 u64 r2047; /* 0x07 (Offset 0x38 ) RX 1519 to 2047 byte frame counter*/ 115 u64 r4095; /* 0x08 (Offset 0x40 ) RX 2048 to 4095 byte frame counter*/ 116 u64 r9216; /* 0x09 (Offset 0x48 ) RX 4096 to 9216 byte frame counter*/ 117 /* 0x0A (Offset 0x50 ) RX 9217 to 16383 byte frame counter */ 118 u64 r16383; 119 u64 rfcs; /* 0x0F (Offset 0x58 ) RX FCS error frame counter*/ 120 u64 rxcf; /* 0x10 (Offset 0x60 ) RX control frame counter*/ 121 u64 rxpf; /* 0x11 (Offset 0x68 ) RX pause frame counter*/ 122 u64 rxpp; /* 0x12 (Offset 0x70 ) RX PFC frame counter*/ 123 u64 raln; /* 0x16 (Offset 0x78 ) RX alignment error counter*/ 124 u64 rfcr; /* 0x19 (Offset 0x80 ) RX false carrier counter */ 125 u64 rovr; /* 0x1A (Offset 0x88 ) RX oversized frame counter*/ 126 u64 rjbr; /* 0x1B (Offset 0x90 ) RX jabber frame counter */ 127 u64 rund; /* 0x34 (Offset 0x98 ) RX undersized frame counter */ 128 u64 rfrg; /* 0x35 (Offset 0xa0 ) RX fragment counter */ 129 u64 t64; /* 0x40 (Offset 0xa8 ) TX 64-byte frame counter */ 130 u64 t127; /* 0x41 (Offset 0xb0 ) TX 65 to 127 byte frame counter */ 131 u64 t255; /* 0x42 (Offset 0xb8 ) TX 128 to 255 byte frame counter*/ 132 u64 t511; /* 0x43 (Offset 0xc0 ) TX 256 to 511 byte frame counter*/ 133 u64 t1023; /* 0x44 (Offset 0xc8 ) TX 512 to 1023 byte frame counter*/ 134 /* 0x45 (Offset 0xd0 ) TX 1024 to 1518 byte frame counter */ 135 u64 t1518; 136 /* 0x47 (Offset 0xd8 ) TX 1519 to 2047 byte frame counter */ 137 u64 t2047; 138 /* 0x48 (Offset 0xe0 ) TX 2048 to 4095 byte frame counter */ 139 u64 t4095; 140 /* 0x49 (Offset 0xe8 ) TX 4096 to 9216 byte frame counter */ 141 u64 t9216; 142 /* 0x4A (Offset 0xf0 ) TX 9217 to 16383 byte frame counter */ 143 u64 t16383; 144 u64 txpf; /* 0x50 (Offset 0xf8 ) TX pause frame counter */ 145 u64 txpp; /* 0x51 (Offset 0x100) TX PFC frame counter */ 146 /* 0x6C (Offset 0x108) Transmit Logical Type LLFC message counter */ 147 u64 tlpiec; 148 u64 tncl; /* 0x6E (Offset 0x110) Transmit Total Collision Counter */ 149 u64 rbyte; /* 0x3d (Offset 0x118) RX byte counter */ 150 u64 rxuca; /* 0x0c (Offset 0x120) RX UC frame counter */ 151 u64 rxmca; /* 0x0d (Offset 0x128) RX MC frame counter */ 152 u64 rxbca; /* 0x0e (Offset 0x130) RX BC frame counter */ 153 /* 0x22 (Offset 0x138) RX good frame (good CRC, not oversized, no ERROR) */ 154 u64 rxpok; 155 u64 tbyte; /* 0x6f (Offset 0x140) TX byte counter */ 156 u64 txuca; /* 0x4d (Offset 0x148) TX UC frame counter */ 157 u64 txmca; /* 0x4e (Offset 0x150) TX MC frame counter */ 158 u64 txbca; /* 0x4f (Offset 0x158) TX BC frame counter */ 159 u64 txcf; /* 0x54 (Offset 0x160) TX control frame counter */ 160 /* HSI - Cannot add more stats to this struct. If needed, then need to open new 161 * struct 162 */ 163 164 }; 165 166 struct brb_stats { 167 u64 brb_truncate[8]; 168 u64 brb_discard[8]; 169 }; 170 171 struct port_stats { 172 struct brb_stats brb; 173 struct eth_stats eth; 174 }; 175 176 /*----+------------------------------------------------------------------------ 177 * C | Number and | Ports in| Ports in|2 PHY-s |# of ports|# of engines 178 * h | rate of | team #1 | team #2 |are used|per path | (paths) 179 * i | physical | | | | | enabled 180 * p | ports | | | | | 181 *====+============+=========+=========+========+==========+=================== 182 * BB | 1x100G | This is special mode, where there are actually 2 HW func 183 * BB | 2x10/20Gbps| 0,1 | NA | No | 1 | 1 184 * BB | 2x40 Gbps | 0,1 | NA | Yes | 1 | 1 185 * BB | 2x50Gbps | 0,1 | NA | No | 1 | 1 186 * BB | 4x10Gbps | 0,2 | 1,3 | No | 1/2 | 1,2 (2 is optional) 187 * BB | 4x10Gbps | 0,1 | 2,3 | No | 1/2 | 1,2 (2 is optional) 188 * BB | 4x10Gbps | 0,3 | 1,2 | No | 1/2 | 1,2 (2 is optional) 189 * BB | 4x10Gbps | 0,1,2,3 | NA | No | 1 | 1 190 * AH | 2x10/20Gbps| 0,1 | NA | NA | 1 | NA 191 * AH | 4x10Gbps | 0,1 | 2,3 | NA | 2 | NA 192 * AH | 4x10Gbps | 0,2 | 1,3 | NA | 2 | NA 193 * AH | 4x10Gbps | 0,3 | 1,2 | NA | 2 | NA 194 * AH | 4x10Gbps | 0,1,2,3 | NA | NA | 1 | NA 195 *====+============+=========+=========+========+==========+=================== 196 */ 197 198 #define CMT_TEAM0 0 199 #define CMT_TEAM1 1 200 #define CMT_TEAM_MAX 2 201 202 struct couple_mode_teaming { 203 u8 port_cmt[MCP_GLOB_PORT_MAX]; 204 #define PORT_CMT_IN_TEAM (1 << 0) 205 206 #define PORT_CMT_PORT_ROLE (1 << 1) 207 #define PORT_CMT_PORT_INACTIVE (0 << 1) 208 #define PORT_CMT_PORT_ACTIVE (1 << 1) 209 210 #define PORT_CMT_TEAM_MASK (1 << 2) 211 #define PORT_CMT_TEAM0 (0 << 2) 212 #define PORT_CMT_TEAM1 (1 << 2) 213 }; 214 215 /************************************** 216 * LLDP and DCBX HSI structures 217 **************************************/ 218 #define LLDP_CHASSIS_ID_STAT_LEN 4 219 #define LLDP_PORT_ID_STAT_LEN 4 220 #define DCBX_MAX_APP_PROTOCOL 32 221 #define MAX_SYSTEM_LLDP_TLV_DATA 32 222 223 typedef enum _lldp_agent_e { 224 LLDP_NEAREST_BRIDGE = 0, 225 LLDP_NEAREST_NON_TPMR_BRIDGE, 226 LLDP_NEAREST_CUSTOMER_BRIDGE, 227 LLDP_MAX_LLDP_AGENTS 228 } lldp_agent_e; 229 230 struct lldp_config_params_s { 231 u32 config; 232 #define LLDP_CONFIG_TX_INTERVAL_MASK 0x000000ff 233 #define LLDP_CONFIG_TX_INTERVAL_SHIFT 0 234 #define LLDP_CONFIG_HOLD_MASK 0x00000f00 235 #define LLDP_CONFIG_HOLD_SHIFT 8 236 #define LLDP_CONFIG_MAX_CREDIT_MASK 0x0000f000 237 #define LLDP_CONFIG_MAX_CREDIT_SHIFT 12 238 #define LLDP_CONFIG_ENABLE_RX_MASK 0x40000000 239 #define LLDP_CONFIG_ENABLE_RX_SHIFT 30 240 #define LLDP_CONFIG_ENABLE_TX_MASK 0x80000000 241 #define LLDP_CONFIG_ENABLE_TX_SHIFT 31 242 /* Holds local Chassis ID TLV header, subtype and 9B of payload. 243 * If firtst byte is 0, then we will use default chassis ID 244 */ 245 u32 local_chassis_id[LLDP_CHASSIS_ID_STAT_LEN]; 246 /* Holds local Port ID TLV header, subtype and 9B of payload. 247 * If firtst byte is 0, then we will use default port ID 248 */ 249 u32 local_port_id[LLDP_PORT_ID_STAT_LEN]; 250 }; 251 252 struct lldp_status_params_s { 253 u32 prefix_seq_num; 254 u32 status; /* TBD */ 255 /* Holds remote Chassis ID TLV header, subtype and 9B of payload. */ 256 u32 peer_chassis_id[LLDP_CHASSIS_ID_STAT_LEN]; 257 /* Holds remote Port ID TLV header, subtype and 9B of payload. */ 258 u32 peer_port_id[LLDP_PORT_ID_STAT_LEN]; 259 u32 suffix_seq_num; 260 }; 261 262 struct dcbx_ets_feature { 263 u32 flags; 264 #define DCBX_ETS_ENABLED_MASK 0x00000001 265 #define DCBX_ETS_ENABLED_SHIFT 0 266 #define DCBX_ETS_WILLING_MASK 0x00000002 267 #define DCBX_ETS_WILLING_SHIFT 1 268 #define DCBX_ETS_ERROR_MASK 0x00000004 269 #define DCBX_ETS_ERROR_SHIFT 2 270 #define DCBX_ETS_CBS_MASK 0x00000008 271 #define DCBX_ETS_CBS_SHIFT 3 272 #define DCBX_ETS_MAX_TCS_MASK 0x000000f0 273 #define DCBX_ETS_MAX_TCS_SHIFT 4 274 #define DCBX_ISCSI_OOO_TC_MASK 0x00000f00 275 #define DCBX_ISCSI_OOO_TC_SHIFT 8 276 /* Entries in tc table are orginized that the left most is pri 0, right most is 277 * prio 7 278 */ 279 280 u32 pri_tc_tbl[1]; 281 #define DCBX_ISCSI_OOO_TC (4) 282 283 #define NIG_ETS_ISCSI_OOO_CLIENT_OFFSET (DCBX_ISCSI_OOO_TC + 1) 284 #define DCBX_CEE_STRICT_PRIORITY 0xf 285 /* Entries in tc table are orginized that the left most is pri 0, right most is 286 * prio 7 287 */ 288 289 u32 tc_bw_tbl[2]; 290 /* Entries in tc table are orginized that the left most is pri 0, right most is 291 * prio 7 292 */ 293 294 u32 tc_tsa_tbl[2]; 295 #define DCBX_ETS_TSA_STRICT 0 296 #define DCBX_ETS_TSA_CBS 1 297 #define DCBX_ETS_TSA_ETS 2 298 }; 299 300 struct dcbx_app_priority_entry { 301 u32 entry; 302 #define DCBX_APP_PRI_MAP_MASK 0x000000ff 303 #define DCBX_APP_PRI_MAP_SHIFT 0 304 #define DCBX_APP_PRI_0 0x01 305 #define DCBX_APP_PRI_1 0x02 306 #define DCBX_APP_PRI_2 0x04 307 #define DCBX_APP_PRI_3 0x08 308 #define DCBX_APP_PRI_4 0x10 309 #define DCBX_APP_PRI_5 0x20 310 #define DCBX_APP_PRI_6 0x40 311 #define DCBX_APP_PRI_7 0x80 312 #define DCBX_APP_SF_MASK 0x00000300 313 #define DCBX_APP_SF_SHIFT 8 314 #define DCBX_APP_SF_ETHTYPE 0 315 #define DCBX_APP_SF_PORT 1 316 #define DCBX_APP_SF_IEEE_MASK 0x0000f000 317 #define DCBX_APP_SF_IEEE_SHIFT 12 318 #define DCBX_APP_SF_IEEE_RESERVED 0 319 #define DCBX_APP_SF_IEEE_ETHTYPE 1 320 #define DCBX_APP_SF_IEEE_TCP_PORT 2 321 #define DCBX_APP_SF_IEEE_UDP_PORT 3 322 #define DCBX_APP_SF_IEEE_TCP_UDP_PORT 4 323 324 #define DCBX_APP_PROTOCOL_ID_MASK 0xffff0000 325 #define DCBX_APP_PROTOCOL_ID_SHIFT 16 326 }; 327 328 329 /* FW structure in BE */ 330 struct dcbx_app_priority_feature { 331 u32 flags; 332 #define DCBX_APP_ENABLED_MASK 0x00000001 333 #define DCBX_APP_ENABLED_SHIFT 0 334 #define DCBX_APP_WILLING_MASK 0x00000002 335 #define DCBX_APP_WILLING_SHIFT 1 336 #define DCBX_APP_ERROR_MASK 0x00000004 337 #define DCBX_APP_ERROR_SHIFT 2 338 /* Not in use 339 #define DCBX_APP_DEFAULT_PRI_MASK 0x00000f00 340 #define DCBX_APP_DEFAULT_PRI_SHIFT 8 341 */ 342 #define DCBX_APP_MAX_TCS_MASK 0x0000f000 343 #define DCBX_APP_MAX_TCS_SHIFT 12 344 #define DCBX_APP_NUM_ENTRIES_MASK 0x00ff0000 345 #define DCBX_APP_NUM_ENTRIES_SHIFT 16 346 struct dcbx_app_priority_entry app_pri_tbl[DCBX_MAX_APP_PROTOCOL]; 347 }; 348 349 /* FW structure in BE */ 350 struct dcbx_features { 351 /* PG feature */ 352 struct dcbx_ets_feature ets; 353 /* PFC feature */ 354 u32 pfc; 355 #define DCBX_PFC_PRI_EN_BITMAP_MASK 0x000000ff 356 #define DCBX_PFC_PRI_EN_BITMAP_SHIFT 0 357 #define DCBX_PFC_PRI_EN_BITMAP_PRI_0 0x01 358 #define DCBX_PFC_PRI_EN_BITMAP_PRI_1 0x02 359 #define DCBX_PFC_PRI_EN_BITMAP_PRI_2 0x04 360 #define DCBX_PFC_PRI_EN_BITMAP_PRI_3 0x08 361 #define DCBX_PFC_PRI_EN_BITMAP_PRI_4 0x10 362 #define DCBX_PFC_PRI_EN_BITMAP_PRI_5 0x20 363 #define DCBX_PFC_PRI_EN_BITMAP_PRI_6 0x40 364 #define DCBX_PFC_PRI_EN_BITMAP_PRI_7 0x80 365 366 #define DCBX_PFC_FLAGS_MASK 0x0000ff00 367 #define DCBX_PFC_FLAGS_SHIFT 8 368 #define DCBX_PFC_CAPS_MASK 0x00000f00 369 #define DCBX_PFC_CAPS_SHIFT 8 370 #define DCBX_PFC_MBC_MASK 0x00004000 371 #define DCBX_PFC_MBC_SHIFT 14 372 #define DCBX_PFC_WILLING_MASK 0x00008000 373 #define DCBX_PFC_WILLING_SHIFT 15 374 #define DCBX_PFC_ENABLED_MASK 0x00010000 375 #define DCBX_PFC_ENABLED_SHIFT 16 376 #define DCBX_PFC_ERROR_MASK 0x00020000 377 #define DCBX_PFC_ERROR_SHIFT 17 378 379 /* APP feature */ 380 struct dcbx_app_priority_feature app; 381 }; 382 383 struct dcbx_local_params { 384 u32 config; 385 #define DCBX_CONFIG_VERSION_MASK 0x00000007 386 #define DCBX_CONFIG_VERSION_SHIFT 0 387 #define DCBX_CONFIG_VERSION_DISABLED 0 388 #define DCBX_CONFIG_VERSION_IEEE 1 389 #define DCBX_CONFIG_VERSION_CEE 2 390 #define DCBX_CONFIG_VERSION_STATIC 4 391 392 u32 flags; 393 struct dcbx_features features; 394 }; 395 396 struct dcbx_mib { 397 u32 prefix_seq_num; 398 u32 flags; 399 /* 400 #define DCBX_CONFIG_VERSION_MASK 0x00000007 401 #define DCBX_CONFIG_VERSION_SHIFT 0 402 #define DCBX_CONFIG_VERSION_DISABLED 0 403 #define DCBX_CONFIG_VERSION_IEEE 1 404 #define DCBX_CONFIG_VERSION_CEE 2 405 #define DCBX_CONFIG_VERSION_STATIC 4 406 */ 407 struct dcbx_features features; 408 u32 suffix_seq_num; 409 }; 410 411 struct lldp_system_tlvs_buffer_s { 412 u16 valid; 413 u16 length; 414 u32 data[MAX_SYSTEM_LLDP_TLV_DATA]; 415 }; 416 417 struct dcb_dscp_map { 418 u32 flags; 419 #define DCB_DSCP_ENABLE_MASK 0x1 420 #define DCB_DSCP_ENABLE_SHIFT 0 421 #define DCB_DSCP_ENABLE 1 422 u32 dscp_pri_map[8]; 423 }; 424 425 /**************************************/ 426 /* */ 427 /* P U B L I C G L O B A L */ 428 /* */ 429 /**************************************/ 430 struct public_global { 431 u32 max_path; /* 32bit is wasty, but this will be used often */ 432 /* (Global) 32bit is wasty, but this will be used often */ 433 u32 max_ports; 434 #define MODE_1P 1 /* TBD - NEED TO THINK OF A BETTER NAME */ 435 #define MODE_2P 2 436 #define MODE_3P 3 437 #define MODE_4P 4 438 u32 debug_mb_offset; 439 u32 phymod_dbg_mb_offset; 440 struct couple_mode_teaming cmt; 441 /* Temperature in Celcius (-255C / +255C), measured every second. */ 442 s32 internal_temperature; 443 u32 mfw_ver; 444 u32 running_bundle_id; 445 s32 external_temperature; 446 u32 mdump_reason; 447 #define MDUMP_REASON_INTERNAL_ERROR (1 << 0) 448 #define MDUMP_REASON_EXTERNAL_TRIGGER (1 << 1) 449 #define MDUMP_REASON_DUMP_AGED (1 << 2) 450 }; 451 452 /**************************************/ 453 /* */ 454 /* P U B L I C P A T H */ 455 /* */ 456 /**************************************/ 457 458 /**************************************************************************** 459 * Shared Memory 2 Region * 460 ****************************************************************************/ 461 /* The fw_flr_ack is actually built in the following way: */ 462 /* 8 bit: PF ack */ 463 /* 128 bit: VF ack */ 464 /* 8 bit: ios_dis_ack */ 465 /* In order to maintain endianity in the mailbox hsi, we want to keep using */ 466 /* u32. The fw must have the VF right after the PF since this is how it */ 467 /* access arrays(it expects always the VF to reside after the PF, and that */ 468 /* makes the calculation much easier for it. ) */ 469 /* In order to answer both limitations, and keep the struct small, the code */ 470 /* will abuse the structure defined here to achieve the actual partition */ 471 /* above */ 472 /****************************************************************************/ 473 struct fw_flr_mb { 474 u32 aggint; 475 u32 opgen_addr; 476 u32 accum_ack; /* 0..15:PF, 16..207:VF, 256..271:IOV_DIS */ 477 #define ACCUM_ACK_PF_BASE 0 478 #define ACCUM_ACK_PF_SHIFT 0 479 480 #define ACCUM_ACK_VF_BASE 8 481 #define ACCUM_ACK_VF_SHIFT 3 482 483 #define ACCUM_ACK_IOV_DIS_BASE 256 484 #define ACCUM_ACK_IOV_DIS_SHIFT 8 485 486 }; 487 488 struct public_path { 489 struct fw_flr_mb flr_mb; 490 /* 491 * mcp_vf_disabled is set by the MCP to indicate the driver about VFs 492 * which were disabled/flred 493 */ 494 u32 mcp_vf_disabled[VF_MAX_STATIC / 32]; /* 0x003c */ 495 496 /* Reset on mcp reset, and incremented for eveny process kill event. */ 497 u32 process_kill; 498 #define PROCESS_KILL_COUNTER_MASK 0x0000ffff 499 #define PROCESS_KILL_COUNTER_SHIFT 0 500 #define PROCESS_KILL_GLOB_AEU_BIT_MASK 0xffff0000 501 #define PROCESS_KILL_GLOB_AEU_BIT_SHIFT 16 502 #define GLOBAL_AEU_BIT(aeu_reg_id, aeu_bit) (aeu_reg_id * 32 + aeu_bit) 503 }; 504 505 /**************************************/ 506 /* */ 507 /* P U B L I C P O R T */ 508 /* */ 509 /**************************************/ 510 #define FC_NPIV_WWPN_SIZE 8 511 #define FC_NPIV_WWNN_SIZE 8 512 struct dci_npiv_settings { 513 u8 npiv_wwpn[FC_NPIV_WWPN_SIZE]; 514 u8 npiv_wwnn[FC_NPIV_WWNN_SIZE]; 515 }; 516 517 struct dci_fc_npiv_cfg { 518 /* hdr used internally by the MFW */ 519 u32 hdr; 520 u32 num_of_npiv; 521 }; 522 523 #define MAX_NUMBER_NPIV 64 524 struct dci_fc_npiv_tbl { 525 struct dci_fc_npiv_cfg fc_npiv_cfg; 526 struct dci_npiv_settings settings[MAX_NUMBER_NPIV]; 527 }; 528 529 /**************************************************************************** 530 * Driver <-> FW Mailbox * 531 ****************************************************************************/ 532 533 struct public_port { 534 u32 validity_map; /* 0x0 (4*2 = 0x8) */ 535 536 /* validity bits */ 537 #define MCP_VALIDITY_PCI_CFG 0x00100000 538 #define MCP_VALIDITY_MB 0x00200000 539 #define MCP_VALIDITY_DEV_INFO 0x00400000 540 #define MCP_VALIDITY_RESERVED 0x00000007 541 542 /* One licensing bit should be set */ 543 /* yaniv - tbd ? license */ 544 #define MCP_VALIDITY_LIC_KEY_IN_EFFECT_MASK 0x00000038 545 #define MCP_VALIDITY_LIC_MANUF_KEY_IN_EFFECT 0x00000008 546 #define MCP_VALIDITY_LIC_UPGRADE_KEY_IN_EFFECT 0x00000010 547 #define MCP_VALIDITY_LIC_NO_KEY_IN_EFFECT 0x00000020 548 549 /* Active MFW */ 550 #define MCP_VALIDITY_ACTIVE_MFW_UNKNOWN 0x00000000 551 #define MCP_VALIDITY_ACTIVE_MFW_MASK 0x000001c0 552 #define MCP_VALIDITY_ACTIVE_MFW_NCSI 0x00000040 553 #define MCP_VALIDITY_ACTIVE_MFW_NONE 0x000001c0 554 555 u32 link_status; 556 #define LINK_STATUS_LINK_UP 0x00000001 557 #define LINK_STATUS_SPEED_AND_DUPLEX_MASK 0x0000001e 558 #define LINK_STATUS_SPEED_AND_DUPLEX_1000THD (1 << 1) 559 #define LINK_STATUS_SPEED_AND_DUPLEX_1000TFD (2 << 1) 560 #define LINK_STATUS_SPEED_AND_DUPLEX_10G (3 << 1) 561 #define LINK_STATUS_SPEED_AND_DUPLEX_20G (4 << 1) 562 #define LINK_STATUS_SPEED_AND_DUPLEX_40G (5 << 1) 563 #define LINK_STATUS_SPEED_AND_DUPLEX_50G (6 << 1) 564 #define LINK_STATUS_SPEED_AND_DUPLEX_100G (7 << 1) 565 #define LINK_STATUS_SPEED_AND_DUPLEX_25G (8 << 1) 566 567 #define LINK_STATUS_AUTO_NEGOTIATE_ENABLED 0x00000020 568 569 #define LINK_STATUS_AUTO_NEGOTIATE_COMPLETE 0x00000040 570 #define LINK_STATUS_PARALLEL_DETECTION_USED 0x00000080 571 572 #define LINK_STATUS_PFC_ENABLED 0x00000100 573 #define LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE 0x00000200 574 #define LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE 0x00000400 575 #define LINK_STATUS_LINK_PARTNER_10G_CAPABLE 0x00000800 576 #define LINK_STATUS_LINK_PARTNER_20G_CAPABLE 0x00001000 577 #define LINK_STATUS_LINK_PARTNER_40G_CAPABLE 0x00002000 578 #define LINK_STATUS_LINK_PARTNER_50G_CAPABLE 0x00004000 579 #define LINK_STATUS_LINK_PARTNER_100G_CAPABLE 0x00008000 580 #define LINK_STATUS_LINK_PARTNER_25G_CAPABLE 0x00010000 581 582 #define LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK 0x000C0000 583 #define LINK_STATUS_LINK_PARTNER_NOT_PAUSE_CAPABLE (0 << 18) 584 #define LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE (1 << 18) 585 #define LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE (2 << 18) 586 #define LINK_STATUS_LINK_PARTNER_BOTH_PAUSE (3 << 18) 587 588 #define LINK_STATUS_SFP_TX_FAULT 0x00100000 589 #define LINK_STATUS_TX_FLOW_CONTROL_ENABLED 0x00200000 590 #define LINK_STATUS_RX_FLOW_CONTROL_ENABLED 0x00400000 591 #define LINK_STATUS_RX_SIGNAL_PRESENT 0x00800000 592 #define LINK_STATUS_MAC_LOCAL_FAULT 0x01000000 593 #define LINK_STATUS_MAC_REMOTE_FAULT 0x02000000 594 #define LINK_STATUS_UNSUPPORTED_SPD_REQ 0x04000000 595 596 #define LINK_STATUS_FEC_MODE_MASK 0x38000000 597 #define LINK_STATUS_FEC_MODE_NONE (0 << 27) 598 #define LINK_STATUS_FEC_MODE_FIRECODE_CL74 (1 << 27) 599 #define LINK_STATUS_FEC_MODE_RS_CL91 (2 << 27) 600 601 u32 link_status1; 602 u32 ext_phy_fw_version; 603 /* Points to struct eth_phy_cfg (For READ-ONLY) */ 604 u32 drv_phy_cfg_addr; 605 606 u32 port_stx; 607 608 u32 stat_nig_timer; 609 610 struct port_mf_cfg port_mf_config; 611 struct port_stats stats; 612 613 u32 media_type; 614 #define MEDIA_UNSPECIFIED 0x0 615 #define MEDIA_SFPP_10G_FIBER 0x1 /* Use MEDIA_MODULE_FIBER instead */ 616 #define MEDIA_XFP_FIBER 0x2 /* Use MEDIA_MODULE_FIBER instead */ 617 #define MEDIA_DA_TWINAX 0x3 618 #define MEDIA_BASE_T 0x4 619 #define MEDIA_SFP_1G_FIBER 0x5 /* Use MEDIA_MODULE_FIBER instead */ 620 #define MEDIA_MODULE_FIBER 0x6 621 #define MEDIA_KR 0xf0 622 #define MEDIA_NOT_PRESENT 0xff 623 624 u32 lfa_status; 625 #define LFA_LINK_FLAP_REASON_OFFSET 0 626 #define LFA_LINK_FLAP_REASON_MASK 0x000000ff 627 #define LFA_NO_REASON (0 << 0) 628 #define LFA_LINK_DOWN (1 << 0) 629 #define LFA_FORCE_INIT (1 << 1) 630 #define LFA_LOOPBACK_MISMATCH (1 << 2) 631 #define LFA_SPEED_MISMATCH (1 << 3) 632 #define LFA_FLOW_CTRL_MISMATCH (1 << 4) 633 #define LFA_ADV_SPEED_MISMATCH (1 << 5) 634 #define LINK_FLAP_AVOIDANCE_COUNT_OFFSET 8 635 #define LINK_FLAP_AVOIDANCE_COUNT_MASK 0x0000ff00 636 #define LINK_FLAP_COUNT_OFFSET 16 637 #define LINK_FLAP_COUNT_MASK 0x00ff0000 638 639 u32 link_change_count; 640 641 /* LLDP params */ 642 /* offset: 536 bytes? */ 643 struct lldp_config_params_s lldp_config_params[LLDP_MAX_LLDP_AGENTS]; 644 struct lldp_status_params_s lldp_status_params[LLDP_MAX_LLDP_AGENTS]; 645 struct lldp_system_tlvs_buffer_s system_lldp_tlvs_buf; 646 647 /* DCBX related MIB */ 648 struct dcbx_local_params local_admin_dcbx_mib; 649 struct dcbx_mib remote_dcbx_mib; 650 struct dcbx_mib operational_dcbx_mib; 651 652 /* FC_NPIV table offset & size in NVRAM value of 0 means not present */ 653 654 u32 fc_npiv_nvram_tbl_addr; 655 u32 fc_npiv_nvram_tbl_size; 656 u32 transceiver_data; 657 #define ETH_TRANSCEIVER_STATE_MASK 0x000000FF 658 #define ETH_TRANSCEIVER_STATE_SHIFT 0x00000000 659 #define ETH_TRANSCEIVER_STATE_UNPLUGGED 0x00000000 660 #define ETH_TRANSCEIVER_STATE_PRESENT 0x00000001 661 #define ETH_TRANSCEIVER_STATE_VALID 0x00000003 662 #define ETH_TRANSCEIVER_STATE_UPDATING 0x00000008 663 #define ETH_TRANSCEIVER_TYPE_MASK 0x0000FF00 664 #define ETH_TRANSCEIVER_TYPE_SHIFT 0x00000008 665 #define ETH_TRANSCEIVER_TYPE_NONE 0x00000000 666 #define ETH_TRANSCEIVER_TYPE_UNKNOWN 0x000000FF 667 /* 1G Passive copper cable */ 668 #define ETH_TRANSCEIVER_TYPE_1G_PCC 0x01 669 /* 1G Active copper cable */ 670 #define ETH_TRANSCEIVER_TYPE_1G_ACC 0x02 671 #define ETH_TRANSCEIVER_TYPE_1G_LX 0x03 672 #define ETH_TRANSCEIVER_TYPE_1G_SX 0x04 673 #define ETH_TRANSCEIVER_TYPE_10G_SR 0x05 674 #define ETH_TRANSCEIVER_TYPE_10G_LR 0x06 675 #define ETH_TRANSCEIVER_TYPE_10G_LRM 0x07 676 #define ETH_TRANSCEIVER_TYPE_10G_ER 0x08 677 /* 10G Passive copper cable */ 678 #define ETH_TRANSCEIVER_TYPE_10G_PCC 0x09 679 /* 10G Active copper cable */ 680 #define ETH_TRANSCEIVER_TYPE_10G_ACC 0x0a 681 #define ETH_TRANSCEIVER_TYPE_XLPPI 0x0b 682 #define ETH_TRANSCEIVER_TYPE_40G_LR4 0x0c 683 #define ETH_TRANSCEIVER_TYPE_40G_SR4 0x0d 684 #define ETH_TRANSCEIVER_TYPE_40G_CR4 0x0e 685 #define ETH_TRANSCEIVER_TYPE_100G_AOC 0x0f /* Active optical cable */ 686 #define ETH_TRANSCEIVER_TYPE_100G_SR4 0x10 687 #define ETH_TRANSCEIVER_TYPE_100G_LR4 0x11 688 #define ETH_TRANSCEIVER_TYPE_100G_ER4 0x12 689 #define ETH_TRANSCEIVER_TYPE_100G_ACC 0x13 /* Active copper cable */ 690 #define ETH_TRANSCEIVER_TYPE_100G_CR4 0x14 691 #define ETH_TRANSCEIVER_TYPE_4x10G_SR 0x15 692 /* 25G Passive copper cable - short */ 693 #define ETH_TRANSCEIVER_TYPE_25G_CA_N 0x16 694 /* 25G Active copper cable - short */ 695 #define ETH_TRANSCEIVER_TYPE_25G_ACC_S 0x17 696 /* 25G Passive copper cable - medium */ 697 #define ETH_TRANSCEIVER_TYPE_25G_CA_S 0x18 698 /* 25G Active copper cable - medium */ 699 #define ETH_TRANSCEIVER_TYPE_25G_ACC_M 0x19 700 /* 25G Passive copper cable - long */ 701 #define ETH_TRANSCEIVER_TYPE_25G_CA_L 0x1a 702 /* 25G Active copper cable - long */ 703 #define ETH_TRANSCEIVER_TYPE_25G_ACC_L 0x1b 704 #define ETH_TRANSCEIVER_TYPE_25G_SR 0x1c 705 #define ETH_TRANSCEIVER_TYPE_25G_LR 0x1d 706 #define ETH_TRANSCEIVER_TYPE_25G_AOC 0x1e 707 708 #define ETH_TRANSCEIVER_TYPE_4x10G 0x1f 709 #define ETH_TRANSCEIVER_TYPE_4x25G_CR 0x20 710 #define ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_40G_SR 0x30 711 #define ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_40G_CR 0x31 712 #define ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_40G_LR 0x32 713 #define ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_SR 0x33 714 #define ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_CR 0x34 715 #define ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_LR 0x35 716 #define ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_AOC 0x36 717 u32 wol_info; 718 u32 wol_pkt_len; 719 u32 wol_pkt_details; 720 struct dcb_dscp_map dcb_dscp_map; 721 }; 722 723 /**************************************/ 724 /* */ 725 /* P U B L I C F U N C */ 726 /* */ 727 /**************************************/ 728 729 struct public_func { 730 u32 iscsi_boot_signature; 731 u32 iscsi_boot_block_offset; 732 733 /* MTU size per funciton is needed for the OV feature */ 734 u32 mtu_size; 735 /* 9 entires for the C2S PCP map for each inner VLAN PCP + 1 default */ 736 737 /* For PCP values 0-3 use the map lower */ 738 /* 0xFF000000 - PCP 0, 0x00FF0000 - PCP 1, 739 * 0x0000FF00 - PCP 2, 0x000000FF PCP 3 740 */ 741 u32 c2s_pcp_map_lower; 742 /* For PCP values 4-7 use the map upper */ 743 /* 0xFF000000 - PCP 4, 0x00FF0000 - PCP 5, 744 * 0x0000FF00 - PCP 6, 0x000000FF PCP 7 745 */ 746 u32 c2s_pcp_map_upper; 747 748 /* For PCP default value get the MSB byte of the map default */ 749 u32 c2s_pcp_map_default; 750 751 u32 reserved[4]; 752 753 /* replace old mf_cfg */ 754 u32 config; 755 /* E/R/I/D */ 756 /* function 0 of each port cannot be hidden */ 757 #define FUNC_MF_CFG_FUNC_HIDE 0x00000001 758 #define FUNC_MF_CFG_PAUSE_ON_HOST_RING 0x00000002 759 #define FUNC_MF_CFG_PAUSE_ON_HOST_RING_SHIFT 0x00000001 760 761 762 #define FUNC_MF_CFG_PROTOCOL_MASK 0x000000f0 763 #define FUNC_MF_CFG_PROTOCOL_SHIFT 4 764 #define FUNC_MF_CFG_PROTOCOL_ETHERNET 0x00000000 765 #define FUNC_MF_CFG_PROTOCOL_ISCSI 0x00000010 766 #define FUNC_MF_CFG_PROTOCOL_FCOE 0x00000020 767 #define FUNC_MF_CFG_PROTOCOL_ROCE 0x00000030 768 #define FUNC_MF_CFG_PROTOCOL_MAX 0x00000030 769 770 /* MINBW, MAXBW */ 771 /* value range - 0..100, increments in 1 % */ 772 #define FUNC_MF_CFG_MIN_BW_MASK 0x0000ff00 773 #define FUNC_MF_CFG_MIN_BW_SHIFT 8 774 #define FUNC_MF_CFG_MIN_BW_DEFAULT 0x00000000 775 #define FUNC_MF_CFG_MAX_BW_MASK 0x00ff0000 776 #define FUNC_MF_CFG_MAX_BW_SHIFT 16 777 #define FUNC_MF_CFG_MAX_BW_DEFAULT 0x00640000 778 779 u32 status; 780 #define FUNC_STATUS_VLINK_DOWN 0x00000001 781 782 u32 mac_upper; /* MAC */ 783 #define FUNC_MF_CFG_UPPERMAC_MASK 0x0000ffff 784 #define FUNC_MF_CFG_UPPERMAC_SHIFT 0 785 #define FUNC_MF_CFG_UPPERMAC_DEFAULT FUNC_MF_CFG_UPPERMAC_MASK 786 u32 mac_lower; 787 #define FUNC_MF_CFG_LOWERMAC_DEFAULT 0xffffffff 788 789 u32 fcoe_wwn_port_name_upper; 790 u32 fcoe_wwn_port_name_lower; 791 792 u32 fcoe_wwn_node_name_upper; 793 u32 fcoe_wwn_node_name_lower; 794 795 u32 ovlan_stag; /* tags */ 796 #define FUNC_MF_CFG_OV_STAG_MASK 0x0000ffff 797 #define FUNC_MF_CFG_OV_STAG_SHIFT 0 798 #define FUNC_MF_CFG_OV_STAG_DEFAULT FUNC_MF_CFG_OV_STAG_MASK 799 800 u32 pf_allocation; /* vf per pf */ 801 802 u32 preserve_data; /* Will be used bt CCM */ 803 804 u32 driver_last_activity_ts; 805 806 /* 807 * drv_ack_vf_disabled is set by the PF driver to ack handled disabled 808 * VFs 809 */ 810 u32 drv_ack_vf_disabled[VF_MAX_STATIC / 32]; /* 0x0044 */ 811 812 u32 drv_id; 813 #define DRV_ID_PDA_COMP_VER_MASK 0x0000ffff 814 #define DRV_ID_PDA_COMP_VER_SHIFT 0 815 816 #define DRV_ID_MCP_HSI_VER_MASK 0x00ff0000 817 #define DRV_ID_MCP_HSI_VER_SHIFT 16 818 #define DRV_ID_MCP_HSI_VER_CURRENT (1 << DRV_ID_MCP_HSI_VER_SHIFT) 819 820 #define DRV_ID_DRV_TYPE_MASK 0x7f000000 821 #define DRV_ID_DRV_TYPE_SHIFT 24 822 #define DRV_ID_DRV_TYPE_UNKNOWN (0 << DRV_ID_DRV_TYPE_SHIFT) 823 #define DRV_ID_DRV_TYPE_LINUX (1 << DRV_ID_DRV_TYPE_SHIFT) 824 #define DRV_ID_DRV_TYPE_WINDOWS (2 << DRV_ID_DRV_TYPE_SHIFT) 825 #define DRV_ID_DRV_TYPE_DIAG (3 << DRV_ID_DRV_TYPE_SHIFT) 826 #define DRV_ID_DRV_TYPE_PREBOOT (4 << DRV_ID_DRV_TYPE_SHIFT) 827 #define DRV_ID_DRV_TYPE_SOLARIS (5 << DRV_ID_DRV_TYPE_SHIFT) 828 #define DRV_ID_DRV_TYPE_VMWARE (6 << DRV_ID_DRV_TYPE_SHIFT) 829 #define DRV_ID_DRV_TYPE_FREEBSD (7 << DRV_ID_DRV_TYPE_SHIFT) 830 #define DRV_ID_DRV_TYPE_AIX (8 << DRV_ID_DRV_TYPE_SHIFT) 831 832 #define DRV_ID_DRV_INIT_HW_MASK 0x80000000 833 #define DRV_ID_DRV_INIT_HW_SHIFT 31 834 #define DRV_ID_DRV_INIT_HW_FLAG (1 << DRV_ID_DRV_INIT_HW_SHIFT) 835 }; 836 837 /**************************************/ 838 /* */ 839 /* P U B L I C M B */ 840 /* */ 841 /**************************************/ 842 /* This is the only section that the driver can write to, and each */ 843 /* Basically each driver request to set feature parameters, 844 * will be done using a different command, which will be linked 845 * to a specific data structure from the union below. 846 * For huge strucuture, the common blank structure should be used. 847 */ 848 849 struct mcp_mac { 850 u32 mac_upper; /* Upper 16 bits are always zeroes */ 851 u32 mac_lower; 852 }; 853 854 struct mcp_val64 { 855 u32 lo; 856 u32 hi; 857 }; 858 859 struct mcp_file_att { 860 u32 nvm_start_addr; 861 u32 len; 862 }; 863 864 struct bist_nvm_image_att { 865 u32 return_code; 866 u32 image_type; /* Image type */ 867 u32 nvm_start_addr; /* NVM address of the image */ 868 u32 len; /* Include CRC */ 869 }; 870 871 #define MCP_DRV_VER_STR_SIZE 16 872 #define MCP_DRV_VER_STR_SIZE_DWORD (MCP_DRV_VER_STR_SIZE / sizeof(u32)) 873 #define MCP_DRV_NVM_BUF_LEN 32 874 struct drv_version_stc { 875 u32 version; 876 u8 name[MCP_DRV_VER_STR_SIZE - 4]; 877 }; 878 879 /* statistics for ncsi */ 880 struct lan_stats_stc { 881 u64 ucast_rx_pkts; 882 u64 ucast_tx_pkts; 883 u32 fcs_err; 884 u32 rserved; 885 }; 886 887 struct fcoe_stats_stc { 888 u64 rx_pkts; 889 u64 tx_pkts; 890 u32 fcs_err; 891 u32 login_failure; 892 }; 893 894 struct iscsi_stats_stc { 895 u64 rx_pdus; 896 u64 tx_pdus; 897 u64 rx_bytes; 898 u64 tx_bytes; 899 }; 900 901 struct rdma_stats_stc { 902 u64 rx_pkts; 903 u64 tx_pkts; 904 u64 rx_bytes; 905 u64 tx_bytes; 906 }; 907 908 struct ocbb_data_stc { 909 u32 ocbb_host_addr; 910 u32 ocsd_host_addr; 911 u32 ocsd_req_update_interval; 912 }; 913 914 #define MAX_NUM_OF_SENSORS 7 915 #define MFW_SENSOR_LOCATION_INTERNAL 1 916 #define MFW_SENSOR_LOCATION_EXTERNAL 2 917 #define MFW_SENSOR_LOCATION_SFP 3 918 919 #define SENSOR_LOCATION_SHIFT 0 920 #define SENSOR_LOCATION_MASK 0x000000ff 921 #define THRESHOLD_HIGH_SHIFT 8 922 #define THRESHOLD_HIGH_MASK 0x0000ff00 923 #define CRITICAL_TEMPERATURE_SHIFT 16 924 #define CRITICAL_TEMPERATURE_MASK 0x00ff0000 925 #define CURRENT_TEMP_SHIFT 24 926 #define CURRENT_TEMP_MASK 0xff000000 927 struct temperature_status_stc { 928 u32 num_of_sensors; 929 u32 sensor[MAX_NUM_OF_SENSORS]; 930 }; 931 932 /* crash dump configuration header */ 933 struct mdump_config_stc { 934 u32 version; 935 u32 config; 936 u32 epoc; 937 u32 num_of_logs; 938 u32 valid_logs; 939 }; 940 941 enum resource_id_enum { 942 RESOURCE_NUM_SB_E = 0, 943 RESOURCE_NUM_L2_QUEUE_E = 1, 944 RESOURCE_NUM_VPORT_E = 2, 945 RESOURCE_NUM_VMQ_E = 3, 946 /* Not a real resource!! it's a factor used to calculate others */ 947 RESOURCE_FACTOR_NUM_RSS_PF_E = 4, 948 /* Not a real resource!! it's a factor used to calculate others */ 949 RESOURCE_FACTOR_RSS_PER_VF_E = 5, 950 RESOURCE_NUM_RL_E = 6, 951 RESOURCE_NUM_PQ_E = 7, 952 RESOURCE_NUM_VF_E = 8, 953 RESOURCE_VFC_FILTER_E = 9, 954 RESOURCE_ILT_E = 10, 955 RESOURCE_CQS_E = 11, 956 RESOURCE_GFT_PROFILES_E = 12, 957 RESOURCE_NUM_TC_E = 13, 958 RESOURCE_NUM_RSS_ENGINES_E = 14, 959 RESOURCE_LL2_QUEUE_E = 15, 960 RESOURCE_RDMA_STATS_QUEUE_E = 16, 961 RESOURCE_MAX_NUM, 962 RESOURCE_NUM_INVALID = 0xFFFFFFFF 963 }; 964 965 /* Resource ID is to be filled by the driver in the MB request 966 * Size, offset & flags to be filled by the MFW in the MB response 967 */ 968 struct resource_info { 969 enum resource_id_enum res_id; 970 u32 size; /* number of allocated resources */ 971 u32 offset; /* Offset of the 1st resource */ 972 u32 vf_size; 973 u32 vf_offset; 974 u32 flags; 975 #define RESOURCE_ELEMENT_STRICT (1 << 0) 976 }; 977 978 union drv_union_data { 979 u32 ver_str[MCP_DRV_VER_STR_SIZE_DWORD]; /* LOAD_REQ */ 980 struct mcp_mac wol_mac; /* UNLOAD_DONE */ 981 982 /* This configuration should be set by the driver for the LINK_SET command. */ 983 984 struct eth_phy_cfg drv_phy_cfg; 985 986 struct mcp_val64 val64; /* For PHY / AVS commands */ 987 988 u8 raw_data[MCP_DRV_NVM_BUF_LEN]; 989 990 struct mcp_file_att file_att; 991 992 u32 ack_vf_disabled[VF_MAX_STATIC / 32]; 993 994 struct drv_version_stc drv_version; 995 996 struct lan_stats_stc lan_stats; 997 struct fcoe_stats_stc fcoe_stats; 998 struct iscsi_stats_stc icsci_stats; 999 struct rdma_stats_stc rdma_stats; 1000 struct ocbb_data_stc ocbb_info; 1001 struct temperature_status_stc temp_info; 1002 struct resource_info resource; 1003 struct bist_nvm_image_att nvm_image_att; 1004 struct mdump_config_stc mdump_config; 1005 /* ... */ 1006 }; 1007 1008 struct public_drv_mb { 1009 u32 drv_mb_header; 1010 #define DRV_MSG_CODE_MASK 0xffff0000 1011 #define DRV_MSG_CODE_LOAD_REQ 0x10000000 1012 #define DRV_MSG_CODE_LOAD_DONE 0x11000000 1013 #define DRV_MSG_CODE_INIT_HW 0x12000000 1014 #define DRV_MSG_CODE_UNLOAD_REQ 0x20000000 1015 #define DRV_MSG_CODE_UNLOAD_DONE 0x21000000 1016 #define DRV_MSG_CODE_INIT_PHY 0x22000000 1017 /* Params - FORCE - Reinitialize the link regardless of LFA */ 1018 /* - DONT_CARE - Don't flap the link if up */ 1019 #define DRV_MSG_CODE_LINK_RESET 0x23000000 1020 1021 /* Vitaly: LLDP commands */ 1022 #define DRV_MSG_CODE_SET_LLDP 0x24000000 1023 #define DRV_MSG_CODE_SET_DCBX 0x25000000 1024 /* OneView feature driver HSI*/ 1025 #define DRV_MSG_CODE_OV_UPDATE_CURR_CFG 0x26000000 1026 #define DRV_MSG_CODE_OV_UPDATE_BUS_NUM 0x27000000 1027 #define DRV_MSG_CODE_OV_UPDATE_BOOT_PROGRESS 0x28000000 1028 #define DRV_MSG_CODE_OV_UPDATE_STORM_FW_VER 0x29000000 1029 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE 0x31000000 1030 #define DRV_MSG_CODE_BW_UPDATE_ACK 0x32000000 1031 #define DRV_MSG_CODE_OV_UPDATE_MTU 0x33000000 1032 1033 #define DRV_MSG_CODE_NIG_DRAIN 0x30000000 1034 1035 /* DRV_MB Param: driver version supp, FW_MB param: MFW version supp, 1036 * data: struct resource_info 1037 */ 1038 #define DRV_MSG_GET_RESOURCE_ALLOC_MSG 0x34000000 1039 1040 /*deprecated don't use*/ 1041 #define DRV_MSG_CODE_INITIATE_FLR_DEPRECATED 0x02000000 1042 #define DRV_MSG_CODE_INITIATE_PF_FLR 0x02010000 1043 #define DRV_MSG_CODE_VF_DISABLED_DONE 0xc0000000 1044 #define DRV_MSG_CODE_CFG_VF_MSIX 0xc0010000 1045 /* Param is either DRV_MB_PARAM_NVM_PUT_FILE_BEGIN_MFW/IMAGE */ 1046 #define DRV_MSG_CODE_NVM_PUT_FILE_BEGIN 0x00010000 1047 /* Param should be set to the transaction size (up to 64 bytes) */ 1048 #define DRV_MSG_CODE_NVM_PUT_FILE_DATA 0x00020000 1049 /* MFW will place the file offset and len in file_att struct */ 1050 #define DRV_MSG_CODE_NVM_GET_FILE_ATT 0x00030000 1051 /* Read 32bytes of nvram data. Param is [0:23] – Offset [24:31] – 1052 * Len in Bytes 1053 */ 1054 #define DRV_MSG_CODE_NVM_READ_NVRAM 0x00050000 1055 /* Writes up to 32Bytes to nvram. Param is [0:23] – Offset [24:31] – 1056 * Len in Bytes. In case this address is in the range of secured file in 1057 * secured mode, the operation will fail 1058 */ 1059 #define DRV_MSG_CODE_NVM_WRITE_NVRAM 0x00060000 1060 /* Delete a file from nvram. Param is image_type. */ 1061 #define DRV_MSG_CODE_NVM_DEL_FILE 0x00080000 1062 /* Reset MCP when no NVM operation is going on, and no drivers are loaded. 1063 * In case operation succeed, MCP will not ack back. 1064 */ 1065 #define DRV_MSG_CODE_MCP_RESET 0x00090000 1066 /* Temporary command to set secure mode, where the param is 0 (None secure) / 1067 * 1 (Secure) / 2 (Full-Secure) 1068 */ 1069 #define DRV_MSG_CODE_SET_SECURE_MODE 0x000a0000 1070 /* Param: [0:15] - Address, [16:18] - lane# (0/1/2/3 - for single lane, 1071 * 4/5 - for dual lanes, 6 - for all lanes, [28] - PMD reg, [29] - select port, 1072 * [30:31] - port 1073 */ 1074 #define DRV_MSG_CODE_PHY_RAW_READ 0x000b0000 1075 /* Param: [0:15] - Address, [16:18] - lane# (0/1/2/3 - for single lane, 1076 * 4/5 - for dual lanes, 6 - for all lanes, [28] - PMD reg, [29] - select port, 1077 * [30:31] - port 1078 */ 1079 #define DRV_MSG_CODE_PHY_RAW_WRITE 0x000c0000 1080 /* Param: [0:15] - Address, [30:31] - port */ 1081 #define DRV_MSG_CODE_PHY_CORE_READ 0x000d0000 1082 /* Param: [0:15] - Address, [30:31] - port */ 1083 #define DRV_MSG_CODE_PHY_CORE_WRITE 0x000e0000 1084 /* Param: [0:3] - version, [4:15] - name (null terminated) */ 1085 #define DRV_MSG_CODE_SET_VERSION 0x000f0000 1086 /* Halts the MCP. To resume MCP, user will need to use 1087 * MCP_REG_CPU_STATE/MCP_REG_CPU_MODE registers. 1088 */ 1089 #define DRV_MSG_CODE_MCP_HALT 0x00100000 1090 /* Host shall provide buffer and size for MFW */ 1091 #define DRV_MSG_CODE_PMD_DIAG_DUMP 0x00140000 1092 /* Host shall provide buffer and size for MFW */ 1093 #define DRV_MSG_CODE_PMD_DIAG_EYE 0x00150000 1094 /* Param: [0:1] - Port, [2:7] - read size, [8:15] - I2C address, 1095 * [16:31] - offset 1096 */ 1097 #define DRV_MSG_CODE_TRANSCEIVER_READ 0x00160000 1098 /* Param: [0:1] - Port, [2:7] - write size, [8:15] - I2C address, 1099 * [16:31] - offset 1100 */ 1101 #define DRV_MSG_CODE_TRANSCEIVER_WRITE 0x00170000 1102 1103 /* Set virtual mac address, params [31:6] - reserved, [5:4] - type, 1104 * [3:0] - func, drv_data[7:0] - MAC/WWNN/WWPN 1105 */ 1106 #define DRV_MSG_CODE_SET_VMAC 0x00110000 1107 /* Set virtual mac address, params [31:6] - reserved, [5:4] - type, 1108 * [3:0] - func, drv_data[7:0] - MAC/WWNN/WWPN 1109 */ 1110 #define DRV_MSG_CODE_GET_VMAC 0x00120000 1111 #define DRV_MSG_CODE_VMAC_TYPE_MAC 1 1112 #define DRV_MSG_CODE_VMAC_TYPE_WWNN 2 1113 #define DRV_MSG_CODE_VMAC_TYPE_WWPN 3 1114 1115 /* Get statistics from pf, params [31:4] - reserved, [3:0] - stats type */ 1116 #define DRV_MSG_CODE_GET_STATS 0x00130000 1117 #define DRV_MSG_CODE_STATS_TYPE_LAN 1 1118 #define DRV_MSG_CODE_STATS_TYPE_FCOE 2 1119 #define DRV_MSG_CODE_STATS_TYPE_ISCSI 3 1120 #define DRV_MSG_CODE_STATS_TYPE_RDMA 4 1121 1122 /* indicate OCBB related information */ 1123 #define DRV_MSG_CODE_OCBB_DATA 0x00180000 1124 1125 /* Set function BW, params[15:8] - min, params[7:0] - max */ 1126 #define DRV_MSG_CODE_SET_BW 0x00190000 1127 #define BW_MAX_MASK 0x000000ff 1128 #define BW_MAX_SHIFT 0 1129 #define BW_MIN_MASK 0x0000ff00 1130 #define BW_MIN_SHIFT 8 1131 1132 /* When param is set to 1, all parities will be masked(disabled). When params 1133 * are set to 0, parities will be unmasked again. 1134 */ 1135 #define DRV_MSG_CODE_MASK_PARITIES 0x001a0000 1136 /* param[0] - Simulate fan failure, param[1] - simulate over temp. */ 1137 #define DRV_MSG_CODE_INDUCE_FAILURE 0x001b0000 1138 #define DRV_MSG_FAN_FAILURE_TYPE (1 << 0) 1139 #define DRV_MSG_TEMPERATURE_FAILURE_TYPE (1 << 1) 1140 1141 /* Param: [0:15] - gpio number */ 1142 #define DRV_MSG_CODE_GPIO_READ 0x001c0000 1143 /* Param: [0:15] - gpio number, [16:31] - gpio value */ 1144 #define DRV_MSG_CODE_GPIO_WRITE 0x001d0000 1145 /* Param: [0:15] - gpio number */ 1146 #define DRV_MSG_CODE_GPIO_INFO 0x00270000 1147 1148 /* Param: [0:7] - test enum, [8:15] - image index, [16:31] - reserved */ 1149 #define DRV_MSG_CODE_BIST_TEST 0x001e0000 1150 #define DRV_MSG_CODE_GET_TEMPERATURE 0x001f0000 1151 1152 /* Set LED mode params :0 operational, 1 LED turn ON, 2 LED turn OFF */ 1153 #define DRV_MSG_CODE_SET_LED_MODE 0x00200000 1154 /* drv_data[7:0] - EPOC in seconds, drv_data[15:8] - 1155 * driver version (MAJ MIN BUILD SUB) 1156 */ 1157 #define DRV_MSG_CODE_TIMESTAMP 0x00210000 1158 /* This is an empty mailbox just return OK*/ 1159 #define DRV_MSG_CODE_EMPTY_MB 0x00220000 1160 /* Param[0:4] - resource number (0-31), Param[5:7] - opcode, 1161 * param[15:8] - age 1162 */ 1163 #define DRV_MSG_CODE_RESOURCE_CMD 0x00230000 1164 1165 /* request resource ownership with default aging */ 1166 #define RESOURCE_OPCODE_REQ 1 1167 /* request resource ownership without aging */ 1168 #define RESOURCE_OPCODE_REQ_WO_AGING 2 1169 /* request resource ownership with specific aging timer (in seconds) */ 1170 #define RESOURCE_OPCODE_REQ_W_AGING 3 1171 #define RESOURCE_OPCODE_RELEASE 4 /* release resource */ 1172 #define RESOURCE_OPCODE_FORCE_RELEASE 5 /* force resource release */ 1173 1174 /* resource is free and granted to requester */ 1175 #define RESOURCE_OPCODE_GNT 1 1176 /* resource is busy, param[7:0] indicates owner as follow 0-15 = PF0-15, 1177 * 16 = MFW, 17 = diag over serial 1178 */ 1179 #define RESOURCE_OPCODE_BUSY 2 1180 /* indicate release request was acknowledged */ 1181 #define RESOURCE_OPCODE_RELEASED 3 1182 /* indicate release request was previously received by other owner */ 1183 #define RESOURCE_OPCODE_RELEASED_PREVIOUS 4 1184 /* indicate wrong owner during release */ 1185 #define RESOURCE_OPCODE_WRONG_OWNER 5 1186 #define RESOURCE_OPCODE_UNKNOWN_CMD 255 1187 /* dedicate resource 0 for dump */ 1188 #define RESOURCE_DUMP (1 << 0) 1189 1190 #define DRV_MSG_CODE_GET_MBA_VERSION 0x00240000 /* Get MBA version */ 1191 1192 /* Send crash dump commands with param[3:0] - opcode */ 1193 #define DRV_MSG_CODE_MDUMP_CMD 0x00250000 1194 #define MDUMP_DRV_PARAM_OPCODE_MASK 0x0000000f 1195 /* acknowledge reception of error indication */ 1196 #define DRV_MSG_CODE_MDUMP_ACK 0x01 1197 /* set epoc and personality as follow: drv_data[3:0] - epoch, 1198 * drv_data[7:4] - personality 1199 */ 1200 #define DRV_MSG_CODE_MDUMP_SET_VALUES 0x02 1201 /* trigger crash dump procedure */ 1202 #define DRV_MSG_CODE_MDUMP_TRIGGER 0x03 1203 /* Request valid logs and config words */ 1204 #define DRV_MSG_CODE_MDUMP_GET_CONFIG 0x04 1205 /* Set triggers mask. drv_mb_param should indicate (bitwise) which trigger 1206 * enabled 1207 */ 1208 #define DRV_MSG_CODE_MDUMP_SET_ENABLE 0x05 1209 #define DRV_MSG_CODE_MDUMP_CLEAR_LOGS 0x06 /* Clear all logs */ 1210 1211 1212 #define DRV_MSG_CODE_MEM_ECC_EVENTS 0x00260000 /* Param: None */ 1213 1214 #define DRV_MSG_SEQ_NUMBER_MASK 0x0000ffff 1215 1216 u32 drv_mb_param; 1217 /* UNLOAD_REQ params */ 1218 #define DRV_MB_PARAM_UNLOAD_WOL_UNKNOWN 0x00000000 1219 #define DRV_MB_PARAM_UNLOAD_WOL_MCP 0x00000001 1220 #define DRV_MB_PARAM_UNLOAD_WOL_DISABLED 0x00000002 1221 #define DRV_MB_PARAM_UNLOAD_WOL_ENABLED 0x00000003 1222 1223 /* UNLOAD_DONE_params */ 1224 #define DRV_MB_PARAM_UNLOAD_NON_D3_POWER 0x00000001 1225 1226 /* INIT_PHY params */ 1227 #define DRV_MB_PARAM_INIT_PHY_FORCE 0x00000001 1228 #define DRV_MB_PARAM_INIT_PHY_DONT_CARE 0x00000002 1229 1230 /* LLDP / DCBX params*/ 1231 #define DRV_MB_PARAM_LLDP_SEND_MASK 0x00000001 1232 #define DRV_MB_PARAM_LLDP_SEND_SHIFT 0 1233 #define DRV_MB_PARAM_LLDP_AGENT_MASK 0x00000006 1234 #define DRV_MB_PARAM_LLDP_AGENT_SHIFT 1 1235 #define DRV_MB_PARAM_DCBX_NOTIFY_MASK 0x00000008 1236 #define DRV_MB_PARAM_DCBX_NOTIFY_SHIFT 3 1237 1238 #define DRV_MB_PARAM_NIG_DRAIN_PERIOD_MS_MASK 0x000000FF 1239 #define DRV_MB_PARAM_NIG_DRAIN_PERIOD_MS_SHIFT 0 1240 1241 #define DRV_MB_PARAM_NVM_PUT_FILE_BEGIN_MFW 0x1 1242 #define DRV_MB_PARAM_NVM_PUT_FILE_BEGIN_IMAGE 0x2 1243 1244 #define DRV_MB_PARAM_NVM_OFFSET_SHIFT 0 1245 #define DRV_MB_PARAM_NVM_OFFSET_MASK 0x00FFFFFF 1246 #define DRV_MB_PARAM_NVM_LEN_SHIFT 24 1247 #define DRV_MB_PARAM_NVM_LEN_MASK 0xFF000000 1248 1249 #define DRV_MB_PARAM_PHY_ADDR_SHIFT 0 1250 #define DRV_MB_PARAM_PHY_ADDR_MASK 0x1FF0FFFF 1251 #define DRV_MB_PARAM_PHY_LANE_SHIFT 16 1252 #define DRV_MB_PARAM_PHY_LANE_MASK 0x000F0000 1253 #define DRV_MB_PARAM_PHY_SELECT_PORT_SHIFT 29 1254 #define DRV_MB_PARAM_PHY_SELECT_PORT_MASK 0x20000000 1255 #define DRV_MB_PARAM_PHY_PORT_SHIFT 30 1256 #define DRV_MB_PARAM_PHY_PORT_MASK 0xc0000000 1257 1258 #define DRV_MB_PARAM_PHYMOD_LANE_SHIFT 0 1259 #define DRV_MB_PARAM_PHYMOD_LANE_MASK 0x000000FF 1260 #define DRV_MB_PARAM_PHYMOD_SIZE_SHIFT 8 1261 #define DRV_MB_PARAM_PHYMOD_SIZE_MASK 0x000FFF00 1262 /* configure vf MSIX params*/ 1263 #define DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_SHIFT 0 1264 #define DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_MASK 0x000000FF 1265 #define DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_SHIFT 8 1266 #define DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_MASK 0x0000FF00 1267 1268 /* OneView configuration parametres */ 1269 #define DRV_MB_PARAM_OV_CURR_CFG_SHIFT 0 1270 #define DRV_MB_PARAM_OV_CURR_CFG_MASK 0x0000000F 1271 #define DRV_MB_PARAM_OV_CURR_CFG_NONE 0 1272 #define DRV_MB_PARAM_OV_CURR_CFG_OS 1 1273 #define DRV_MB_PARAM_OV_CURR_CFG_VENDOR_SPEC 2 1274 #define DRV_MB_PARAM_OV_CURR_CFG_OTHER 3 1275 #define DRV_MB_PARAM_OV_CURR_CFG_VC_CLP 4 1276 #define DRV_MB_PARAM_OV_CURR_CFG_CNU 5 1277 #define DRV_MB_PARAM_OV_CURR_CFG_DCI 6 1278 #define DRV_MB_PARAM_OV_CURR_CFG_HII 7 1279 1280 #define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_SHIFT 0 1281 #define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_MASK 0x000000FF 1282 #define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_NONE (1 << 0) 1283 #define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_ISCSI_IP_ACQUIRED (1 << 1) 1284 #define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_FCOE_FABRIC_LOGIN_SUCCESS (1 << 1) 1285 #define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_TRARGET_FOUND (1 << 2) 1286 #define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_ISCSI_CHAP_SUCCESS (1 << 3) 1287 #define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_FCOE_LUN_FOUND (1 << 3) 1288 #define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_LOGGED_INTO_TGT (1 << 4) 1289 #define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_IMG_DOWNLOADED (1 << 5) 1290 #define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_OS_HANDOFF (1 << 6) 1291 #define DRV_MB_PARAM_OV_UPDATE_BOOT_COMPLETED 0 1292 1293 #define DRV_MB_PARAM_OV_PCI_BUS_NUM_SHIFT 0 1294 #define DRV_MB_PARAM_OV_PCI_BUS_NUM_MASK 0x000000FF 1295 1296 #define DRV_MB_PARAM_OV_STORM_FW_VER_SHIFT 0 1297 #define DRV_MB_PARAM_OV_STORM_FW_VER_MASK 0xFFFFFFFF 1298 #define DRV_MB_PARAM_OV_STORM_FW_VER_MAJOR_MASK 0xFF000000 1299 #define DRV_MB_PARAM_OV_STORM_FW_VER_MINOR_MASK 0x00FF0000 1300 #define DRV_MB_PARAM_OV_STORM_FW_VER_BUILD_MASK 0x0000FF00 1301 #define DRV_MB_PARAM_OV_STORM_FW_VER_DROP_MASK 0x000000FF 1302 1303 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_SHIFT 0 1304 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_MASK 0xF 1305 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_UNKNOWN 0x1 1306 /* Not Installed*/ 1307 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_NOT_LOADED 0x2 1308 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_LOADING 0x3 1309 /* installed but disabled by user/admin/OS */ 1310 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_DISABLED 0x4 1311 /* installed and active */ 1312 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_ACTIVE 0x5 1313 1314 #define DRV_MB_PARAM_OV_MTU_SIZE_SHIFT 0 1315 #define DRV_MB_PARAM_OV_MTU_SIZE_MASK 0xFFFFFFFF 1316 1317 #define DRV_MB_PARAM_SET_LED_MODE_OPER 0x0 1318 #define DRV_MB_PARAM_SET_LED_MODE_ON 0x1 1319 #define DRV_MB_PARAM_SET_LED_MODE_OFF 0x2 1320 1321 #define DRV_MB_PARAM_TRANSCEIVER_PORT_SHIFT 0 1322 #define DRV_MB_PARAM_TRANSCEIVER_PORT_MASK 0x00000003 1323 #define DRV_MB_PARAM_TRANSCEIVER_SIZE_SHIFT 2 1324 #define DRV_MB_PARAM_TRANSCEIVER_SIZE_MASK 0x000000FC 1325 #define DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_SHIFT 8 1326 #define DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_MASK 0x0000FF00 1327 #define DRV_MB_PARAM_TRANSCEIVER_OFFSET_SHIFT 16 1328 #define DRV_MB_PARAM_TRANSCEIVER_OFFSET_MASK 0xFFFF0000 1329 1330 #define DRV_MB_PARAM_GPIO_NUMBER_SHIFT 0 1331 #define DRV_MB_PARAM_GPIO_NUMBER_MASK 0x0000FFFF 1332 #define DRV_MB_PARAM_GPIO_VALUE_SHIFT 16 1333 #define DRV_MB_PARAM_GPIO_VALUE_MASK 0xFFFF0000 1334 #define DRV_MB_PARAM_GPIO_DIRECTION_SHIFT 16 1335 #define DRV_MB_PARAM_GPIO_DIRECTION_MASK 0x00FF0000 1336 #define DRV_MB_PARAM_GPIO_CTRL_SHIFT 24 1337 #define DRV_MB_PARAM_GPIO_CTRL_MASK 0xFF000000 1338 1339 /* Resource Allocation params - Driver version support*/ 1340 #define DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_MASK 0xFFFF0000 1341 #define DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_SHIFT 16 1342 #define DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_MASK 0x0000FFFF 1343 #define DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_SHIFT 0 1344 1345 #define DRV_MB_PARAM_BIST_UNKNOWN_TEST 0 1346 #define DRV_MB_PARAM_BIST_REGISTER_TEST 1 1347 #define DRV_MB_PARAM_BIST_CLOCK_TEST 2 1348 #define DRV_MB_PARAM_BIST_NVM_TEST_NUM_IMAGES 3 1349 #define DRV_MB_PARAM_BIST_NVM_TEST_IMAGE_BY_INDEX 4 1350 1351 #define DRV_MB_PARAM_BIST_RC_UNKNOWN 0 1352 #define DRV_MB_PARAM_BIST_RC_PASSED 1 1353 #define DRV_MB_PARAM_BIST_RC_FAILED 2 1354 #define DRV_MB_PARAM_BIST_RC_INVALID_PARAMETER 3 1355 1356 #define DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT 0 1357 #define DRV_MB_PARAM_BIST_TEST_INDEX_MASK 0x000000FF 1358 #define DRV_MB_PARAM_BIST_TEST_IMAGE_INDEX_SHIFT 8 1359 #define DRV_MB_PARAM_BIST_TEST_IMAGE_INDEX_MASK 0x0000FF00 1360 1361 u32 fw_mb_header; 1362 #define FW_MSG_CODE_MASK 0xffff0000 1363 #define FW_MSG_CODE_DRV_LOAD_ENGINE 0x10100000 1364 #define FW_MSG_CODE_DRV_LOAD_PORT 0x10110000 1365 #define FW_MSG_CODE_DRV_LOAD_FUNCTION 0x10120000 1366 #define FW_MSG_CODE_DRV_LOAD_REFUSED_PDA 0x10200000 1367 #define FW_MSG_CODE_DRV_LOAD_REFUSED_HSI 0x10210000 1368 #define FW_MSG_CODE_DRV_LOAD_REFUSED_DIAG 0x10220000 1369 #define FW_MSG_CODE_DRV_LOAD_DONE 0x11100000 1370 #define FW_MSG_CODE_DRV_UNLOAD_ENGINE 0x20110000 1371 #define FW_MSG_CODE_DRV_UNLOAD_PORT 0x20120000 1372 #define FW_MSG_CODE_DRV_UNLOAD_FUNCTION 0x20130000 1373 #define FW_MSG_CODE_DRV_UNLOAD_DONE 0x21100000 1374 #define FW_MSG_CODE_INIT_PHY_DONE 0x21200000 1375 #define FW_MSG_CODE_INIT_PHY_ERR_INVALID_ARGS 0x21300000 1376 #define FW_MSG_CODE_LINK_RESET_DONE 0x23000000 1377 #define FW_MSG_CODE_SET_LLDP_DONE 0x24000000 1378 #define FW_MSG_CODE_SET_LLDP_UNSUPPORTED_AGENT 0x24010000 1379 #define FW_MSG_CODE_SET_DCBX_DONE 0x25000000 1380 #define FW_MSG_CODE_UPDATE_CURR_CFG_DONE 0x26000000 1381 #define FW_MSG_CODE_UPDATE_BUS_NUM_DONE 0x27000000 1382 #define FW_MSG_CODE_UPDATE_BOOT_PROGRESS_DONE 0x28000000 1383 #define FW_MSG_CODE_UPDATE_STORM_FW_VER_DONE 0x29000000 1384 #define FW_MSG_CODE_UPDATE_DRIVER_STATE_DONE 0x31000000 1385 #define FW_MSG_CODE_DRV_MSG_CODE_BW_UPDATE_DONE 0x32000000 1386 #define FW_MSG_CODE_DRV_MSG_CODE_MTU_SIZE_DONE 0x33000000 1387 #define FW_MSG_CODE_RESOURCE_ALLOC_OK 0x34000000 1388 #define FW_MSG_CODE_RESOURCE_ALLOC_UNKNOWN 0x35000000 1389 #define FW_MSG_CODE_RESOURCE_ALLOC_DEPRECATED 0x36000000 1390 #define FW_MSG_CODE_RESOURCE_ALLOC_GEN_ERR 0x37000000 1391 #define FW_MSG_CODE_NIG_DRAIN_DONE 0x30000000 1392 #define FW_MSG_CODE_VF_DISABLED_DONE 0xb0000000 1393 #define FW_MSG_CODE_DRV_CFG_VF_MSIX_DONE 0xb0010000 1394 #define FW_MSG_CODE_FLR_ACK 0x02000000 1395 #define FW_MSG_CODE_FLR_NACK 0x02100000 1396 #define FW_MSG_CODE_SET_DRIVER_DONE 0x02200000 1397 #define FW_MSG_CODE_SET_VMAC_SUCCESS 0x02300000 1398 #define FW_MSG_CODE_SET_VMAC_FAIL 0x02400000 1399 1400 #define FW_MSG_CODE_NVM_OK 0x00010000 1401 #define FW_MSG_CODE_NVM_INVALID_MODE 0x00020000 1402 #define FW_MSG_CODE_NVM_PREV_CMD_WAS_NOT_FINISHED 0x00030000 1403 #define FW_MSG_CODE_NVM_FAILED_TO_ALLOCATE_PAGE 0x00040000 1404 #define FW_MSG_CODE_NVM_INVALID_DIR_FOUND 0x00050000 1405 #define FW_MSG_CODE_NVM_PAGE_NOT_FOUND 0x00060000 1406 #define FW_MSG_CODE_NVM_FAILED_PARSING_BNDLE_HEADER 0x00070000 1407 #define FW_MSG_CODE_NVM_FAILED_PARSING_IMAGE_HEADER 0x00080000 1408 #define FW_MSG_CODE_NVM_PARSING_OUT_OF_SYNC 0x00090000 1409 #define FW_MSG_CODE_NVM_FAILED_UPDATING_DIR 0x000a0000 1410 #define FW_MSG_CODE_NVM_FAILED_TO_FREE_PAGE 0x000b0000 1411 #define FW_MSG_CODE_NVM_FILE_NOT_FOUND 0x000c0000 1412 #define FW_MSG_CODE_NVM_OPERATION_FAILED 0x000d0000 1413 #define FW_MSG_CODE_NVM_FAILED_UNALIGNED 0x000e0000 1414 #define FW_MSG_CODE_NVM_BAD_OFFSET 0x000f0000 1415 #define FW_MSG_CODE_NVM_BAD_SIGNATURE 0x00100000 1416 #define FW_MSG_CODE_NVM_FILE_READ_ONLY 0x00200000 1417 #define FW_MSG_CODE_NVM_UNKNOWN_FILE 0x00300000 1418 #define FW_MSG_CODE_NVM_PUT_FILE_FINISH_OK 0x00400000 1419 /* MFW reject "mcp reset" command if one of the drivers is up */ 1420 #define FW_MSG_CODE_MCP_RESET_REJECT 0x00600000 1421 #define FW_MSG_CODE_PHY_OK 0x00110000 1422 #define FW_MSG_CODE_PHY_ERROR 0x00120000 1423 #define FW_MSG_CODE_SET_SECURE_MODE_ERROR 0x00130000 1424 #define FW_MSG_CODE_SET_SECURE_MODE_OK 0x00140000 1425 #define FW_MSG_MODE_PHY_PRIVILEGE_ERROR 0x00150000 1426 #define FW_MSG_CODE_OK 0x00160000 1427 #define FW_MSG_CODE_LED_MODE_INVALID 0x00170000 1428 #define FW_MSG_CODE_PHY_DIAG_OK 0x00160000 1429 #define FW_MSG_CODE_PHY_DIAG_ERROR 0x00170000 1430 #define FW_MSG_CODE_INIT_HW_FAILED_TO_ALLOCATE_PAGE 0x00040000 1431 #define FW_MSG_CODE_INIT_HW_FAILED_BAD_STATE 0x00170000 1432 #define FW_MSG_CODE_INIT_HW_FAILED_TO_SET_WINDOW 0x000d0000 1433 #define FW_MSG_CODE_INIT_HW_FAILED_NO_IMAGE 0x000c0000 1434 #define FW_MSG_CODE_INIT_HW_FAILED_VERSION_MISMATCH 0x00100000 1435 #define FW_MSG_CODE_TRANSCEIVER_DIAG_OK 0x00160000 1436 #define FW_MSG_CODE_TRANSCEIVER_DIAG_ERROR 0x00170000 1437 #define FW_MSG_CODE_TRANSCEIVER_NOT_PRESENT 0x00020000 1438 #define FW_MSG_CODE_TRANSCEIVER_BAD_BUFFER_SIZE 0x000f0000 1439 #define FW_MSG_CODE_GPIO_OK 0x00160000 1440 #define FW_MSG_CODE_GPIO_DIRECTION_ERR 0x00170000 1441 #define FW_MSG_CODE_GPIO_CTRL_ERR 0x00020000 1442 #define FW_MSG_CODE_GPIO_INVALID 0x000f0000 1443 #define FW_MSG_CODE_GPIO_INVALID_VALUE 0x00050000 1444 #define FW_MSG_CODE_BIST_TEST_INVALID 0x000f0000 1445 1446 /* mdump related response codes */ 1447 #define FW_MSG_CODE_MDUMP_NO_IMAGE_FOUND 0x00010000 1448 #define FW_MSG_CODE_MDUMP_ALLOC_FAILED 0x00020000 1449 #define FW_MSG_CODE_MDUMP_INVALID_CMD 0x00030000 1450 #define FW_MSG_CODE_MDUMP_IN_PROGRESS 0x00040000 1451 #define FW_MSG_CODE_MDUMP_WRITE_FAILED 0x00050000 1452 1453 #define FW_MSG_SEQ_NUMBER_MASK 0x0000ffff 1454 1455 1456 u32 fw_mb_param; 1457 /* Resource Allocation params - MFW version support*/ 1458 #define FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_MASK 0xFFFF0000 1459 #define FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_SHIFT 16 1460 #define FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_MASK 0x0000FFFF 1461 #define FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_SHIFT 0 1462 1463 1464 u32 drv_pulse_mb; 1465 #define DRV_PULSE_SEQ_MASK 0x00007fff 1466 #define DRV_PULSE_SYSTEM_TIME_MASK 0xffff0000 1467 /* 1468 * The system time is in the format of 1469 * (year-2001)*12*32 + month*32 + day. 1470 */ 1471 #define DRV_PULSE_ALWAYS_ALIVE 0x00008000 1472 /* 1473 * Indicate to the firmware not to go into the 1474 * OS-absent when it is not getting driver pulse. 1475 * This is used for debugging as well for PXE(MBA). 1476 */ 1477 1478 u32 mcp_pulse_mb; 1479 #define MCP_PULSE_SEQ_MASK 0x00007fff 1480 #define MCP_PULSE_ALWAYS_ALIVE 0x00008000 1481 /* Indicates to the driver not to assert due to lack 1482 * of MCP response 1483 */ 1484 #define MCP_EVENT_MASK 0xffff0000 1485 #define MCP_EVENT_OTHER_DRIVER_RESET_REQ 0x00010000 1486 1487 /* The union data is used by the driver to pass parameters to the scratchpad. */ 1488 1489 union drv_union_data union_data; 1490 1491 }; 1492 1493 /* MFW - DRV MB */ 1494 /********************************************************************** 1495 * Description 1496 * Incremental Aggregative 1497 * 8-bit MFW counter per message 1498 * 8-bit ack-counter per message 1499 * Capabilities 1500 * Provides up to 256 aggregative message per type 1501 * Provides 4 message types in dword 1502 * Message type pointers to byte offset 1503 * Backward Compatibility by using sizeof for the counters. 1504 * No lock requires for 32bit messages 1505 * Limitations: 1506 * In case of messages greater than 32bit, a dedicated mechanism(e.g lock) 1507 * is required to prevent data corruption. 1508 **********************************************************************/ 1509 enum MFW_DRV_MSG_TYPE { 1510 MFW_DRV_MSG_LINK_CHANGE, 1511 MFW_DRV_MSG_FLR_FW_ACK_FAILED, 1512 MFW_DRV_MSG_VF_DISABLED, 1513 MFW_DRV_MSG_LLDP_DATA_UPDATED, 1514 MFW_DRV_MSG_DCBX_REMOTE_MIB_UPDATED, 1515 MFW_DRV_MSG_DCBX_OPERATIONAL_MIB_UPDATED, 1516 MFW_DRV_MSG_ERROR_RECOVERY, 1517 MFW_DRV_MSG_BW_UPDATE, 1518 MFW_DRV_MSG_S_TAG_UPDATE, 1519 MFW_DRV_MSG_GET_LAN_STATS, 1520 MFW_DRV_MSG_GET_FCOE_STATS, 1521 MFW_DRV_MSG_GET_ISCSI_STATS, 1522 MFW_DRV_MSG_GET_RDMA_STATS, 1523 MFW_DRV_MSG_FAILURE_DETECTED, 1524 MFW_DRV_MSG_TRANSCEIVER_STATE_CHANGE, 1525 MFW_DRV_MSG_CRITICAL_ERROR_OCCURRED, 1526 MFW_DRV_MSG_MAX 1527 }; 1528 1529 #define MFW_DRV_MSG_MAX_DWORDS(msgs) (((msgs - 1) >> 2) + 1) 1530 #define MFW_DRV_MSG_DWORD(msg_id) (msg_id >> 2) 1531 #define MFW_DRV_MSG_OFFSET(msg_id) ((msg_id & 0x3) << 3) 1532 #define MFW_DRV_MSG_MASK(msg_id) (0xff << MFW_DRV_MSG_OFFSET(msg_id)) 1533 1534 #ifdef BIG_ENDIAN /* Like MFW */ 1535 #define DRV_ACK_MSG(msg_p, msg_id) \ 1536 ((u8)((u8 *)msg_p)[msg_id]++;) 1537 #else 1538 #define DRV_ACK_MSG(msg_p, msg_id) \ 1539 ((u8)((u8 *)msg_p)[((msg_id & ~3) | ((~msg_id) & 3))]++;) 1540 #endif 1541 1542 #define MFW_DRV_UPDATE(shmem_func, msg_id) \ 1543 ((u8)((u8 *)(MFW_MB_P(shmem_func)->msg))[msg_id]++;) 1544 1545 struct public_mfw_mb { 1546 u32 sup_msgs; /* Assigend with MFW_DRV_MSG_MAX */ 1547 /* Incremented by the MFW */ 1548 u32 msg[MFW_DRV_MSG_MAX_DWORDS(MFW_DRV_MSG_MAX)]; 1549 /* Incremented by the driver */ 1550 u32 ack[MFW_DRV_MSG_MAX_DWORDS(MFW_DRV_MSG_MAX)]; 1551 }; 1552 1553 /**************************************/ 1554 /* */ 1555 /* P U B L I C D A T A */ 1556 /* */ 1557 /**************************************/ 1558 enum public_sections { 1559 PUBLIC_DRV_MB, /* Points to the first drv_mb of path0 */ 1560 PUBLIC_MFW_MB, /* Points to the first mfw_mb of path0 */ 1561 PUBLIC_GLOBAL, 1562 PUBLIC_PATH, 1563 PUBLIC_PORT, 1564 PUBLIC_FUNC, 1565 PUBLIC_MAX_SECTIONS 1566 }; 1567 1568 struct drv_ver_info_stc { 1569 u32 ver; 1570 u8 name[32]; 1571 }; 1572 1573 /* Runtime data needs about 1/2K. We use 2K to be on the safe side. 1574 * Please make sure data does not exceed this size. 1575 */ 1576 #define NUM_RUNTIME_DWORDS 16 1577 struct drv_init_hw_stc { 1578 u32 init_hw_bitmask[NUM_RUNTIME_DWORDS]; 1579 u32 init_hw_data[NUM_RUNTIME_DWORDS * 32]; 1580 }; 1581 1582 struct mcp_public_data { 1583 /* The sections fields is an array */ 1584 u32 num_sections; 1585 offsize_t sections[PUBLIC_MAX_SECTIONS]; 1586 struct public_drv_mb drv_mb[MCP_GLOB_FUNC_MAX]; 1587 struct public_mfw_mb mfw_mb[MCP_GLOB_FUNC_MAX]; 1588 struct public_global global; 1589 struct public_path path[MCP_GLOB_PATH_MAX]; 1590 struct public_port port[MCP_GLOB_PORT_MAX]; 1591 struct public_func func[MCP_GLOB_FUNC_MAX]; 1592 }; 1593 1594 #define I2C_TRANSCEIVER_ADDR 0xa0 1595 #define MAX_I2C_TRANSACTION_SIZE 16 1596 #define MAX_I2C_TRANSCEIVER_PAGE_SIZE 256 1597 1598 #endif /* MCP_PUBLIC_H */ 1599