1 /* 2 * Copyright (c) 2016 QLogic Corporation. 3 * All rights reserved. 4 * www.qlogic.com 5 * 6 * See LICENSE.qede_pmd for copyright and licensing details. 7 */ 8 9 /**************************************************************************** 10 * 11 * Name: mcp_public.h 12 * 13 * Description: MCP public data 14 * 15 * Created: 13/01/2013 yanivr 16 * 17 ****************************************************************************/ 18 19 #ifndef MCP_PUBLIC_H 20 #define MCP_PUBLIC_H 21 22 #define VF_MAX_STATIC 192 /* In case of AH */ 23 24 #define MCP_GLOB_PATH_MAX 2 25 #define MCP_PORT_MAX 2 /* Global */ 26 #define MCP_GLOB_PORT_MAX 4 /* Global */ 27 #define MCP_GLOB_FUNC_MAX 16 /* Global */ 28 29 typedef u32 offsize_t; /* In DWORDS !!! */ 30 /* Offset from the beginning of the MCP scratchpad */ 31 #define OFFSIZE_OFFSET_SHIFT 0 32 #define OFFSIZE_OFFSET_MASK 0x0000ffff 33 /* Size of specific element (not the whole array if any) */ 34 #define OFFSIZE_SIZE_SHIFT 16 35 #define OFFSIZE_SIZE_MASK 0xffff0000 36 37 /* SECTION_OFFSET is calculating the offset in bytes out of offsize */ 38 #define SECTION_OFFSET(_offsize) \ 39 ((((_offsize & OFFSIZE_OFFSET_MASK) >> OFFSIZE_OFFSET_SHIFT) << 2)) 40 41 /* SECTION_SIZE is calculating the size in bytes out of offsize */ 42 #define SECTION_SIZE(_offsize) \ 43 (((_offsize & OFFSIZE_SIZE_MASK) >> OFFSIZE_SIZE_SHIFT) << 2) 44 45 /* SECTION_ADDR returns the GRC addr of a section, given offsize and index 46 * within section 47 */ 48 #define SECTION_ADDR(_offsize, idx) \ 49 (MCP_REG_SCRATCH + \ 50 SECTION_OFFSET(_offsize) + (SECTION_SIZE(_offsize) * idx)) 51 52 /* SECTION_OFFSIZE_ADDR returns the GRC addr to the offsize address. Use 53 * offsetof, since the OFFSETUP collide with the firmware definition 54 */ 55 #define SECTION_OFFSIZE_ADDR(_pub_base, _section) \ 56 (_pub_base + offsetof(struct mcp_public_data, sections[_section])) 57 /* PHY configuration */ 58 struct eth_phy_cfg { 59 /* 0 = autoneg, 1000/10000/20000/25000/40000/50000/100000 */ 60 u32 speed; 61 #define ETH_SPEED_AUTONEG 0 62 #define ETH_SPEED_SMARTLINQ 0x8 63 64 u32 pause; /* bitmask */ 65 #define ETH_PAUSE_NONE 0x0 66 #define ETH_PAUSE_AUTONEG 0x1 67 #define ETH_PAUSE_RX 0x2 68 #define ETH_PAUSE_TX 0x4 69 70 u32 adv_speed; /* Default should be the speed_cap_mask */ 71 u32 loopback_mode; 72 #define ETH_LOOPBACK_NONE (0) 73 /* Serdes loopback. In AH, it refers to Near End */ 74 #define ETH_LOOPBACK_INT_PHY (1) 75 #define ETH_LOOPBACK_EXT_PHY (2) /* External PHY Loopback */ 76 /* External Loopback (Require loopback plug) */ 77 #define ETH_LOOPBACK_EXT (3) 78 #define ETH_LOOPBACK_MAC (4) /* MAC Loopback - not supported */ 79 #define ETH_LOOPBACK_CNIG_AH_ONLY_0123 (5) /* Port to itself */ 80 #define ETH_LOOPBACK_CNIG_AH_ONLY_2301 (6) /* Port to Port */ 81 #define ETH_LOOPBACK_PCS_AH_ONLY (7) /* PCS loopback (TX to RX) */ 82 /* Loop RX packet from PCS to TX */ 83 #define ETH_LOOPBACK_REVERSE_MAC_AH_ONLY (8) 84 /* Remote Serdes Loopback (RX to TX) */ 85 #define ETH_LOOPBACK_INT_PHY_FEA_AH_ONLY (9) 86 87 /* Used to configure the EEE Tx LPI timer, has several modes of 88 * operation, according to bits 29:28 89 * 2'b00: Timer will be configured by nvram, output will be the value 90 * from nvram. 91 * 2'b01: Timer will be configured by nvram, output will be in 92 * 16xmicroseconds. 93 * 2'b10: bits 1:0 contain an nvram value which will be used instead 94 * of the one located in the nvram. Output will be that value. 95 * 2'b11: bits 19:0 contain the idle timer in microseconds; output 96 * will be in 16xmicroseconds. 97 * Bits 31:30 should be 2'b11 in order for EEE to be enabled. 98 */ 99 u32 eee_mode; 100 #define EEE_MODE_TIMER_USEC_MASK (0x000fffff) 101 #define EEE_MODE_TIMER_USEC_OFFSET (0) 102 #define EEE_MODE_TIMER_USEC_BALANCED_TIME (0xa00) 103 #define EEE_MODE_TIMER_USEC_AGGRESSIVE_TIME (0x100) 104 #define EEE_MODE_TIMER_USEC_LATENCY_TIME (0x6000) 105 /* Set by the driver to request status timer will be in microseconds and and not 106 * in EEE policy definition 107 */ 108 #define EEE_MODE_OUTPUT_TIME (1 << 28) 109 /* Set by the driver to override default nvm timer */ 110 #define EEE_MODE_OVERRIDE_NVRAM (1 << 29) 111 #define EEE_MODE_ENABLE_LPI (1 << 30) /* Set when */ 112 #define EEE_MODE_ADV_LPI (1 << 31) /* Set when EEE is enabled */ 113 }; 114 115 struct port_mf_cfg { 116 u32 dynamic_cfg; /* device control channel */ 117 #define PORT_MF_CFG_OV_TAG_MASK 0x0000ffff 118 #define PORT_MF_CFG_OV_TAG_SHIFT 0 119 #define PORT_MF_CFG_OV_TAG_DEFAULT PORT_MF_CFG_OV_TAG_MASK 120 121 u32 reserved[1]; 122 }; 123 124 /* DO NOT add new fields in the middle 125 * MUST be synced with struct pmm_stats_map 126 */ 127 struct eth_stats { 128 u64 r64; /* 0x00 (Offset 0x00 ) RX 64-byte frame counter*/ 129 u64 r127; /* 0x01 (Offset 0x08 ) RX 65 to 127 byte frame counter*/ 130 u64 r255; /* 0x02 (Offset 0x10 ) RX 128 to 255 byte frame counter*/ 131 u64 r511; /* 0x03 (Offset 0x18 ) RX 256 to 511 byte frame counter*/ 132 u64 r1023; /* 0x04 (Offset 0x20 ) RX 512 to 1023 byte frame counter*/ 133 /* 0x05 (Offset 0x28 ) RX 1024 to 1518 byte frame counter */ 134 u64 r1518; 135 /* 0x06 (Offset 0x30 ) RX 1519 to 1522 byte VLAN-tagged frame counter */ 136 u64 r1522; 137 u64 r2047; /* 0x07 (Offset 0x38 ) RX 1519 to 2047 byte frame counter*/ 138 u64 r4095; /* 0x08 (Offset 0x40 ) RX 2048 to 4095 byte frame counter*/ 139 u64 r9216; /* 0x09 (Offset 0x48 ) RX 4096 to 9216 byte frame counter*/ 140 /* 0x0A (Offset 0x50 ) RX 9217 to 16383 byte frame counter */ 141 u64 r16383; 142 u64 rfcs; /* 0x0F (Offset 0x58 ) RX FCS error frame counter*/ 143 u64 rxcf; /* 0x10 (Offset 0x60 ) RX control frame counter*/ 144 u64 rxpf; /* 0x11 (Offset 0x68 ) RX pause frame counter*/ 145 u64 rxpp; /* 0x12 (Offset 0x70 ) RX PFC frame counter*/ 146 u64 raln; /* 0x16 (Offset 0x78 ) RX alignment error counter*/ 147 u64 rfcr; /* 0x19 (Offset 0x80 ) RX false carrier counter */ 148 u64 rovr; /* 0x1A (Offset 0x88 ) RX oversized frame counter*/ 149 u64 rjbr; /* 0x1B (Offset 0x90 ) RX jabber frame counter */ 150 u64 rund; /* 0x34 (Offset 0x98 ) RX undersized frame counter */ 151 u64 rfrg; /* 0x35 (Offset 0xa0 ) RX fragment counter */ 152 u64 t64; /* 0x40 (Offset 0xa8 ) TX 64-byte frame counter */ 153 u64 t127; /* 0x41 (Offset 0xb0 ) TX 65 to 127 byte frame counter */ 154 u64 t255; /* 0x42 (Offset 0xb8 ) TX 128 to 255 byte frame counter*/ 155 u64 t511; /* 0x43 (Offset 0xc0 ) TX 256 to 511 byte frame counter*/ 156 u64 t1023; /* 0x44 (Offset 0xc8 ) TX 512 to 1023 byte frame counter*/ 157 /* 0x45 (Offset 0xd0 ) TX 1024 to 1518 byte frame counter */ 158 u64 t1518; 159 /* 0x47 (Offset 0xd8 ) TX 1519 to 2047 byte frame counter */ 160 u64 t2047; 161 /* 0x48 (Offset 0xe0 ) TX 2048 to 4095 byte frame counter */ 162 u64 t4095; 163 /* 0x49 (Offset 0xe8 ) TX 4096 to 9216 byte frame counter */ 164 u64 t9216; 165 /* 0x4A (Offset 0xf0 ) TX 9217 to 16383 byte frame counter */ 166 u64 t16383; 167 u64 txpf; /* 0x50 (Offset 0xf8 ) TX pause frame counter */ 168 u64 txpp; /* 0x51 (Offset 0x100) TX PFC frame counter */ 169 /* 0x6C (Offset 0x108) Transmit Logical Type LLFC message counter */ 170 u64 tlpiec; 171 u64 tncl; /* 0x6E (Offset 0x110) Transmit Total Collision Counter */ 172 u64 rbyte; /* 0x3d (Offset 0x118) RX byte counter */ 173 u64 rxuca; /* 0x0c (Offset 0x120) RX UC frame counter */ 174 u64 rxmca; /* 0x0d (Offset 0x128) RX MC frame counter */ 175 u64 rxbca; /* 0x0e (Offset 0x130) RX BC frame counter */ 176 /* 0x22 (Offset 0x138) RX good frame (good CRC, not oversized, no ERROR) */ 177 u64 rxpok; 178 u64 tbyte; /* 0x6f (Offset 0x140) TX byte counter */ 179 u64 txuca; /* 0x4d (Offset 0x148) TX UC frame counter */ 180 u64 txmca; /* 0x4e (Offset 0x150) TX MC frame counter */ 181 u64 txbca; /* 0x4f (Offset 0x158) TX BC frame counter */ 182 u64 txcf; /* 0x54 (Offset 0x160) TX control frame counter */ 183 /* HSI - Cannot add more stats to this struct. If needed, then need to open new 184 * struct 185 */ 186 187 }; 188 189 struct brb_stats { 190 u64 brb_truncate[8]; 191 u64 brb_discard[8]; 192 }; 193 194 struct port_stats { 195 struct brb_stats brb; 196 struct eth_stats eth; 197 }; 198 199 /*----+------------------------------------------------------------------------ 200 * C | Number and | Ports in| Ports in|2 PHY-s |# of ports|# of engines 201 * h | rate of | team #1 | team #2 |are used|per path | (paths) 202 * i | physical | | | | | enabled 203 * p | ports | | | | | 204 *====+============+=========+=========+========+==========+=================== 205 * BB | 1x100G | This is special mode, where there are actually 2 HW func 206 * BB | 2x10/20Gbps| 0,1 | NA | No | 1 | 1 207 * BB | 2x40 Gbps | 0,1 | NA | Yes | 1 | 1 208 * BB | 2x50Gbps | 0,1 | NA | No | 1 | 1 209 * BB | 4x10Gbps | 0,2 | 1,3 | No | 1/2 | 1,2 (2 is optional) 210 * BB | 4x10Gbps | 0,1 | 2,3 | No | 1/2 | 1,2 (2 is optional) 211 * BB | 4x10Gbps | 0,3 | 1,2 | No | 1/2 | 1,2 (2 is optional) 212 * BB | 4x10Gbps | 0,1,2,3 | NA | No | 1 | 1 213 * AH | 2x10/20Gbps| 0,1 | NA | NA | 1 | NA 214 * AH | 4x10Gbps | 0,1 | 2,3 | NA | 2 | NA 215 * AH | 4x10Gbps | 0,2 | 1,3 | NA | 2 | NA 216 * AH | 4x10Gbps | 0,3 | 1,2 | NA | 2 | NA 217 * AH | 4x10Gbps | 0,1,2,3 | NA | NA | 1 | NA 218 *====+============+=========+=========+========+==========+=================== 219 */ 220 221 #define CMT_TEAM0 0 222 #define CMT_TEAM1 1 223 #define CMT_TEAM_MAX 2 224 225 struct couple_mode_teaming { 226 u8 port_cmt[MCP_GLOB_PORT_MAX]; 227 #define PORT_CMT_IN_TEAM (1 << 0) 228 229 #define PORT_CMT_PORT_ROLE (1 << 1) 230 #define PORT_CMT_PORT_INACTIVE (0 << 1) 231 #define PORT_CMT_PORT_ACTIVE (1 << 1) 232 233 #define PORT_CMT_TEAM_MASK (1 << 2) 234 #define PORT_CMT_TEAM0 (0 << 2) 235 #define PORT_CMT_TEAM1 (1 << 2) 236 }; 237 238 /************************************** 239 * LLDP and DCBX HSI structures 240 **************************************/ 241 #define LLDP_CHASSIS_ID_STAT_LEN 4 242 #define LLDP_PORT_ID_STAT_LEN 4 243 #define DCBX_MAX_APP_PROTOCOL 32 244 #define MAX_SYSTEM_LLDP_TLV_DATA 32 245 246 typedef enum _lldp_agent_e { 247 LLDP_NEAREST_BRIDGE = 0, 248 LLDP_NEAREST_NON_TPMR_BRIDGE, 249 LLDP_NEAREST_CUSTOMER_BRIDGE, 250 LLDP_MAX_LLDP_AGENTS 251 } lldp_agent_e; 252 253 struct lldp_config_params_s { 254 u32 config; 255 #define LLDP_CONFIG_TX_INTERVAL_MASK 0x000000ff 256 #define LLDP_CONFIG_TX_INTERVAL_SHIFT 0 257 #define LLDP_CONFIG_HOLD_MASK 0x00000f00 258 #define LLDP_CONFIG_HOLD_SHIFT 8 259 #define LLDP_CONFIG_MAX_CREDIT_MASK 0x0000f000 260 #define LLDP_CONFIG_MAX_CREDIT_SHIFT 12 261 #define LLDP_CONFIG_ENABLE_RX_MASK 0x40000000 262 #define LLDP_CONFIG_ENABLE_RX_SHIFT 30 263 #define LLDP_CONFIG_ENABLE_TX_MASK 0x80000000 264 #define LLDP_CONFIG_ENABLE_TX_SHIFT 31 265 /* Holds local Chassis ID TLV header, subtype and 9B of payload. 266 * If firtst byte is 0, then we will use default chassis ID 267 */ 268 u32 local_chassis_id[LLDP_CHASSIS_ID_STAT_LEN]; 269 /* Holds local Port ID TLV header, subtype and 9B of payload. 270 * If firtst byte is 0, then we will use default port ID 271 */ 272 u32 local_port_id[LLDP_PORT_ID_STAT_LEN]; 273 }; 274 275 struct lldp_status_params_s { 276 u32 prefix_seq_num; 277 u32 status; /* TBD */ 278 /* Holds remote Chassis ID TLV header, subtype and 9B of payload. */ 279 u32 peer_chassis_id[LLDP_CHASSIS_ID_STAT_LEN]; 280 /* Holds remote Port ID TLV header, subtype and 9B of payload. */ 281 u32 peer_port_id[LLDP_PORT_ID_STAT_LEN]; 282 u32 suffix_seq_num; 283 }; 284 285 struct dcbx_ets_feature { 286 u32 flags; 287 #define DCBX_ETS_ENABLED_MASK 0x00000001 288 #define DCBX_ETS_ENABLED_SHIFT 0 289 #define DCBX_ETS_WILLING_MASK 0x00000002 290 #define DCBX_ETS_WILLING_SHIFT 1 291 #define DCBX_ETS_ERROR_MASK 0x00000004 292 #define DCBX_ETS_ERROR_SHIFT 2 293 #define DCBX_ETS_CBS_MASK 0x00000008 294 #define DCBX_ETS_CBS_SHIFT 3 295 #define DCBX_ETS_MAX_TCS_MASK 0x000000f0 296 #define DCBX_ETS_MAX_TCS_SHIFT 4 297 #define DCBX_ISCSI_OOO_TC_MASK 0x00000f00 298 #define DCBX_ISCSI_OOO_TC_SHIFT 8 299 /* Entries in tc table are orginized that the left most is pri 0, right most is 300 * prio 7 301 */ 302 303 u32 pri_tc_tbl[1]; 304 #define DCBX_ISCSI_OOO_TC (4) 305 306 #define NIG_ETS_ISCSI_OOO_CLIENT_OFFSET (DCBX_ISCSI_OOO_TC + 1) 307 #define DCBX_CEE_STRICT_PRIORITY 0xf 308 /* Entries in tc table are orginized that the left most is pri 0, right most is 309 * prio 7 310 */ 311 312 u32 tc_bw_tbl[2]; 313 /* Entries in tc table are orginized that the left most is pri 0, right most is 314 * prio 7 315 */ 316 317 u32 tc_tsa_tbl[2]; 318 #define DCBX_ETS_TSA_STRICT 0 319 #define DCBX_ETS_TSA_CBS 1 320 #define DCBX_ETS_TSA_ETS 2 321 }; 322 323 struct dcbx_app_priority_entry { 324 u32 entry; 325 #define DCBX_APP_PRI_MAP_MASK 0x000000ff 326 #define DCBX_APP_PRI_MAP_SHIFT 0 327 #define DCBX_APP_PRI_0 0x01 328 #define DCBX_APP_PRI_1 0x02 329 #define DCBX_APP_PRI_2 0x04 330 #define DCBX_APP_PRI_3 0x08 331 #define DCBX_APP_PRI_4 0x10 332 #define DCBX_APP_PRI_5 0x20 333 #define DCBX_APP_PRI_6 0x40 334 #define DCBX_APP_PRI_7 0x80 335 #define DCBX_APP_SF_MASK 0x00000300 336 #define DCBX_APP_SF_SHIFT 8 337 #define DCBX_APP_SF_ETHTYPE 0 338 #define DCBX_APP_SF_PORT 1 339 #define DCBX_APP_SF_IEEE_MASK 0x0000f000 340 #define DCBX_APP_SF_IEEE_SHIFT 12 341 #define DCBX_APP_SF_IEEE_RESERVED 0 342 #define DCBX_APP_SF_IEEE_ETHTYPE 1 343 #define DCBX_APP_SF_IEEE_TCP_PORT 2 344 #define DCBX_APP_SF_IEEE_UDP_PORT 3 345 #define DCBX_APP_SF_IEEE_TCP_UDP_PORT 4 346 347 #define DCBX_APP_PROTOCOL_ID_MASK 0xffff0000 348 #define DCBX_APP_PROTOCOL_ID_SHIFT 16 349 }; 350 351 352 /* FW structure in BE */ 353 struct dcbx_app_priority_feature { 354 u32 flags; 355 #define DCBX_APP_ENABLED_MASK 0x00000001 356 #define DCBX_APP_ENABLED_SHIFT 0 357 #define DCBX_APP_WILLING_MASK 0x00000002 358 #define DCBX_APP_WILLING_SHIFT 1 359 #define DCBX_APP_ERROR_MASK 0x00000004 360 #define DCBX_APP_ERROR_SHIFT 2 361 /* Not in use 362 #define DCBX_APP_DEFAULT_PRI_MASK 0x00000f00 363 #define DCBX_APP_DEFAULT_PRI_SHIFT 8 364 */ 365 #define DCBX_APP_MAX_TCS_MASK 0x0000f000 366 #define DCBX_APP_MAX_TCS_SHIFT 12 367 #define DCBX_APP_NUM_ENTRIES_MASK 0x00ff0000 368 #define DCBX_APP_NUM_ENTRIES_SHIFT 16 369 struct dcbx_app_priority_entry app_pri_tbl[DCBX_MAX_APP_PROTOCOL]; 370 }; 371 372 /* FW structure in BE */ 373 struct dcbx_features { 374 /* PG feature */ 375 struct dcbx_ets_feature ets; 376 /* PFC feature */ 377 u32 pfc; 378 #define DCBX_PFC_PRI_EN_BITMAP_MASK 0x000000ff 379 #define DCBX_PFC_PRI_EN_BITMAP_SHIFT 0 380 #define DCBX_PFC_PRI_EN_BITMAP_PRI_0 0x01 381 #define DCBX_PFC_PRI_EN_BITMAP_PRI_1 0x02 382 #define DCBX_PFC_PRI_EN_BITMAP_PRI_2 0x04 383 #define DCBX_PFC_PRI_EN_BITMAP_PRI_3 0x08 384 #define DCBX_PFC_PRI_EN_BITMAP_PRI_4 0x10 385 #define DCBX_PFC_PRI_EN_BITMAP_PRI_5 0x20 386 #define DCBX_PFC_PRI_EN_BITMAP_PRI_6 0x40 387 #define DCBX_PFC_PRI_EN_BITMAP_PRI_7 0x80 388 389 #define DCBX_PFC_FLAGS_MASK 0x0000ff00 390 #define DCBX_PFC_FLAGS_SHIFT 8 391 #define DCBX_PFC_CAPS_MASK 0x00000f00 392 #define DCBX_PFC_CAPS_SHIFT 8 393 #define DCBX_PFC_MBC_MASK 0x00004000 394 #define DCBX_PFC_MBC_SHIFT 14 395 #define DCBX_PFC_WILLING_MASK 0x00008000 396 #define DCBX_PFC_WILLING_SHIFT 15 397 #define DCBX_PFC_ENABLED_MASK 0x00010000 398 #define DCBX_PFC_ENABLED_SHIFT 16 399 #define DCBX_PFC_ERROR_MASK 0x00020000 400 #define DCBX_PFC_ERROR_SHIFT 17 401 402 /* APP feature */ 403 struct dcbx_app_priority_feature app; 404 }; 405 406 struct dcbx_local_params { 407 u32 config; 408 #define DCBX_CONFIG_VERSION_MASK 0x00000007 409 #define DCBX_CONFIG_VERSION_SHIFT 0 410 #define DCBX_CONFIG_VERSION_DISABLED 0 411 #define DCBX_CONFIG_VERSION_IEEE 1 412 #define DCBX_CONFIG_VERSION_CEE 2 413 #define DCBX_CONFIG_VERSION_STATIC 4 414 415 u32 flags; 416 struct dcbx_features features; 417 }; 418 419 struct dcbx_mib { 420 u32 prefix_seq_num; 421 u32 flags; 422 /* 423 #define DCBX_CONFIG_VERSION_MASK 0x00000007 424 #define DCBX_CONFIG_VERSION_SHIFT 0 425 #define DCBX_CONFIG_VERSION_DISABLED 0 426 #define DCBX_CONFIG_VERSION_IEEE 1 427 #define DCBX_CONFIG_VERSION_CEE 2 428 #define DCBX_CONFIG_VERSION_STATIC 4 429 */ 430 struct dcbx_features features; 431 u32 suffix_seq_num; 432 }; 433 434 struct lldp_system_tlvs_buffer_s { 435 u16 valid; 436 u16 length; 437 u32 data[MAX_SYSTEM_LLDP_TLV_DATA]; 438 }; 439 440 struct dcb_dscp_map { 441 u32 flags; 442 #define DCB_DSCP_ENABLE_MASK 0x1 443 #define DCB_DSCP_ENABLE_SHIFT 0 444 #define DCB_DSCP_ENABLE 1 445 u32 dscp_pri_map[8]; 446 }; 447 448 /**************************************/ 449 /* */ 450 /* P U B L I C G L O B A L */ 451 /* */ 452 /**************************************/ 453 struct public_global { 454 u32 max_path; /* 32bit is wasty, but this will be used often */ 455 /* (Global) 32bit is wasty, but this will be used often */ 456 u32 max_ports; 457 #define MODE_1P 1 /* TBD - NEED TO THINK OF A BETTER NAME */ 458 #define MODE_2P 2 459 #define MODE_3P 3 460 #define MODE_4P 4 461 u32 debug_mb_offset; 462 u32 phymod_dbg_mb_offset; 463 struct couple_mode_teaming cmt; 464 /* Temperature in Celcius (-255C / +255C), measured every second. */ 465 s32 internal_temperature; 466 u32 mfw_ver; 467 u32 running_bundle_id; 468 s32 external_temperature; 469 u32 mdump_reason; 470 #define MDUMP_REASON_INTERNAL_ERROR (1 << 0) 471 #define MDUMP_REASON_EXTERNAL_TRIGGER (1 << 1) 472 #define MDUMP_REASON_DUMP_AGED (1 << 2) 473 u32 ext_phy_upgrade_fw; 474 #define EXT_PHY_FW_UPGRADE_STATUS_MASK (0x0000ffff) 475 #define EXT_PHY_FW_UPGRADE_STATUS_SHIFT (0) 476 #define EXT_PHY_FW_UPGRADE_STATUS_IN_PROGRESS (1) 477 #define EXT_PHY_FW_UPGRADE_STATUS_FAILED (2) 478 #define EXT_PHY_FW_UPGRADE_STATUS_SUCCESS (3) 479 #define EXT_PHY_FW_UPGRADE_TYPE_MASK (0xffff0000) 480 #define EXT_PHY_FW_UPGRADE_TYPE_SHIFT (16) 481 }; 482 483 /**************************************/ 484 /* */ 485 /* P U B L I C P A T H */ 486 /* */ 487 /**************************************/ 488 489 /**************************************************************************** 490 * Shared Memory 2 Region * 491 ****************************************************************************/ 492 /* The fw_flr_ack is actually built in the following way: */ 493 /* 8 bit: PF ack */ 494 /* 128 bit: VF ack */ 495 /* 8 bit: ios_dis_ack */ 496 /* In order to maintain endianity in the mailbox hsi, we want to keep using */ 497 /* u32. The fw must have the VF right after the PF since this is how it */ 498 /* access arrays(it expects always the VF to reside after the PF, and that */ 499 /* makes the calculation much easier for it. ) */ 500 /* In order to answer both limitations, and keep the struct small, the code */ 501 /* will abuse the structure defined here to achieve the actual partition */ 502 /* above */ 503 /****************************************************************************/ 504 struct fw_flr_mb { 505 u32 aggint; 506 u32 opgen_addr; 507 u32 accum_ack; /* 0..15:PF, 16..207:VF, 256..271:IOV_DIS */ 508 #define ACCUM_ACK_PF_BASE 0 509 #define ACCUM_ACK_PF_SHIFT 0 510 511 #define ACCUM_ACK_VF_BASE 8 512 #define ACCUM_ACK_VF_SHIFT 3 513 514 #define ACCUM_ACK_IOV_DIS_BASE 256 515 #define ACCUM_ACK_IOV_DIS_SHIFT 8 516 517 }; 518 519 struct public_path { 520 struct fw_flr_mb flr_mb; 521 /* 522 * mcp_vf_disabled is set by the MCP to indicate the driver about VFs 523 * which were disabled/flred 524 */ 525 u32 mcp_vf_disabled[VF_MAX_STATIC / 32]; /* 0x003c */ 526 527 /* Reset on mcp reset, and incremented for eveny process kill event. */ 528 u32 process_kill; 529 #define PROCESS_KILL_COUNTER_MASK 0x0000ffff 530 #define PROCESS_KILL_COUNTER_SHIFT 0 531 #define PROCESS_KILL_GLOB_AEU_BIT_MASK 0xffff0000 532 #define PROCESS_KILL_GLOB_AEU_BIT_SHIFT 16 533 #define GLOBAL_AEU_BIT(aeu_reg_id, aeu_bit) (aeu_reg_id * 32 + aeu_bit) 534 }; 535 536 /**************************************/ 537 /* */ 538 /* P U B L I C P O R T */ 539 /* */ 540 /**************************************/ 541 #define FC_NPIV_WWPN_SIZE 8 542 #define FC_NPIV_WWNN_SIZE 8 543 struct dci_npiv_settings { 544 u8 npiv_wwpn[FC_NPIV_WWPN_SIZE]; 545 u8 npiv_wwnn[FC_NPIV_WWNN_SIZE]; 546 }; 547 548 struct dci_fc_npiv_cfg { 549 /* hdr used internally by the MFW */ 550 u32 hdr; 551 u32 num_of_npiv; 552 }; 553 554 #define MAX_NUMBER_NPIV 64 555 struct dci_fc_npiv_tbl { 556 struct dci_fc_npiv_cfg fc_npiv_cfg; 557 struct dci_npiv_settings settings[MAX_NUMBER_NPIV]; 558 }; 559 560 /**************************************************************************** 561 * Driver <-> FW Mailbox * 562 ****************************************************************************/ 563 564 struct public_port { 565 u32 validity_map; /* 0x0 (4*2 = 0x8) */ 566 567 /* validity bits */ 568 #define MCP_VALIDITY_PCI_CFG 0x00100000 569 #define MCP_VALIDITY_MB 0x00200000 570 #define MCP_VALIDITY_DEV_INFO 0x00400000 571 #define MCP_VALIDITY_RESERVED 0x00000007 572 573 /* One licensing bit should be set */ 574 /* yaniv - tbd ? license */ 575 #define MCP_VALIDITY_LIC_KEY_IN_EFFECT_MASK 0x00000038 576 #define MCP_VALIDITY_LIC_MANUF_KEY_IN_EFFECT 0x00000008 577 #define MCP_VALIDITY_LIC_UPGRADE_KEY_IN_EFFECT 0x00000010 578 #define MCP_VALIDITY_LIC_NO_KEY_IN_EFFECT 0x00000020 579 580 /* Active MFW */ 581 #define MCP_VALIDITY_ACTIVE_MFW_UNKNOWN 0x00000000 582 #define MCP_VALIDITY_ACTIVE_MFW_MASK 0x000001c0 583 #define MCP_VALIDITY_ACTIVE_MFW_NCSI 0x00000040 584 #define MCP_VALIDITY_ACTIVE_MFW_NONE 0x000001c0 585 586 u32 link_status; 587 #define LINK_STATUS_LINK_UP 0x00000001 588 #define LINK_STATUS_SPEED_AND_DUPLEX_MASK 0x0000001e 589 #define LINK_STATUS_SPEED_AND_DUPLEX_1000THD (1 << 1) 590 #define LINK_STATUS_SPEED_AND_DUPLEX_1000TFD (2 << 1) 591 #define LINK_STATUS_SPEED_AND_DUPLEX_10G (3 << 1) 592 #define LINK_STATUS_SPEED_AND_DUPLEX_20G (4 << 1) 593 #define LINK_STATUS_SPEED_AND_DUPLEX_40G (5 << 1) 594 #define LINK_STATUS_SPEED_AND_DUPLEX_50G (6 << 1) 595 #define LINK_STATUS_SPEED_AND_DUPLEX_100G (7 << 1) 596 #define LINK_STATUS_SPEED_AND_DUPLEX_25G (8 << 1) 597 #define LINK_STATUS_AUTO_NEGOTIATE_ENABLED 0x00000020 598 #define LINK_STATUS_AUTO_NEGOTIATE_COMPLETE 0x00000040 599 #define LINK_STATUS_PARALLEL_DETECTION_USED 0x00000080 600 #define LINK_STATUS_PFC_ENABLED 0x00000100 601 #define LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE 0x00000200 602 #define LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE 0x00000400 603 #define LINK_STATUS_LINK_PARTNER_10G_CAPABLE 0x00000800 604 #define LINK_STATUS_LINK_PARTNER_20G_CAPABLE 0x00001000 605 #define LINK_STATUS_LINK_PARTNER_40G_CAPABLE 0x00002000 606 #define LINK_STATUS_LINK_PARTNER_50G_CAPABLE 0x00004000 607 #define LINK_STATUS_LINK_PARTNER_100G_CAPABLE 0x00008000 608 #define LINK_STATUS_LINK_PARTNER_25G_CAPABLE 0x00010000 609 #define LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK 0x000C0000 610 #define LINK_STATUS_LINK_PARTNER_NOT_PAUSE_CAPABLE (0 << 18) 611 #define LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE (1 << 18) 612 #define LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE (2 << 18) 613 #define LINK_STATUS_LINK_PARTNER_BOTH_PAUSE (3 << 18) 614 #define LINK_STATUS_SFP_TX_FAULT 0x00100000 615 #define LINK_STATUS_TX_FLOW_CONTROL_ENABLED 0x00200000 616 #define LINK_STATUS_RX_FLOW_CONTROL_ENABLED 0x00400000 617 #define LINK_STATUS_RX_SIGNAL_PRESENT 0x00800000 618 #define LINK_STATUS_MAC_LOCAL_FAULT 0x01000000 619 #define LINK_STATUS_MAC_REMOTE_FAULT 0x02000000 620 #define LINK_STATUS_UNSUPPORTED_SPD_REQ 0x04000000 621 #define LINK_STATUS_FEC_MODE_MASK 0x38000000 622 #define LINK_STATUS_FEC_MODE_NONE (0 << 27) 623 #define LINK_STATUS_FEC_MODE_FIRECODE_CL74 (1 << 27) 624 #define LINK_STATUS_FEC_MODE_RS_CL91 (2 << 27) 625 #define LINK_STATUS_EXT_PHY_LINK_UP 0x40000000 626 627 u32 link_status1; 628 u32 ext_phy_fw_version; 629 /* Points to struct eth_phy_cfg (For READ-ONLY) */ 630 u32 drv_phy_cfg_addr; 631 632 u32 port_stx; 633 634 u32 stat_nig_timer; 635 636 struct port_mf_cfg port_mf_config; 637 struct port_stats stats; 638 639 u32 media_type; 640 #define MEDIA_UNSPECIFIED 0x0 641 #define MEDIA_SFPP_10G_FIBER 0x1 /* Use MEDIA_MODULE_FIBER instead */ 642 #define MEDIA_XFP_FIBER 0x2 /* Use MEDIA_MODULE_FIBER instead */ 643 #define MEDIA_DA_TWINAX 0x3 644 #define MEDIA_BASE_T 0x4 645 #define MEDIA_SFP_1G_FIBER 0x5 /* Use MEDIA_MODULE_FIBER instead */ 646 #define MEDIA_MODULE_FIBER 0x6 647 #define MEDIA_KR 0xf0 648 #define MEDIA_NOT_PRESENT 0xff 649 650 u32 lfa_status; 651 #define LFA_LINK_FLAP_REASON_OFFSET 0 652 #define LFA_LINK_FLAP_REASON_MASK 0x000000ff 653 #define LFA_NO_REASON (0 << 0) 654 #define LFA_LINK_DOWN (1 << 0) 655 #define LFA_FORCE_INIT (1 << 1) 656 #define LFA_LOOPBACK_MISMATCH (1 << 2) 657 #define LFA_SPEED_MISMATCH (1 << 3) 658 #define LFA_FLOW_CTRL_MISMATCH (1 << 4) 659 #define LFA_ADV_SPEED_MISMATCH (1 << 5) 660 #define LINK_FLAP_AVOIDANCE_COUNT_OFFSET 8 661 #define LINK_FLAP_AVOIDANCE_COUNT_MASK 0x0000ff00 662 #define LINK_FLAP_COUNT_OFFSET 16 663 #define LINK_FLAP_COUNT_MASK 0x00ff0000 664 665 u32 link_change_count; 666 667 /* LLDP params */ 668 /* offset: 536 bytes? */ 669 struct lldp_config_params_s lldp_config_params[LLDP_MAX_LLDP_AGENTS]; 670 struct lldp_status_params_s lldp_status_params[LLDP_MAX_LLDP_AGENTS]; 671 struct lldp_system_tlvs_buffer_s system_lldp_tlvs_buf; 672 673 /* DCBX related MIB */ 674 struct dcbx_local_params local_admin_dcbx_mib; 675 struct dcbx_mib remote_dcbx_mib; 676 struct dcbx_mib operational_dcbx_mib; 677 678 /* FC_NPIV table offset & size in NVRAM value of 0 means not present */ 679 680 u32 fc_npiv_nvram_tbl_addr; 681 u32 fc_npiv_nvram_tbl_size; 682 u32 transceiver_data; 683 #define ETH_TRANSCEIVER_STATE_MASK 0x000000FF 684 #define ETH_TRANSCEIVER_STATE_SHIFT 0x00000000 685 #define ETH_TRANSCEIVER_STATE_UNPLUGGED 0x00000000 686 #define ETH_TRANSCEIVER_STATE_PRESENT 0x00000001 687 #define ETH_TRANSCEIVER_STATE_VALID 0x00000003 688 #define ETH_TRANSCEIVER_STATE_UPDATING 0x00000008 689 #define ETH_TRANSCEIVER_TYPE_MASK 0x0000FF00 690 #define ETH_TRANSCEIVER_TYPE_SHIFT 0x00000008 691 #define ETH_TRANSCEIVER_TYPE_NONE 0x00000000 692 #define ETH_TRANSCEIVER_TYPE_UNKNOWN 0x000000FF 693 /* 1G Passive copper cable */ 694 #define ETH_TRANSCEIVER_TYPE_1G_PCC 0x01 695 /* 1G Active copper cable */ 696 #define ETH_TRANSCEIVER_TYPE_1G_ACC 0x02 697 #define ETH_TRANSCEIVER_TYPE_1G_LX 0x03 698 #define ETH_TRANSCEIVER_TYPE_1G_SX 0x04 699 #define ETH_TRANSCEIVER_TYPE_10G_SR 0x05 700 #define ETH_TRANSCEIVER_TYPE_10G_LR 0x06 701 #define ETH_TRANSCEIVER_TYPE_10G_LRM 0x07 702 #define ETH_TRANSCEIVER_TYPE_10G_ER 0x08 703 /* 10G Passive copper cable */ 704 #define ETH_TRANSCEIVER_TYPE_10G_PCC 0x09 705 /* 10G Active copper cable */ 706 #define ETH_TRANSCEIVER_TYPE_10G_ACC 0x0a 707 #define ETH_TRANSCEIVER_TYPE_XLPPI 0x0b 708 #define ETH_TRANSCEIVER_TYPE_40G_LR4 0x0c 709 #define ETH_TRANSCEIVER_TYPE_40G_SR4 0x0d 710 #define ETH_TRANSCEIVER_TYPE_40G_CR4 0x0e 711 /* Active optical cable */ 712 #define ETH_TRANSCEIVER_TYPE_100G_AOC 0x0f 713 #define ETH_TRANSCEIVER_TYPE_100G_SR4 0x10 714 #define ETH_TRANSCEIVER_TYPE_100G_LR4 0x11 715 #define ETH_TRANSCEIVER_TYPE_100G_ER4 0x12 716 /* Active copper cable */ 717 #define ETH_TRANSCEIVER_TYPE_100G_ACC 0x13 718 #define ETH_TRANSCEIVER_TYPE_100G_CR4 0x14 719 #define ETH_TRANSCEIVER_TYPE_4x10G_SR 0x15 720 /* 25G Passive copper cable - short */ 721 #define ETH_TRANSCEIVER_TYPE_25G_CA_N 0x16 722 /* 25G Active copper cable - short */ 723 #define ETH_TRANSCEIVER_TYPE_25G_ACC_S 0x17 724 /* 25G Passive copper cable - medium */ 725 #define ETH_TRANSCEIVER_TYPE_25G_CA_S 0x18 726 /* 25G Active copper cable - medium */ 727 #define ETH_TRANSCEIVER_TYPE_25G_ACC_M 0x19 728 /* 25G Passive copper cable - long */ 729 #define ETH_TRANSCEIVER_TYPE_25G_CA_L 0x1a 730 /* 25G Active copper cable - long */ 731 #define ETH_TRANSCEIVER_TYPE_25G_ACC_L 0x1b 732 #define ETH_TRANSCEIVER_TYPE_25G_SR 0x1c 733 #define ETH_TRANSCEIVER_TYPE_25G_LR 0x1d 734 #define ETH_TRANSCEIVER_TYPE_25G_AOC 0x1e 735 736 #define ETH_TRANSCEIVER_TYPE_4x10G 0x1f 737 #define ETH_TRANSCEIVER_TYPE_4x25G_CR 0x20 738 #define ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_40G_SR 0x30 739 #define ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_40G_CR 0x31 740 #define ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_40G_LR 0x32 741 #define ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_SR 0x33 742 #define ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_CR 0x34 743 #define ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_LR 0x35 744 #define ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_AOC 0x36 745 u32 wol_info; 746 u32 wol_pkt_len; 747 u32 wol_pkt_details; 748 struct dcb_dscp_map dcb_dscp_map; 749 750 /* the status of EEE auto-negotiation 751 * bits 19:0 the configured tx-lpi entry timer value. Depends on bit 31. 752 * bits 23:20 the speeds advertised for EEE. 753 * bits 27:24 the speeds the Link partner advertised for EEE. 754 * The supported/adv. modes in bits 27:19 originate from the 755 * SHMEM_EEE_XXX_ADV definitions (where XXX is replaced by speed). 756 * bit 28 when 1'b1 EEE was requested. 757 * bit 29 when 1'b1 tx lpi was requested. 758 * bit 30 when 1'b1 EEE was negotiated. Tx lpi will be asserted if 30:29 759 * are 2'b11. 760 * bit 31 - When 1'b0 bits 15:0 contain 761 * NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_XXX define as value. 762 * When 1'b1 those bits contains a value times 16 microseconds. 763 */ 764 u32 eee_status; 765 #define EEE_TIMER_MASK 0x000fffff 766 #define EEE_ADV_STATUS_MASK 0x00f00000 767 #define EEE_1G_ADV (1 << 1) 768 #define EEE_10G_ADV (1 << 2) 769 #define EEE_ADV_STATUS_SHIFT 20 770 #define EEE_LP_ADV_STATUS_MASK 0x0f000000 771 #define EEE_LP_ADV_STATUS_SHIFT 24 772 #define EEE_REQUESTED_BIT 0x10000000 773 #define EEE_LPI_REQUESTED_BIT 0x20000000 774 #define EEE_ACTIVE_BIT 0x40000000 775 #define EEE_TIME_OUTPUT_BIT 0x80000000 776 777 u32 eee_remote; /* Used for EEE in LLDP */ 778 #define EEE_REMOTE_TW_TX_MASK 0x0000ffff 779 #define EEE_REMOTE_TW_TX_SHIFT 0 780 #define EEE_REMOTE_TW_RX_MASK 0xffff0000 781 #define EEE_REMOTE_TW_RX_SHIFT 16 782 }; 783 784 /**************************************/ 785 /* */ 786 /* P U B L I C F U N C */ 787 /* */ 788 /**************************************/ 789 790 struct public_func { 791 u32 iscsi_boot_signature; 792 u32 iscsi_boot_block_offset; 793 794 /* MTU size per funciton is needed for the OV feature */ 795 u32 mtu_size; 796 /* 9 entires for the C2S PCP map for each inner VLAN PCP + 1 default */ 797 798 /* For PCP values 0-3 use the map lower */ 799 /* 0xFF000000 - PCP 0, 0x00FF0000 - PCP 1, 800 * 0x0000FF00 - PCP 2, 0x000000FF PCP 3 801 */ 802 u32 c2s_pcp_map_lower; 803 /* For PCP values 4-7 use the map upper */ 804 /* 0xFF000000 - PCP 4, 0x00FF0000 - PCP 5, 805 * 0x0000FF00 - PCP 6, 0x000000FF PCP 7 806 */ 807 u32 c2s_pcp_map_upper; 808 809 /* For PCP default value get the MSB byte of the map default */ 810 u32 c2s_pcp_map_default; 811 812 u32 reserved[4]; 813 814 /* replace old mf_cfg */ 815 u32 config; 816 /* E/R/I/D */ 817 /* function 0 of each port cannot be hidden */ 818 #define FUNC_MF_CFG_FUNC_HIDE 0x00000001 819 #define FUNC_MF_CFG_PAUSE_ON_HOST_RING 0x00000002 820 #define FUNC_MF_CFG_PAUSE_ON_HOST_RING_SHIFT 0x00000001 821 822 823 #define FUNC_MF_CFG_PROTOCOL_MASK 0x000000f0 824 #define FUNC_MF_CFG_PROTOCOL_SHIFT 4 825 #define FUNC_MF_CFG_PROTOCOL_ETHERNET 0x00000000 826 #define FUNC_MF_CFG_PROTOCOL_ISCSI 0x00000010 827 #define FUNC_MF_CFG_PROTOCOL_FCOE 0x00000020 828 #define FUNC_MF_CFG_PROTOCOL_ROCE 0x00000030 829 #define FUNC_MF_CFG_PROTOCOL_MAX 0x00000030 830 831 /* MINBW, MAXBW */ 832 /* value range - 0..100, increments in 1 % */ 833 #define FUNC_MF_CFG_MIN_BW_MASK 0x0000ff00 834 #define FUNC_MF_CFG_MIN_BW_SHIFT 8 835 #define FUNC_MF_CFG_MIN_BW_DEFAULT 0x00000000 836 #define FUNC_MF_CFG_MAX_BW_MASK 0x00ff0000 837 #define FUNC_MF_CFG_MAX_BW_SHIFT 16 838 #define FUNC_MF_CFG_MAX_BW_DEFAULT 0x00640000 839 840 u32 status; 841 #define FUNC_STATUS_VLINK_DOWN 0x00000001 842 843 u32 mac_upper; /* MAC */ 844 #define FUNC_MF_CFG_UPPERMAC_MASK 0x0000ffff 845 #define FUNC_MF_CFG_UPPERMAC_SHIFT 0 846 #define FUNC_MF_CFG_UPPERMAC_DEFAULT FUNC_MF_CFG_UPPERMAC_MASK 847 u32 mac_lower; 848 #define FUNC_MF_CFG_LOWERMAC_DEFAULT 0xffffffff 849 850 u32 fcoe_wwn_port_name_upper; 851 u32 fcoe_wwn_port_name_lower; 852 853 u32 fcoe_wwn_node_name_upper; 854 u32 fcoe_wwn_node_name_lower; 855 856 u32 ovlan_stag; /* tags */ 857 #define FUNC_MF_CFG_OV_STAG_MASK 0x0000ffff 858 #define FUNC_MF_CFG_OV_STAG_SHIFT 0 859 #define FUNC_MF_CFG_OV_STAG_DEFAULT FUNC_MF_CFG_OV_STAG_MASK 860 861 u32 pf_allocation; /* vf per pf */ 862 863 u32 preserve_data; /* Will be used bt CCM */ 864 865 u32 driver_last_activity_ts; 866 867 /* 868 * drv_ack_vf_disabled is set by the PF driver to ack handled disabled 869 * VFs 870 */ 871 u32 drv_ack_vf_disabled[VF_MAX_STATIC / 32]; /* 0x0044 */ 872 873 u32 drv_id; 874 #define DRV_ID_PDA_COMP_VER_MASK 0x0000ffff 875 #define DRV_ID_PDA_COMP_VER_SHIFT 0 876 877 #define DRV_ID_MCP_HSI_VER_MASK 0x00ff0000 878 #define DRV_ID_MCP_HSI_VER_SHIFT 16 879 #define DRV_ID_MCP_HSI_VER_CURRENT (1 << DRV_ID_MCP_HSI_VER_SHIFT) 880 881 #define DRV_ID_DRV_TYPE_MASK 0x7f000000 882 #define DRV_ID_DRV_TYPE_SHIFT 24 883 #define DRV_ID_DRV_TYPE_UNKNOWN (0 << DRV_ID_DRV_TYPE_SHIFT) 884 #define DRV_ID_DRV_TYPE_LINUX (1 << DRV_ID_DRV_TYPE_SHIFT) 885 #define DRV_ID_DRV_TYPE_WINDOWS (2 << DRV_ID_DRV_TYPE_SHIFT) 886 #define DRV_ID_DRV_TYPE_DIAG (3 << DRV_ID_DRV_TYPE_SHIFT) 887 #define DRV_ID_DRV_TYPE_PREBOOT (4 << DRV_ID_DRV_TYPE_SHIFT) 888 #define DRV_ID_DRV_TYPE_SOLARIS (5 << DRV_ID_DRV_TYPE_SHIFT) 889 #define DRV_ID_DRV_TYPE_VMWARE (6 << DRV_ID_DRV_TYPE_SHIFT) 890 #define DRV_ID_DRV_TYPE_FREEBSD (7 << DRV_ID_DRV_TYPE_SHIFT) 891 #define DRV_ID_DRV_TYPE_AIX (8 << DRV_ID_DRV_TYPE_SHIFT) 892 893 #define DRV_ID_DRV_INIT_HW_MASK 0x80000000 894 #define DRV_ID_DRV_INIT_HW_SHIFT 31 895 #define DRV_ID_DRV_INIT_HW_FLAG (1 << DRV_ID_DRV_INIT_HW_SHIFT) 896 }; 897 898 /**************************************/ 899 /* */ 900 /* P U B L I C M B */ 901 /* */ 902 /**************************************/ 903 /* This is the only section that the driver can write to, and each */ 904 /* Basically each driver request to set feature parameters, 905 * will be done using a different command, which will be linked 906 * to a specific data structure from the union below. 907 * For huge strucuture, the common blank structure should be used. 908 */ 909 910 struct mcp_mac { 911 u32 mac_upper; /* Upper 16 bits are always zeroes */ 912 u32 mac_lower; 913 }; 914 915 struct mcp_val64 { 916 u32 lo; 917 u32 hi; 918 }; 919 920 struct mcp_file_att { 921 u32 nvm_start_addr; 922 u32 len; 923 }; 924 925 struct bist_nvm_image_att { 926 u32 return_code; 927 u32 image_type; /* Image type */ 928 u32 nvm_start_addr; /* NVM address of the image */ 929 u32 len; /* Include CRC */ 930 }; 931 932 #define MCP_DRV_VER_STR_SIZE 16 933 #define MCP_DRV_VER_STR_SIZE_DWORD (MCP_DRV_VER_STR_SIZE / sizeof(u32)) 934 #define MCP_DRV_NVM_BUF_LEN 32 935 struct drv_version_stc { 936 u32 version; 937 u8 name[MCP_DRV_VER_STR_SIZE - 4]; 938 }; 939 940 /* statistics for ncsi */ 941 struct lan_stats_stc { 942 u64 ucast_rx_pkts; 943 u64 ucast_tx_pkts; 944 u32 fcs_err; 945 u32 rserved; 946 }; 947 948 struct fcoe_stats_stc { 949 u64 rx_pkts; 950 u64 tx_pkts; 951 u32 fcs_err; 952 u32 login_failure; 953 }; 954 955 struct iscsi_stats_stc { 956 u64 rx_pdus; 957 u64 tx_pdus; 958 u64 rx_bytes; 959 u64 tx_bytes; 960 }; 961 962 struct rdma_stats_stc { 963 u64 rx_pkts; 964 u64 tx_pkts; 965 u64 rx_bytes; 966 u64 tx_bytes; 967 }; 968 969 struct ocbb_data_stc { 970 u32 ocbb_host_addr; 971 u32 ocsd_host_addr; 972 u32 ocsd_req_update_interval; 973 }; 974 975 #define MAX_NUM_OF_SENSORS 7 976 #define MFW_SENSOR_LOCATION_INTERNAL 1 977 #define MFW_SENSOR_LOCATION_EXTERNAL 2 978 #define MFW_SENSOR_LOCATION_SFP 3 979 980 #define SENSOR_LOCATION_SHIFT 0 981 #define SENSOR_LOCATION_MASK 0x000000ff 982 #define THRESHOLD_HIGH_SHIFT 8 983 #define THRESHOLD_HIGH_MASK 0x0000ff00 984 #define CRITICAL_TEMPERATURE_SHIFT 16 985 #define CRITICAL_TEMPERATURE_MASK 0x00ff0000 986 #define CURRENT_TEMP_SHIFT 24 987 #define CURRENT_TEMP_MASK 0xff000000 988 struct temperature_status_stc { 989 u32 num_of_sensors; 990 u32 sensor[MAX_NUM_OF_SENSORS]; 991 }; 992 993 /* crash dump configuration header */ 994 struct mdump_config_stc { 995 u32 version; 996 u32 config; 997 u32 epoc; 998 u32 num_of_logs; 999 u32 valid_logs; 1000 }; 1001 1002 enum resource_id_enum { 1003 RESOURCE_NUM_SB_E = 0, 1004 RESOURCE_NUM_L2_QUEUE_E = 1, 1005 RESOURCE_NUM_VPORT_E = 2, 1006 RESOURCE_NUM_VMQ_E = 3, 1007 /* Not a real resource!! it's a factor used to calculate others */ 1008 RESOURCE_FACTOR_NUM_RSS_PF_E = 4, 1009 /* Not a real resource!! it's a factor used to calculate others */ 1010 RESOURCE_FACTOR_RSS_PER_VF_E = 5, 1011 RESOURCE_NUM_RL_E = 6, 1012 RESOURCE_NUM_PQ_E = 7, 1013 RESOURCE_NUM_VF_E = 8, 1014 RESOURCE_VFC_FILTER_E = 9, 1015 RESOURCE_ILT_E = 10, 1016 RESOURCE_CQS_E = 11, 1017 RESOURCE_GFT_PROFILES_E = 12, 1018 RESOURCE_NUM_TC_E = 13, 1019 RESOURCE_NUM_RSS_ENGINES_E = 14, 1020 RESOURCE_LL2_QUEUE_E = 15, 1021 RESOURCE_RDMA_STATS_QUEUE_E = 16, 1022 RESOURCE_MAX_NUM, 1023 RESOURCE_NUM_INVALID = 0xFFFFFFFF 1024 }; 1025 1026 /* Resource ID is to be filled by the driver in the MB request 1027 * Size, offset & flags to be filled by the MFW in the MB response 1028 */ 1029 struct resource_info { 1030 enum resource_id_enum res_id; 1031 u32 size; /* number of allocated resources */ 1032 u32 offset; /* Offset of the 1st resource */ 1033 u32 vf_size; 1034 u32 vf_offset; 1035 u32 flags; 1036 #define RESOURCE_ELEMENT_STRICT (1 << 0) 1037 }; 1038 1039 union drv_union_data { 1040 u32 ver_str[MCP_DRV_VER_STR_SIZE_DWORD]; /* LOAD_REQ */ 1041 struct mcp_mac wol_mac; /* UNLOAD_DONE */ 1042 1043 /* This configuration should be set by the driver for the LINK_SET command. */ 1044 1045 struct eth_phy_cfg drv_phy_cfg; 1046 1047 struct mcp_val64 val64; /* For PHY / AVS commands */ 1048 1049 u8 raw_data[MCP_DRV_NVM_BUF_LEN]; 1050 1051 struct mcp_file_att file_att; 1052 1053 u32 ack_vf_disabled[VF_MAX_STATIC / 32]; 1054 1055 struct drv_version_stc drv_version; 1056 1057 struct lan_stats_stc lan_stats; 1058 struct fcoe_stats_stc fcoe_stats; 1059 struct iscsi_stats_stc icsci_stats; 1060 struct rdma_stats_stc rdma_stats; 1061 struct ocbb_data_stc ocbb_info; 1062 struct temperature_status_stc temp_info; 1063 struct resource_info resource; 1064 struct bist_nvm_image_att nvm_image_att; 1065 struct mdump_config_stc mdump_config; 1066 u32 dword; 1067 /* ... */ 1068 }; 1069 1070 struct public_drv_mb { 1071 u32 drv_mb_header; 1072 #define DRV_MSG_CODE_MASK 0xffff0000 1073 #define DRV_MSG_CODE_LOAD_REQ 0x10000000 1074 #define DRV_MSG_CODE_LOAD_DONE 0x11000000 1075 #define DRV_MSG_CODE_INIT_HW 0x12000000 1076 #define DRV_MSG_CODE_UNLOAD_REQ 0x20000000 1077 #define DRV_MSG_CODE_UNLOAD_DONE 0x21000000 1078 #define DRV_MSG_CODE_INIT_PHY 0x22000000 1079 /* Params - FORCE - Reinitialize the link regardless of LFA */ 1080 /* - DONT_CARE - Don't flap the link if up */ 1081 #define DRV_MSG_CODE_LINK_RESET 0x23000000 1082 1083 /* Vitaly: LLDP commands */ 1084 #define DRV_MSG_CODE_SET_LLDP 0x24000000 1085 #define DRV_MSG_CODE_SET_DCBX 0x25000000 1086 /* OneView feature driver HSI*/ 1087 #define DRV_MSG_CODE_OV_UPDATE_CURR_CFG 0x26000000 1088 #define DRV_MSG_CODE_OV_UPDATE_BUS_NUM 0x27000000 1089 #define DRV_MSG_CODE_OV_UPDATE_BOOT_PROGRESS 0x28000000 1090 #define DRV_MSG_CODE_OV_UPDATE_STORM_FW_VER 0x29000000 1091 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE 0x31000000 1092 #define DRV_MSG_CODE_BW_UPDATE_ACK 0x32000000 1093 #define DRV_MSG_CODE_OV_UPDATE_MTU 0x33000000 1094 1095 #define DRV_MSG_CODE_NIG_DRAIN 0x30000000 1096 1097 /* DRV_MB Param: driver version supp, FW_MB param: MFW version supp, 1098 * data: struct resource_info 1099 */ 1100 #define DRV_MSG_GET_RESOURCE_ALLOC_MSG 0x34000000 1101 1102 /*deprecated don't use*/ 1103 #define DRV_MSG_CODE_INITIATE_FLR_DEPRECATED 0x02000000 1104 #define DRV_MSG_CODE_INITIATE_PF_FLR 0x02010000 1105 #define DRV_MSG_CODE_VF_DISABLED_DONE 0xc0000000 1106 #define DRV_MSG_CODE_CFG_VF_MSIX 0xc0010000 1107 /* Param is either DRV_MB_PARAM_NVM_PUT_FILE_BEGIN_MFW/IMAGE */ 1108 #define DRV_MSG_CODE_NVM_PUT_FILE_BEGIN 0x00010000 1109 /* Param should be set to the transaction size (up to 64 bytes) */ 1110 #define DRV_MSG_CODE_NVM_PUT_FILE_DATA 0x00020000 1111 /* MFW will place the file offset and len in file_att struct */ 1112 #define DRV_MSG_CODE_NVM_GET_FILE_ATT 0x00030000 1113 /* Read 32bytes of nvram data. Param is [0:23] – Offset [24:31] – 1114 * Len in Bytes 1115 */ 1116 #define DRV_MSG_CODE_NVM_READ_NVRAM 0x00050000 1117 /* Writes up to 32Bytes to nvram. Param is [0:23] – Offset [24:31] – 1118 * Len in Bytes. In case this address is in the range of secured file in 1119 * secured mode, the operation will fail 1120 */ 1121 #define DRV_MSG_CODE_NVM_WRITE_NVRAM 0x00060000 1122 /* Delete a file from nvram. Param is image_type. */ 1123 #define DRV_MSG_CODE_NVM_DEL_FILE 0x00080000 1124 /* Reset MCP when no NVM operation is going on, and no drivers are loaded. 1125 * In case operation succeed, MCP will not ack back. 1126 */ 1127 #define DRV_MSG_CODE_MCP_RESET 0x00090000 1128 /* Temporary command to set secure mode, where the param is 0 (None secure) / 1129 * 1 (Secure) / 2 (Full-Secure) 1130 */ 1131 #define DRV_MSG_CODE_SET_SECURE_MODE 0x000a0000 1132 /* Param: [0:15] - Address, [16:18] - lane# (0/1/2/3 - for single lane, 1133 * 4/5 - for dual lanes, 6 - for all lanes, [28] - PMD reg, [29] - select port, 1134 * [30:31] - port 1135 */ 1136 #define DRV_MSG_CODE_PHY_RAW_READ 0x000b0000 1137 /* Param: [0:15] - Address, [16:18] - lane# (0/1/2/3 - for single lane, 1138 * 4/5 - for dual lanes, 6 - for all lanes, [28] - PMD reg, [29] - select port, 1139 * [30:31] - port 1140 */ 1141 #define DRV_MSG_CODE_PHY_RAW_WRITE 0x000c0000 1142 /* Param: [0:15] - Address, [30:31] - port */ 1143 #define DRV_MSG_CODE_PHY_CORE_READ 0x000d0000 1144 /* Param: [0:15] - Address, [30:31] - port */ 1145 #define DRV_MSG_CODE_PHY_CORE_WRITE 0x000e0000 1146 /* Param: [0:3] - version, [4:15] - name (null terminated) */ 1147 #define DRV_MSG_CODE_SET_VERSION 0x000f0000 1148 /* Halts the MCP. To resume MCP, user will need to use 1149 * MCP_REG_CPU_STATE/MCP_REG_CPU_MODE registers. 1150 */ 1151 #define DRV_MSG_CODE_MCP_HALT 0x00100000 1152 /* Set virtual mac address, params [31:6] - reserved, [5:4] - type, 1153 * [3:0] - func, drv_data[7:0] - MAC/WWNN/WWPN 1154 */ 1155 #define DRV_MSG_CODE_SET_VMAC 0x00110000 1156 /* Set virtual mac address, params [31:6] - reserved, [5:4] - type, 1157 * [3:0] - func, drv_data[7:0] - MAC/WWNN/WWPN 1158 */ 1159 #define DRV_MSG_CODE_GET_VMAC 0x00120000 1160 #define DRV_MSG_CODE_VMAC_TYPE_MAC 1 1161 #define DRV_MSG_CODE_VMAC_TYPE_WWNN 2 1162 #define DRV_MSG_CODE_VMAC_TYPE_WWPN 3 1163 /* Get statistics from pf, params [31:4] - reserved, [3:0] - stats type */ 1164 #define DRV_MSG_CODE_GET_STATS 0x00130000 1165 #define DRV_MSG_CODE_STATS_TYPE_LAN 1 1166 #define DRV_MSG_CODE_STATS_TYPE_FCOE 2 1167 #define DRV_MSG_CODE_STATS_TYPE_ISCSI 3 1168 #define DRV_MSG_CODE_STATS_TYPE_RDMA 4 1169 /* Host shall provide buffer and size for MFW */ 1170 #define DRV_MSG_CODE_PMD_DIAG_DUMP 0x00140000 1171 /* Host shall provide buffer and size for MFW */ 1172 #define DRV_MSG_CODE_PMD_DIAG_EYE 0x00150000 1173 /* Param: [0:1] - Port, [2:7] - read size, [8:15] - I2C address, 1174 * [16:31] - offset 1175 */ 1176 #define DRV_MSG_CODE_TRANSCEIVER_READ 0x00160000 1177 /* Param: [0:1] - Port, [2:7] - write size, [8:15] - I2C address, 1178 * [16:31] - offset 1179 */ 1180 #define DRV_MSG_CODE_TRANSCEIVER_WRITE 0x00170000 1181 /* indicate OCBB related information */ 1182 #define DRV_MSG_CODE_OCBB_DATA 0x00180000 1183 /* Set function BW, params[15:8] - min, params[7:0] - max */ 1184 #define DRV_MSG_CODE_SET_BW 0x00190000 1185 #define BW_MAX_MASK 0x000000ff 1186 #define BW_MAX_SHIFT 0 1187 #define BW_MIN_MASK 0x0000ff00 1188 #define BW_MIN_SHIFT 8 1189 1190 /* When param is set to 1, all parities will be masked(disabled). When params 1191 * are set to 0, parities will be unmasked again. 1192 */ 1193 #define DRV_MSG_CODE_MASK_PARITIES 0x001a0000 1194 /* param[0] - Simulate fan failure, param[1] - simulate over temp. */ 1195 #define DRV_MSG_CODE_INDUCE_FAILURE 0x001b0000 1196 #define DRV_MSG_FAN_FAILURE_TYPE (1 << 0) 1197 #define DRV_MSG_TEMPERATURE_FAILURE_TYPE (1 << 1) 1198 /* Param: [0:15] - gpio number */ 1199 #define DRV_MSG_CODE_GPIO_READ 0x001c0000 1200 /* Param: [0:15] - gpio number, [16:31] - gpio value */ 1201 #define DRV_MSG_CODE_GPIO_WRITE 0x001d0000 1202 /* Param: [0:7] - test enum, [8:15] - image index, [16:31] - reserved */ 1203 #define DRV_MSG_CODE_BIST_TEST 0x001e0000 1204 #define DRV_MSG_CODE_GET_TEMPERATURE 0x001f0000 1205 1206 /* Set LED mode params :0 operational, 1 LED turn ON, 2 LED turn OFF */ 1207 #define DRV_MSG_CODE_SET_LED_MODE 0x00200000 1208 /* drv_data[7:0] - EPOC in seconds, drv_data[15:8] - 1209 * driver version (MAJ MIN BUILD SUB) 1210 */ 1211 #define DRV_MSG_CODE_TIMESTAMP 0x00210000 1212 /* This is an empty mailbox just return OK*/ 1213 #define DRV_MSG_CODE_EMPTY_MB 0x00220000 1214 /* Param[0:4] - resource number (0-31), Param[5:7] - opcode, 1215 * param[15:8] - age 1216 */ 1217 #define DRV_MSG_CODE_RESOURCE_CMD 0x00230000 1218 /* request resource ownership with default aging */ 1219 #define RESOURCE_OPCODE_REQ 1 1220 /* request resource ownership without aging */ 1221 #define RESOURCE_OPCODE_REQ_WO_AGING 2 1222 /* request resource ownership with specific aging timer (in seconds) */ 1223 #define RESOURCE_OPCODE_REQ_W_AGING 3 1224 #define RESOURCE_OPCODE_RELEASE 4 /* release resource */ 1225 /* force resource release */ 1226 #define RESOURCE_OPCODE_FORCE_RELEASE 5 1227 /* resource is free and granted to requester */ 1228 #define RESOURCE_OPCODE_GNT 1 1229 /* resource is busy, param[7:0] indicates owner as follow 0-15 = PF0-15, 1230 * 16 = MFW, 17 = diag over serial 1231 */ 1232 #define RESOURCE_OPCODE_BUSY 2 1233 /* indicate release request was acknowledged */ 1234 #define RESOURCE_OPCODE_RELEASED 3 1235 /* indicate release request was previously received by other owner */ 1236 #define RESOURCE_OPCODE_RELEASED_PREVIOUS 4 1237 /* indicate wrong owner during release */ 1238 #define RESOURCE_OPCODE_WRONG_OWNER 5 1239 #define RESOURCE_OPCODE_UNKNOWN_CMD 255 1240 /* dedicate resource 0 for dump */ 1241 #define RESOURCE_DUMP (1 << 0) 1242 #define DRV_MSG_CODE_GET_MBA_VERSION 0x00240000 /* Get MBA version */ 1243 /* Send crash dump commands with param[3:0] - opcode */ 1244 #define DRV_MSG_CODE_MDUMP_CMD 0x00250000 1245 #define MDUMP_DRV_PARAM_OPCODE_MASK 0x0000000f 1246 /* acknowledge reception of error indication */ 1247 #define DRV_MSG_CODE_MDUMP_ACK 0x01 1248 /* set epoc and personality as follow: drv_data[3:0] - epoch, 1249 * drv_data[7:4] - personality 1250 */ 1251 #define DRV_MSG_CODE_MDUMP_SET_VALUES 0x02 1252 /* trigger crash dump procedure */ 1253 #define DRV_MSG_CODE_MDUMP_TRIGGER 0x03 1254 /* Request valid logs and config words */ 1255 #define DRV_MSG_CODE_MDUMP_GET_CONFIG 0x04 1256 /* Set triggers mask. drv_mb_param should indicate (bitwise) which 1257 * trigger enabled 1258 */ 1259 #define DRV_MSG_CODE_MDUMP_SET_ENABLE 0x05 1260 /* Clear all logs */ 1261 #define DRV_MSG_CODE_MDUMP_CLEAR_LOGS 0x06 1262 #define DRV_MSG_CODE_MEM_ECC_EVENTS 0x00260000 /* Param: None */ 1263 /* Param: [0:15] - gpio number */ 1264 #define DRV_MSG_CODE_GPIO_INFO 0x00270000 1265 /* Value will be placed in union */ 1266 #define DRV_MSG_CODE_EXT_PHY_READ 0x00280000 1267 /* Value should be placed in union */ 1268 #define DRV_MSG_CODE_EXT_PHY_WRITE 0x00290000 1269 #define DRV_MB_PARAM_ADDR_SHIFT 0 1270 #define DRV_MB_PARAM_ADDR_MASK 0x0000FFFF 1271 #define DRV_MB_PARAM_DEVAD_SHIFT 16 1272 #define DRV_MB_PARAM_DEVAD_MASK 0x001F0000 1273 #define DRV_MB_PARAM_PORT_SHIFT 21 1274 #define DRV_MB_PARAM_PORT_MASK 0x00600000 1275 #define DRV_MSG_CODE_EXT_PHY_FW_UPGRADE 0x002a0000 1276 1277 #define DRV_MSG_SEQ_NUMBER_MASK 0x0000ffff 1278 1279 u32 drv_mb_param; 1280 /* UNLOAD_REQ params */ 1281 #define DRV_MB_PARAM_UNLOAD_WOL_UNKNOWN 0x00000000 1282 #define DRV_MB_PARAM_UNLOAD_WOL_MCP 0x00000001 1283 #define DRV_MB_PARAM_UNLOAD_WOL_DISABLED 0x00000002 1284 #define DRV_MB_PARAM_UNLOAD_WOL_ENABLED 0x00000003 1285 1286 /* UNLOAD_DONE_params */ 1287 #define DRV_MB_PARAM_UNLOAD_NON_D3_POWER 0x00000001 1288 1289 /* INIT_PHY params */ 1290 #define DRV_MB_PARAM_INIT_PHY_FORCE 0x00000001 1291 #define DRV_MB_PARAM_INIT_PHY_DONT_CARE 0x00000002 1292 1293 /* LLDP / DCBX params*/ 1294 #define DRV_MB_PARAM_LLDP_SEND_MASK 0x00000001 1295 #define DRV_MB_PARAM_LLDP_SEND_SHIFT 0 1296 #define DRV_MB_PARAM_LLDP_AGENT_MASK 0x00000006 1297 #define DRV_MB_PARAM_LLDP_AGENT_SHIFT 1 1298 #define DRV_MB_PARAM_DCBX_NOTIFY_MASK 0x00000008 1299 #define DRV_MB_PARAM_DCBX_NOTIFY_SHIFT 3 1300 1301 #define DRV_MB_PARAM_NIG_DRAIN_PERIOD_MS_MASK 0x000000FF 1302 #define DRV_MB_PARAM_NIG_DRAIN_PERIOD_MS_SHIFT 0 1303 1304 #define DRV_MB_PARAM_NVM_PUT_FILE_BEGIN_MFW 0x1 1305 #define DRV_MB_PARAM_NVM_PUT_FILE_BEGIN_IMAGE 0x2 1306 1307 #define DRV_MB_PARAM_NVM_OFFSET_SHIFT 0 1308 #define DRV_MB_PARAM_NVM_OFFSET_MASK 0x00FFFFFF 1309 #define DRV_MB_PARAM_NVM_LEN_SHIFT 24 1310 #define DRV_MB_PARAM_NVM_LEN_MASK 0xFF000000 1311 1312 #define DRV_MB_PARAM_PHY_ADDR_SHIFT 0 1313 #define DRV_MB_PARAM_PHY_ADDR_MASK 0x1FF0FFFF 1314 #define DRV_MB_PARAM_PHY_LANE_SHIFT 16 1315 #define DRV_MB_PARAM_PHY_LANE_MASK 0x000F0000 1316 #define DRV_MB_PARAM_PHY_SELECT_PORT_SHIFT 29 1317 #define DRV_MB_PARAM_PHY_SELECT_PORT_MASK 0x20000000 1318 #define DRV_MB_PARAM_PHY_PORT_SHIFT 30 1319 #define DRV_MB_PARAM_PHY_PORT_MASK 0xc0000000 1320 1321 #define DRV_MB_PARAM_PHYMOD_LANE_SHIFT 0 1322 #define DRV_MB_PARAM_PHYMOD_LANE_MASK 0x000000FF 1323 #define DRV_MB_PARAM_PHYMOD_SIZE_SHIFT 8 1324 #define DRV_MB_PARAM_PHYMOD_SIZE_MASK 0x000FFF00 1325 /* configure vf MSIX params*/ 1326 #define DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_SHIFT 0 1327 #define DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_MASK 0x000000FF 1328 #define DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_SHIFT 8 1329 #define DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_MASK 0x0000FF00 1330 1331 /* OneView configuration parametres */ 1332 #define DRV_MB_PARAM_OV_CURR_CFG_SHIFT 0 1333 #define DRV_MB_PARAM_OV_CURR_CFG_MASK 0x0000000F 1334 #define DRV_MB_PARAM_OV_CURR_CFG_NONE 0 1335 #define DRV_MB_PARAM_OV_CURR_CFG_OS 1 1336 #define DRV_MB_PARAM_OV_CURR_CFG_VENDOR_SPEC 2 1337 #define DRV_MB_PARAM_OV_CURR_CFG_OTHER 3 1338 #define DRV_MB_PARAM_OV_CURR_CFG_VC_CLP 4 1339 #define DRV_MB_PARAM_OV_CURR_CFG_CNU 5 1340 #define DRV_MB_PARAM_OV_CURR_CFG_DCI 6 1341 #define DRV_MB_PARAM_OV_CURR_CFG_HII 7 1342 1343 #define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_SHIFT 0 1344 #define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_MASK 0x000000FF 1345 #define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_NONE (1 << 0) 1346 #define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_ISCSI_IP_ACQUIRED (1 << 1) 1347 #define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_FCOE_FABRIC_LOGIN_SUCCESS (1 << 1) 1348 #define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_TRARGET_FOUND (1 << 2) 1349 #define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_ISCSI_CHAP_SUCCESS (1 << 3) 1350 #define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_FCOE_LUN_FOUND (1 << 3) 1351 #define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_LOGGED_INTO_TGT (1 << 4) 1352 #define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_IMG_DOWNLOADED (1 << 5) 1353 #define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_OS_HANDOFF (1 << 6) 1354 #define DRV_MB_PARAM_OV_UPDATE_BOOT_COMPLETED 0 1355 1356 #define DRV_MB_PARAM_OV_PCI_BUS_NUM_SHIFT 0 1357 #define DRV_MB_PARAM_OV_PCI_BUS_NUM_MASK 0x000000FF 1358 1359 #define DRV_MB_PARAM_OV_STORM_FW_VER_SHIFT 0 1360 #define DRV_MB_PARAM_OV_STORM_FW_VER_MASK 0xFFFFFFFF 1361 #define DRV_MB_PARAM_OV_STORM_FW_VER_MAJOR_MASK 0xFF000000 1362 #define DRV_MB_PARAM_OV_STORM_FW_VER_MINOR_MASK 0x00FF0000 1363 #define DRV_MB_PARAM_OV_STORM_FW_VER_BUILD_MASK 0x0000FF00 1364 #define DRV_MB_PARAM_OV_STORM_FW_VER_DROP_MASK 0x000000FF 1365 1366 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_SHIFT 0 1367 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_MASK 0xF 1368 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_UNKNOWN 0x1 1369 /* Not Installed*/ 1370 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_NOT_LOADED 0x2 1371 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_LOADING 0x3 1372 /* installed but disabled by user/admin/OS */ 1373 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_DISABLED 0x4 1374 /* installed and active */ 1375 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_ACTIVE 0x5 1376 1377 #define DRV_MB_PARAM_OV_MTU_SIZE_SHIFT 0 1378 #define DRV_MB_PARAM_OV_MTU_SIZE_MASK 0xFFFFFFFF 1379 1380 #define DRV_MB_PARAM_SET_LED_MODE_OPER 0x0 1381 #define DRV_MB_PARAM_SET_LED_MODE_ON 0x1 1382 #define DRV_MB_PARAM_SET_LED_MODE_OFF 0x2 1383 1384 #define DRV_MB_PARAM_TRANSCEIVER_PORT_SHIFT 0 1385 #define DRV_MB_PARAM_TRANSCEIVER_PORT_MASK 0x00000003 1386 #define DRV_MB_PARAM_TRANSCEIVER_SIZE_SHIFT 2 1387 #define DRV_MB_PARAM_TRANSCEIVER_SIZE_MASK 0x000000FC 1388 #define DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_SHIFT 8 1389 #define DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_MASK 0x0000FF00 1390 #define DRV_MB_PARAM_TRANSCEIVER_OFFSET_SHIFT 16 1391 #define DRV_MB_PARAM_TRANSCEIVER_OFFSET_MASK 0xFFFF0000 1392 1393 #define DRV_MB_PARAM_GPIO_NUMBER_SHIFT 0 1394 #define DRV_MB_PARAM_GPIO_NUMBER_MASK 0x0000FFFF 1395 #define DRV_MB_PARAM_GPIO_VALUE_SHIFT 16 1396 #define DRV_MB_PARAM_GPIO_VALUE_MASK 0xFFFF0000 1397 #define DRV_MB_PARAM_GPIO_DIRECTION_SHIFT 16 1398 #define DRV_MB_PARAM_GPIO_DIRECTION_MASK 0x00FF0000 1399 #define DRV_MB_PARAM_GPIO_CTRL_SHIFT 24 1400 #define DRV_MB_PARAM_GPIO_CTRL_MASK 0xFF000000 1401 1402 /* Resource Allocation params - Driver version support*/ 1403 #define DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_MASK 0xFFFF0000 1404 #define DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_SHIFT 16 1405 #define DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_MASK 0x0000FFFF 1406 #define DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_SHIFT 0 1407 1408 #define DRV_MB_PARAM_BIST_UNKNOWN_TEST 0 1409 #define DRV_MB_PARAM_BIST_REGISTER_TEST 1 1410 #define DRV_MB_PARAM_BIST_CLOCK_TEST 2 1411 #define DRV_MB_PARAM_BIST_NVM_TEST_NUM_IMAGES 3 1412 #define DRV_MB_PARAM_BIST_NVM_TEST_IMAGE_BY_INDEX 4 1413 1414 #define DRV_MB_PARAM_BIST_RC_UNKNOWN 0 1415 #define DRV_MB_PARAM_BIST_RC_PASSED 1 1416 #define DRV_MB_PARAM_BIST_RC_FAILED 2 1417 #define DRV_MB_PARAM_BIST_RC_INVALID_PARAMETER 3 1418 1419 #define DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT 0 1420 #define DRV_MB_PARAM_BIST_TEST_INDEX_MASK 0x000000FF 1421 #define DRV_MB_PARAM_BIST_TEST_IMAGE_INDEX_SHIFT 8 1422 #define DRV_MB_PARAM_BIST_TEST_IMAGE_INDEX_MASK 0x0000FF00 1423 1424 u32 fw_mb_header; 1425 #define FW_MSG_CODE_MASK 0xffff0000 1426 #define FW_MSG_CODE_DRV_LOAD_ENGINE 0x10100000 1427 #define FW_MSG_CODE_DRV_LOAD_PORT 0x10110000 1428 #define FW_MSG_CODE_DRV_LOAD_FUNCTION 0x10120000 1429 #define FW_MSG_CODE_DRV_LOAD_REFUSED_PDA 0x10200000 1430 #define FW_MSG_CODE_DRV_LOAD_REFUSED_HSI 0x10210000 1431 #define FW_MSG_CODE_DRV_LOAD_REFUSED_DIAG 0x10220000 1432 #define FW_MSG_CODE_DRV_LOAD_DONE 0x11100000 1433 #define FW_MSG_CODE_DRV_UNLOAD_ENGINE 0x20110000 1434 #define FW_MSG_CODE_DRV_UNLOAD_PORT 0x20120000 1435 #define FW_MSG_CODE_DRV_UNLOAD_FUNCTION 0x20130000 1436 #define FW_MSG_CODE_DRV_UNLOAD_DONE 0x21100000 1437 #define FW_MSG_CODE_INIT_PHY_DONE 0x21200000 1438 #define FW_MSG_CODE_INIT_PHY_ERR_INVALID_ARGS 0x21300000 1439 #define FW_MSG_CODE_LINK_RESET_DONE 0x23000000 1440 #define FW_MSG_CODE_SET_LLDP_DONE 0x24000000 1441 #define FW_MSG_CODE_SET_LLDP_UNSUPPORTED_AGENT 0x24010000 1442 #define FW_MSG_CODE_SET_DCBX_DONE 0x25000000 1443 #define FW_MSG_CODE_UPDATE_CURR_CFG_DONE 0x26000000 1444 #define FW_MSG_CODE_UPDATE_BUS_NUM_DONE 0x27000000 1445 #define FW_MSG_CODE_UPDATE_BOOT_PROGRESS_DONE 0x28000000 1446 #define FW_MSG_CODE_UPDATE_STORM_FW_VER_DONE 0x29000000 1447 #define FW_MSG_CODE_UPDATE_DRIVER_STATE_DONE 0x31000000 1448 #define FW_MSG_CODE_DRV_MSG_CODE_BW_UPDATE_DONE 0x32000000 1449 #define FW_MSG_CODE_DRV_MSG_CODE_MTU_SIZE_DONE 0x33000000 1450 #define FW_MSG_CODE_RESOURCE_ALLOC_OK 0x34000000 1451 #define FW_MSG_CODE_RESOURCE_ALLOC_UNKNOWN 0x35000000 1452 #define FW_MSG_CODE_RESOURCE_ALLOC_DEPRECATED 0x36000000 1453 #define FW_MSG_CODE_RESOURCE_ALLOC_GEN_ERR 0x37000000 1454 #define FW_MSG_CODE_NIG_DRAIN_DONE 0x30000000 1455 #define FW_MSG_CODE_VF_DISABLED_DONE 0xb0000000 1456 #define FW_MSG_CODE_DRV_CFG_VF_MSIX_DONE 0xb0010000 1457 #define FW_MSG_CODE_FLR_ACK 0x02000000 1458 #define FW_MSG_CODE_FLR_NACK 0x02100000 1459 #define FW_MSG_CODE_SET_DRIVER_DONE 0x02200000 1460 #define FW_MSG_CODE_SET_VMAC_SUCCESS 0x02300000 1461 #define FW_MSG_CODE_SET_VMAC_FAIL 0x02400000 1462 1463 #define FW_MSG_CODE_NVM_OK 0x00010000 1464 #define FW_MSG_CODE_NVM_INVALID_MODE 0x00020000 1465 #define FW_MSG_CODE_NVM_PREV_CMD_WAS_NOT_FINISHED 0x00030000 1466 #define FW_MSG_CODE_NVM_FAILED_TO_ALLOCATE_PAGE 0x00040000 1467 #define FW_MSG_CODE_NVM_INVALID_DIR_FOUND 0x00050000 1468 #define FW_MSG_CODE_NVM_PAGE_NOT_FOUND 0x00060000 1469 #define FW_MSG_CODE_NVM_FAILED_PARSING_BNDLE_HEADER 0x00070000 1470 #define FW_MSG_CODE_NVM_FAILED_PARSING_IMAGE_HEADER 0x00080000 1471 #define FW_MSG_CODE_NVM_PARSING_OUT_OF_SYNC 0x00090000 1472 #define FW_MSG_CODE_NVM_FAILED_UPDATING_DIR 0x000a0000 1473 #define FW_MSG_CODE_NVM_FAILED_TO_FREE_PAGE 0x000b0000 1474 #define FW_MSG_CODE_NVM_FILE_NOT_FOUND 0x000c0000 1475 #define FW_MSG_CODE_NVM_OPERATION_FAILED 0x000d0000 1476 #define FW_MSG_CODE_NVM_FAILED_UNALIGNED 0x000e0000 1477 #define FW_MSG_CODE_NVM_BAD_OFFSET 0x000f0000 1478 #define FW_MSG_CODE_NVM_BAD_SIGNATURE 0x00100000 1479 #define FW_MSG_CODE_NVM_FILE_READ_ONLY 0x00200000 1480 #define FW_MSG_CODE_NVM_UNKNOWN_FILE 0x00300000 1481 #define FW_MSG_CODE_NVM_PUT_FILE_FINISH_OK 0x00400000 1482 /* MFW reject "mcp reset" command if one of the drivers is up */ 1483 #define FW_MSG_CODE_MCP_RESET_REJECT 0x00600000 1484 #define FW_MSG_CODE_PHY_OK 0x00110000 1485 #define FW_MSG_CODE_PHY_ERROR 0x00120000 1486 #define FW_MSG_CODE_SET_SECURE_MODE_ERROR 0x00130000 1487 #define FW_MSG_CODE_SET_SECURE_MODE_OK 0x00140000 1488 #define FW_MSG_MODE_PHY_PRIVILEGE_ERROR 0x00150000 1489 #define FW_MSG_CODE_OK 0x00160000 1490 #define FW_MSG_CODE_LED_MODE_INVALID 0x00170000 1491 #define FW_MSG_CODE_PHY_DIAG_OK 0x00160000 1492 #define FW_MSG_CODE_PHY_DIAG_ERROR 0x00170000 1493 #define FW_MSG_CODE_INIT_HW_FAILED_TO_ALLOCATE_PAGE 0x00040000 1494 #define FW_MSG_CODE_INIT_HW_FAILED_BAD_STATE 0x00170000 1495 #define FW_MSG_CODE_INIT_HW_FAILED_TO_SET_WINDOW 0x000d0000 1496 #define FW_MSG_CODE_INIT_HW_FAILED_NO_IMAGE 0x000c0000 1497 #define FW_MSG_CODE_INIT_HW_FAILED_VERSION_MISMATCH 0x00100000 1498 #define FW_MSG_CODE_TRANSCEIVER_DIAG_OK 0x00160000 1499 #define FW_MSG_CODE_TRANSCEIVER_DIAG_ERROR 0x00170000 1500 #define FW_MSG_CODE_TRANSCEIVER_NOT_PRESENT 0x00020000 1501 #define FW_MSG_CODE_TRANSCEIVER_BAD_BUFFER_SIZE 0x000f0000 1502 #define FW_MSG_CODE_GPIO_OK 0x00160000 1503 #define FW_MSG_CODE_GPIO_DIRECTION_ERR 0x00170000 1504 #define FW_MSG_CODE_GPIO_CTRL_ERR 0x00020000 1505 #define FW_MSG_CODE_GPIO_INVALID 0x000f0000 1506 #define FW_MSG_CODE_GPIO_INVALID_VALUE 0x00050000 1507 #define FW_MSG_CODE_BIST_TEST_INVALID 0x000f0000 1508 #define FW_MSG_CODE_EXTPHY_INVALID_IMAGE_HEADER 0x00700000 1509 #define FW_MSG_CODE_EXTPHY_INVALID_PHY_TYPE 0x00710000 1510 #define FW_MSG_CODE_EXTPHY_OPERATION_FAILED 0x00720000 1511 #define FW_MSG_CODE_EXTPHY_NO_PHY_DETECTED 0x00730000 1512 1513 /* mdump related response codes */ 1514 #define FW_MSG_CODE_MDUMP_NO_IMAGE_FOUND 0x00010000 1515 #define FW_MSG_CODE_MDUMP_ALLOC_FAILED 0x00020000 1516 #define FW_MSG_CODE_MDUMP_INVALID_CMD 0x00030000 1517 #define FW_MSG_CODE_MDUMP_IN_PROGRESS 0x00040000 1518 #define FW_MSG_CODE_MDUMP_WRITE_FAILED 0x00050000 1519 1520 #define FW_MSG_SEQ_NUMBER_MASK 0x0000ffff 1521 1522 1523 u32 fw_mb_param; 1524 /* Resource Allocation params - MFW version support*/ 1525 #define FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_MASK 0xFFFF0000 1526 #define FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_SHIFT 16 1527 #define FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_MASK 0x0000FFFF 1528 #define FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_SHIFT 0 1529 1530 1531 u32 drv_pulse_mb; 1532 #define DRV_PULSE_SEQ_MASK 0x00007fff 1533 #define DRV_PULSE_SYSTEM_TIME_MASK 0xffff0000 1534 /* 1535 * The system time is in the format of 1536 * (year-2001)*12*32 + month*32 + day. 1537 */ 1538 #define DRV_PULSE_ALWAYS_ALIVE 0x00008000 1539 /* 1540 * Indicate to the firmware not to go into the 1541 * OS-absent when it is not getting driver pulse. 1542 * This is used for debugging as well for PXE(MBA). 1543 */ 1544 1545 u32 mcp_pulse_mb; 1546 #define MCP_PULSE_SEQ_MASK 0x00007fff 1547 #define MCP_PULSE_ALWAYS_ALIVE 0x00008000 1548 /* Indicates to the driver not to assert due to lack 1549 * of MCP response 1550 */ 1551 #define MCP_EVENT_MASK 0xffff0000 1552 #define MCP_EVENT_OTHER_DRIVER_RESET_REQ 0x00010000 1553 1554 /* The union data is used by the driver to pass parameters to the scratchpad. */ 1555 1556 union drv_union_data union_data; 1557 1558 }; 1559 1560 /* MFW - DRV MB */ 1561 /********************************************************************** 1562 * Description 1563 * Incremental Aggregative 1564 * 8-bit MFW counter per message 1565 * 8-bit ack-counter per message 1566 * Capabilities 1567 * Provides up to 256 aggregative message per type 1568 * Provides 4 message types in dword 1569 * Message type pointers to byte offset 1570 * Backward Compatibility by using sizeof for the counters. 1571 * No lock requires for 32bit messages 1572 * Limitations: 1573 * In case of messages greater than 32bit, a dedicated mechanism(e.g lock) 1574 * is required to prevent data corruption. 1575 **********************************************************************/ 1576 enum MFW_DRV_MSG_TYPE { 1577 MFW_DRV_MSG_LINK_CHANGE, 1578 MFW_DRV_MSG_FLR_FW_ACK_FAILED, 1579 MFW_DRV_MSG_VF_DISABLED, 1580 MFW_DRV_MSG_LLDP_DATA_UPDATED, 1581 MFW_DRV_MSG_DCBX_REMOTE_MIB_UPDATED, 1582 MFW_DRV_MSG_DCBX_OPERATIONAL_MIB_UPDATED, 1583 MFW_DRV_MSG_ERROR_RECOVERY, 1584 MFW_DRV_MSG_BW_UPDATE, 1585 MFW_DRV_MSG_S_TAG_UPDATE, 1586 MFW_DRV_MSG_GET_LAN_STATS, 1587 MFW_DRV_MSG_GET_FCOE_STATS, 1588 MFW_DRV_MSG_GET_ISCSI_STATS, 1589 MFW_DRV_MSG_GET_RDMA_STATS, 1590 MFW_DRV_MSG_FAILURE_DETECTED, 1591 MFW_DRV_MSG_TRANSCEIVER_STATE_CHANGE, 1592 MFW_DRV_MSG_CRITICAL_ERROR_OCCURRED, 1593 MFW_DRV_MSG_EEE_NEGOTIATION_COMPLETE, 1594 MFW_DRV_MSG_MAX 1595 }; 1596 1597 #define MFW_DRV_MSG_MAX_DWORDS(msgs) (((msgs - 1) >> 2) + 1) 1598 #define MFW_DRV_MSG_DWORD(msg_id) (msg_id >> 2) 1599 #define MFW_DRV_MSG_OFFSET(msg_id) ((msg_id & 0x3) << 3) 1600 #define MFW_DRV_MSG_MASK(msg_id) (0xff << MFW_DRV_MSG_OFFSET(msg_id)) 1601 1602 #ifdef BIG_ENDIAN /* Like MFW */ 1603 #define DRV_ACK_MSG(msg_p, msg_id) \ 1604 ((u8)((u8 *)msg_p)[msg_id]++;) 1605 #else 1606 #define DRV_ACK_MSG(msg_p, msg_id) \ 1607 ((u8)((u8 *)msg_p)[((msg_id & ~3) | ((~msg_id) & 3))]++;) 1608 #endif 1609 1610 #define MFW_DRV_UPDATE(shmem_func, msg_id) \ 1611 ((u8)((u8 *)(MFW_MB_P(shmem_func)->msg))[msg_id]++;) 1612 1613 struct public_mfw_mb { 1614 u32 sup_msgs; /* Assigend with MFW_DRV_MSG_MAX */ 1615 /* Incremented by the MFW */ 1616 u32 msg[MFW_DRV_MSG_MAX_DWORDS(MFW_DRV_MSG_MAX)]; 1617 /* Incremented by the driver */ 1618 u32 ack[MFW_DRV_MSG_MAX_DWORDS(MFW_DRV_MSG_MAX)]; 1619 }; 1620 1621 /**************************************/ 1622 /* */ 1623 /* P U B L I C D A T A */ 1624 /* */ 1625 /**************************************/ 1626 enum public_sections { 1627 PUBLIC_DRV_MB, /* Points to the first drv_mb of path0 */ 1628 PUBLIC_MFW_MB, /* Points to the first mfw_mb of path0 */ 1629 PUBLIC_GLOBAL, 1630 PUBLIC_PATH, 1631 PUBLIC_PORT, 1632 PUBLIC_FUNC, 1633 PUBLIC_MAX_SECTIONS 1634 }; 1635 1636 struct drv_ver_info_stc { 1637 u32 ver; 1638 u8 name[32]; 1639 }; 1640 1641 /* Runtime data needs about 1/2K. We use 2K to be on the safe side. 1642 * Please make sure data does not exceed this size. 1643 */ 1644 #define NUM_RUNTIME_DWORDS 16 1645 struct drv_init_hw_stc { 1646 u32 init_hw_bitmask[NUM_RUNTIME_DWORDS]; 1647 u32 init_hw_data[NUM_RUNTIME_DWORDS * 32]; 1648 }; 1649 1650 struct mcp_public_data { 1651 /* The sections fields is an array */ 1652 u32 num_sections; 1653 offsize_t sections[PUBLIC_MAX_SECTIONS]; 1654 struct public_drv_mb drv_mb[MCP_GLOB_FUNC_MAX]; 1655 struct public_mfw_mb mfw_mb[MCP_GLOB_FUNC_MAX]; 1656 struct public_global global; 1657 struct public_path path[MCP_GLOB_PATH_MAX]; 1658 struct public_port port[MCP_GLOB_PORT_MAX]; 1659 struct public_func func[MCP_GLOB_FUNC_MAX]; 1660 }; 1661 1662 #define I2C_TRANSCEIVER_ADDR 0xa0 1663 #define MAX_I2C_TRANSACTION_SIZE 16 1664 #define MAX_I2C_TRANSCEIVER_PAGE_SIZE 256 1665 1666 #endif /* MCP_PUBLIC_H */ 1667