1 /* 2 * Copyright (c) 2016 QLogic Corporation. 3 * All rights reserved. 4 * www.qlogic.com 5 * 6 * See LICENSE.qede_pmd for copyright and licensing details. 7 */ 8 9 /**************************************************************************** 10 * 11 * Name: mcp_public.h 12 * 13 * Description: MCP public data 14 * 15 * Created: 13/01/2013 yanivr 16 * 17 ****************************************************************************/ 18 19 #ifndef MCP_PUBLIC_H 20 #define MCP_PUBLIC_H 21 22 #define VF_MAX_STATIC 192 /* In case of AH */ 23 24 #define MCP_GLOB_PATH_MAX 2 25 #define MCP_PORT_MAX 2 /* Global */ 26 #define MCP_GLOB_PORT_MAX 4 /* Global */ 27 #define MCP_GLOB_FUNC_MAX 16 /* Global */ 28 29 typedef u32 offsize_t; /* In DWORDS !!! */ 30 /* Offset from the beginning of the MCP scratchpad */ 31 #define OFFSIZE_OFFSET_SHIFT 0 32 #define OFFSIZE_OFFSET_MASK 0x0000ffff 33 /* Size of specific element (not the whole array if any) */ 34 #define OFFSIZE_SIZE_SHIFT 16 35 #define OFFSIZE_SIZE_MASK 0xffff0000 36 37 /* SECTION_OFFSET is calculating the offset in bytes out of offsize */ 38 #define SECTION_OFFSET(_offsize) \ 39 ((((_offsize & OFFSIZE_OFFSET_MASK) >> OFFSIZE_OFFSET_SHIFT) << 2)) 40 41 /* SECTION_SIZE is calculating the size in bytes out of offsize */ 42 #define SECTION_SIZE(_offsize) \ 43 (((_offsize & OFFSIZE_SIZE_MASK) >> OFFSIZE_SIZE_SHIFT) << 2) 44 45 /* SECTION_ADDR returns the GRC addr of a section, given offsize and index 46 * within section 47 */ 48 #define SECTION_ADDR(_offsize, idx) \ 49 (MCP_REG_SCRATCH + \ 50 SECTION_OFFSET(_offsize) + (SECTION_SIZE(_offsize) * idx)) 51 52 /* SECTION_OFFSIZE_ADDR returns the GRC addr to the offsize address. Use 53 * offsetof, since the OFFSETUP collide with the firmware definition 54 */ 55 #define SECTION_OFFSIZE_ADDR(_pub_base, _section) \ 56 (_pub_base + offsetof(struct mcp_public_data, sections[_section])) 57 /* PHY configuration */ 58 struct eth_phy_cfg { 59 /* 0 = autoneg, 1000/10000/20000/25000/40000/50000/100000 */ 60 u32 speed; 61 #define ETH_SPEED_AUTONEG 0 62 #define ETH_SPEED_SMARTLINQ 0x8 63 64 u32 pause; /* bitmask */ 65 #define ETH_PAUSE_NONE 0x0 66 #define ETH_PAUSE_AUTONEG 0x1 67 #define ETH_PAUSE_RX 0x2 68 #define ETH_PAUSE_TX 0x4 69 70 u32 adv_speed; /* Default should be the speed_cap_mask */ 71 u32 loopback_mode; 72 #define ETH_LOOPBACK_NONE (0) 73 /* Serdes loopback. In AH, it refers to Near End */ 74 #define ETH_LOOPBACK_INT_PHY (1) 75 #define ETH_LOOPBACK_EXT_PHY (2) /* External PHY Loopback */ 76 /* External Loopback (Require loopback plug) */ 77 #define ETH_LOOPBACK_EXT (3) 78 #define ETH_LOOPBACK_MAC (4) /* MAC Loopback - not supported */ 79 #define ETH_LOOPBACK_CNIG_AH_ONLY_0123 (5) /* Port to itself */ 80 #define ETH_LOOPBACK_CNIG_AH_ONLY_2301 (6) /* Port to Port */ 81 #define ETH_LOOPBACK_PCS_AH_ONLY (7) /* PCS loopback (TX to RX) */ 82 /* Loop RX packet from PCS to TX */ 83 #define ETH_LOOPBACK_REVERSE_MAC_AH_ONLY (8) 84 /* Remote Serdes Loopback (RX to TX) */ 85 #define ETH_LOOPBACK_INT_PHY_FEA_AH_ONLY (9) 86 87 /* Used to configure the EEE Tx LPI timer, has several modes of 88 * operation, according to bits 29:28 89 * 2'b00: Timer will be configured by nvram, output will be the value 90 * from nvram. 91 * 2'b01: Timer will be configured by nvram, output will be in 92 * 16xmicroseconds. 93 * 2'b10: bits 1:0 contain an nvram value which will be used instead 94 * of the one located in the nvram. Output will be that value. 95 * 2'b11: bits 19:0 contain the idle timer in microseconds; output 96 * will be in 16xmicroseconds. 97 * Bits 31:30 should be 2'b11 in order for EEE to be enabled. 98 */ 99 u32 eee_mode; 100 #define EEE_MODE_TIMER_USEC_MASK (0x000fffff) 101 #define EEE_MODE_TIMER_USEC_OFFSET (0) 102 #define EEE_MODE_TIMER_USEC_BALANCED_TIME (0xa00) 103 #define EEE_MODE_TIMER_USEC_AGGRESSIVE_TIME (0x100) 104 #define EEE_MODE_TIMER_USEC_LATENCY_TIME (0x6000) 105 /* Set by the driver to request status timer will be in microseconds and and not 106 * in EEE policy definition 107 */ 108 #define EEE_MODE_OUTPUT_TIME (1 << 28) 109 /* Set by the driver to override default nvm timer */ 110 #define EEE_MODE_OVERRIDE_NVRAM (1 << 29) 111 #define EEE_MODE_ENABLE_LPI (1 << 30) /* Set when */ 112 #define EEE_MODE_ADV_LPI (1 << 31) /* Set when EEE is enabled */ 113 }; 114 115 struct port_mf_cfg { 116 u32 dynamic_cfg; /* device control channel */ 117 #define PORT_MF_CFG_OV_TAG_MASK 0x0000ffff 118 #define PORT_MF_CFG_OV_TAG_SHIFT 0 119 #define PORT_MF_CFG_OV_TAG_DEFAULT PORT_MF_CFG_OV_TAG_MASK 120 121 u32 reserved[1]; 122 }; 123 124 /* DO NOT add new fields in the middle 125 * MUST be synced with struct pmm_stats_map 126 */ 127 struct eth_stats { 128 u64 r64; /* 0x00 (Offset 0x00 ) RX 64-byte frame counter*/ 129 u64 r127; /* 0x01 (Offset 0x08 ) RX 65 to 127 byte frame counter*/ 130 u64 r255; /* 0x02 (Offset 0x10 ) RX 128 to 255 byte frame counter*/ 131 u64 r511; /* 0x03 (Offset 0x18 ) RX 256 to 511 byte frame counter*/ 132 u64 r1023; /* 0x04 (Offset 0x20 ) RX 512 to 1023 byte frame counter*/ 133 /* 0x05 (Offset 0x28 ) RX 1024 to 1518 byte frame counter */ 134 u64 r1518; 135 /* 0x06 (Offset 0x30 ) RX 1519 to 1522 byte VLAN-tagged frame counter */ 136 u64 r1522; 137 u64 r2047; /* 0x07 (Offset 0x38 ) RX 1519 to 2047 byte frame counter*/ 138 u64 r4095; /* 0x08 (Offset 0x40 ) RX 2048 to 4095 byte frame counter*/ 139 u64 r9216; /* 0x09 (Offset 0x48 ) RX 4096 to 9216 byte frame counter*/ 140 /* 0x0A (Offset 0x50 ) RX 9217 to 16383 byte frame counter */ 141 u64 r16383; 142 u64 rfcs; /* 0x0F (Offset 0x58 ) RX FCS error frame counter*/ 143 u64 rxcf; /* 0x10 (Offset 0x60 ) RX control frame counter*/ 144 u64 rxpf; /* 0x11 (Offset 0x68 ) RX pause frame counter*/ 145 u64 rxpp; /* 0x12 (Offset 0x70 ) RX PFC frame counter*/ 146 u64 raln; /* 0x16 (Offset 0x78 ) RX alignment error counter*/ 147 u64 rfcr; /* 0x19 (Offset 0x80 ) RX false carrier counter */ 148 u64 rovr; /* 0x1A (Offset 0x88 ) RX oversized frame counter*/ 149 u64 rjbr; /* 0x1B (Offset 0x90 ) RX jabber frame counter */ 150 u64 rund; /* 0x34 (Offset 0x98 ) RX undersized frame counter */ 151 u64 rfrg; /* 0x35 (Offset 0xa0 ) RX fragment counter */ 152 u64 t64; /* 0x40 (Offset 0xa8 ) TX 64-byte frame counter */ 153 u64 t127; /* 0x41 (Offset 0xb0 ) TX 65 to 127 byte frame counter */ 154 u64 t255; /* 0x42 (Offset 0xb8 ) TX 128 to 255 byte frame counter*/ 155 u64 t511; /* 0x43 (Offset 0xc0 ) TX 256 to 511 byte frame counter*/ 156 u64 t1023; /* 0x44 (Offset 0xc8 ) TX 512 to 1023 byte frame counter*/ 157 /* 0x45 (Offset 0xd0 ) TX 1024 to 1518 byte frame counter */ 158 u64 t1518; 159 /* 0x47 (Offset 0xd8 ) TX 1519 to 2047 byte frame counter */ 160 u64 t2047; 161 /* 0x48 (Offset 0xe0 ) TX 2048 to 4095 byte frame counter */ 162 u64 t4095; 163 /* 0x49 (Offset 0xe8 ) TX 4096 to 9216 byte frame counter */ 164 u64 t9216; 165 /* 0x4A (Offset 0xf0 ) TX 9217 to 16383 byte frame counter */ 166 u64 t16383; 167 u64 txpf; /* 0x50 (Offset 0xf8 ) TX pause frame counter */ 168 u64 txpp; /* 0x51 (Offset 0x100) TX PFC frame counter */ 169 /* 0x6C (Offset 0x108) Transmit Logical Type LLFC message counter */ 170 u64 tlpiec; 171 u64 tncl; /* 0x6E (Offset 0x110) Transmit Total Collision Counter */ 172 u64 rbyte; /* 0x3d (Offset 0x118) RX byte counter */ 173 u64 rxuca; /* 0x0c (Offset 0x120) RX UC frame counter */ 174 u64 rxmca; /* 0x0d (Offset 0x128) RX MC frame counter */ 175 u64 rxbca; /* 0x0e (Offset 0x130) RX BC frame counter */ 176 /* 0x22 (Offset 0x138) RX good frame (good CRC, not oversized, no ERROR) */ 177 u64 rxpok; 178 u64 tbyte; /* 0x6f (Offset 0x140) TX byte counter */ 179 u64 txuca; /* 0x4d (Offset 0x148) TX UC frame counter */ 180 u64 txmca; /* 0x4e (Offset 0x150) TX MC frame counter */ 181 u64 txbca; /* 0x4f (Offset 0x158) TX BC frame counter */ 182 u64 txcf; /* 0x54 (Offset 0x160) TX control frame counter */ 183 /* HSI - Cannot add more stats to this struct. If needed, then need to open new 184 * struct 185 */ 186 187 }; 188 189 struct brb_stats { 190 u64 brb_truncate[8]; 191 u64 brb_discard[8]; 192 }; 193 194 struct port_stats { 195 struct brb_stats brb; 196 struct eth_stats eth; 197 }; 198 199 /*----+------------------------------------------------------------------------ 200 * C | Number and | Ports in| Ports in|2 PHY-s |# of ports|# of engines 201 * h | rate of | team #1 | team #2 |are used|per path | (paths) 202 * i | physical | | | | | enabled 203 * p | ports | | | | | 204 *====+============+=========+=========+========+==========+=================== 205 * BB | 1x100G | This is special mode, where there are actually 2 HW func 206 * BB | 2x10/20Gbps| 0,1 | NA | No | 1 | 1 207 * BB | 2x40 Gbps | 0,1 | NA | Yes | 1 | 1 208 * BB | 2x50Gbps | 0,1 | NA | No | 1 | 1 209 * BB | 4x10Gbps | 0,2 | 1,3 | No | 1/2 | 1,2 (2 is optional) 210 * BB | 4x10Gbps | 0,1 | 2,3 | No | 1/2 | 1,2 (2 is optional) 211 * BB | 4x10Gbps | 0,3 | 1,2 | No | 1/2 | 1,2 (2 is optional) 212 * BB | 4x10Gbps | 0,1,2,3 | NA | No | 1 | 1 213 * AH | 2x10/20Gbps| 0,1 | NA | NA | 1 | NA 214 * AH | 4x10Gbps | 0,1 | 2,3 | NA | 2 | NA 215 * AH | 4x10Gbps | 0,2 | 1,3 | NA | 2 | NA 216 * AH | 4x10Gbps | 0,3 | 1,2 | NA | 2 | NA 217 * AH | 4x10Gbps | 0,1,2,3 | NA | NA | 1 | NA 218 *====+============+=========+=========+========+==========+=================== 219 */ 220 221 #define CMT_TEAM0 0 222 #define CMT_TEAM1 1 223 #define CMT_TEAM_MAX 2 224 225 struct couple_mode_teaming { 226 u8 port_cmt[MCP_GLOB_PORT_MAX]; 227 #define PORT_CMT_IN_TEAM (1 << 0) 228 229 #define PORT_CMT_PORT_ROLE (1 << 1) 230 #define PORT_CMT_PORT_INACTIVE (0 << 1) 231 #define PORT_CMT_PORT_ACTIVE (1 << 1) 232 233 #define PORT_CMT_TEAM_MASK (1 << 2) 234 #define PORT_CMT_TEAM0 (0 << 2) 235 #define PORT_CMT_TEAM1 (1 << 2) 236 }; 237 238 /************************************** 239 * LLDP and DCBX HSI structures 240 **************************************/ 241 #define LLDP_CHASSIS_ID_STAT_LEN 4 242 #define LLDP_PORT_ID_STAT_LEN 4 243 #define DCBX_MAX_APP_PROTOCOL 32 244 #define MAX_SYSTEM_LLDP_TLV_DATA 32 245 246 typedef enum _lldp_agent_e { 247 LLDP_NEAREST_BRIDGE = 0, 248 LLDP_NEAREST_NON_TPMR_BRIDGE, 249 LLDP_NEAREST_CUSTOMER_BRIDGE, 250 LLDP_MAX_LLDP_AGENTS 251 } lldp_agent_e; 252 253 struct lldp_config_params_s { 254 u32 config; 255 #define LLDP_CONFIG_TX_INTERVAL_MASK 0x000000ff 256 #define LLDP_CONFIG_TX_INTERVAL_SHIFT 0 257 #define LLDP_CONFIG_HOLD_MASK 0x00000f00 258 #define LLDP_CONFIG_HOLD_SHIFT 8 259 #define LLDP_CONFIG_MAX_CREDIT_MASK 0x0000f000 260 #define LLDP_CONFIG_MAX_CREDIT_SHIFT 12 261 #define LLDP_CONFIG_ENABLE_RX_MASK 0x40000000 262 #define LLDP_CONFIG_ENABLE_RX_SHIFT 30 263 #define LLDP_CONFIG_ENABLE_TX_MASK 0x80000000 264 #define LLDP_CONFIG_ENABLE_TX_SHIFT 31 265 /* Holds local Chassis ID TLV header, subtype and 9B of payload. 266 * If firtst byte is 0, then we will use default chassis ID 267 */ 268 u32 local_chassis_id[LLDP_CHASSIS_ID_STAT_LEN]; 269 /* Holds local Port ID TLV header, subtype and 9B of payload. 270 * If firtst byte is 0, then we will use default port ID 271 */ 272 u32 local_port_id[LLDP_PORT_ID_STAT_LEN]; 273 }; 274 275 struct lldp_status_params_s { 276 u32 prefix_seq_num; 277 u32 status; /* TBD */ 278 /* Holds remote Chassis ID TLV header, subtype and 9B of payload. */ 279 u32 peer_chassis_id[LLDP_CHASSIS_ID_STAT_LEN]; 280 /* Holds remote Port ID TLV header, subtype and 9B of payload. */ 281 u32 peer_port_id[LLDP_PORT_ID_STAT_LEN]; 282 u32 suffix_seq_num; 283 }; 284 285 struct dcbx_ets_feature { 286 u32 flags; 287 #define DCBX_ETS_ENABLED_MASK 0x00000001 288 #define DCBX_ETS_ENABLED_SHIFT 0 289 #define DCBX_ETS_WILLING_MASK 0x00000002 290 #define DCBX_ETS_WILLING_SHIFT 1 291 #define DCBX_ETS_ERROR_MASK 0x00000004 292 #define DCBX_ETS_ERROR_SHIFT 2 293 #define DCBX_ETS_CBS_MASK 0x00000008 294 #define DCBX_ETS_CBS_SHIFT 3 295 #define DCBX_ETS_MAX_TCS_MASK 0x000000f0 296 #define DCBX_ETS_MAX_TCS_SHIFT 4 297 #define DCBX_OOO_TC_MASK 0x00000f00 298 #define DCBX_OOO_TC_SHIFT 8 299 /* Entries in tc table are orginized that the left most is pri 0, right most is 300 * prio 7 301 */ 302 303 u32 pri_tc_tbl[1]; 304 /* Fixed TCP OOO TC usage is deprecated and used only for driver backward 305 * compatibility 306 */ 307 #define DCBX_TCP_OOO_TC (4) 308 #define DCBX_TCP_OOO_K2_4PORT_TC (3) 309 310 #define NIG_ETS_ISCSI_OOO_CLIENT_OFFSET (DCBX_TCP_OOO_TC + 1) 311 #define DCBX_CEE_STRICT_PRIORITY 0xf 312 /* Entries in tc table are orginized that the left most is pri 0, right most is 313 * prio 7 314 */ 315 316 u32 tc_bw_tbl[2]; 317 /* Entries in tc table are orginized that the left most is pri 0, right most is 318 * prio 7 319 */ 320 321 u32 tc_tsa_tbl[2]; 322 #define DCBX_ETS_TSA_STRICT 0 323 #define DCBX_ETS_TSA_CBS 1 324 #define DCBX_ETS_TSA_ETS 2 325 }; 326 327 struct dcbx_app_priority_entry { 328 u32 entry; 329 #define DCBX_APP_PRI_MAP_MASK 0x000000ff 330 #define DCBX_APP_PRI_MAP_SHIFT 0 331 #define DCBX_APP_PRI_0 0x01 332 #define DCBX_APP_PRI_1 0x02 333 #define DCBX_APP_PRI_2 0x04 334 #define DCBX_APP_PRI_3 0x08 335 #define DCBX_APP_PRI_4 0x10 336 #define DCBX_APP_PRI_5 0x20 337 #define DCBX_APP_PRI_6 0x40 338 #define DCBX_APP_PRI_7 0x80 339 #define DCBX_APP_SF_MASK 0x00000300 340 #define DCBX_APP_SF_SHIFT 8 341 #define DCBX_APP_SF_ETHTYPE 0 342 #define DCBX_APP_SF_PORT 1 343 #define DCBX_APP_SF_IEEE_MASK 0x0000f000 344 #define DCBX_APP_SF_IEEE_SHIFT 12 345 #define DCBX_APP_SF_IEEE_RESERVED 0 346 #define DCBX_APP_SF_IEEE_ETHTYPE 1 347 #define DCBX_APP_SF_IEEE_TCP_PORT 2 348 #define DCBX_APP_SF_IEEE_UDP_PORT 3 349 #define DCBX_APP_SF_IEEE_TCP_UDP_PORT 4 350 351 #define DCBX_APP_PROTOCOL_ID_MASK 0xffff0000 352 #define DCBX_APP_PROTOCOL_ID_SHIFT 16 353 }; 354 355 356 /* FW structure in BE */ 357 struct dcbx_app_priority_feature { 358 u32 flags; 359 #define DCBX_APP_ENABLED_MASK 0x00000001 360 #define DCBX_APP_ENABLED_SHIFT 0 361 #define DCBX_APP_WILLING_MASK 0x00000002 362 #define DCBX_APP_WILLING_SHIFT 1 363 #define DCBX_APP_ERROR_MASK 0x00000004 364 #define DCBX_APP_ERROR_SHIFT 2 365 /* Not in use 366 #define DCBX_APP_DEFAULT_PRI_MASK 0x00000f00 367 #define DCBX_APP_DEFAULT_PRI_SHIFT 8 368 */ 369 #define DCBX_APP_MAX_TCS_MASK 0x0000f000 370 #define DCBX_APP_MAX_TCS_SHIFT 12 371 #define DCBX_APP_NUM_ENTRIES_MASK 0x00ff0000 372 #define DCBX_APP_NUM_ENTRIES_SHIFT 16 373 struct dcbx_app_priority_entry app_pri_tbl[DCBX_MAX_APP_PROTOCOL]; 374 }; 375 376 /* FW structure in BE */ 377 struct dcbx_features { 378 /* PG feature */ 379 struct dcbx_ets_feature ets; 380 /* PFC feature */ 381 u32 pfc; 382 #define DCBX_PFC_PRI_EN_BITMAP_MASK 0x000000ff 383 #define DCBX_PFC_PRI_EN_BITMAP_SHIFT 0 384 #define DCBX_PFC_PRI_EN_BITMAP_PRI_0 0x01 385 #define DCBX_PFC_PRI_EN_BITMAP_PRI_1 0x02 386 #define DCBX_PFC_PRI_EN_BITMAP_PRI_2 0x04 387 #define DCBX_PFC_PRI_EN_BITMAP_PRI_3 0x08 388 #define DCBX_PFC_PRI_EN_BITMAP_PRI_4 0x10 389 #define DCBX_PFC_PRI_EN_BITMAP_PRI_5 0x20 390 #define DCBX_PFC_PRI_EN_BITMAP_PRI_6 0x40 391 #define DCBX_PFC_PRI_EN_BITMAP_PRI_7 0x80 392 393 #define DCBX_PFC_FLAGS_MASK 0x0000ff00 394 #define DCBX_PFC_FLAGS_SHIFT 8 395 #define DCBX_PFC_CAPS_MASK 0x00000f00 396 #define DCBX_PFC_CAPS_SHIFT 8 397 #define DCBX_PFC_MBC_MASK 0x00004000 398 #define DCBX_PFC_MBC_SHIFT 14 399 #define DCBX_PFC_WILLING_MASK 0x00008000 400 #define DCBX_PFC_WILLING_SHIFT 15 401 #define DCBX_PFC_ENABLED_MASK 0x00010000 402 #define DCBX_PFC_ENABLED_SHIFT 16 403 #define DCBX_PFC_ERROR_MASK 0x00020000 404 #define DCBX_PFC_ERROR_SHIFT 17 405 406 /* APP feature */ 407 struct dcbx_app_priority_feature app; 408 }; 409 410 struct dcbx_local_params { 411 u32 config; 412 #define DCBX_CONFIG_VERSION_MASK 0x00000007 413 #define DCBX_CONFIG_VERSION_SHIFT 0 414 #define DCBX_CONFIG_VERSION_DISABLED 0 415 #define DCBX_CONFIG_VERSION_IEEE 1 416 #define DCBX_CONFIG_VERSION_CEE 2 417 #define DCBX_CONFIG_VERSION_STATIC 4 418 419 u32 flags; 420 struct dcbx_features features; 421 }; 422 423 struct dcbx_mib { 424 u32 prefix_seq_num; 425 u32 flags; 426 /* 427 #define DCBX_CONFIG_VERSION_MASK 0x00000007 428 #define DCBX_CONFIG_VERSION_SHIFT 0 429 #define DCBX_CONFIG_VERSION_DISABLED 0 430 #define DCBX_CONFIG_VERSION_IEEE 1 431 #define DCBX_CONFIG_VERSION_CEE 2 432 #define DCBX_CONFIG_VERSION_STATIC 4 433 */ 434 struct dcbx_features features; 435 u32 suffix_seq_num; 436 }; 437 438 struct lldp_system_tlvs_buffer_s { 439 u16 valid; 440 u16 length; 441 u32 data[MAX_SYSTEM_LLDP_TLV_DATA]; 442 }; 443 444 struct dcb_dscp_map { 445 u32 flags; 446 #define DCB_DSCP_ENABLE_MASK 0x1 447 #define DCB_DSCP_ENABLE_SHIFT 0 448 #define DCB_DSCP_ENABLE 1 449 u32 dscp_pri_map[8]; 450 }; 451 452 /**************************************/ 453 /* */ 454 /* P U B L I C G L O B A L */ 455 /* */ 456 /**************************************/ 457 struct public_global { 458 u32 max_path; /* 32bit is wasty, but this will be used often */ 459 /* (Global) 32bit is wasty, but this will be used often */ 460 u32 max_ports; 461 #define MODE_1P 1 /* TBD - NEED TO THINK OF A BETTER NAME */ 462 #define MODE_2P 2 463 #define MODE_3P 3 464 #define MODE_4P 4 465 u32 debug_mb_offset; 466 u32 phymod_dbg_mb_offset; 467 struct couple_mode_teaming cmt; 468 /* Temperature in Celcius (-255C / +255C), measured every second. */ 469 s32 internal_temperature; 470 u32 mfw_ver; 471 u32 running_bundle_id; 472 s32 external_temperature; 473 u32 mdump_reason; 474 #define MDUMP_REASON_INTERNAL_ERROR (1 << 0) 475 #define MDUMP_REASON_EXTERNAL_TRIGGER (1 << 1) 476 #define MDUMP_REASON_DUMP_AGED (1 << 2) 477 u32 ext_phy_upgrade_fw; 478 #define EXT_PHY_FW_UPGRADE_STATUS_MASK (0x0000ffff) 479 #define EXT_PHY_FW_UPGRADE_STATUS_SHIFT (0) 480 #define EXT_PHY_FW_UPGRADE_STATUS_IN_PROGRESS (1) 481 #define EXT_PHY_FW_UPGRADE_STATUS_FAILED (2) 482 #define EXT_PHY_FW_UPGRADE_STATUS_SUCCESS (3) 483 #define EXT_PHY_FW_UPGRADE_TYPE_MASK (0xffff0000) 484 #define EXT_PHY_FW_UPGRADE_TYPE_SHIFT (16) 485 }; 486 487 /**************************************/ 488 /* */ 489 /* P U B L I C P A T H */ 490 /* */ 491 /**************************************/ 492 493 /**************************************************************************** 494 * Shared Memory 2 Region * 495 ****************************************************************************/ 496 /* The fw_flr_ack is actually built in the following way: */ 497 /* 8 bit: PF ack */ 498 /* 128 bit: VF ack */ 499 /* 8 bit: ios_dis_ack */ 500 /* In order to maintain endianity in the mailbox hsi, we want to keep using */ 501 /* u32. The fw must have the VF right after the PF since this is how it */ 502 /* access arrays(it expects always the VF to reside after the PF, and that */ 503 /* makes the calculation much easier for it. ) */ 504 /* In order to answer both limitations, and keep the struct small, the code */ 505 /* will abuse the structure defined here to achieve the actual partition */ 506 /* above */ 507 /****************************************************************************/ 508 struct fw_flr_mb { 509 u32 aggint; 510 u32 opgen_addr; 511 u32 accum_ack; /* 0..15:PF, 16..207:VF, 256..271:IOV_DIS */ 512 #define ACCUM_ACK_PF_BASE 0 513 #define ACCUM_ACK_PF_SHIFT 0 514 515 #define ACCUM_ACK_VF_BASE 8 516 #define ACCUM_ACK_VF_SHIFT 3 517 518 #define ACCUM_ACK_IOV_DIS_BASE 256 519 #define ACCUM_ACK_IOV_DIS_SHIFT 8 520 521 }; 522 523 struct public_path { 524 struct fw_flr_mb flr_mb; 525 /* 526 * mcp_vf_disabled is set by the MCP to indicate the driver about VFs 527 * which were disabled/flred 528 */ 529 u32 mcp_vf_disabled[VF_MAX_STATIC / 32]; /* 0x003c */ 530 531 /* Reset on mcp reset, and incremented for eveny process kill event. */ 532 u32 process_kill; 533 #define PROCESS_KILL_COUNTER_MASK 0x0000ffff 534 #define PROCESS_KILL_COUNTER_SHIFT 0 535 #define PROCESS_KILL_GLOB_AEU_BIT_MASK 0xffff0000 536 #define PROCESS_KILL_GLOB_AEU_BIT_SHIFT 16 537 #define GLOBAL_AEU_BIT(aeu_reg_id, aeu_bit) (aeu_reg_id * 32 + aeu_bit) 538 }; 539 540 /**************************************/ 541 /* */ 542 /* P U B L I C P O R T */ 543 /* */ 544 /**************************************/ 545 #define FC_NPIV_WWPN_SIZE 8 546 #define FC_NPIV_WWNN_SIZE 8 547 struct dci_npiv_settings { 548 u8 npiv_wwpn[FC_NPIV_WWPN_SIZE]; 549 u8 npiv_wwnn[FC_NPIV_WWNN_SIZE]; 550 }; 551 552 struct dci_fc_npiv_cfg { 553 /* hdr used internally by the MFW */ 554 u32 hdr; 555 u32 num_of_npiv; 556 }; 557 558 #define MAX_NUMBER_NPIV 64 559 struct dci_fc_npiv_tbl { 560 struct dci_fc_npiv_cfg fc_npiv_cfg; 561 struct dci_npiv_settings settings[MAX_NUMBER_NPIV]; 562 }; 563 564 /**************************************************************************** 565 * Driver <-> FW Mailbox * 566 ****************************************************************************/ 567 568 struct public_port { 569 u32 validity_map; /* 0x0 (4*2 = 0x8) */ 570 571 /* validity bits */ 572 #define MCP_VALIDITY_PCI_CFG 0x00100000 573 #define MCP_VALIDITY_MB 0x00200000 574 #define MCP_VALIDITY_DEV_INFO 0x00400000 575 #define MCP_VALIDITY_RESERVED 0x00000007 576 577 /* One licensing bit should be set */ 578 /* yaniv - tbd ? license */ 579 #define MCP_VALIDITY_LIC_KEY_IN_EFFECT_MASK 0x00000038 580 #define MCP_VALIDITY_LIC_MANUF_KEY_IN_EFFECT 0x00000008 581 #define MCP_VALIDITY_LIC_UPGRADE_KEY_IN_EFFECT 0x00000010 582 #define MCP_VALIDITY_LIC_NO_KEY_IN_EFFECT 0x00000020 583 584 /* Active MFW */ 585 #define MCP_VALIDITY_ACTIVE_MFW_UNKNOWN 0x00000000 586 #define MCP_VALIDITY_ACTIVE_MFW_MASK 0x000001c0 587 #define MCP_VALIDITY_ACTIVE_MFW_NCSI 0x00000040 588 #define MCP_VALIDITY_ACTIVE_MFW_NONE 0x000001c0 589 590 u32 link_status; 591 #define LINK_STATUS_LINK_UP 0x00000001 592 #define LINK_STATUS_SPEED_AND_DUPLEX_MASK 0x0000001e 593 #define LINK_STATUS_SPEED_AND_DUPLEX_1000THD (1 << 1) 594 #define LINK_STATUS_SPEED_AND_DUPLEX_1000TFD (2 << 1) 595 #define LINK_STATUS_SPEED_AND_DUPLEX_10G (3 << 1) 596 #define LINK_STATUS_SPEED_AND_DUPLEX_20G (4 << 1) 597 #define LINK_STATUS_SPEED_AND_DUPLEX_40G (5 << 1) 598 #define LINK_STATUS_SPEED_AND_DUPLEX_50G (6 << 1) 599 #define LINK_STATUS_SPEED_AND_DUPLEX_100G (7 << 1) 600 #define LINK_STATUS_SPEED_AND_DUPLEX_25G (8 << 1) 601 #define LINK_STATUS_AUTO_NEGOTIATE_ENABLED 0x00000020 602 #define LINK_STATUS_AUTO_NEGOTIATE_COMPLETE 0x00000040 603 #define LINK_STATUS_PARALLEL_DETECTION_USED 0x00000080 604 #define LINK_STATUS_PFC_ENABLED 0x00000100 605 #define LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE 0x00000200 606 #define LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE 0x00000400 607 #define LINK_STATUS_LINK_PARTNER_10G_CAPABLE 0x00000800 608 #define LINK_STATUS_LINK_PARTNER_20G_CAPABLE 0x00001000 609 #define LINK_STATUS_LINK_PARTNER_40G_CAPABLE 0x00002000 610 #define LINK_STATUS_LINK_PARTNER_50G_CAPABLE 0x00004000 611 #define LINK_STATUS_LINK_PARTNER_100G_CAPABLE 0x00008000 612 #define LINK_STATUS_LINK_PARTNER_25G_CAPABLE 0x00010000 613 #define LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK 0x000C0000 614 #define LINK_STATUS_LINK_PARTNER_NOT_PAUSE_CAPABLE (0 << 18) 615 #define LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE (1 << 18) 616 #define LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE (2 << 18) 617 #define LINK_STATUS_LINK_PARTNER_BOTH_PAUSE (3 << 18) 618 #define LINK_STATUS_SFP_TX_FAULT 0x00100000 619 #define LINK_STATUS_TX_FLOW_CONTROL_ENABLED 0x00200000 620 #define LINK_STATUS_RX_FLOW_CONTROL_ENABLED 0x00400000 621 #define LINK_STATUS_RX_SIGNAL_PRESENT 0x00800000 622 #define LINK_STATUS_MAC_LOCAL_FAULT 0x01000000 623 #define LINK_STATUS_MAC_REMOTE_FAULT 0x02000000 624 #define LINK_STATUS_UNSUPPORTED_SPD_REQ 0x04000000 625 #define LINK_STATUS_FEC_MODE_MASK 0x38000000 626 #define LINK_STATUS_FEC_MODE_NONE (0 << 27) 627 #define LINK_STATUS_FEC_MODE_FIRECODE_CL74 (1 << 27) 628 #define LINK_STATUS_FEC_MODE_RS_CL91 (2 << 27) 629 #define LINK_STATUS_EXT_PHY_LINK_UP 0x40000000 630 631 u32 link_status1; 632 u32 ext_phy_fw_version; 633 /* Points to struct eth_phy_cfg (For READ-ONLY) */ 634 u32 drv_phy_cfg_addr; 635 636 u32 port_stx; 637 638 u32 stat_nig_timer; 639 640 struct port_mf_cfg port_mf_config; 641 struct port_stats stats; 642 643 u32 media_type; 644 #define MEDIA_UNSPECIFIED 0x0 645 #define MEDIA_SFPP_10G_FIBER 0x1 /* Use MEDIA_MODULE_FIBER instead */ 646 #define MEDIA_XFP_FIBER 0x2 /* Use MEDIA_MODULE_FIBER instead */ 647 #define MEDIA_DA_TWINAX 0x3 648 #define MEDIA_BASE_T 0x4 649 #define MEDIA_SFP_1G_FIBER 0x5 /* Use MEDIA_MODULE_FIBER instead */ 650 #define MEDIA_MODULE_FIBER 0x6 651 #define MEDIA_KR 0xf0 652 #define MEDIA_NOT_PRESENT 0xff 653 654 u32 lfa_status; 655 #define LFA_LINK_FLAP_REASON_OFFSET 0 656 #define LFA_LINK_FLAP_REASON_MASK 0x000000ff 657 #define LFA_NO_REASON (0 << 0) 658 #define LFA_LINK_DOWN (1 << 0) 659 #define LFA_FORCE_INIT (1 << 1) 660 #define LFA_LOOPBACK_MISMATCH (1 << 2) 661 #define LFA_SPEED_MISMATCH (1 << 3) 662 #define LFA_FLOW_CTRL_MISMATCH (1 << 4) 663 #define LFA_ADV_SPEED_MISMATCH (1 << 5) 664 #define LINK_FLAP_AVOIDANCE_COUNT_OFFSET 8 665 #define LINK_FLAP_AVOIDANCE_COUNT_MASK 0x0000ff00 666 #define LINK_FLAP_COUNT_OFFSET 16 667 #define LINK_FLAP_COUNT_MASK 0x00ff0000 668 669 u32 link_change_count; 670 671 /* LLDP params */ 672 /* offset: 536 bytes? */ 673 struct lldp_config_params_s lldp_config_params[LLDP_MAX_LLDP_AGENTS]; 674 struct lldp_status_params_s lldp_status_params[LLDP_MAX_LLDP_AGENTS]; 675 struct lldp_system_tlvs_buffer_s system_lldp_tlvs_buf; 676 677 /* DCBX related MIB */ 678 struct dcbx_local_params local_admin_dcbx_mib; 679 struct dcbx_mib remote_dcbx_mib; 680 struct dcbx_mib operational_dcbx_mib; 681 682 /* FC_NPIV table offset & size in NVRAM value of 0 means not present */ 683 684 u32 fc_npiv_nvram_tbl_addr; 685 u32 fc_npiv_nvram_tbl_size; 686 u32 transceiver_data; 687 #define ETH_TRANSCEIVER_STATE_MASK 0x000000FF 688 #define ETH_TRANSCEIVER_STATE_SHIFT 0x00000000 689 #define ETH_TRANSCEIVER_STATE_UNPLUGGED 0x00000000 690 #define ETH_TRANSCEIVER_STATE_PRESENT 0x00000001 691 #define ETH_TRANSCEIVER_STATE_VALID 0x00000003 692 #define ETH_TRANSCEIVER_STATE_UPDATING 0x00000008 693 #define ETH_TRANSCEIVER_TYPE_MASK 0x0000FF00 694 #define ETH_TRANSCEIVER_TYPE_SHIFT 0x00000008 695 #define ETH_TRANSCEIVER_TYPE_NONE 0x00000000 696 #define ETH_TRANSCEIVER_TYPE_UNKNOWN 0x000000FF 697 /* 1G Passive copper cable */ 698 #define ETH_TRANSCEIVER_TYPE_1G_PCC 0x01 699 /* 1G Active copper cable */ 700 #define ETH_TRANSCEIVER_TYPE_1G_ACC 0x02 701 #define ETH_TRANSCEIVER_TYPE_1G_LX 0x03 702 #define ETH_TRANSCEIVER_TYPE_1G_SX 0x04 703 #define ETH_TRANSCEIVER_TYPE_10G_SR 0x05 704 #define ETH_TRANSCEIVER_TYPE_10G_LR 0x06 705 #define ETH_TRANSCEIVER_TYPE_10G_LRM 0x07 706 #define ETH_TRANSCEIVER_TYPE_10G_ER 0x08 707 /* 10G Passive copper cable */ 708 #define ETH_TRANSCEIVER_TYPE_10G_PCC 0x09 709 /* 10G Active copper cable */ 710 #define ETH_TRANSCEIVER_TYPE_10G_ACC 0x0a 711 #define ETH_TRANSCEIVER_TYPE_XLPPI 0x0b 712 #define ETH_TRANSCEIVER_TYPE_40G_LR4 0x0c 713 #define ETH_TRANSCEIVER_TYPE_40G_SR4 0x0d 714 #define ETH_TRANSCEIVER_TYPE_40G_CR4 0x0e 715 /* Active optical cable */ 716 #define ETH_TRANSCEIVER_TYPE_100G_AOC 0x0f 717 #define ETH_TRANSCEIVER_TYPE_100G_SR4 0x10 718 #define ETH_TRANSCEIVER_TYPE_100G_LR4 0x11 719 #define ETH_TRANSCEIVER_TYPE_100G_ER4 0x12 720 /* Active copper cable */ 721 #define ETH_TRANSCEIVER_TYPE_100G_ACC 0x13 722 #define ETH_TRANSCEIVER_TYPE_100G_CR4 0x14 723 #define ETH_TRANSCEIVER_TYPE_4x10G_SR 0x15 724 /* 25G Passive copper cable - short */ 725 #define ETH_TRANSCEIVER_TYPE_25G_CA_N 0x16 726 /* 25G Active copper cable - short */ 727 #define ETH_TRANSCEIVER_TYPE_25G_ACC_S 0x17 728 /* 25G Passive copper cable - medium */ 729 #define ETH_TRANSCEIVER_TYPE_25G_CA_S 0x18 730 /* 25G Active copper cable - medium */ 731 #define ETH_TRANSCEIVER_TYPE_25G_ACC_M 0x19 732 /* 25G Passive copper cable - long */ 733 #define ETH_TRANSCEIVER_TYPE_25G_CA_L 0x1a 734 /* 25G Active copper cable - long */ 735 #define ETH_TRANSCEIVER_TYPE_25G_ACC_L 0x1b 736 #define ETH_TRANSCEIVER_TYPE_25G_SR 0x1c 737 #define ETH_TRANSCEIVER_TYPE_25G_LR 0x1d 738 #define ETH_TRANSCEIVER_TYPE_25G_AOC 0x1e 739 740 #define ETH_TRANSCEIVER_TYPE_4x10G 0x1f 741 #define ETH_TRANSCEIVER_TYPE_4x25G_CR 0x20 742 #define ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_40G_SR 0x30 743 #define ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_40G_CR 0x31 744 #define ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_40G_LR 0x32 745 #define ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_SR 0x33 746 #define ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_CR 0x34 747 #define ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_LR 0x35 748 #define ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_AOC 0x36 749 u32 wol_info; 750 u32 wol_pkt_len; 751 u32 wol_pkt_details; 752 struct dcb_dscp_map dcb_dscp_map; 753 754 /* the status of EEE auto-negotiation 755 * bits 19:0 the configured tx-lpi entry timer value. Depends on bit 31. 756 * bits 23:20 the speeds advertised for EEE. 757 * bits 27:24 the speeds the Link partner advertised for EEE. 758 * The supported/adv. modes in bits 27:19 originate from the 759 * SHMEM_EEE_XXX_ADV definitions (where XXX is replaced by speed). 760 * bit 28 when 1'b1 EEE was requested. 761 * bit 29 when 1'b1 tx lpi was requested. 762 * bit 30 when 1'b1 EEE was negotiated. Tx lpi will be asserted if 30:29 763 * are 2'b11. 764 * bit 31 - When 1'b0 bits 15:0 contain 765 * NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_XXX define as value. 766 * When 1'b1 those bits contains a value times 16 microseconds. 767 */ 768 u32 eee_status; 769 #define EEE_TIMER_MASK 0x000fffff 770 #define EEE_ADV_STATUS_MASK 0x00f00000 771 #define EEE_1G_ADV (1 << 1) 772 #define EEE_10G_ADV (1 << 2) 773 #define EEE_ADV_STATUS_SHIFT 20 774 #define EEE_LP_ADV_STATUS_MASK 0x0f000000 775 #define EEE_LP_ADV_STATUS_SHIFT 24 776 #define EEE_REQUESTED_BIT 0x10000000 777 #define EEE_LPI_REQUESTED_BIT 0x20000000 778 #define EEE_ACTIVE_BIT 0x40000000 779 #define EEE_TIME_OUTPUT_BIT 0x80000000 780 781 u32 eee_remote; /* Used for EEE in LLDP */ 782 #define EEE_REMOTE_TW_TX_MASK 0x0000ffff 783 #define EEE_REMOTE_TW_TX_SHIFT 0 784 #define EEE_REMOTE_TW_RX_MASK 0xffff0000 785 #define EEE_REMOTE_TW_RX_SHIFT 16 786 }; 787 788 /**************************************/ 789 /* */ 790 /* P U B L I C F U N C */ 791 /* */ 792 /**************************************/ 793 794 struct public_func { 795 u32 iscsi_boot_signature; 796 u32 iscsi_boot_block_offset; 797 798 /* MTU size per funciton is needed for the OV feature */ 799 u32 mtu_size; 800 /* 9 entires for the C2S PCP map for each inner VLAN PCP + 1 default */ 801 802 /* For PCP values 0-3 use the map lower */ 803 /* 0xFF000000 - PCP 0, 0x00FF0000 - PCP 1, 804 * 0x0000FF00 - PCP 2, 0x000000FF PCP 3 805 */ 806 u32 c2s_pcp_map_lower; 807 /* For PCP values 4-7 use the map upper */ 808 /* 0xFF000000 - PCP 4, 0x00FF0000 - PCP 5, 809 * 0x0000FF00 - PCP 6, 0x000000FF PCP 7 810 */ 811 u32 c2s_pcp_map_upper; 812 813 /* For PCP default value get the MSB byte of the map default */ 814 u32 c2s_pcp_map_default; 815 816 u32 reserved[4]; 817 818 /* replace old mf_cfg */ 819 u32 config; 820 /* E/R/I/D */ 821 /* function 0 of each port cannot be hidden */ 822 #define FUNC_MF_CFG_FUNC_HIDE 0x00000001 823 #define FUNC_MF_CFG_PAUSE_ON_HOST_RING 0x00000002 824 #define FUNC_MF_CFG_PAUSE_ON_HOST_RING_SHIFT 0x00000001 825 826 827 #define FUNC_MF_CFG_PROTOCOL_MASK 0x000000f0 828 #define FUNC_MF_CFG_PROTOCOL_SHIFT 4 829 #define FUNC_MF_CFG_PROTOCOL_ETHERNET 0x00000000 830 #define FUNC_MF_CFG_PROTOCOL_ISCSI 0x00000010 831 #define FUNC_MF_CFG_PROTOCOL_FCOE 0x00000020 832 #define FUNC_MF_CFG_PROTOCOL_ROCE 0x00000030 833 #define FUNC_MF_CFG_PROTOCOL_MAX 0x00000030 834 835 /* MINBW, MAXBW */ 836 /* value range - 0..100, increments in 1 % */ 837 #define FUNC_MF_CFG_MIN_BW_MASK 0x0000ff00 838 #define FUNC_MF_CFG_MIN_BW_SHIFT 8 839 #define FUNC_MF_CFG_MIN_BW_DEFAULT 0x00000000 840 #define FUNC_MF_CFG_MAX_BW_MASK 0x00ff0000 841 #define FUNC_MF_CFG_MAX_BW_SHIFT 16 842 #define FUNC_MF_CFG_MAX_BW_DEFAULT 0x00640000 843 844 u32 status; 845 #define FUNC_STATUS_VLINK_DOWN 0x00000001 846 847 u32 mac_upper; /* MAC */ 848 #define FUNC_MF_CFG_UPPERMAC_MASK 0x0000ffff 849 #define FUNC_MF_CFG_UPPERMAC_SHIFT 0 850 #define FUNC_MF_CFG_UPPERMAC_DEFAULT FUNC_MF_CFG_UPPERMAC_MASK 851 u32 mac_lower; 852 #define FUNC_MF_CFG_LOWERMAC_DEFAULT 0xffffffff 853 854 u32 fcoe_wwn_port_name_upper; 855 u32 fcoe_wwn_port_name_lower; 856 857 u32 fcoe_wwn_node_name_upper; 858 u32 fcoe_wwn_node_name_lower; 859 860 u32 ovlan_stag; /* tags */ 861 #define FUNC_MF_CFG_OV_STAG_MASK 0x0000ffff 862 #define FUNC_MF_CFG_OV_STAG_SHIFT 0 863 #define FUNC_MF_CFG_OV_STAG_DEFAULT FUNC_MF_CFG_OV_STAG_MASK 864 865 u32 pf_allocation; /* vf per pf */ 866 867 u32 preserve_data; /* Will be used bt CCM */ 868 869 u32 driver_last_activity_ts; 870 871 /* 872 * drv_ack_vf_disabled is set by the PF driver to ack handled disabled 873 * VFs 874 */ 875 u32 drv_ack_vf_disabled[VF_MAX_STATIC / 32]; /* 0x0044 */ 876 877 u32 drv_id; 878 #define DRV_ID_PDA_COMP_VER_MASK 0x0000ffff 879 #define DRV_ID_PDA_COMP_VER_SHIFT 0 880 881 #define LOAD_REQ_HSI_VERSION 2 882 #define DRV_ID_MCP_HSI_VER_MASK 0x00ff0000 883 #define DRV_ID_MCP_HSI_VER_SHIFT 16 884 #define DRV_ID_MCP_HSI_VER_CURRENT (LOAD_REQ_HSI_VERSION << \ 885 DRV_ID_MCP_HSI_VER_SHIFT) 886 887 #define DRV_ID_DRV_TYPE_MASK 0x7f000000 888 #define DRV_ID_DRV_TYPE_SHIFT 24 889 #define DRV_ID_DRV_TYPE_UNKNOWN (0 << DRV_ID_DRV_TYPE_SHIFT) 890 #define DRV_ID_DRV_TYPE_LINUX (1 << DRV_ID_DRV_TYPE_SHIFT) 891 #define DRV_ID_DRV_TYPE_WINDOWS (2 << DRV_ID_DRV_TYPE_SHIFT) 892 #define DRV_ID_DRV_TYPE_DIAG (3 << DRV_ID_DRV_TYPE_SHIFT) 893 #define DRV_ID_DRV_TYPE_PREBOOT (4 << DRV_ID_DRV_TYPE_SHIFT) 894 #define DRV_ID_DRV_TYPE_SOLARIS (5 << DRV_ID_DRV_TYPE_SHIFT) 895 #define DRV_ID_DRV_TYPE_VMWARE (6 << DRV_ID_DRV_TYPE_SHIFT) 896 #define DRV_ID_DRV_TYPE_FREEBSD (7 << DRV_ID_DRV_TYPE_SHIFT) 897 #define DRV_ID_DRV_TYPE_AIX (8 << DRV_ID_DRV_TYPE_SHIFT) 898 899 #define DRV_ID_DRV_INIT_HW_MASK 0x80000000 900 #define DRV_ID_DRV_INIT_HW_SHIFT 31 901 #define DRV_ID_DRV_INIT_HW_FLAG (1 << DRV_ID_DRV_INIT_HW_SHIFT) 902 }; 903 904 /**************************************/ 905 /* */ 906 /* P U B L I C M B */ 907 /* */ 908 /**************************************/ 909 /* This is the only section that the driver can write to, and each */ 910 /* Basically each driver request to set feature parameters, 911 * will be done using a different command, which will be linked 912 * to a specific data structure from the union below. 913 * For huge strucuture, the common blank structure should be used. 914 */ 915 916 struct mcp_mac { 917 u32 mac_upper; /* Upper 16 bits are always zeroes */ 918 u32 mac_lower; 919 }; 920 921 struct mcp_val64 { 922 u32 lo; 923 u32 hi; 924 }; 925 926 struct mcp_file_att { 927 u32 nvm_start_addr; 928 u32 len; 929 }; 930 931 struct bist_nvm_image_att { 932 u32 return_code; 933 u32 image_type; /* Image type */ 934 u32 nvm_start_addr; /* NVM address of the image */ 935 u32 len; /* Include CRC */ 936 }; 937 938 #define MCP_DRV_VER_STR_SIZE 16 939 #define MCP_DRV_VER_STR_SIZE_DWORD (MCP_DRV_VER_STR_SIZE / sizeof(u32)) 940 #define MCP_DRV_NVM_BUF_LEN 32 941 struct drv_version_stc { 942 u32 version; 943 u8 name[MCP_DRV_VER_STR_SIZE - 4]; 944 }; 945 946 /* statistics for ncsi */ 947 struct lan_stats_stc { 948 u64 ucast_rx_pkts; 949 u64 ucast_tx_pkts; 950 u32 fcs_err; 951 u32 rserved; 952 }; 953 954 struct fcoe_stats_stc { 955 u64 rx_pkts; 956 u64 tx_pkts; 957 u32 fcs_err; 958 u32 login_failure; 959 }; 960 961 struct iscsi_stats_stc { 962 u64 rx_pdus; 963 u64 tx_pdus; 964 u64 rx_bytes; 965 u64 tx_bytes; 966 }; 967 968 struct rdma_stats_stc { 969 u64 rx_pkts; 970 u64 tx_pkts; 971 u64 rx_bytes; 972 u64 tx_bytes; 973 }; 974 975 struct ocbb_data_stc { 976 u32 ocbb_host_addr; 977 u32 ocsd_host_addr; 978 u32 ocsd_req_update_interval; 979 }; 980 981 #define MAX_NUM_OF_SENSORS 7 982 #define MFW_SENSOR_LOCATION_INTERNAL 1 983 #define MFW_SENSOR_LOCATION_EXTERNAL 2 984 #define MFW_SENSOR_LOCATION_SFP 3 985 986 #define SENSOR_LOCATION_SHIFT 0 987 #define SENSOR_LOCATION_MASK 0x000000ff 988 #define THRESHOLD_HIGH_SHIFT 8 989 #define THRESHOLD_HIGH_MASK 0x0000ff00 990 #define CRITICAL_TEMPERATURE_SHIFT 16 991 #define CRITICAL_TEMPERATURE_MASK 0x00ff0000 992 #define CURRENT_TEMP_SHIFT 24 993 #define CURRENT_TEMP_MASK 0xff000000 994 struct temperature_status_stc { 995 u32 num_of_sensors; 996 u32 sensor[MAX_NUM_OF_SENSORS]; 997 }; 998 999 /* crash dump configuration header */ 1000 struct mdump_config_stc { 1001 u32 version; 1002 u32 config; 1003 u32 epoc; 1004 u32 num_of_logs; 1005 u32 valid_logs; 1006 }; 1007 1008 enum resource_id_enum { 1009 RESOURCE_NUM_SB_E = 0, 1010 RESOURCE_NUM_L2_QUEUE_E = 1, 1011 RESOURCE_NUM_VPORT_E = 2, 1012 RESOURCE_NUM_VMQ_E = 3, 1013 /* Not a real resource!! it's a factor used to calculate others */ 1014 RESOURCE_FACTOR_NUM_RSS_PF_E = 4, 1015 /* Not a real resource!! it's a factor used to calculate others */ 1016 RESOURCE_FACTOR_RSS_PER_VF_E = 5, 1017 RESOURCE_NUM_RL_E = 6, 1018 RESOURCE_NUM_PQ_E = 7, 1019 RESOURCE_NUM_VF_E = 8, 1020 RESOURCE_VFC_FILTER_E = 9, 1021 RESOURCE_ILT_E = 10, 1022 RESOURCE_CQS_E = 11, 1023 RESOURCE_GFT_PROFILES_E = 12, 1024 RESOURCE_NUM_TC_E = 13, 1025 RESOURCE_NUM_RSS_ENGINES_E = 14, 1026 RESOURCE_LL2_QUEUE_E = 15, 1027 RESOURCE_RDMA_STATS_QUEUE_E = 16, 1028 RESOURCE_BDQ_E = 17, 1029 RESOURCE_MAX_NUM, 1030 RESOURCE_NUM_INVALID = 0xFFFFFFFF 1031 }; 1032 1033 /* Resource ID is to be filled by the driver in the MB request 1034 * Size, offset & flags to be filled by the MFW in the MB response 1035 */ 1036 struct resource_info { 1037 enum resource_id_enum res_id; 1038 u32 size; /* number of allocated resources */ 1039 u32 offset; /* Offset of the 1st resource */ 1040 u32 vf_size; 1041 u32 vf_offset; 1042 u32 flags; 1043 #define RESOURCE_ELEMENT_STRICT (1 << 0) 1044 }; 1045 1046 #define DRV_ROLE_NONE 0 1047 #define DRV_ROLE_PREBOOT 1 1048 #define DRV_ROLE_OS 2 1049 #define DRV_ROLE_KDUMP 3 1050 1051 struct load_req_stc { 1052 u32 drv_ver_0; 1053 u32 drv_ver_1; 1054 u32 fw_ver; 1055 u32 misc0; 1056 #define LOAD_REQ_ROLE_MASK 0x000000FF 1057 #define LOAD_REQ_ROLE_SHIFT 0 1058 #define LOAD_REQ_LOCK_TO_MASK 0x0000FF00 1059 #define LOAD_REQ_LOCK_TO_SHIFT 0 /* @DPDK */ 1060 #define LOAD_REQ_LOCK_TO_DEFAULT 0 1061 #define LOAD_REQ_LOCK_TO_NONE 255 1062 #define LOAD_REQ_FORCE_MASK 0x000F0000 1063 #define LOAD_REQ_FORCE_SHIFT 0 /* @DPDK */ 1064 #define LOAD_REQ_FORCE_NONE 0 1065 #define LOAD_REQ_FORCE_PF 1 1066 #define LOAD_REQ_FORCE_ALL 2 1067 #define LOAD_REQ_FLAGS0_MASK 0x00F00000 1068 #define LOAD_REQ_FLAGS0_SHIFT 0 /* @DPDK */ 1069 #define LOAD_REQ_FLAGS0_AVOID_RESET (0x1 << 0) 1070 }; 1071 1072 struct load_rsp_stc { 1073 u32 drv_ver_0; 1074 u32 drv_ver_1; 1075 u32 fw_ver; 1076 u32 misc0; 1077 #define LOAD_RSP_ROLE_MASK 0x000000FF 1078 #define LOAD_RSP_ROLE_SHIFT 0 1079 #define LOAD_RSP_HSI_MASK 0x0000FF00 1080 #define LOAD_RSP_HSI_SHIFT 8 1081 #define LOAD_RSP_FLAGS0_MASK 0x000F0000 1082 #define LOAD_RSP_FLAGS0_SHIFT 16 1083 #define LOAD_RSP_FLAGS0_DRV_EXISTS (0x1 << 0) 1084 }; 1085 1086 union drv_union_data { 1087 struct mcp_mac wol_mac; /* UNLOAD_DONE */ 1088 1089 /* This configuration should be set by the driver for the LINK_SET command. */ 1090 1091 struct eth_phy_cfg drv_phy_cfg; 1092 1093 struct mcp_val64 val64; /* For PHY / AVS commands */ 1094 1095 u8 raw_data[MCP_DRV_NVM_BUF_LEN]; 1096 1097 struct mcp_file_att file_att; 1098 1099 u32 ack_vf_disabled[VF_MAX_STATIC / 32]; 1100 1101 struct drv_version_stc drv_version; 1102 1103 struct lan_stats_stc lan_stats; 1104 struct fcoe_stats_stc fcoe_stats; 1105 struct iscsi_stats_stc iscsi_stats; 1106 struct rdma_stats_stc rdma_stats; 1107 struct ocbb_data_stc ocbb_info; 1108 struct temperature_status_stc temp_info; 1109 struct resource_info resource; 1110 struct bist_nvm_image_att nvm_image_att; 1111 struct mdump_config_stc mdump_config; 1112 u32 dword; 1113 1114 struct load_req_stc load_req; 1115 struct load_rsp_stc load_rsp; 1116 /* ... */ 1117 }; 1118 1119 struct public_drv_mb { 1120 u32 drv_mb_header; 1121 #define DRV_MSG_CODE_MASK 0xffff0000 1122 #define DRV_MSG_CODE_LOAD_REQ 0x10000000 1123 #define DRV_MSG_CODE_LOAD_DONE 0x11000000 1124 #define DRV_MSG_CODE_INIT_HW 0x12000000 1125 #define DRV_MSG_CODE_CANCEL_LOAD_REQ 0x13000000 1126 #define DRV_MSG_CODE_UNLOAD_REQ 0x20000000 1127 #define DRV_MSG_CODE_UNLOAD_DONE 0x21000000 1128 #define DRV_MSG_CODE_INIT_PHY 0x22000000 1129 /* Params - FORCE - Reinitialize the link regardless of LFA */ 1130 /* - DONT_CARE - Don't flap the link if up */ 1131 #define DRV_MSG_CODE_LINK_RESET 0x23000000 1132 1133 /* Vitaly: LLDP commands */ 1134 #define DRV_MSG_CODE_SET_LLDP 0x24000000 1135 #define DRV_MSG_CODE_SET_DCBX 0x25000000 1136 /* OneView feature driver HSI*/ 1137 #define DRV_MSG_CODE_OV_UPDATE_CURR_CFG 0x26000000 1138 #define DRV_MSG_CODE_OV_UPDATE_BUS_NUM 0x27000000 1139 #define DRV_MSG_CODE_OV_UPDATE_BOOT_PROGRESS 0x28000000 1140 #define DRV_MSG_CODE_OV_UPDATE_STORM_FW_VER 0x29000000 1141 #define DRV_MSG_CODE_NIG_DRAIN 0x30000000 1142 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE 0x31000000 1143 #define DRV_MSG_CODE_BW_UPDATE_ACK 0x32000000 1144 #define DRV_MSG_CODE_OV_UPDATE_MTU 0x33000000 1145 /* DRV_MB Param: driver version supp, FW_MB param: MFW version supp, 1146 * data: struct resource_info 1147 */ 1148 #define DRV_MSG_GET_RESOURCE_ALLOC_MSG 0x34000000 1149 #define DRV_MSG_SET_RESOURCE_VALUE_MSG 0x35000000 1150 1151 /*deprecated don't use*/ 1152 #define DRV_MSG_CODE_INITIATE_FLR_DEPRECATED 0x02000000 1153 #define DRV_MSG_CODE_INITIATE_PF_FLR 0x02010000 1154 #define DRV_MSG_CODE_VF_DISABLED_DONE 0xc0000000 1155 #define DRV_MSG_CODE_CFG_VF_MSIX 0xc0010000 1156 /* Param is either DRV_MB_PARAM_NVM_PUT_FILE_BEGIN_MFW/IMAGE */ 1157 #define DRV_MSG_CODE_NVM_PUT_FILE_BEGIN 0x00010000 1158 /* Param should be set to the transaction size (up to 64 bytes) */ 1159 #define DRV_MSG_CODE_NVM_PUT_FILE_DATA 0x00020000 1160 /* MFW will place the file offset and len in file_att struct */ 1161 #define DRV_MSG_CODE_NVM_GET_FILE_ATT 0x00030000 1162 /* Read 32bytes of nvram data. Param is [0:23] – Offset [24:31] – 1163 * Len in Bytes 1164 */ 1165 #define DRV_MSG_CODE_NVM_READ_NVRAM 0x00050000 1166 /* Writes up to 32Bytes to nvram. Param is [0:23] – Offset [24:31] – 1167 * Len in Bytes. In case this address is in the range of secured file in 1168 * secured mode, the operation will fail 1169 */ 1170 #define DRV_MSG_CODE_NVM_WRITE_NVRAM 0x00060000 1171 /* Delete a file from nvram. Param is image_type. */ 1172 #define DRV_MSG_CODE_NVM_DEL_FILE 0x00080000 1173 /* Reset MCP when no NVM operation is going on, and no drivers are loaded. 1174 * In case operation succeed, MCP will not ack back. 1175 */ 1176 #define DRV_MSG_CODE_MCP_RESET 0x00090000 1177 /* Temporary command to set secure mode, where the param is 0 (None secure) / 1178 * 1 (Secure) / 2 (Full-Secure) 1179 */ 1180 #define DRV_MSG_CODE_SET_SECURE_MODE 0x000a0000 1181 /* Param: [0:15] - Address, [16:18] - lane# (0/1/2/3 - for single lane, 1182 * 4/5 - for dual lanes, 6 - for all lanes, [28] - PMD reg, [29] - select port, 1183 * [30:31] - port 1184 */ 1185 #define DRV_MSG_CODE_PHY_RAW_READ 0x000b0000 1186 /* Param: [0:15] - Address, [16:18] - lane# (0/1/2/3 - for single lane, 1187 * 4/5 - for dual lanes, 6 - for all lanes, [28] - PMD reg, [29] - select port, 1188 * [30:31] - port 1189 */ 1190 #define DRV_MSG_CODE_PHY_RAW_WRITE 0x000c0000 1191 /* Param: [0:15] - Address, [30:31] - port */ 1192 #define DRV_MSG_CODE_PHY_CORE_READ 0x000d0000 1193 /* Param: [0:15] - Address, [30:31] - port */ 1194 #define DRV_MSG_CODE_PHY_CORE_WRITE 0x000e0000 1195 /* Param: [0:3] - version, [4:15] - name (null terminated) */ 1196 #define DRV_MSG_CODE_SET_VERSION 0x000f0000 1197 /* Halts the MCP. To resume MCP, user will need to use 1198 * MCP_REG_CPU_STATE/MCP_REG_CPU_MODE registers. 1199 */ 1200 #define DRV_MSG_CODE_MCP_HALT 0x00100000 1201 /* Set virtual mac address, params [31:6] - reserved, [5:4] - type, 1202 * [3:0] - func, drv_data[7:0] - MAC/WWNN/WWPN 1203 */ 1204 #define DRV_MSG_CODE_SET_VMAC 0x00110000 1205 /* Set virtual mac address, params [31:6] - reserved, [5:4] - type, 1206 * [3:0] - func, drv_data[7:0] - MAC/WWNN/WWPN 1207 */ 1208 #define DRV_MSG_CODE_GET_VMAC 0x00120000 1209 #define DRV_MSG_CODE_VMAC_TYPE_SHIFT 4 1210 #define DRV_MSG_CODE_VMAC_TYPE_MASK 0x30 1211 #define DRV_MSG_CODE_VMAC_TYPE_MAC 1 1212 #define DRV_MSG_CODE_VMAC_TYPE_WWNN 2 1213 #define DRV_MSG_CODE_VMAC_TYPE_WWPN 3 1214 /* Get statistics from pf, params [31:4] - reserved, [3:0] - stats type */ 1215 #define DRV_MSG_CODE_GET_STATS 0x00130000 1216 #define DRV_MSG_CODE_STATS_TYPE_LAN 1 1217 #define DRV_MSG_CODE_STATS_TYPE_FCOE 2 1218 #define DRV_MSG_CODE_STATS_TYPE_ISCSI 3 1219 #define DRV_MSG_CODE_STATS_TYPE_RDMA 4 1220 /* Host shall provide buffer and size for MFW */ 1221 #define DRV_MSG_CODE_PMD_DIAG_DUMP 0x00140000 1222 /* Host shall provide buffer and size for MFW */ 1223 #define DRV_MSG_CODE_PMD_DIAG_EYE 0x00150000 1224 /* Param: [0:1] - Port, [2:7] - read size, [8:15] - I2C address, 1225 * [16:31] - offset 1226 */ 1227 #define DRV_MSG_CODE_TRANSCEIVER_READ 0x00160000 1228 /* Param: [0:1] - Port, [2:7] - write size, [8:15] - I2C address, 1229 * [16:31] - offset 1230 */ 1231 #define DRV_MSG_CODE_TRANSCEIVER_WRITE 0x00170000 1232 /* indicate OCBB related information */ 1233 #define DRV_MSG_CODE_OCBB_DATA 0x00180000 1234 /* Set function BW, params[15:8] - min, params[7:0] - max */ 1235 #define DRV_MSG_CODE_SET_BW 0x00190000 1236 #define BW_MAX_MASK 0x000000ff 1237 #define BW_MAX_SHIFT 0 1238 #define BW_MIN_MASK 0x0000ff00 1239 #define BW_MIN_SHIFT 8 1240 1241 /* When param is set to 1, all parities will be masked(disabled). When params 1242 * are set to 0, parities will be unmasked again. 1243 */ 1244 #define DRV_MSG_CODE_MASK_PARITIES 0x001a0000 1245 /* param[0] - Simulate fan failure, param[1] - simulate over temp. */ 1246 #define DRV_MSG_CODE_INDUCE_FAILURE 0x001b0000 1247 #define DRV_MSG_FAN_FAILURE_TYPE (1 << 0) 1248 #define DRV_MSG_TEMPERATURE_FAILURE_TYPE (1 << 1) 1249 /* Param: [0:15] - gpio number */ 1250 #define DRV_MSG_CODE_GPIO_READ 0x001c0000 1251 /* Param: [0:15] - gpio number, [16:31] - gpio value */ 1252 #define DRV_MSG_CODE_GPIO_WRITE 0x001d0000 1253 /* Param: [0:7] - test enum, [8:15] - image index, [16:31] - reserved */ 1254 #define DRV_MSG_CODE_BIST_TEST 0x001e0000 1255 #define DRV_MSG_CODE_GET_TEMPERATURE 0x001f0000 1256 1257 /* Set LED mode params :0 operational, 1 LED turn ON, 2 LED turn OFF */ 1258 #define DRV_MSG_CODE_SET_LED_MODE 0x00200000 1259 /* drv_data[7:0] - EPOC in seconds, drv_data[15:8] - 1260 * driver version (MAJ MIN BUILD SUB) 1261 */ 1262 #define DRV_MSG_CODE_TIMESTAMP 0x00210000 1263 /* This is an empty mailbox just return OK*/ 1264 #define DRV_MSG_CODE_EMPTY_MB 0x00220000 1265 1266 /* Param[0:4] - resource number (0-31), Param[5:7] - opcode, 1267 * param[15:8] - age 1268 */ 1269 #define DRV_MSG_CODE_RESOURCE_CMD 0x00230000 1270 1271 #define RESOURCE_CMD_REQ_RESC_MASK 0x0000001F 1272 #define RESOURCE_CMD_REQ_RESC_SHIFT 0 1273 #define RESOURCE_CMD_REQ_OPCODE_MASK 0x000000E0 1274 #define RESOURCE_CMD_REQ_OPCODE_SHIFT 5 1275 /* request resource ownership with default aging */ 1276 #define RESOURCE_OPCODE_REQ 1 1277 /* request resource ownership without aging */ 1278 #define RESOURCE_OPCODE_REQ_WO_AGING 2 1279 /* request resource ownership with specific aging timer (in seconds) */ 1280 #define RESOURCE_OPCODE_REQ_W_AGING 3 1281 #define RESOURCE_OPCODE_RELEASE 4 /* release resource */ 1282 /* force resource release */ 1283 #define RESOURCE_OPCODE_FORCE_RELEASE 5 1284 #define RESOURCE_CMD_REQ_AGE_MASK 0x0000FF00 1285 #define RESOURCE_CMD_REQ_AGE_SHIFT 8 1286 1287 #define RESOURCE_CMD_RSP_OWNER_MASK 0x000000FF 1288 #define RESOURCE_CMD_RSP_OWNER_SHIFT 0 1289 #define RESOURCE_CMD_RSP_OPCODE_MASK 0x00000700 1290 #define RESOURCE_CMD_RSP_OPCODE_SHIFT 8 1291 /* resource is free and granted to requester */ 1292 #define RESOURCE_OPCODE_GNT 1 1293 /* resource is busy, param[7:0] indicates owner as follow 0-15 = PF0-15, 1294 * 16 = MFW, 17 = diag over serial 1295 */ 1296 #define RESOURCE_OPCODE_BUSY 2 1297 /* indicate release request was acknowledged */ 1298 #define RESOURCE_OPCODE_RELEASED 3 1299 /* indicate release request was previously received by other owner */ 1300 #define RESOURCE_OPCODE_RELEASED_PREVIOUS 4 1301 /* indicate wrong owner during release */ 1302 #define RESOURCE_OPCODE_WRONG_OWNER 5 1303 #define RESOURCE_OPCODE_UNKNOWN_CMD 255 1304 1305 /* dedicate resource 0 for dump */ 1306 #define RESOURCE_DUMP 0 1307 1308 #define DRV_MSG_CODE_GET_MBA_VERSION 0x00240000 /* Get MBA version */ 1309 /* Send crash dump commands with param[3:0] - opcode */ 1310 #define DRV_MSG_CODE_MDUMP_CMD 0x00250000 1311 #define MDUMP_DRV_PARAM_OPCODE_MASK 0x0000000f 1312 /* acknowledge reception of error indication */ 1313 #define DRV_MSG_CODE_MDUMP_ACK 0x01 1314 /* set epoc and personality as follow: drv_data[3:0] - epoch, 1315 * drv_data[7:4] - personality 1316 */ 1317 #define DRV_MSG_CODE_MDUMP_SET_VALUES 0x02 1318 /* trigger crash dump procedure */ 1319 #define DRV_MSG_CODE_MDUMP_TRIGGER 0x03 1320 /* Request valid logs and config words */ 1321 #define DRV_MSG_CODE_MDUMP_GET_CONFIG 0x04 1322 /* Set triggers mask. drv_mb_param should indicate (bitwise) which 1323 * trigger enabled 1324 */ 1325 #define DRV_MSG_CODE_MDUMP_SET_ENABLE 0x05 1326 /* Clear all logs */ 1327 #define DRV_MSG_CODE_MDUMP_CLEAR_LOGS 0x06 1328 #define DRV_MSG_CODE_MEM_ECC_EVENTS 0x00260000 /* Param: None */ 1329 /* Param: [0:15] - gpio number */ 1330 #define DRV_MSG_CODE_GPIO_INFO 0x00270000 1331 /* Value will be placed in union */ 1332 #define DRV_MSG_CODE_EXT_PHY_READ 0x00280000 1333 /* Value should be placed in union */ 1334 #define DRV_MSG_CODE_EXT_PHY_WRITE 0x00290000 1335 #define DRV_MB_PARAM_ADDR_SHIFT 0 1336 #define DRV_MB_PARAM_ADDR_MASK 0x0000FFFF 1337 #define DRV_MB_PARAM_DEVAD_SHIFT 16 1338 #define DRV_MB_PARAM_DEVAD_MASK 0x001F0000 1339 #define DRV_MB_PARAM_PORT_SHIFT 21 1340 #define DRV_MB_PARAM_PORT_MASK 0x00600000 1341 #define DRV_MSG_CODE_EXT_PHY_FW_UPGRADE 0x002a0000 1342 1343 #define DRV_MSG_SEQ_NUMBER_MASK 0x0000ffff 1344 1345 u32 drv_mb_param; 1346 /* UNLOAD_REQ params */ 1347 #define DRV_MB_PARAM_UNLOAD_WOL_UNKNOWN 0x00000000 1348 #define DRV_MB_PARAM_UNLOAD_WOL_MCP 0x00000001 1349 #define DRV_MB_PARAM_UNLOAD_WOL_DISABLED 0x00000002 1350 #define DRV_MB_PARAM_UNLOAD_WOL_ENABLED 0x00000003 1351 1352 /* UNLOAD_DONE_params */ 1353 #define DRV_MB_PARAM_UNLOAD_NON_D3_POWER 0x00000001 1354 1355 /* INIT_PHY params */ 1356 #define DRV_MB_PARAM_INIT_PHY_FORCE 0x00000001 1357 #define DRV_MB_PARAM_INIT_PHY_DONT_CARE 0x00000002 1358 1359 /* LLDP / DCBX params*/ 1360 #define DRV_MB_PARAM_LLDP_SEND_MASK 0x00000001 1361 #define DRV_MB_PARAM_LLDP_SEND_SHIFT 0 1362 #define DRV_MB_PARAM_LLDP_AGENT_MASK 0x00000006 1363 #define DRV_MB_PARAM_LLDP_AGENT_SHIFT 1 1364 #define DRV_MB_PARAM_DCBX_NOTIFY_MASK 0x00000008 1365 #define DRV_MB_PARAM_DCBX_NOTIFY_SHIFT 3 1366 1367 #define DRV_MB_PARAM_NIG_DRAIN_PERIOD_MS_MASK 0x000000FF 1368 #define DRV_MB_PARAM_NIG_DRAIN_PERIOD_MS_SHIFT 0 1369 1370 #define DRV_MB_PARAM_NVM_PUT_FILE_BEGIN_MFW 0x1 1371 #define DRV_MB_PARAM_NVM_PUT_FILE_BEGIN_IMAGE 0x2 1372 1373 #define DRV_MB_PARAM_NVM_OFFSET_SHIFT 0 1374 #define DRV_MB_PARAM_NVM_OFFSET_MASK 0x00FFFFFF 1375 #define DRV_MB_PARAM_NVM_LEN_SHIFT 24 1376 #define DRV_MB_PARAM_NVM_LEN_MASK 0xFF000000 1377 1378 #define DRV_MB_PARAM_PHY_ADDR_SHIFT 0 1379 #define DRV_MB_PARAM_PHY_ADDR_MASK 0x1FF0FFFF 1380 #define DRV_MB_PARAM_PHY_LANE_SHIFT 16 1381 #define DRV_MB_PARAM_PHY_LANE_MASK 0x000F0000 1382 #define DRV_MB_PARAM_PHY_SELECT_PORT_SHIFT 29 1383 #define DRV_MB_PARAM_PHY_SELECT_PORT_MASK 0x20000000 1384 #define DRV_MB_PARAM_PHY_PORT_SHIFT 30 1385 #define DRV_MB_PARAM_PHY_PORT_MASK 0xc0000000 1386 1387 #define DRV_MB_PARAM_PHYMOD_LANE_SHIFT 0 1388 #define DRV_MB_PARAM_PHYMOD_LANE_MASK 0x000000FF 1389 #define DRV_MB_PARAM_PHYMOD_SIZE_SHIFT 8 1390 #define DRV_MB_PARAM_PHYMOD_SIZE_MASK 0x000FFF00 1391 /* configure vf MSIX params*/ 1392 #define DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_SHIFT 0 1393 #define DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_MASK 0x000000FF 1394 #define DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_SHIFT 8 1395 #define DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_MASK 0x0000FF00 1396 1397 /* OneView configuration parametres */ 1398 #define DRV_MB_PARAM_OV_CURR_CFG_SHIFT 0 1399 #define DRV_MB_PARAM_OV_CURR_CFG_MASK 0x0000000F 1400 #define DRV_MB_PARAM_OV_CURR_CFG_NONE 0 1401 #define DRV_MB_PARAM_OV_CURR_CFG_OS 1 1402 #define DRV_MB_PARAM_OV_CURR_CFG_VENDOR_SPEC 2 1403 #define DRV_MB_PARAM_OV_CURR_CFG_OTHER 3 1404 #define DRV_MB_PARAM_OV_CURR_CFG_VC_CLP 4 1405 #define DRV_MB_PARAM_OV_CURR_CFG_CNU 5 1406 #define DRV_MB_PARAM_OV_CURR_CFG_DCI 6 1407 #define DRV_MB_PARAM_OV_CURR_CFG_HII 7 1408 1409 #define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_SHIFT 0 1410 #define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_MASK 0x000000FF 1411 #define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_NONE (1 << 0) 1412 #define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_ISCSI_IP_ACQUIRED (1 << 1) 1413 #define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_FCOE_FABRIC_LOGIN_SUCCESS (1 << 1) 1414 #define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_TRARGET_FOUND (1 << 2) 1415 #define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_ISCSI_CHAP_SUCCESS (1 << 3) 1416 #define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_FCOE_LUN_FOUND (1 << 3) 1417 #define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_LOGGED_INTO_TGT (1 << 4) 1418 #define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_IMG_DOWNLOADED (1 << 5) 1419 #define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_OS_HANDOFF (1 << 6) 1420 #define DRV_MB_PARAM_OV_UPDATE_BOOT_COMPLETED 0 1421 1422 #define DRV_MB_PARAM_OV_PCI_BUS_NUM_SHIFT 0 1423 #define DRV_MB_PARAM_OV_PCI_BUS_NUM_MASK 0x000000FF 1424 1425 #define DRV_MB_PARAM_OV_STORM_FW_VER_SHIFT 0 1426 #define DRV_MB_PARAM_OV_STORM_FW_VER_MASK 0xFFFFFFFF 1427 #define DRV_MB_PARAM_OV_STORM_FW_VER_MAJOR_MASK 0xFF000000 1428 #define DRV_MB_PARAM_OV_STORM_FW_VER_MINOR_MASK 0x00FF0000 1429 #define DRV_MB_PARAM_OV_STORM_FW_VER_BUILD_MASK 0x0000FF00 1430 #define DRV_MB_PARAM_OV_STORM_FW_VER_DROP_MASK 0x000000FF 1431 1432 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_SHIFT 0 1433 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_MASK 0xF 1434 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_UNKNOWN 0x1 1435 /* Not Installed*/ 1436 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_NOT_LOADED 0x2 1437 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_LOADING 0x3 1438 /* installed but disabled by user/admin/OS */ 1439 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_DISABLED 0x4 1440 /* installed and active */ 1441 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_ACTIVE 0x5 1442 1443 #define DRV_MB_PARAM_OV_MTU_SIZE_SHIFT 0 1444 #define DRV_MB_PARAM_OV_MTU_SIZE_MASK 0xFFFFFFFF 1445 1446 #define DRV_MB_PARAM_SET_LED_MODE_OPER 0x0 1447 #define DRV_MB_PARAM_SET_LED_MODE_ON 0x1 1448 #define DRV_MB_PARAM_SET_LED_MODE_OFF 0x2 1449 1450 #define DRV_MB_PARAM_TRANSCEIVER_PORT_SHIFT 0 1451 #define DRV_MB_PARAM_TRANSCEIVER_PORT_MASK 0x00000003 1452 #define DRV_MB_PARAM_TRANSCEIVER_SIZE_SHIFT 2 1453 #define DRV_MB_PARAM_TRANSCEIVER_SIZE_MASK 0x000000FC 1454 #define DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_SHIFT 8 1455 #define DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_MASK 0x0000FF00 1456 #define DRV_MB_PARAM_TRANSCEIVER_OFFSET_SHIFT 16 1457 #define DRV_MB_PARAM_TRANSCEIVER_OFFSET_MASK 0xFFFF0000 1458 1459 #define DRV_MB_PARAM_GPIO_NUMBER_SHIFT 0 1460 #define DRV_MB_PARAM_GPIO_NUMBER_MASK 0x0000FFFF 1461 #define DRV_MB_PARAM_GPIO_VALUE_SHIFT 16 1462 #define DRV_MB_PARAM_GPIO_VALUE_MASK 0xFFFF0000 1463 #define DRV_MB_PARAM_GPIO_DIRECTION_SHIFT 16 1464 #define DRV_MB_PARAM_GPIO_DIRECTION_MASK 0x00FF0000 1465 #define DRV_MB_PARAM_GPIO_CTRL_SHIFT 24 1466 #define DRV_MB_PARAM_GPIO_CTRL_MASK 0xFF000000 1467 1468 /* Resource Allocation params - Driver version support*/ 1469 #define DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_MASK 0xFFFF0000 1470 #define DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_SHIFT 16 1471 #define DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_MASK 0x0000FFFF 1472 #define DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_SHIFT 0 1473 1474 #define DRV_MB_PARAM_BIST_UNKNOWN_TEST 0 1475 #define DRV_MB_PARAM_BIST_REGISTER_TEST 1 1476 #define DRV_MB_PARAM_BIST_CLOCK_TEST 2 1477 #define DRV_MB_PARAM_BIST_NVM_TEST_NUM_IMAGES 3 1478 #define DRV_MB_PARAM_BIST_NVM_TEST_IMAGE_BY_INDEX 4 1479 1480 #define DRV_MB_PARAM_BIST_RC_UNKNOWN 0 1481 #define DRV_MB_PARAM_BIST_RC_PASSED 1 1482 #define DRV_MB_PARAM_BIST_RC_FAILED 2 1483 #define DRV_MB_PARAM_BIST_RC_INVALID_PARAMETER 3 1484 1485 #define DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT 0 1486 #define DRV_MB_PARAM_BIST_TEST_INDEX_MASK 0x000000FF 1487 #define DRV_MB_PARAM_BIST_TEST_IMAGE_INDEX_SHIFT 8 1488 #define DRV_MB_PARAM_BIST_TEST_IMAGE_INDEX_MASK 0x0000FF00 1489 1490 u32 fw_mb_header; 1491 #define FW_MSG_CODE_MASK 0xffff0000 1492 #define FW_MSG_CODE_UNSUPPORTED 0x00000000 1493 #define FW_MSG_CODE_DRV_LOAD_ENGINE 0x10100000 1494 #define FW_MSG_CODE_DRV_LOAD_PORT 0x10110000 1495 #define FW_MSG_CODE_DRV_LOAD_FUNCTION 0x10120000 1496 #define FW_MSG_CODE_DRV_LOAD_REFUSED_PDA 0x10200000 1497 #define FW_MSG_CODE_DRV_LOAD_REFUSED_HSI_1 0x10210000 1498 #define FW_MSG_CODE_DRV_LOAD_REFUSED_DIAG 0x10220000 1499 #define FW_MSG_CODE_DRV_LOAD_REFUSED_HSI 0x10230000 1500 #define FW_MSG_CODE_DRV_LOAD_REFUSED_REQUIRES_FORCE 0x10300000 1501 #define FW_MSG_CODE_DRV_LOAD_REFUSED_REJECT 0x10310000 1502 #define FW_MSG_CODE_DRV_LOAD_DONE 0x11100000 1503 #define FW_MSG_CODE_DRV_UNLOAD_ENGINE 0x20110000 1504 #define FW_MSG_CODE_DRV_UNLOAD_PORT 0x20120000 1505 #define FW_MSG_CODE_DRV_UNLOAD_FUNCTION 0x20130000 1506 #define FW_MSG_CODE_DRV_UNLOAD_DONE 0x21100000 1507 #define FW_MSG_CODE_INIT_PHY_DONE 0x21200000 1508 #define FW_MSG_CODE_INIT_PHY_ERR_INVALID_ARGS 0x21300000 1509 #define FW_MSG_CODE_LINK_RESET_DONE 0x23000000 1510 #define FW_MSG_CODE_SET_LLDP_DONE 0x24000000 1511 #define FW_MSG_CODE_SET_LLDP_UNSUPPORTED_AGENT 0x24010000 1512 #define FW_MSG_CODE_SET_DCBX_DONE 0x25000000 1513 #define FW_MSG_CODE_UPDATE_CURR_CFG_DONE 0x26000000 1514 #define FW_MSG_CODE_UPDATE_BUS_NUM_DONE 0x27000000 1515 #define FW_MSG_CODE_UPDATE_BOOT_PROGRESS_DONE 0x28000000 1516 #define FW_MSG_CODE_UPDATE_STORM_FW_VER_DONE 0x29000000 1517 #define FW_MSG_CODE_UPDATE_DRIVER_STATE_DONE 0x31000000 1518 #define FW_MSG_CODE_DRV_MSG_CODE_BW_UPDATE_DONE 0x32000000 1519 #define FW_MSG_CODE_DRV_MSG_CODE_MTU_SIZE_DONE 0x33000000 1520 #define FW_MSG_CODE_RESOURCE_ALLOC_OK 0x34000000 1521 #define FW_MSG_CODE_RESOURCE_ALLOC_UNKNOWN 0x35000000 1522 #define FW_MSG_CODE_RESOURCE_ALLOC_DEPRECATED 0x36000000 1523 #define FW_MSG_CODE_RESOURCE_ALLOC_GEN_ERR 0x37000000 1524 #define FW_MSG_CODE_NIG_DRAIN_DONE 0x30000000 1525 #define FW_MSG_CODE_VF_DISABLED_DONE 0xb0000000 1526 #define FW_MSG_CODE_DRV_CFG_VF_MSIX_DONE 0xb0010000 1527 #define FW_MSG_CODE_FLR_ACK 0x02000000 1528 #define FW_MSG_CODE_FLR_NACK 0x02100000 1529 #define FW_MSG_CODE_SET_DRIVER_DONE 0x02200000 1530 #define FW_MSG_CODE_SET_VMAC_SUCCESS 0x02300000 1531 #define FW_MSG_CODE_SET_VMAC_FAIL 0x02400000 1532 1533 #define FW_MSG_CODE_NVM_OK 0x00010000 1534 #define FW_MSG_CODE_NVM_INVALID_MODE 0x00020000 1535 #define FW_MSG_CODE_NVM_PREV_CMD_WAS_NOT_FINISHED 0x00030000 1536 #define FW_MSG_CODE_NVM_FAILED_TO_ALLOCATE_PAGE 0x00040000 1537 #define FW_MSG_CODE_NVM_INVALID_DIR_FOUND 0x00050000 1538 #define FW_MSG_CODE_NVM_PAGE_NOT_FOUND 0x00060000 1539 #define FW_MSG_CODE_NVM_FAILED_PARSING_BNDLE_HEADER 0x00070000 1540 #define FW_MSG_CODE_NVM_FAILED_PARSING_IMAGE_HEADER 0x00080000 1541 #define FW_MSG_CODE_NVM_PARSING_OUT_OF_SYNC 0x00090000 1542 #define FW_MSG_CODE_NVM_FAILED_UPDATING_DIR 0x000a0000 1543 #define FW_MSG_CODE_NVM_FAILED_TO_FREE_PAGE 0x000b0000 1544 #define FW_MSG_CODE_NVM_FILE_NOT_FOUND 0x000c0000 1545 #define FW_MSG_CODE_NVM_OPERATION_FAILED 0x000d0000 1546 #define FW_MSG_CODE_NVM_FAILED_UNALIGNED 0x000e0000 1547 #define FW_MSG_CODE_NVM_BAD_OFFSET 0x000f0000 1548 #define FW_MSG_CODE_NVM_BAD_SIGNATURE 0x00100000 1549 #define FW_MSG_CODE_NVM_FILE_READ_ONLY 0x00200000 1550 #define FW_MSG_CODE_NVM_UNKNOWN_FILE 0x00300000 1551 #define FW_MSG_CODE_NVM_PUT_FILE_FINISH_OK 0x00400000 1552 /* MFW reject "mcp reset" command if one of the drivers is up */ 1553 #define FW_MSG_CODE_MCP_RESET_REJECT 0x00600000 1554 #define FW_MSG_CODE_NVM_FAILED_CALC_HASH 0x00310000 1555 #define FW_MSG_CODE_NVM_PUBLIC_KEY_MISSING 0x00320000 1556 #define FW_MSG_CODE_NVM_INVALID_PUBLIC_KEY 0x00330000 1557 1558 #define FW_MSG_CODE_PHY_OK 0x00110000 1559 #define FW_MSG_CODE_PHY_ERROR 0x00120000 1560 #define FW_MSG_CODE_SET_SECURE_MODE_ERROR 0x00130000 1561 #define FW_MSG_CODE_SET_SECURE_MODE_OK 0x00140000 1562 #define FW_MSG_MODE_PHY_PRIVILEGE_ERROR 0x00150000 1563 #define FW_MSG_CODE_OK 0x00160000 1564 #define FW_MSG_CODE_LED_MODE_INVALID 0x00170000 1565 #define FW_MSG_CODE_PHY_DIAG_OK 0x00160000 1566 #define FW_MSG_CODE_PHY_DIAG_ERROR 0x00170000 1567 #define FW_MSG_CODE_INIT_HW_FAILED_TO_ALLOCATE_PAGE 0x00040000 1568 #define FW_MSG_CODE_INIT_HW_FAILED_BAD_STATE 0x00170000 1569 #define FW_MSG_CODE_INIT_HW_FAILED_TO_SET_WINDOW 0x000d0000 1570 #define FW_MSG_CODE_INIT_HW_FAILED_NO_IMAGE 0x000c0000 1571 #define FW_MSG_CODE_INIT_HW_FAILED_VERSION_MISMATCH 0x00100000 1572 #define FW_MSG_CODE_TRANSCEIVER_DIAG_OK 0x00160000 1573 #define FW_MSG_CODE_TRANSCEIVER_DIAG_ERROR 0x00170000 1574 #define FW_MSG_CODE_TRANSCEIVER_NOT_PRESENT 0x00020000 1575 #define FW_MSG_CODE_TRANSCEIVER_BAD_BUFFER_SIZE 0x000f0000 1576 #define FW_MSG_CODE_GPIO_OK 0x00160000 1577 #define FW_MSG_CODE_GPIO_DIRECTION_ERR 0x00170000 1578 #define FW_MSG_CODE_GPIO_CTRL_ERR 0x00020000 1579 #define FW_MSG_CODE_GPIO_INVALID 0x000f0000 1580 #define FW_MSG_CODE_GPIO_INVALID_VALUE 0x00050000 1581 #define FW_MSG_CODE_BIST_TEST_INVALID 0x000f0000 1582 #define FW_MSG_CODE_EXTPHY_INVALID_IMAGE_HEADER 0x00700000 1583 #define FW_MSG_CODE_EXTPHY_INVALID_PHY_TYPE 0x00710000 1584 #define FW_MSG_CODE_EXTPHY_OPERATION_FAILED 0x00720000 1585 #define FW_MSG_CODE_EXTPHY_NO_PHY_DETECTED 0x00730000 1586 #define FW_MSG_CODE_RECOVERY_MODE 0x00740000 1587 1588 /* mdump related response codes */ 1589 #define FW_MSG_CODE_MDUMP_NO_IMAGE_FOUND 0x00010000 1590 #define FW_MSG_CODE_MDUMP_ALLOC_FAILED 0x00020000 1591 #define FW_MSG_CODE_MDUMP_INVALID_CMD 0x00030000 1592 #define FW_MSG_CODE_MDUMP_IN_PROGRESS 0x00040000 1593 #define FW_MSG_CODE_MDUMP_WRITE_FAILED 0x00050000 1594 1595 #define FW_MSG_SEQ_NUMBER_MASK 0x0000ffff 1596 1597 1598 u32 fw_mb_param; 1599 /* Resource Allocation params - MFW version support */ 1600 #define FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_MASK 0xFFFF0000 1601 #define FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_SHIFT 16 1602 #define FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_MASK 0x0000FFFF 1603 #define FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_SHIFT 0 1604 1605 1606 u32 drv_pulse_mb; 1607 #define DRV_PULSE_SEQ_MASK 0x00007fff 1608 #define DRV_PULSE_SYSTEM_TIME_MASK 0xffff0000 1609 /* 1610 * The system time is in the format of 1611 * (year-2001)*12*32 + month*32 + day. 1612 */ 1613 #define DRV_PULSE_ALWAYS_ALIVE 0x00008000 1614 /* 1615 * Indicate to the firmware not to go into the 1616 * OS-absent when it is not getting driver pulse. 1617 * This is used for debugging as well for PXE(MBA). 1618 */ 1619 1620 u32 mcp_pulse_mb; 1621 #define MCP_PULSE_SEQ_MASK 0x00007fff 1622 #define MCP_PULSE_ALWAYS_ALIVE 0x00008000 1623 /* Indicates to the driver not to assert due to lack 1624 * of MCP response 1625 */ 1626 #define MCP_EVENT_MASK 0xffff0000 1627 #define MCP_EVENT_OTHER_DRIVER_RESET_REQ 0x00010000 1628 1629 /* The union data is used by the driver to pass parameters to the scratchpad. */ 1630 1631 union drv_union_data union_data; 1632 1633 }; 1634 1635 /* MFW - DRV MB */ 1636 /********************************************************************** 1637 * Description 1638 * Incremental Aggregative 1639 * 8-bit MFW counter per message 1640 * 8-bit ack-counter per message 1641 * Capabilities 1642 * Provides up to 256 aggregative message per type 1643 * Provides 4 message types in dword 1644 * Message type pointers to byte offset 1645 * Backward Compatibility by using sizeof for the counters. 1646 * No lock requires for 32bit messages 1647 * Limitations: 1648 * In case of messages greater than 32bit, a dedicated mechanism(e.g lock) 1649 * is required to prevent data corruption. 1650 **********************************************************************/ 1651 enum MFW_DRV_MSG_TYPE { 1652 MFW_DRV_MSG_LINK_CHANGE, 1653 MFW_DRV_MSG_FLR_FW_ACK_FAILED, 1654 MFW_DRV_MSG_VF_DISABLED, 1655 MFW_DRV_MSG_LLDP_DATA_UPDATED, 1656 MFW_DRV_MSG_DCBX_REMOTE_MIB_UPDATED, 1657 MFW_DRV_MSG_DCBX_OPERATIONAL_MIB_UPDATED, 1658 MFW_DRV_MSG_ERROR_RECOVERY, 1659 MFW_DRV_MSG_BW_UPDATE, 1660 MFW_DRV_MSG_S_TAG_UPDATE, 1661 MFW_DRV_MSG_GET_LAN_STATS, 1662 MFW_DRV_MSG_GET_FCOE_STATS, 1663 MFW_DRV_MSG_GET_ISCSI_STATS, 1664 MFW_DRV_MSG_GET_RDMA_STATS, 1665 MFW_DRV_MSG_FAILURE_DETECTED, 1666 MFW_DRV_MSG_TRANSCEIVER_STATE_CHANGE, 1667 MFW_DRV_MSG_CRITICAL_ERROR_OCCURRED, 1668 MFW_DRV_MSG_EEE_NEGOTIATION_COMPLETE, 1669 MFW_DRV_MSG_MAX 1670 }; 1671 1672 #define MFW_DRV_MSG_MAX_DWORDS(msgs) (((msgs - 1) >> 2) + 1) 1673 #define MFW_DRV_MSG_DWORD(msg_id) (msg_id >> 2) 1674 #define MFW_DRV_MSG_OFFSET(msg_id) ((msg_id & 0x3) << 3) 1675 #define MFW_DRV_MSG_MASK(msg_id) (0xff << MFW_DRV_MSG_OFFSET(msg_id)) 1676 1677 #ifdef BIG_ENDIAN /* Like MFW */ 1678 #define DRV_ACK_MSG(msg_p, msg_id) \ 1679 ((u8)((u8 *)msg_p)[msg_id]++;) 1680 #else 1681 #define DRV_ACK_MSG(msg_p, msg_id) \ 1682 ((u8)((u8 *)msg_p)[((msg_id & ~3) | ((~msg_id) & 3))]++;) 1683 #endif 1684 1685 #define MFW_DRV_UPDATE(shmem_func, msg_id) \ 1686 ((u8)((u8 *)(MFW_MB_P(shmem_func)->msg))[msg_id]++;) 1687 1688 struct public_mfw_mb { 1689 u32 sup_msgs; /* Assigend with MFW_DRV_MSG_MAX */ 1690 /* Incremented by the MFW */ 1691 u32 msg[MFW_DRV_MSG_MAX_DWORDS(MFW_DRV_MSG_MAX)]; 1692 /* Incremented by the driver */ 1693 u32 ack[MFW_DRV_MSG_MAX_DWORDS(MFW_DRV_MSG_MAX)]; 1694 }; 1695 1696 /**************************************/ 1697 /* */ 1698 /* P U B L I C D A T A */ 1699 /* */ 1700 /**************************************/ 1701 enum public_sections { 1702 PUBLIC_DRV_MB, /* Points to the first drv_mb of path0 */ 1703 PUBLIC_MFW_MB, /* Points to the first mfw_mb of path0 */ 1704 PUBLIC_GLOBAL, 1705 PUBLIC_PATH, 1706 PUBLIC_PORT, 1707 PUBLIC_FUNC, 1708 PUBLIC_MAX_SECTIONS 1709 }; 1710 1711 struct drv_ver_info_stc { 1712 u32 ver; 1713 u8 name[32]; 1714 }; 1715 1716 /* Runtime data needs about 1/2K. We use 2K to be on the safe side. 1717 * Please make sure data does not exceed this size. 1718 */ 1719 #define NUM_RUNTIME_DWORDS 16 1720 struct drv_init_hw_stc { 1721 u32 init_hw_bitmask[NUM_RUNTIME_DWORDS]; 1722 u32 init_hw_data[NUM_RUNTIME_DWORDS * 32]; 1723 }; 1724 1725 struct mcp_public_data { 1726 /* The sections fields is an array */ 1727 u32 num_sections; 1728 offsize_t sections[PUBLIC_MAX_SECTIONS]; 1729 struct public_drv_mb drv_mb[MCP_GLOB_FUNC_MAX]; 1730 struct public_mfw_mb mfw_mb[MCP_GLOB_FUNC_MAX]; 1731 struct public_global global; 1732 struct public_path path[MCP_GLOB_PATH_MAX]; 1733 struct public_port port[MCP_GLOB_PORT_MAX]; 1734 struct public_func func[MCP_GLOB_FUNC_MAX]; 1735 }; 1736 1737 #define I2C_TRANSCEIVER_ADDR 0xa0 1738 #define MAX_I2C_TRANSACTION_SIZE 16 1739 #define MAX_I2C_TRANSCEIVER_PAGE_SIZE 256 1740 1741 #endif /* MCP_PUBLIC_H */ 1742