1 /* 2 * Copyright (c) 2016 - 2018 Cavium Inc. 3 * All rights reserved. 4 * www.cavium.com 5 * 6 * See LICENSE.qede_pmd for copyright and licensing details. 7 */ 8 9 #ifndef __ECORE_MCP_API_H__ 10 #define __ECORE_MCP_API_H__ 11 12 #include "ecore_status.h" 13 14 struct ecore_mcp_link_speed_params { 15 bool autoneg; 16 u32 advertised_speeds; /* bitmask of DRV_SPEED_CAPABILITY */ 17 u32 forced_speed; /* In Mb/s */ 18 }; 19 20 struct ecore_mcp_link_pause_params { 21 bool autoneg; 22 bool forced_rx; 23 bool forced_tx; 24 }; 25 26 enum ecore_mcp_eee_mode { 27 ECORE_MCP_EEE_DISABLED, 28 ECORE_MCP_EEE_ENABLED, 29 ECORE_MCP_EEE_UNSUPPORTED 30 }; 31 32 struct ecore_link_eee_params { 33 u32 tx_lpi_timer; 34 #define ECORE_EEE_1G_ADV (1 << 0) 35 #define ECORE_EEE_10G_ADV (1 << 1) 36 /* Capabilities are represented using ECORE_EEE_*_ADV values */ 37 u8 adv_caps; 38 u8 lp_adv_caps; 39 bool enable; 40 bool tx_lpi_enable; 41 }; 42 43 struct ecore_mcp_link_params { 44 struct ecore_mcp_link_speed_params speed; 45 struct ecore_mcp_link_pause_params pause; 46 u32 loopback_mode; /* in PMM_LOOPBACK values */ 47 struct ecore_link_eee_params eee; 48 }; 49 50 struct ecore_mcp_link_capabilities { 51 u32 speed_capabilities; 52 bool default_speed_autoneg; /* In Mb/s */ 53 u32 default_speed; /* In Mb/s */ 54 enum ecore_mcp_eee_mode default_eee; 55 u32 eee_lpi_timer; 56 u8 eee_speed_caps; 57 }; 58 59 struct ecore_mcp_link_state { 60 bool link_up; 61 62 u32 min_pf_rate; /* In Mb/s */ 63 64 /* Actual link speed in Mb/s */ 65 u32 line_speed; 66 67 /* PF max speed in MB/s, deduced from line_speed 68 * according to PF max bandwidth configuration. 69 */ 70 u32 speed; 71 bool full_duplex; 72 73 bool an; 74 bool an_complete; 75 bool parallel_detection; 76 bool pfc_enabled; 77 78 #define ECORE_LINK_PARTNER_SPEED_1G_HD (1 << 0) 79 #define ECORE_LINK_PARTNER_SPEED_1G_FD (1 << 1) 80 #define ECORE_LINK_PARTNER_SPEED_10G (1 << 2) 81 #define ECORE_LINK_PARTNER_SPEED_20G (1 << 3) 82 #define ECORE_LINK_PARTNER_SPEED_25G (1 << 4) 83 #define ECORE_LINK_PARTNER_SPEED_40G (1 << 5) 84 #define ECORE_LINK_PARTNER_SPEED_50G (1 << 6) 85 #define ECORE_LINK_PARTNER_SPEED_100G (1 << 7) 86 u32 partner_adv_speed; 87 88 bool partner_tx_flow_ctrl_en; 89 bool partner_rx_flow_ctrl_en; 90 91 #define ECORE_LINK_PARTNER_SYMMETRIC_PAUSE (1) 92 #define ECORE_LINK_PARTNER_ASYMMETRIC_PAUSE (2) 93 #define ECORE_LINK_PARTNER_BOTH_PAUSE (3) 94 u8 partner_adv_pause; 95 96 bool sfp_tx_fault; 97 98 bool eee_active; 99 u8 eee_adv_caps; 100 u8 eee_lp_adv_caps; 101 }; 102 103 struct ecore_mcp_function_info { 104 u8 pause_on_host; 105 106 enum ecore_pci_personality protocol; 107 108 u8 bandwidth_min; 109 u8 bandwidth_max; 110 111 u8 mac[ETH_ALEN]; 112 113 u64 wwn_port; 114 u64 wwn_node; 115 116 #define ECORE_MCP_VLAN_UNSET (0xffff) 117 u16 ovlan; 118 119 u16 mtu; 120 }; 121 122 #ifndef __EXTRACT__LINUX__ 123 enum ecore_nvm_images { 124 ECORE_NVM_IMAGE_ISCSI_CFG, 125 ECORE_NVM_IMAGE_FCOE_CFG, 126 }; 127 #endif 128 129 struct ecore_mcp_drv_version { 130 u32 version; 131 u8 name[MCP_DRV_VER_STR_SIZE - 4]; 132 }; 133 134 struct ecore_mcp_lan_stats { 135 u64 ucast_rx_pkts; 136 u64 ucast_tx_pkts; 137 u32 fcs_err; 138 }; 139 140 #ifndef ECORE_PROTO_STATS 141 #define ECORE_PROTO_STATS 142 struct ecore_mcp_fcoe_stats { 143 u64 rx_pkts; 144 u64 tx_pkts; 145 u32 fcs_err; 146 u32 login_failure; 147 }; 148 149 struct ecore_mcp_iscsi_stats { 150 u64 rx_pdus; 151 u64 tx_pdus; 152 u64 rx_bytes; 153 u64 tx_bytes; 154 }; 155 156 struct ecore_mcp_rdma_stats { 157 u64 rx_pkts; 158 u64 tx_pkts; 159 u64 rx_bytes; 160 u64 tx_byts; 161 }; 162 163 enum ecore_mcp_protocol_type { 164 ECORE_MCP_LAN_STATS, 165 ECORE_MCP_FCOE_STATS, 166 ECORE_MCP_ISCSI_STATS, 167 ECORE_MCP_RDMA_STATS 168 }; 169 170 union ecore_mcp_protocol_stats { 171 struct ecore_mcp_lan_stats lan_stats; 172 struct ecore_mcp_fcoe_stats fcoe_stats; 173 struct ecore_mcp_iscsi_stats iscsi_stats; 174 struct ecore_mcp_rdma_stats rdma_stats; 175 }; 176 #endif 177 178 enum ecore_ov_client { 179 ECORE_OV_CLIENT_DRV, 180 ECORE_OV_CLIENT_USER, 181 ECORE_OV_CLIENT_VENDOR_SPEC 182 }; 183 184 enum ecore_ov_driver_state { 185 ECORE_OV_DRIVER_STATE_NOT_LOADED, 186 ECORE_OV_DRIVER_STATE_DISABLED, 187 ECORE_OV_DRIVER_STATE_ACTIVE 188 }; 189 190 #define ECORE_MAX_NPIV_ENTRIES 128 191 #define ECORE_WWN_SIZE 8 192 struct ecore_fc_npiv_tbl { 193 u32 count; 194 u8 wwpn[ECORE_MAX_NPIV_ENTRIES][ECORE_WWN_SIZE]; 195 u8 wwnn[ECORE_MAX_NPIV_ENTRIES][ECORE_WWN_SIZE]; 196 }; 197 198 #ifndef __EXTRACT__LINUX__ 199 enum ecore_led_mode { 200 ECORE_LED_MODE_OFF, 201 ECORE_LED_MODE_ON, 202 ECORE_LED_MODE_RESTORE 203 }; 204 #endif 205 206 struct ecore_temperature_sensor { 207 u8 sensor_location; 208 u8 threshold_high; 209 u8 critical; 210 u8 current_temp; 211 }; 212 213 #define ECORE_MAX_NUM_OF_SENSORS 7 214 struct ecore_temperature_info { 215 u32 num_sensors; 216 struct ecore_temperature_sensor sensors[ECORE_MAX_NUM_OF_SENSORS]; 217 }; 218 219 enum ecore_mba_img_idx { 220 ECORE_MBA_LEGACY_IDX, 221 ECORE_MBA_PCI3CLP_IDX, 222 ECORE_MBA_PCI3_IDX, 223 ECORE_MBA_FCODE_IDX, 224 ECORE_EFI_X86_IDX, 225 ECORE_EFI_IPF_IDX, 226 ECORE_EFI_EBC_IDX, 227 ECORE_EFI_X64_IDX, 228 ECORE_MAX_NUM_OF_ROMIMG 229 }; 230 231 struct ecore_mba_vers { 232 u32 mba_vers[ECORE_MAX_NUM_OF_ROMIMG]; 233 }; 234 235 enum ecore_mfw_tlv_type { 236 ECORE_MFW_TLV_GENERIC = 0x1, /* Core driver TLVs */ 237 ECORE_MFW_TLV_ETH = 0x2, /* L2 driver TLVs */ 238 ECORE_MFW_TLV_FCOE = 0x4, /* FCoE protocol TLVs */ 239 ECORE_MFW_TLV_ISCSI = 0x8, /* SCSI protocol TLVs */ 240 ECORE_MFW_TLV_MAX = 0x16, 241 }; 242 243 struct ecore_mfw_tlv_generic { 244 u16 feat_flags; 245 bool feat_flags_set; 246 u64 local_mac; 247 bool local_mac_set; 248 u64 additional_mac1; 249 bool additional_mac1_set; 250 u64 additional_mac2; 251 bool additional_mac2_set; 252 u8 drv_state; 253 bool drv_state_set; 254 u8 pxe_progress; 255 bool pxe_progress_set; 256 u64 rx_frames; 257 bool rx_frames_set; 258 u64 rx_bytes; 259 bool rx_bytes_set; 260 u64 tx_frames; 261 bool tx_frames_set; 262 u64 tx_bytes; 263 bool tx_bytes_set; 264 }; 265 266 struct ecore_mfw_tlv_eth { 267 u16 lso_maxoff_size; 268 bool lso_maxoff_size_set; 269 u16 lso_minseg_size; 270 bool lso_minseg_size_set; 271 u8 prom_mode; 272 bool prom_mode_set; 273 u16 tx_descr_size; 274 bool tx_descr_size_set; 275 u16 rx_descr_size; 276 bool rx_descr_size_set; 277 u16 netq_count; 278 bool netq_count_set; 279 u32 tcp4_offloads; 280 bool tcp4_offloads_set; 281 u32 tcp6_offloads; 282 bool tcp6_offloads_set; 283 u16 tx_descr_qdepth; 284 bool tx_descr_qdepth_set; 285 u16 rx_descr_qdepth; 286 bool rx_descr_qdepth_set; 287 u8 iov_offload; 288 bool iov_offload_set; 289 u8 txqs_empty; 290 bool txqs_empty_set; 291 u8 rxqs_empty; 292 bool rxqs_empty_set; 293 u8 num_txqs_full; 294 bool num_txqs_full_set; 295 u8 num_rxqs_full; 296 bool num_rxqs_full_set; 297 }; 298 299 struct ecore_mfw_tlv_fcoe { 300 u8 scsi_timeout; 301 bool scsi_timeout_set; 302 u32 rt_tov; 303 bool rt_tov_set; 304 u32 ra_tov; 305 bool ra_tov_set; 306 u32 ed_tov; 307 bool ed_tov_set; 308 u32 cr_tov; 309 bool cr_tov_set; 310 u8 boot_type; 311 bool boot_type_set; 312 u8 npiv_state; 313 bool npiv_state_set; 314 u32 num_npiv_ids; 315 bool num_npiv_ids_set; 316 u8 switch_name[8]; 317 bool switch_name_set; 318 u16 switch_portnum; 319 bool switch_portnum_set; 320 u8 switch_portid[3]; 321 bool switch_portid_set; 322 u8 vendor_name[8]; 323 bool vendor_name_set; 324 u8 switch_model[8]; 325 bool switch_model_set; 326 u8 switch_fw_version[8]; 327 bool switch_fw_version_set; 328 u8 qos_pri; 329 bool qos_pri_set; 330 u8 port_alias[3]; 331 bool port_alias_set; 332 u8 port_state; 333 bool port_state_set; 334 u16 fip_tx_descr_size; 335 bool fip_tx_descr_size_set; 336 u16 fip_rx_descr_size; 337 bool fip_rx_descr_size_set; 338 u16 link_failures; 339 bool link_failures_set; 340 u8 fcoe_boot_progress; 341 bool fcoe_boot_progress_set; 342 u64 rx_bcast; 343 bool rx_bcast_set; 344 u64 tx_bcast; 345 bool tx_bcast_set; 346 u16 fcoe_txq_depth; 347 bool fcoe_txq_depth_set; 348 u16 fcoe_rxq_depth; 349 bool fcoe_rxq_depth_set; 350 u64 fcoe_rx_frames; 351 bool fcoe_rx_frames_set; 352 u64 fcoe_rx_bytes; 353 bool fcoe_rx_bytes_set; 354 u64 fcoe_tx_frames; 355 bool fcoe_tx_frames_set; 356 u64 fcoe_tx_bytes; 357 bool fcoe_tx_bytes_set; 358 u16 crc_count; 359 bool crc_count_set; 360 u32 crc_err_src_fcid[5]; 361 bool crc_err_src_fcid_set[5]; 362 u8 crc_err_tstamp[5][14]; 363 bool crc_err_tstamp_set[5]; 364 u16 losync_err; 365 bool losync_err_set; 366 u16 losig_err; 367 bool losig_err_set; 368 u16 primtive_err; 369 bool primtive_err_set; 370 u16 disparity_err; 371 bool disparity_err_set; 372 u16 code_violation_err; 373 bool code_violation_err_set; 374 u32 flogi_param[4]; 375 bool flogi_param_set[4]; 376 u8 flogi_tstamp[14]; 377 bool flogi_tstamp_set; 378 u32 flogi_acc_param[4]; 379 bool flogi_acc_param_set[4]; 380 u8 flogi_acc_tstamp[14]; 381 bool flogi_acc_tstamp_set; 382 u32 flogi_rjt; 383 bool flogi_rjt_set; 384 u8 flogi_rjt_tstamp[14]; 385 bool flogi_rjt_tstamp_set; 386 u32 fdiscs; 387 bool fdiscs_set; 388 u8 fdisc_acc; 389 bool fdisc_acc_set; 390 u8 fdisc_rjt; 391 bool fdisc_rjt_set; 392 u8 plogi; 393 bool plogi_set; 394 u8 plogi_acc; 395 bool plogi_acc_set; 396 u8 plogi_rjt; 397 bool plogi_rjt_set; 398 u32 plogi_dst_fcid[5]; 399 bool plogi_dst_fcid_set[5]; 400 u8 plogi_tstamp[5][14]; 401 bool plogi_tstamp_set[5]; 402 u32 plogi_acc_src_fcid[5]; 403 bool plogi_acc_src_fcid_set[5]; 404 u8 plogi_acc_tstamp[5][14]; 405 bool plogi_acc_tstamp_set[5]; 406 u8 tx_plogos; 407 bool tx_plogos_set; 408 u8 plogo_acc; 409 bool plogo_acc_set; 410 u8 plogo_rjt; 411 bool plogo_rjt_set; 412 u32 plogo_src_fcid[5]; 413 bool plogo_src_fcid_set[5]; 414 u8 plogo_tstamp[5][14]; 415 bool plogo_tstamp_set[5]; 416 u8 rx_logos; 417 bool rx_logos_set; 418 u8 tx_accs; 419 bool tx_accs_set; 420 u8 tx_prlis; 421 bool tx_prlis_set; 422 u8 rx_accs; 423 bool rx_accs_set; 424 u8 tx_abts; 425 bool tx_abts_set; 426 u8 rx_abts_acc; 427 bool rx_abts_acc_set; 428 u8 rx_abts_rjt; 429 bool rx_abts_rjt_set; 430 u32 abts_dst_fcid[5]; 431 bool abts_dst_fcid_set[5]; 432 u8 abts_tstamp[5][14]; 433 bool abts_tstamp_set[5]; 434 u8 rx_rscn; 435 bool rx_rscn_set; 436 u32 rx_rscn_nport[4]; 437 bool rx_rscn_nport_set[4]; 438 u8 tx_lun_rst; 439 bool tx_lun_rst_set; 440 u8 abort_task_sets; 441 bool abort_task_sets_set; 442 u8 tx_tprlos; 443 bool tx_tprlos_set; 444 u8 tx_nos; 445 bool tx_nos_set; 446 u8 rx_nos; 447 bool rx_nos_set; 448 u8 ols; 449 bool ols_set; 450 u8 lr; 451 bool lr_set; 452 u8 lrr; 453 bool lrr_set; 454 u8 tx_lip; 455 bool tx_lip_set; 456 u8 rx_lip; 457 bool rx_lip_set; 458 u8 eofa; 459 bool eofa_set; 460 u8 eofni; 461 bool eofni_set; 462 u8 scsi_chks; 463 bool scsi_chks_set; 464 u8 scsi_cond_met; 465 bool scsi_cond_met_set; 466 u8 scsi_busy; 467 bool scsi_busy_set; 468 u8 scsi_inter; 469 bool scsi_inter_set; 470 u8 scsi_inter_cond_met; 471 bool scsi_inter_cond_met_set; 472 u8 scsi_rsv_conflicts; 473 bool scsi_rsv_conflicts_set; 474 u8 scsi_tsk_full; 475 bool scsi_tsk_full_set; 476 u8 scsi_aca_active; 477 bool scsi_aca_active_set; 478 u8 scsi_tsk_abort; 479 bool scsi_tsk_abort_set; 480 u32 scsi_rx_chk[5]; 481 bool scsi_rx_chk_set[5]; 482 u8 scsi_chk_tstamp[5][14]; 483 bool scsi_chk_tstamp_set[5]; 484 }; 485 486 struct ecore_mfw_tlv_iscsi { 487 u8 target_llmnr; 488 bool target_llmnr_set; 489 u8 header_digest; 490 bool header_digest_set; 491 u8 data_digest; 492 bool data_digest_set; 493 u8 auth_method; 494 bool auth_method_set; 495 u16 boot_taget_portal; 496 bool boot_taget_portal_set; 497 u16 frame_size; 498 bool frame_size_set; 499 u16 tx_desc_size; 500 bool tx_desc_size_set; 501 u16 rx_desc_size; 502 bool rx_desc_size_set; 503 u8 boot_progress; 504 bool boot_progress_set; 505 u16 tx_desc_qdepth; 506 bool tx_desc_qdepth_set; 507 u16 rx_desc_qdepth; 508 bool rx_desc_qdepth_set; 509 u64 rx_frames; 510 bool rx_frames_set; 511 u64 rx_bytes; 512 bool rx_bytes_set; 513 u64 tx_frames; 514 bool tx_frames_set; 515 u64 tx_bytes; 516 bool tx_bytes_set; 517 }; 518 519 union ecore_mfw_tlv_data { 520 struct ecore_mfw_tlv_generic generic; 521 struct ecore_mfw_tlv_eth eth; 522 struct ecore_mfw_tlv_fcoe fcoe; 523 struct ecore_mfw_tlv_iscsi iscsi; 524 }; 525 526 /** 527 * @brief - returns the link params of the hw function 528 * 529 * @param p_hwfn 530 * 531 * @returns pointer to link params 532 */ 533 struct ecore_mcp_link_params *ecore_mcp_get_link_params(struct ecore_hwfn *); 534 535 /** 536 * @brief - return the link state of the hw function 537 * 538 * @param p_hwfn 539 * 540 * @returns pointer to link state 541 */ 542 struct ecore_mcp_link_state *ecore_mcp_get_link_state(struct ecore_hwfn *); 543 544 /** 545 * @brief - return the link capabilities of the hw function 546 * 547 * @param p_hwfn 548 * 549 * @returns pointer to link capabilities 550 */ 551 struct ecore_mcp_link_capabilities 552 *ecore_mcp_get_link_capabilities(struct ecore_hwfn *p_hwfn); 553 554 /** 555 * @brief Request the MFW to set the link according to 'link_input'. 556 * 557 * @param p_hwfn 558 * @param p_ptt 559 * @param b_up - raise link if `true'. Reset link if `false'. 560 * 561 * @return enum _ecore_status_t 562 */ 563 enum _ecore_status_t ecore_mcp_set_link(struct ecore_hwfn *p_hwfn, 564 struct ecore_ptt *p_ptt, 565 bool b_up); 566 567 /** 568 * @brief Get the management firmware version value 569 * 570 * @param p_hwfn 571 * @param p_ptt 572 * @param p_mfw_ver - mfw version value 573 * @param p_running_bundle_id - image id in nvram; Optional. 574 * 575 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful. 576 */ 577 enum _ecore_status_t ecore_mcp_get_mfw_ver(struct ecore_hwfn *p_hwfn, 578 struct ecore_ptt *p_ptt, 579 u32 *p_mfw_ver, 580 u32 *p_running_bundle_id); 581 582 /** 583 * @brief Get media type value of the port. 584 * 585 * @param p_dev - ecore dev pointer 586 * @param p_ptt 587 * @param mfw_ver - media type value 588 * 589 * @return enum _ecore_status_t - 590 * ECORE_SUCCESS - Operation was successful. 591 * ECORE_BUSY - Operation failed 592 */ 593 enum _ecore_status_t ecore_mcp_get_media_type(struct ecore_hwfn *p_hwfn, 594 struct ecore_ptt *p_ptt, 595 u32 *media_type); 596 597 /** 598 * @brief Get transceiver data of the port. 599 * 600 * @param p_dev - ecore dev pointer 601 * @param p_ptt 602 * @param p_transceiver_type - media type value 603 * 604 * @return enum _ecore_status_t - 605 * ECORE_SUCCESS - Operation was successful. 606 * ECORE_BUSY - Operation failed 607 */ 608 enum _ecore_status_t ecore_mcp_get_transceiver_data(struct ecore_hwfn *p_hwfn, 609 struct ecore_ptt *p_ptt, 610 u32 *p_tranceiver_type); 611 612 /** 613 * @brief Get transceiver supported speed mask. 614 * 615 * @param p_dev - ecore dev pointer 616 * @param p_ptt 617 * @param p_speed_mask - Bit mask of all supported speeds. 618 * 619 * @return enum _ecore_status_t - 620 * ECORE_SUCCESS - Operation was successful. 621 * ECORE_BUSY - Operation failed 622 */ 623 624 enum _ecore_status_t ecore_mcp_trans_speed_mask(struct ecore_hwfn *p_hwfn, 625 struct ecore_ptt *p_ptt, 626 u32 *p_speed_mask); 627 628 /** 629 * @brief Get board configuration. 630 * 631 * @param p_dev - ecore dev pointer 632 * @param p_ptt 633 * @param p_board_config - Board config. 634 * 635 * @return enum _ecore_status_t - 636 * ECORE_SUCCESS - Operation was successful. 637 * ECORE_BUSY - Operation failed 638 */ 639 enum _ecore_status_t ecore_mcp_get_board_config(struct ecore_hwfn *p_hwfn, 640 struct ecore_ptt *p_ptt, 641 u32 *p_board_config); 642 643 /** 644 * @brief - Sends a command to the MCP mailbox. 645 * 646 * @param p_hwfn - hw function 647 * @param p_ptt - PTT required for register access 648 * @param cmd - command to be sent to the MCP 649 * @param param - Optional param 650 * @param o_mcp_resp - The MCP response code (exclude sequence) 651 * @param o_mcp_param - Optional parameter provided by the MCP response 652 * 653 * @return enum _ecore_status_t - 654 * ECORE_SUCCESS - operation was successful 655 * ECORE_BUSY - operation failed 656 */ 657 enum _ecore_status_t ecore_mcp_cmd(struct ecore_hwfn *p_hwfn, 658 struct ecore_ptt *p_ptt, u32 cmd, u32 param, 659 u32 *o_mcp_resp, u32 *o_mcp_param); 660 661 /** 662 * @brief - drains the nig, allowing completion to pass in case of pauses. 663 * (Should be called only from sleepable context) 664 * 665 * @param p_hwfn 666 * @param p_ptt 667 */ 668 enum _ecore_status_t ecore_mcp_drain(struct ecore_hwfn *p_hwfn, 669 struct ecore_ptt *p_ptt); 670 671 #ifndef LINUX_REMOVE 672 /** 673 * @brief - return the mcp function info of the hw function 674 * 675 * @param p_hwfn 676 * 677 * @returns pointer to mcp function info 678 */ 679 const struct ecore_mcp_function_info 680 *ecore_mcp_get_function_info(struct ecore_hwfn *p_hwfn); 681 #endif 682 683 #ifndef LINUX_REMOVE 684 /** 685 * @brief - count number of function with a matching personality on engine. 686 * 687 * @param p_hwfn 688 * @param p_ptt 689 * @param personalities - a bitmask of ecore_pci_personality values 690 * 691 * @returns the count of all devices on engine whose personality match one of 692 * the bitsmasks. 693 */ 694 int ecore_mcp_get_personality_cnt(struct ecore_hwfn *p_hwfn, 695 struct ecore_ptt *p_ptt, 696 u32 personalities); 697 #endif 698 699 /** 700 * @brief Get the flash size value 701 * 702 * @param p_hwfn 703 * @param p_ptt 704 * @param p_flash_size - flash size in bytes to be filled. 705 * 706 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful. 707 */ 708 enum _ecore_status_t ecore_mcp_get_flash_size(struct ecore_hwfn *p_hwfn, 709 struct ecore_ptt *p_ptt, 710 u32 *p_flash_size); 711 712 /** 713 * @brief Send driver version to MFW 714 * 715 * @param p_hwfn 716 * @param p_ptt 717 * @param version - Version value 718 * @param name - Protocol driver name 719 * 720 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful. 721 */ 722 enum _ecore_status_t 723 ecore_mcp_send_drv_version(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt, 724 struct ecore_mcp_drv_version *p_ver); 725 726 /** 727 * @brief Read the MFW process kill counter 728 * 729 * @param p_hwfn 730 * @param p_ptt 731 * 732 * @return u32 733 */ 734 u32 ecore_get_process_kill_counter(struct ecore_hwfn *p_hwfn, 735 struct ecore_ptt *p_ptt); 736 737 /** 738 * @brief Trigger a recovery process 739 * 740 * @param p_hwfn 741 * @param p_ptt 742 * 743 * @return enum _ecore_status_t 744 */ 745 enum _ecore_status_t ecore_start_recovery_process(struct ecore_hwfn *p_hwfn, 746 struct ecore_ptt *p_ptt); 747 748 /** 749 * @brief A recovery handler must call this function as its first step. 750 * It is assumed that the handler is not run from an interrupt context. 751 * 752 * @param p_dev 753 * @param p_ptt 754 * 755 * @return enum _ecore_status_t 756 */ 757 enum _ecore_status_t ecore_recovery_prolog(struct ecore_dev *p_dev); 758 759 /** 760 * @brief Notify MFW about the change in base device properties 761 * 762 * @param p_hwfn 763 * @param p_ptt 764 * @param client - ecore client type 765 * 766 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful. 767 */ 768 enum _ecore_status_t 769 ecore_mcp_ov_update_current_config(struct ecore_hwfn *p_hwfn, 770 struct ecore_ptt *p_ptt, 771 enum ecore_ov_client client); 772 773 /** 774 * @brief Notify MFW about the driver state 775 * 776 * @param p_hwfn 777 * @param p_ptt 778 * @param drv_state - Driver state 779 * 780 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful. 781 */ 782 enum _ecore_status_t 783 ecore_mcp_ov_update_driver_state(struct ecore_hwfn *p_hwfn, 784 struct ecore_ptt *p_ptt, 785 enum ecore_ov_driver_state drv_state); 786 787 /** 788 * @brief Read NPIV settings form the MFW 789 * 790 * @param p_hwfn 791 * @param p_ptt 792 * @param p_table - Array to hold the FC NPIV data. Client need allocate the 793 * required buffer. The field 'count' specifies number of NPIV 794 * entries. A value of 0 means the table was not populated. 795 * 796 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful. 797 */ 798 enum _ecore_status_t 799 ecore_mcp_ov_get_fc_npiv(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt, 800 struct ecore_fc_npiv_tbl *p_table); 801 802 /** 803 * @brief Send MTU size to MFW 804 * 805 * @param p_hwfn 806 * @param p_ptt 807 * @param mtu - MTU size 808 * 809 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful. 810 */ 811 enum _ecore_status_t ecore_mcp_ov_update_mtu(struct ecore_hwfn *p_hwfn, 812 struct ecore_ptt *p_ptt, u16 mtu); 813 814 /** 815 * @brief Set LED status 816 * 817 * @param p_hwfn 818 * @param p_ptt 819 * @param mode - LED mode 820 * 821 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful. 822 */ 823 enum _ecore_status_t ecore_mcp_set_led(struct ecore_hwfn *p_hwfn, 824 struct ecore_ptt *p_ptt, 825 enum ecore_led_mode mode); 826 827 /** 828 * @brief Set secure mode 829 * 830 * @param p_dev 831 * @param addr - nvm offset 832 * 833 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful. 834 */ 835 enum _ecore_status_t ecore_mcp_nvm_set_secure_mode(struct ecore_dev *p_dev, 836 u32 addr); 837 838 /** 839 * @brief Write to phy 840 * 841 * @param p_dev 842 * @param addr - nvm offset 843 * @param cmd - nvm command 844 * @param p_buf - nvm write buffer 845 * @param len - buffer len 846 * 847 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful. 848 */ 849 enum _ecore_status_t ecore_mcp_phy_write(struct ecore_dev *p_dev, u32 cmd, 850 u32 addr, u8 *p_buf, u32 len); 851 852 /** 853 * @brief Write to nvm 854 * 855 * @param p_dev 856 * @param addr - nvm offset 857 * @param cmd - nvm command 858 * @param p_buf - nvm write buffer 859 * @param len - buffer len 860 * 861 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful. 862 */ 863 enum _ecore_status_t ecore_mcp_nvm_write(struct ecore_dev *p_dev, u32 cmd, 864 u32 addr, u8 *p_buf, u32 len); 865 866 /** 867 * @brief Put file begin 868 * 869 * @param p_dev 870 * @param addr - nvm offset 871 * 872 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful. 873 */ 874 enum _ecore_status_t ecore_mcp_nvm_put_file_begin(struct ecore_dev *p_dev, 875 u32 addr); 876 877 /** 878 * @brief Delete file 879 * 880 * @param p_dev 881 * @param addr - nvm offset 882 * 883 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful. 884 */ 885 enum _ecore_status_t ecore_mcp_nvm_del_file(struct ecore_dev *p_dev, 886 u32 addr); 887 888 /** 889 * @brief Check latest response 890 * 891 * @param p_dev 892 * @param p_buf - nvm write buffer 893 * 894 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful. 895 */ 896 enum _ecore_status_t ecore_mcp_nvm_resp(struct ecore_dev *p_dev, u8 *p_buf); 897 898 /** 899 * @brief Read from phy 900 * 901 * @param p_dev 902 * @param addr - nvm offset 903 * @param cmd - nvm command 904 * @param p_buf - nvm read buffer 905 * @param len - buffer len 906 * 907 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful. 908 */ 909 enum _ecore_status_t ecore_mcp_phy_read(struct ecore_dev *p_dev, u32 cmd, 910 u32 addr, u8 *p_buf, u32 len); 911 912 /** 913 * @brief Read from nvm 914 * 915 * @param p_dev 916 * @param addr - nvm offset 917 * @param p_buf - nvm read buffer 918 * @param len - buffer len 919 * 920 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful. 921 */ 922 enum _ecore_status_t ecore_mcp_nvm_read(struct ecore_dev *p_dev, u32 addr, 923 u8 *p_buf, u32 len); 924 925 /** 926 * @brief - Sends an NVM write command request to the MFW with 927 * payload. 928 * 929 * @param p_hwfn 930 * @param p_ptt 931 * @param cmd - Command: Either DRV_MSG_CODE_NVM_WRITE_NVRAM or 932 * DRV_MSG_CODE_NVM_PUT_FILE_DATA 933 * @param param - [0:23] - Offset [24:31] - Size 934 * @param o_mcp_resp - MCP response 935 * @param o_mcp_param - MCP response param 936 * @param i_txn_size - Buffer size 937 * @param i_buf - Pointer to the buffer 938 * 939 * @param return ECORE_SUCCESS upon success. 940 */ 941 enum _ecore_status_t ecore_mcp_nvm_wr_cmd(struct ecore_hwfn *p_hwfn, 942 struct ecore_ptt *p_ptt, 943 u32 cmd, 944 u32 param, 945 u32 *o_mcp_resp, 946 u32 *o_mcp_param, 947 u32 i_txn_size, 948 u32 *i_buf); 949 950 /** 951 * @brief - Sends an NVM read command request to the MFW to get 952 * a buffer. 953 * 954 * @param p_hwfn 955 * @param p_ptt 956 * @param cmd - Command: DRV_MSG_CODE_NVM_GET_FILE_DATA or 957 * DRV_MSG_CODE_NVM_READ_NVRAM commands 958 * @param param - [0:23] - Offset [24:31] - Size 959 * @param o_mcp_resp - MCP response 960 * @param o_mcp_param - MCP response param 961 * @param o_txn_size - Buffer size output 962 * @param o_buf - Pointer to the buffer returned by the MFW. 963 * 964 * @param return ECORE_SUCCESS upon success. 965 */ 966 enum _ecore_status_t ecore_mcp_nvm_rd_cmd(struct ecore_hwfn *p_hwfn, 967 struct ecore_ptt *p_ptt, 968 u32 cmd, 969 u32 param, 970 u32 *o_mcp_resp, 971 u32 *o_mcp_param, 972 u32 *o_txn_size, 973 u32 *o_buf); 974 975 /** 976 * @brief Read from sfp 977 * 978 * @param p_hwfn - hw function 979 * @param p_ptt - PTT required for register access 980 * @param port - transceiver port 981 * @param addr - I2C address 982 * @param offset - offset in sfp 983 * @param len - buffer length 984 * @param p_buf - buffer to read into 985 * 986 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful. 987 */ 988 enum _ecore_status_t ecore_mcp_phy_sfp_read(struct ecore_hwfn *p_hwfn, 989 struct ecore_ptt *p_ptt, 990 u32 port, u32 addr, u32 offset, 991 u32 len, u8 *p_buf); 992 993 /** 994 * @brief Write to sfp 995 * 996 * @param p_hwfn - hw function 997 * @param p_ptt - PTT required for register access 998 * @param port - transceiver port 999 * @param addr - I2C address 1000 * @param offset - offset in sfp 1001 * @param len - buffer length 1002 * @param p_buf - buffer to write from 1003 * 1004 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful. 1005 */ 1006 enum _ecore_status_t ecore_mcp_phy_sfp_write(struct ecore_hwfn *p_hwfn, 1007 struct ecore_ptt *p_ptt, 1008 u32 port, u32 addr, u32 offset, 1009 u32 len, u8 *p_buf); 1010 1011 /** 1012 * @brief Gpio read 1013 * 1014 * @param p_hwfn - hw function 1015 * @param p_ptt - PTT required for register access 1016 * @param gpio - gpio number 1017 * @param gpio_val - value read from gpio 1018 * 1019 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful. 1020 */ 1021 enum _ecore_status_t ecore_mcp_gpio_read(struct ecore_hwfn *p_hwfn, 1022 struct ecore_ptt *p_ptt, 1023 u16 gpio, u32 *gpio_val); 1024 1025 /** 1026 * @brief Gpio write 1027 * 1028 * @param p_hwfn - hw function 1029 * @param p_ptt - PTT required for register access 1030 * @param gpio - gpio number 1031 * @param gpio_val - value to write to gpio 1032 * 1033 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful. 1034 */ 1035 enum _ecore_status_t ecore_mcp_gpio_write(struct ecore_hwfn *p_hwfn, 1036 struct ecore_ptt *p_ptt, 1037 u16 gpio, u16 gpio_val); 1038 1039 /** 1040 * @brief Gpio get information 1041 * 1042 * @param p_hwfn - hw function 1043 * @param p_ptt - PTT required for register access 1044 * @param gpio - gpio number 1045 * @param gpio_direction - gpio is output (0) or input (1) 1046 * @param gpio_ctrl - gpio control is uninitialized (0), 1047 * path 0 (1), path 1 (2) or shared(3) 1048 * 1049 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful. 1050 */ 1051 enum _ecore_status_t ecore_mcp_gpio_info(struct ecore_hwfn *p_hwfn, 1052 struct ecore_ptt *p_ptt, 1053 u16 gpio, u32 *gpio_direction, 1054 u32 *gpio_ctrl); 1055 1056 /** 1057 * @brief Bist register test 1058 * 1059 * @param p_hwfn - hw function 1060 * @param p_ptt - PTT required for register access 1061 * 1062 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful. 1063 */ 1064 enum _ecore_status_t ecore_mcp_bist_register_test(struct ecore_hwfn *p_hwfn, 1065 struct ecore_ptt *p_ptt); 1066 1067 /** 1068 * @brief Bist clock test 1069 * 1070 * @param p_hwfn - hw function 1071 * @param p_ptt - PTT required for register access 1072 * 1073 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful. 1074 */ 1075 enum _ecore_status_t ecore_mcp_bist_clock_test(struct ecore_hwfn *p_hwfn, 1076 struct ecore_ptt *p_ptt); 1077 1078 /** 1079 * @brief Bist nvm test - get number of images 1080 * 1081 * @param p_hwfn - hw function 1082 * @param p_ptt - PTT required for register access 1083 * @param num_images - number of images if operation was 1084 * successful. 0 if not. 1085 * 1086 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful. 1087 */ 1088 enum _ecore_status_t ecore_mcp_bist_nvm_test_get_num_images( 1089 struct ecore_hwfn *p_hwfn, 1090 struct ecore_ptt *p_ptt, 1091 u32 *num_images); 1092 1093 /** 1094 * @brief Bist nvm test - get image attributes by index 1095 * 1096 * @param p_hwfn - hw function 1097 * @param p_ptt - PTT required for register access 1098 * @param p_image_att - Attributes of image 1099 * @param image_index - Index of image to get information for 1100 * 1101 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful. 1102 */ 1103 enum _ecore_status_t ecore_mcp_bist_nvm_test_get_image_att( 1104 struct ecore_hwfn *p_hwfn, 1105 struct ecore_ptt *p_ptt, 1106 struct bist_nvm_image_att *p_image_att, 1107 u32 image_index); 1108 1109 /** 1110 * @brief ecore_mcp_get_temperature_info - get the status of the temperature 1111 * sensors 1112 * 1113 * @param p_hwfn - hw function 1114 * @param p_ptt - PTT required for register access 1115 * @param p_temp_status - A pointer to an ecore_temperature_info structure to 1116 * be filled with the temperature data 1117 * 1118 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful. 1119 */ 1120 enum _ecore_status_t 1121 ecore_mcp_get_temperature_info(struct ecore_hwfn *p_hwfn, 1122 struct ecore_ptt *p_ptt, 1123 struct ecore_temperature_info *p_temp_info); 1124 1125 /** 1126 * @brief Get MBA versions - get MBA sub images versions 1127 * 1128 * @param p_hwfn - hw function 1129 * @param p_ptt - PTT required for register access 1130 * @param p_mba_vers - MBA versions array to fill 1131 * 1132 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful. 1133 */ 1134 enum _ecore_status_t ecore_mcp_get_mba_versions( 1135 struct ecore_hwfn *p_hwfn, 1136 struct ecore_ptt *p_ptt, 1137 struct ecore_mba_vers *p_mba_vers); 1138 1139 /** 1140 * @brief Count memory ecc events 1141 * 1142 * @param p_hwfn - hw function 1143 * @param p_ptt - PTT required for register access 1144 * @param num_events - number of memory ecc events 1145 * 1146 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful. 1147 */ 1148 enum _ecore_status_t ecore_mcp_mem_ecc_events(struct ecore_hwfn *p_hwfn, 1149 struct ecore_ptt *p_ptt, 1150 u64 *num_events); 1151 1152 struct ecore_mdump_info { 1153 u32 reason; 1154 u32 version; 1155 u32 config; 1156 u32 epoch; 1157 u32 num_of_logs; 1158 u32 valid_logs; 1159 }; 1160 1161 /** 1162 * @brief - Gets the MFW crash dump configuration and logs info. 1163 * 1164 * @param p_hwfn 1165 * @param p_ptt 1166 * @param p_mdump_info 1167 * 1168 * @param return ECORE_SUCCESS upon success. 1169 */ 1170 enum _ecore_status_t 1171 ecore_mcp_mdump_get_info(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt, 1172 struct ecore_mdump_info *p_mdump_info); 1173 1174 /** 1175 * @brief - Clears the MFW crash dump logs. 1176 * 1177 * @param p_hwfn 1178 * @param p_ptt 1179 * 1180 * @param return ECORE_SUCCESS upon success. 1181 */ 1182 enum _ecore_status_t ecore_mcp_mdump_clear_logs(struct ecore_hwfn *p_hwfn, 1183 struct ecore_ptt *p_ptt); 1184 1185 /** 1186 * @brief - Clear the mdump retained data. 1187 * 1188 * @param p_hwfn 1189 * @param p_ptt 1190 * 1191 * @param return ECORE_SUCCESS upon success. 1192 */ 1193 enum _ecore_status_t ecore_mcp_mdump_clr_retain(struct ecore_hwfn *p_hwfn, 1194 struct ecore_ptt *p_ptt); 1195 1196 /** 1197 * @brief - Processes the TLV request from MFW i.e., get the required TLV info 1198 * from the ecore client and send it to the MFW. 1199 * 1200 * @param p_hwfn 1201 * @param p_ptt 1202 * 1203 * @param return ECORE_SUCCESS upon success. 1204 */ 1205 enum _ecore_status_t ecore_mfw_process_tlv_req(struct ecore_hwfn *p_hwfn, 1206 struct ecore_ptt *p_ptt); 1207 1208 1209 /** 1210 * @brief - Return whether management firmware support smart AN 1211 * 1212 * @param p_hwfn 1213 * 1214 * @return bool - true iff feature is supported. 1215 */ 1216 bool ecore_mcp_is_smart_an_supported(struct ecore_hwfn *p_hwfn); 1217 #endif 1218