1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright (c) 2016 - 2018 Cavium Inc. 3 * All rights reserved. 4 * www.cavium.com 5 */ 6 7 #ifndef __ECORE_MCP_API_H__ 8 #define __ECORE_MCP_API_H__ 9 10 #include "ecore_status.h" 11 12 struct ecore_mcp_link_speed_params { 13 bool autoneg; 14 u32 advertised_speeds; /* bitmask of DRV_SPEED_CAPABILITY */ 15 u32 forced_speed; /* In Mb/s */ 16 }; 17 18 struct ecore_mcp_link_pause_params { 19 bool autoneg; 20 bool forced_rx; 21 bool forced_tx; 22 }; 23 24 enum ecore_mcp_eee_mode { 25 ECORE_MCP_EEE_DISABLED, 26 ECORE_MCP_EEE_ENABLED, 27 ECORE_MCP_EEE_UNSUPPORTED 28 }; 29 30 struct ecore_link_eee_params { 31 u32 tx_lpi_timer; 32 #define ECORE_EEE_1G_ADV (1 << 0) 33 #define ECORE_EEE_10G_ADV (1 << 1) 34 /* Capabilities are represented using ECORE_EEE_*_ADV values */ 35 u8 adv_caps; 36 u8 lp_adv_caps; 37 bool enable; 38 bool tx_lpi_enable; 39 }; 40 41 struct ecore_mcp_link_params { 42 struct ecore_mcp_link_speed_params speed; 43 struct ecore_mcp_link_pause_params pause; 44 u32 loopback_mode; /* in PMM_LOOPBACK values */ 45 struct ecore_link_eee_params eee; 46 }; 47 48 struct ecore_mcp_link_capabilities { 49 u32 speed_capabilities; 50 bool default_speed_autoneg; /* In Mb/s */ 51 u32 default_speed; /* In Mb/s */ 52 enum ecore_mcp_eee_mode default_eee; 53 u32 eee_lpi_timer; 54 u8 eee_speed_caps; 55 }; 56 57 struct ecore_mcp_link_state { 58 bool link_up; 59 60 u32 min_pf_rate; /* In Mb/s */ 61 62 /* Actual link speed in Mb/s */ 63 u32 line_speed; 64 65 /* PF max speed in MB/s, deduced from line_speed 66 * according to PF max bandwidth configuration. 67 */ 68 u32 speed; 69 bool full_duplex; 70 71 bool an; 72 bool an_complete; 73 bool parallel_detection; 74 bool pfc_enabled; 75 76 #define ECORE_LINK_PARTNER_SPEED_1G_HD (1 << 0) 77 #define ECORE_LINK_PARTNER_SPEED_1G_FD (1 << 1) 78 #define ECORE_LINK_PARTNER_SPEED_10G (1 << 2) 79 #define ECORE_LINK_PARTNER_SPEED_20G (1 << 3) 80 #define ECORE_LINK_PARTNER_SPEED_25G (1 << 4) 81 #define ECORE_LINK_PARTNER_SPEED_40G (1 << 5) 82 #define ECORE_LINK_PARTNER_SPEED_50G (1 << 6) 83 #define ECORE_LINK_PARTNER_SPEED_100G (1 << 7) 84 u32 partner_adv_speed; 85 86 bool partner_tx_flow_ctrl_en; 87 bool partner_rx_flow_ctrl_en; 88 89 #define ECORE_LINK_PARTNER_SYMMETRIC_PAUSE (1) 90 #define ECORE_LINK_PARTNER_ASYMMETRIC_PAUSE (2) 91 #define ECORE_LINK_PARTNER_BOTH_PAUSE (3) 92 u8 partner_adv_pause; 93 94 bool sfp_tx_fault; 95 96 bool eee_active; 97 u8 eee_adv_caps; 98 u8 eee_lp_adv_caps; 99 }; 100 101 struct ecore_mcp_function_info { 102 u8 pause_on_host; 103 104 enum ecore_pci_personality protocol; 105 106 u8 bandwidth_min; 107 u8 bandwidth_max; 108 109 u8 mac[ETH_ALEN]; 110 111 u64 wwn_port; 112 u64 wwn_node; 113 114 #define ECORE_MCP_VLAN_UNSET (0xffff) 115 u16 ovlan; 116 117 u16 mtu; 118 }; 119 120 #ifndef __EXTRACT__LINUX__ 121 enum ecore_nvm_images { 122 ECORE_NVM_IMAGE_ISCSI_CFG, 123 ECORE_NVM_IMAGE_FCOE_CFG, 124 ECORE_NVM_IMAGE_MDUMP, 125 ECORE_NVM_IMAGE_NVM_CFG1, 126 ECORE_NVM_IMAGE_DEFAULT_CFG, 127 ECORE_NVM_IMAGE_NVM_META, 128 }; 129 #endif 130 131 struct ecore_mcp_drv_version { 132 u32 version; 133 u8 name[MCP_DRV_VER_STR_SIZE - 4]; 134 }; 135 136 struct ecore_mcp_lan_stats { 137 u64 ucast_rx_pkts; 138 u64 ucast_tx_pkts; 139 u32 fcs_err; 140 }; 141 142 #ifndef ECORE_PROTO_STATS 143 #define ECORE_PROTO_STATS 144 struct ecore_mcp_fcoe_stats { 145 u64 rx_pkts; 146 u64 tx_pkts; 147 u32 fcs_err; 148 u32 login_failure; 149 }; 150 151 struct ecore_mcp_iscsi_stats { 152 u64 rx_pdus; 153 u64 tx_pdus; 154 u64 rx_bytes; 155 u64 tx_bytes; 156 }; 157 158 struct ecore_mcp_rdma_stats { 159 u64 rx_pkts; 160 u64 tx_pkts; 161 u64 rx_bytes; 162 u64 tx_byts; 163 }; 164 165 enum ecore_mcp_protocol_type { 166 ECORE_MCP_LAN_STATS, 167 ECORE_MCP_FCOE_STATS, 168 ECORE_MCP_ISCSI_STATS, 169 ECORE_MCP_RDMA_STATS 170 }; 171 172 union ecore_mcp_protocol_stats { 173 struct ecore_mcp_lan_stats lan_stats; 174 struct ecore_mcp_fcoe_stats fcoe_stats; 175 struct ecore_mcp_iscsi_stats iscsi_stats; 176 struct ecore_mcp_rdma_stats rdma_stats; 177 }; 178 #endif 179 180 enum ecore_ov_client { 181 ECORE_OV_CLIENT_DRV, 182 ECORE_OV_CLIENT_USER, 183 ECORE_OV_CLIENT_VENDOR_SPEC 184 }; 185 186 enum ecore_ov_driver_state { 187 ECORE_OV_DRIVER_STATE_NOT_LOADED, 188 ECORE_OV_DRIVER_STATE_DISABLED, 189 ECORE_OV_DRIVER_STATE_ACTIVE 190 }; 191 192 enum ecore_ov_eswitch { 193 ECORE_OV_ESWITCH_NONE, 194 ECORE_OV_ESWITCH_VEB, 195 ECORE_OV_ESWITCH_VEPA 196 }; 197 198 #define ECORE_MAX_NPIV_ENTRIES 128 199 #define ECORE_WWN_SIZE 8 200 struct ecore_fc_npiv_tbl { 201 u32 count; 202 u8 wwpn[ECORE_MAX_NPIV_ENTRIES][ECORE_WWN_SIZE]; 203 u8 wwnn[ECORE_MAX_NPIV_ENTRIES][ECORE_WWN_SIZE]; 204 }; 205 206 #ifndef __EXTRACT__LINUX__ 207 enum ecore_led_mode { 208 ECORE_LED_MODE_OFF, 209 ECORE_LED_MODE_ON, 210 ECORE_LED_MODE_RESTORE 211 }; 212 #endif 213 214 struct ecore_temperature_sensor { 215 u8 sensor_location; 216 u8 threshold_high; 217 u8 critical; 218 u8 current_temp; 219 }; 220 221 #define ECORE_MAX_NUM_OF_SENSORS 7 222 struct ecore_temperature_info { 223 u32 num_sensors; 224 struct ecore_temperature_sensor sensors[ECORE_MAX_NUM_OF_SENSORS]; 225 }; 226 227 enum ecore_mba_img_idx { 228 ECORE_MBA_LEGACY_IDX, 229 ECORE_MBA_PCI3CLP_IDX, 230 ECORE_MBA_PCI3_IDX, 231 ECORE_MBA_FCODE_IDX, 232 ECORE_EFI_X86_IDX, 233 ECORE_EFI_IPF_IDX, 234 ECORE_EFI_EBC_IDX, 235 ECORE_EFI_X64_IDX, 236 ECORE_MAX_NUM_OF_ROMIMG 237 }; 238 239 struct ecore_mba_vers { 240 u32 mba_vers[ECORE_MAX_NUM_OF_ROMIMG]; 241 }; 242 243 enum ecore_mfw_tlv_type { 244 ECORE_MFW_TLV_GENERIC = 0x1, /* Core driver TLVs */ 245 ECORE_MFW_TLV_ETH = 0x2, /* L2 driver TLVs */ 246 ECORE_MFW_TLV_FCOE = 0x4, /* FCoE protocol TLVs */ 247 ECORE_MFW_TLV_ISCSI = 0x8, /* SCSI protocol TLVs */ 248 ECORE_MFW_TLV_MAX = 0x16, 249 }; 250 251 struct ecore_mfw_tlv_generic { 252 u16 feat_flags; 253 bool feat_flags_set; 254 u64 local_mac; 255 bool local_mac_set; 256 u64 additional_mac1; 257 bool additional_mac1_set; 258 u64 additional_mac2; 259 bool additional_mac2_set; 260 u8 drv_state; 261 bool drv_state_set; 262 u8 pxe_progress; 263 bool pxe_progress_set; 264 u64 rx_frames; 265 bool rx_frames_set; 266 u64 rx_bytes; 267 bool rx_bytes_set; 268 u64 tx_frames; 269 bool tx_frames_set; 270 u64 tx_bytes; 271 bool tx_bytes_set; 272 }; 273 274 struct ecore_mfw_tlv_eth { 275 u16 lso_maxoff_size; 276 bool lso_maxoff_size_set; 277 u16 lso_minseg_size; 278 bool lso_minseg_size_set; 279 u8 prom_mode; 280 bool prom_mode_set; 281 u16 tx_descr_size; 282 bool tx_descr_size_set; 283 u16 rx_descr_size; 284 bool rx_descr_size_set; 285 u16 netq_count; 286 bool netq_count_set; 287 u32 tcp4_offloads; 288 bool tcp4_offloads_set; 289 u32 tcp6_offloads; 290 bool tcp6_offloads_set; 291 u16 tx_descr_qdepth; 292 bool tx_descr_qdepth_set; 293 u16 rx_descr_qdepth; 294 bool rx_descr_qdepth_set; 295 u8 iov_offload; 296 bool iov_offload_set; 297 u8 txqs_empty; 298 bool txqs_empty_set; 299 u8 rxqs_empty; 300 bool rxqs_empty_set; 301 u8 num_txqs_full; 302 bool num_txqs_full_set; 303 u8 num_rxqs_full; 304 bool num_rxqs_full_set; 305 }; 306 307 struct ecore_mfw_tlv_fcoe { 308 u8 scsi_timeout; 309 bool scsi_timeout_set; 310 u32 rt_tov; 311 bool rt_tov_set; 312 u32 ra_tov; 313 bool ra_tov_set; 314 u32 ed_tov; 315 bool ed_tov_set; 316 u32 cr_tov; 317 bool cr_tov_set; 318 u8 boot_type; 319 bool boot_type_set; 320 u8 npiv_state; 321 bool npiv_state_set; 322 u32 num_npiv_ids; 323 bool num_npiv_ids_set; 324 u8 switch_name[8]; 325 bool switch_name_set; 326 u16 switch_portnum; 327 bool switch_portnum_set; 328 u8 switch_portid[3]; 329 bool switch_portid_set; 330 u8 vendor_name[8]; 331 bool vendor_name_set; 332 u8 switch_model[8]; 333 bool switch_model_set; 334 u8 switch_fw_version[8]; 335 bool switch_fw_version_set; 336 u8 qos_pri; 337 bool qos_pri_set; 338 u8 port_alias[3]; 339 bool port_alias_set; 340 u8 port_state; 341 bool port_state_set; 342 u16 fip_tx_descr_size; 343 bool fip_tx_descr_size_set; 344 u16 fip_rx_descr_size; 345 bool fip_rx_descr_size_set; 346 u16 link_failures; 347 bool link_failures_set; 348 u8 fcoe_boot_progress; 349 bool fcoe_boot_progress_set; 350 u64 rx_bcast; 351 bool rx_bcast_set; 352 u64 tx_bcast; 353 bool tx_bcast_set; 354 u16 fcoe_txq_depth; 355 bool fcoe_txq_depth_set; 356 u16 fcoe_rxq_depth; 357 bool fcoe_rxq_depth_set; 358 u64 fcoe_rx_frames; 359 bool fcoe_rx_frames_set; 360 u64 fcoe_rx_bytes; 361 bool fcoe_rx_bytes_set; 362 u64 fcoe_tx_frames; 363 bool fcoe_tx_frames_set; 364 u64 fcoe_tx_bytes; 365 bool fcoe_tx_bytes_set; 366 u16 crc_count; 367 bool crc_count_set; 368 u32 crc_err_src_fcid[5]; 369 bool crc_err_src_fcid_set[5]; 370 u8 crc_err_tstamp[5][14]; 371 bool crc_err_tstamp_set[5]; 372 u16 losync_err; 373 bool losync_err_set; 374 u16 losig_err; 375 bool losig_err_set; 376 u16 primtive_err; 377 bool primtive_err_set; 378 u16 disparity_err; 379 bool disparity_err_set; 380 u16 code_violation_err; 381 bool code_violation_err_set; 382 u32 flogi_param[4]; 383 bool flogi_param_set[4]; 384 u8 flogi_tstamp[14]; 385 bool flogi_tstamp_set; 386 u32 flogi_acc_param[4]; 387 bool flogi_acc_param_set[4]; 388 u8 flogi_acc_tstamp[14]; 389 bool flogi_acc_tstamp_set; 390 u32 flogi_rjt; 391 bool flogi_rjt_set; 392 u8 flogi_rjt_tstamp[14]; 393 bool flogi_rjt_tstamp_set; 394 u32 fdiscs; 395 bool fdiscs_set; 396 u8 fdisc_acc; 397 bool fdisc_acc_set; 398 u8 fdisc_rjt; 399 bool fdisc_rjt_set; 400 u8 plogi; 401 bool plogi_set; 402 u8 plogi_acc; 403 bool plogi_acc_set; 404 u8 plogi_rjt; 405 bool plogi_rjt_set; 406 u32 plogi_dst_fcid[5]; 407 bool plogi_dst_fcid_set[5]; 408 u8 plogi_tstamp[5][14]; 409 bool plogi_tstamp_set[5]; 410 u32 plogi_acc_src_fcid[5]; 411 bool plogi_acc_src_fcid_set[5]; 412 u8 plogi_acc_tstamp[5][14]; 413 bool plogi_acc_tstamp_set[5]; 414 u8 tx_plogos; 415 bool tx_plogos_set; 416 u8 plogo_acc; 417 bool plogo_acc_set; 418 u8 plogo_rjt; 419 bool plogo_rjt_set; 420 u32 plogo_src_fcid[5]; 421 bool plogo_src_fcid_set[5]; 422 u8 plogo_tstamp[5][14]; 423 bool plogo_tstamp_set[5]; 424 u8 rx_logos; 425 bool rx_logos_set; 426 u8 tx_accs; 427 bool tx_accs_set; 428 u8 tx_prlis; 429 bool tx_prlis_set; 430 u8 rx_accs; 431 bool rx_accs_set; 432 u8 tx_abts; 433 bool tx_abts_set; 434 u8 rx_abts_acc; 435 bool rx_abts_acc_set; 436 u8 rx_abts_rjt; 437 bool rx_abts_rjt_set; 438 u32 abts_dst_fcid[5]; 439 bool abts_dst_fcid_set[5]; 440 u8 abts_tstamp[5][14]; 441 bool abts_tstamp_set[5]; 442 u8 rx_rscn; 443 bool rx_rscn_set; 444 u32 rx_rscn_nport[4]; 445 bool rx_rscn_nport_set[4]; 446 u8 tx_lun_rst; 447 bool tx_lun_rst_set; 448 u8 abort_task_sets; 449 bool abort_task_sets_set; 450 u8 tx_tprlos; 451 bool tx_tprlos_set; 452 u8 tx_nos; 453 bool tx_nos_set; 454 u8 rx_nos; 455 bool rx_nos_set; 456 u8 ols; 457 bool ols_set; 458 u8 lr; 459 bool lr_set; 460 u8 lrr; 461 bool lrr_set; 462 u8 tx_lip; 463 bool tx_lip_set; 464 u8 rx_lip; 465 bool rx_lip_set; 466 u8 eofa; 467 bool eofa_set; 468 u8 eofni; 469 bool eofni_set; 470 u8 scsi_chks; 471 bool scsi_chks_set; 472 u8 scsi_cond_met; 473 bool scsi_cond_met_set; 474 u8 scsi_busy; 475 bool scsi_busy_set; 476 u8 scsi_inter; 477 bool scsi_inter_set; 478 u8 scsi_inter_cond_met; 479 bool scsi_inter_cond_met_set; 480 u8 scsi_rsv_conflicts; 481 bool scsi_rsv_conflicts_set; 482 u8 scsi_tsk_full; 483 bool scsi_tsk_full_set; 484 u8 scsi_aca_active; 485 bool scsi_aca_active_set; 486 u8 scsi_tsk_abort; 487 bool scsi_tsk_abort_set; 488 u32 scsi_rx_chk[5]; 489 bool scsi_rx_chk_set[5]; 490 u8 scsi_chk_tstamp[5][14]; 491 bool scsi_chk_tstamp_set[5]; 492 }; 493 494 struct ecore_mfw_tlv_iscsi { 495 u8 target_llmnr; 496 bool target_llmnr_set; 497 u8 header_digest; 498 bool header_digest_set; 499 u8 data_digest; 500 bool data_digest_set; 501 u8 auth_method; 502 bool auth_method_set; 503 u16 boot_taget_portal; 504 bool boot_taget_portal_set; 505 u16 frame_size; 506 bool frame_size_set; 507 u16 tx_desc_size; 508 bool tx_desc_size_set; 509 u16 rx_desc_size; 510 bool rx_desc_size_set; 511 u8 boot_progress; 512 bool boot_progress_set; 513 u16 tx_desc_qdepth; 514 bool tx_desc_qdepth_set; 515 u16 rx_desc_qdepth; 516 bool rx_desc_qdepth_set; 517 u64 rx_frames; 518 bool rx_frames_set; 519 u64 rx_bytes; 520 bool rx_bytes_set; 521 u64 tx_frames; 522 bool tx_frames_set; 523 u64 tx_bytes; 524 bool tx_bytes_set; 525 }; 526 527 union ecore_mfw_tlv_data { 528 struct ecore_mfw_tlv_generic generic; 529 struct ecore_mfw_tlv_eth eth; 530 struct ecore_mfw_tlv_fcoe fcoe; 531 struct ecore_mfw_tlv_iscsi iscsi; 532 }; 533 534 enum ecore_hw_info_change { 535 ECORE_HW_INFO_CHANGE_OVLAN, 536 }; 537 538 /** 539 * @brief - returns the link params of the hw function 540 * 541 * @param p_hwfn 542 * 543 * @returns pointer to link params 544 */ 545 struct ecore_mcp_link_params *ecore_mcp_get_link_params(struct ecore_hwfn *); 546 547 /** 548 * @brief - return the link state of the hw function 549 * 550 * @param p_hwfn 551 * 552 * @returns pointer to link state 553 */ 554 struct ecore_mcp_link_state *ecore_mcp_get_link_state(struct ecore_hwfn *); 555 556 /** 557 * @brief - return the link capabilities of the hw function 558 * 559 * @param p_hwfn 560 * 561 * @returns pointer to link capabilities 562 */ 563 struct ecore_mcp_link_capabilities 564 *ecore_mcp_get_link_capabilities(struct ecore_hwfn *p_hwfn); 565 566 /** 567 * @brief Request the MFW to set the link according to 'link_input'. 568 * 569 * @param p_hwfn 570 * @param p_ptt 571 * @param b_up - raise link if `true'. Reset link if `false'. 572 * 573 * @return enum _ecore_status_t 574 */ 575 enum _ecore_status_t ecore_mcp_set_link(struct ecore_hwfn *p_hwfn, 576 struct ecore_ptt *p_ptt, 577 bool b_up); 578 579 /** 580 * @brief Get the management firmware version value 581 * 582 * @param p_hwfn 583 * @param p_ptt 584 * @param p_mfw_ver - mfw version value 585 * @param p_running_bundle_id - image id in nvram; Optional. 586 * 587 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful. 588 */ 589 enum _ecore_status_t ecore_mcp_get_mfw_ver(struct ecore_hwfn *p_hwfn, 590 struct ecore_ptt *p_ptt, 591 u32 *p_mfw_ver, 592 u32 *p_running_bundle_id); 593 594 /** 595 * @brief Get the MBI version value 596 * 597 * @param p_hwfn 598 * @param p_ptt 599 * @param p_mbi_ver - A pointer to a variable to be filled with the MBI version. 600 * 601 * @return int - 0 - operation was successful. 602 */ 603 int ecore_mcp_get_mbi_ver(struct ecore_hwfn *p_hwfn, 604 struct ecore_ptt *p_ptt, u32 *p_mbi_ver); 605 606 /** 607 * @brief Get media type value of the port. 608 * 609 * @param p_dev - ecore dev pointer 610 * @param p_ptt 611 * @param mfw_ver - media type value 612 * 613 * @return enum _ecore_status_t - 614 * ECORE_SUCCESS - Operation was successful. 615 * ECORE_BUSY - Operation failed 616 */ 617 enum _ecore_status_t ecore_mcp_get_media_type(struct ecore_hwfn *p_hwfn, 618 struct ecore_ptt *p_ptt, 619 u32 *media_type); 620 621 /** 622 * @brief Get transceiver data of the port. 623 * 624 * @param p_dev - ecore dev pointer 625 * @param p_ptt 626 * @param p_transceiver_state - transceiver state. 627 * @param p_transceiver_type - media type value 628 * 629 * @return enum _ecore_status_t - 630 * ECORE_SUCCESS - Operation was successful. 631 * ECORE_BUSY - Operation failed 632 */ 633 enum _ecore_status_t ecore_mcp_get_transceiver_data(struct ecore_hwfn *p_hwfn, 634 struct ecore_ptt *p_ptt, 635 u32 *p_transceiver_state, 636 u32 *p_tranceiver_type); 637 638 /** 639 * @brief Get transceiver supported speed mask. 640 * 641 * @param p_dev - ecore dev pointer 642 * @param p_ptt 643 * @param p_speed_mask - Bit mask of all supported speeds. 644 * 645 * @return enum _ecore_status_t - 646 * ECORE_SUCCESS - Operation was successful. 647 * ECORE_BUSY - Operation failed 648 */ 649 650 enum _ecore_status_t ecore_mcp_trans_speed_mask(struct ecore_hwfn *p_hwfn, 651 struct ecore_ptt *p_ptt, 652 u32 *p_speed_mask); 653 654 /** 655 * @brief Get board configuration. 656 * 657 * @param p_dev - ecore dev pointer 658 * @param p_ptt 659 * @param p_board_config - Board config. 660 * 661 * @return enum _ecore_status_t - 662 * ECORE_SUCCESS - Operation was successful. 663 * ECORE_BUSY - Operation failed 664 */ 665 enum _ecore_status_t ecore_mcp_get_board_config(struct ecore_hwfn *p_hwfn, 666 struct ecore_ptt *p_ptt, 667 u32 *p_board_config); 668 669 /** 670 * @brief - Sends a command to the MCP mailbox. 671 * 672 * @param p_hwfn - hw function 673 * @param p_ptt - PTT required for register access 674 * @param cmd - command to be sent to the MCP 675 * @param param - Optional param 676 * @param o_mcp_resp - The MCP response code (exclude sequence) 677 * @param o_mcp_param - Optional parameter provided by the MCP response 678 * 679 * @return enum _ecore_status_t - 680 * ECORE_SUCCESS - operation was successful 681 * ECORE_BUSY - operation failed 682 */ 683 enum _ecore_status_t ecore_mcp_cmd(struct ecore_hwfn *p_hwfn, 684 struct ecore_ptt *p_ptt, u32 cmd, u32 param, 685 u32 *o_mcp_resp, u32 *o_mcp_param); 686 687 /** 688 * @brief - drains the nig, allowing completion to pass in case of pauses. 689 * (Should be called only from sleepable context) 690 * 691 * @param p_hwfn 692 * @param p_ptt 693 */ 694 enum _ecore_status_t ecore_mcp_drain(struct ecore_hwfn *p_hwfn, 695 struct ecore_ptt *p_ptt); 696 697 #ifndef LINUX_REMOVE 698 /** 699 * @brief - return the mcp function info of the hw function 700 * 701 * @param p_hwfn 702 * 703 * @returns pointer to mcp function info 704 */ 705 const struct ecore_mcp_function_info 706 *ecore_mcp_get_function_info(struct ecore_hwfn *p_hwfn); 707 #endif 708 709 #ifndef LINUX_REMOVE 710 /** 711 * @brief - count number of function with a matching personality on engine. 712 * 713 * @param p_hwfn 714 * @param p_ptt 715 * @param personalities - a bitmask of ecore_pci_personality values 716 * 717 * @returns the count of all devices on engine whose personality match one of 718 * the bitsmasks. 719 */ 720 int ecore_mcp_get_personality_cnt(struct ecore_hwfn *p_hwfn, 721 struct ecore_ptt *p_ptt, 722 u32 personalities); 723 #endif 724 725 /** 726 * @brief Get the flash size value 727 * 728 * @param p_hwfn 729 * @param p_ptt 730 * @param p_flash_size - flash size in bytes to be filled. 731 * 732 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful. 733 */ 734 enum _ecore_status_t ecore_mcp_get_flash_size(struct ecore_hwfn *p_hwfn, 735 struct ecore_ptt *p_ptt, 736 u32 *p_flash_size); 737 738 /** 739 * @brief Send driver version to MFW 740 * 741 * @param p_hwfn 742 * @param p_ptt 743 * @param version - Version value 744 * @param name - Protocol driver name 745 * 746 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful. 747 */ 748 enum _ecore_status_t 749 ecore_mcp_send_drv_version(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt, 750 struct ecore_mcp_drv_version *p_ver); 751 752 /** 753 * @brief Read the MFW process kill counter 754 * 755 * @param p_hwfn 756 * @param p_ptt 757 * 758 * @return u32 759 */ 760 u32 ecore_get_process_kill_counter(struct ecore_hwfn *p_hwfn, 761 struct ecore_ptt *p_ptt); 762 763 /** 764 * @brief Trigger a recovery process 765 * 766 * @param p_hwfn 767 * @param p_ptt 768 * 769 * @return enum _ecore_status_t 770 */ 771 enum _ecore_status_t ecore_start_recovery_process(struct ecore_hwfn *p_hwfn, 772 struct ecore_ptt *p_ptt); 773 774 /** 775 * @brief A recovery handler must call this function as its first step. 776 * It is assumed that the handler is not run from an interrupt context. 777 * 778 * @param p_dev 779 * @param p_ptt 780 * 781 * @return enum _ecore_status_t 782 */ 783 enum _ecore_status_t ecore_recovery_prolog(struct ecore_dev *p_dev); 784 785 /** 786 * @brief Notify MFW about the change in base device properties 787 * 788 * @param p_hwfn 789 * @param p_ptt 790 * @param client - ecore client type 791 * 792 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful. 793 */ 794 enum _ecore_status_t 795 ecore_mcp_ov_update_current_config(struct ecore_hwfn *p_hwfn, 796 struct ecore_ptt *p_ptt, 797 enum ecore_ov_client client); 798 799 /** 800 * @brief Notify MFW about the driver state 801 * 802 * @param p_hwfn 803 * @param p_ptt 804 * @param drv_state - Driver state 805 * 806 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful. 807 */ 808 enum _ecore_status_t 809 ecore_mcp_ov_update_driver_state(struct ecore_hwfn *p_hwfn, 810 struct ecore_ptt *p_ptt, 811 enum ecore_ov_driver_state drv_state); 812 813 /** 814 * @brief Read NPIV settings form the MFW 815 * 816 * @param p_hwfn 817 * @param p_ptt 818 * @param p_table - Array to hold the FC NPIV data. Client need allocate the 819 * required buffer. The field 'count' specifies number of NPIV 820 * entries. A value of 0 means the table was not populated. 821 * 822 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful. 823 */ 824 enum _ecore_status_t 825 ecore_mcp_ov_get_fc_npiv(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt, 826 struct ecore_fc_npiv_tbl *p_table); 827 828 /** 829 * @brief Send MTU size to MFW 830 * 831 * @param p_hwfn 832 * @param p_ptt 833 * @param mtu - MTU size 834 * 835 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful. 836 */ 837 enum _ecore_status_t ecore_mcp_ov_update_mtu(struct ecore_hwfn *p_hwfn, 838 struct ecore_ptt *p_ptt, u16 mtu); 839 840 /** 841 * @brief Send MAC address to MFW 842 * 843 * @param p_hwfn 844 * @param p_ptt 845 * @param mac - MAC address 846 * 847 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful. 848 */ 849 enum _ecore_status_t 850 ecore_mcp_ov_update_mac(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt, 851 u8 *mac); 852 853 /** 854 * @brief Send eswitch mode to MFW 855 * 856 * @param p_hwfn 857 * @param p_ptt 858 * @param eswitch - eswitch mode 859 * 860 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful. 861 */ 862 enum _ecore_status_t 863 ecore_mcp_ov_update_eswitch(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt, 864 enum ecore_ov_eswitch eswitch); 865 866 /** 867 * @brief Set LED status 868 * 869 * @param p_hwfn 870 * @param p_ptt 871 * @param mode - LED mode 872 * 873 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful. 874 */ 875 enum _ecore_status_t ecore_mcp_set_led(struct ecore_hwfn *p_hwfn, 876 struct ecore_ptt *p_ptt, 877 enum ecore_led_mode mode); 878 879 /** 880 * @brief Set secure mode 881 * 882 * @param p_dev 883 * @param addr - nvm offset 884 * 885 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful. 886 */ 887 enum _ecore_status_t ecore_mcp_nvm_set_secure_mode(struct ecore_dev *p_dev, 888 u32 addr); 889 890 /** 891 * @brief Write to phy 892 * 893 * @param p_dev 894 * @param addr - nvm offset 895 * @param cmd - nvm command 896 * @param p_buf - nvm write buffer 897 * @param len - buffer len 898 * 899 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful. 900 */ 901 enum _ecore_status_t ecore_mcp_phy_write(struct ecore_dev *p_dev, u32 cmd, 902 u32 addr, u8 *p_buf, u32 len); 903 904 /** 905 * @brief Write to nvm 906 * 907 * @param p_dev 908 * @param addr - nvm offset 909 * @param cmd - nvm command 910 * @param p_buf - nvm write buffer 911 * @param len - buffer len 912 * 913 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful. 914 */ 915 enum _ecore_status_t ecore_mcp_nvm_write(struct ecore_dev *p_dev, u32 cmd, 916 u32 addr, u8 *p_buf, u32 len); 917 918 /** 919 * @brief Put file begin 920 * 921 * @param p_dev 922 * @param addr - nvm offset 923 * 924 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful. 925 */ 926 enum _ecore_status_t ecore_mcp_nvm_put_file_begin(struct ecore_dev *p_dev, 927 u32 addr); 928 929 /** 930 * @brief Delete file 931 * 932 * @param p_dev 933 * @param addr - nvm offset 934 * 935 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful. 936 */ 937 enum _ecore_status_t ecore_mcp_nvm_del_file(struct ecore_dev *p_dev, 938 u32 addr); 939 940 /** 941 * @brief Check latest response 942 * 943 * @param p_dev 944 * @param p_buf - nvm write buffer 945 * 946 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful. 947 */ 948 enum _ecore_status_t ecore_mcp_nvm_resp(struct ecore_dev *p_dev, u8 *p_buf); 949 950 /** 951 * @brief Read from phy 952 * 953 * @param p_dev 954 * @param addr - nvm offset 955 * @param cmd - nvm command 956 * @param p_buf - nvm read buffer 957 * @param len - buffer len 958 * 959 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful. 960 */ 961 enum _ecore_status_t ecore_mcp_phy_read(struct ecore_dev *p_dev, u32 cmd, 962 u32 addr, u8 *p_buf, u32 *p_len); 963 964 /** 965 * @brief Read from nvm 966 * 967 * @param p_dev 968 * @param addr - nvm offset 969 * @param p_buf - nvm read buffer 970 * @param len - buffer len 971 * 972 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful. 973 */ 974 enum _ecore_status_t ecore_mcp_nvm_read(struct ecore_dev *p_dev, u32 addr, 975 u8 *p_buf, u32 len); 976 977 struct ecore_nvm_image_att { 978 u32 start_addr; 979 u32 length; 980 }; 981 982 /** 983 * @brief Allows reading a whole nvram image 984 * 985 * @param p_hwfn 986 * @param image_id - image to get attributes for 987 * @param p_image_att - image attributes structure into which to fill data 988 * 989 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful. 990 */ 991 enum _ecore_status_t 992 ecore_mcp_get_nvm_image_att(struct ecore_hwfn *p_hwfn, 993 enum ecore_nvm_images image_id, 994 struct ecore_nvm_image_att *p_image_att); 995 996 /** 997 * @brief Allows reading a whole nvram image 998 * 999 * @param p_hwfn 1000 * @param image_id - image requested for reading 1001 * @param p_buffer - allocated buffer into which to fill data 1002 * @param buffer_len - length of the allocated buffer. 1003 * 1004 * @return ECORE_SUCCESS if p_buffer now contains the nvram image. 1005 */ 1006 enum _ecore_status_t ecore_mcp_get_nvm_image(struct ecore_hwfn *p_hwfn, 1007 enum ecore_nvm_images image_id, 1008 u8 *p_buffer, u32 buffer_len); 1009 1010 /** 1011 * @brief - Sends an NVM write command request to the MFW with 1012 * payload. 1013 * 1014 * @param p_hwfn 1015 * @param p_ptt 1016 * @param cmd - Command: Either DRV_MSG_CODE_NVM_WRITE_NVRAM or 1017 * DRV_MSG_CODE_NVM_PUT_FILE_DATA 1018 * @param param - [0:23] - Offset [24:31] - Size 1019 * @param o_mcp_resp - MCP response 1020 * @param o_mcp_param - MCP response param 1021 * @param i_txn_size - Buffer size 1022 * @param i_buf - Pointer to the buffer 1023 * 1024 * @param return ECORE_SUCCESS upon success. 1025 */ 1026 enum _ecore_status_t ecore_mcp_nvm_wr_cmd(struct ecore_hwfn *p_hwfn, 1027 struct ecore_ptt *p_ptt, 1028 u32 cmd, 1029 u32 param, 1030 u32 *o_mcp_resp, 1031 u32 *o_mcp_param, 1032 u32 i_txn_size, 1033 u32 *i_buf); 1034 1035 /** 1036 * @brief - Sends an NVM read command request to the MFW to get 1037 * a buffer. 1038 * 1039 * @param p_hwfn 1040 * @param p_ptt 1041 * @param cmd - Command: DRV_MSG_CODE_NVM_GET_FILE_DATA or 1042 * DRV_MSG_CODE_NVM_READ_NVRAM commands 1043 * @param param - [0:23] - Offset [24:31] - Size 1044 * @param o_mcp_resp - MCP response 1045 * @param o_mcp_param - MCP response param 1046 * @param o_txn_size - Buffer size output 1047 * @param o_buf - Pointer to the buffer returned by the MFW. 1048 * 1049 * @param return ECORE_SUCCESS upon success. 1050 */ 1051 enum _ecore_status_t ecore_mcp_nvm_rd_cmd(struct ecore_hwfn *p_hwfn, 1052 struct ecore_ptt *p_ptt, 1053 u32 cmd, 1054 u32 param, 1055 u32 *o_mcp_resp, 1056 u32 *o_mcp_param, 1057 u32 *o_txn_size, 1058 u32 *o_buf); 1059 1060 /** 1061 * @brief Read from sfp 1062 * 1063 * @param p_hwfn - hw function 1064 * @param p_ptt - PTT required for register access 1065 * @param port - transceiver port 1066 * @param addr - I2C address 1067 * @param offset - offset in sfp 1068 * @param len - buffer length 1069 * @param p_buf - buffer to read into 1070 * 1071 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful. 1072 */ 1073 enum _ecore_status_t ecore_mcp_phy_sfp_read(struct ecore_hwfn *p_hwfn, 1074 struct ecore_ptt *p_ptt, 1075 u32 port, u32 addr, u32 offset, 1076 u32 len, u8 *p_buf); 1077 1078 /** 1079 * @brief Write to sfp 1080 * 1081 * @param p_hwfn - hw function 1082 * @param p_ptt - PTT required for register access 1083 * @param port - transceiver port 1084 * @param addr - I2C address 1085 * @param offset - offset in sfp 1086 * @param len - buffer length 1087 * @param p_buf - buffer to write from 1088 * 1089 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful. 1090 */ 1091 enum _ecore_status_t ecore_mcp_phy_sfp_write(struct ecore_hwfn *p_hwfn, 1092 struct ecore_ptt *p_ptt, 1093 u32 port, u32 addr, u32 offset, 1094 u32 len, u8 *p_buf); 1095 1096 /** 1097 * @brief Gpio read 1098 * 1099 * @param p_hwfn - hw function 1100 * @param p_ptt - PTT required for register access 1101 * @param gpio - gpio number 1102 * @param gpio_val - value read from gpio 1103 * 1104 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful. 1105 */ 1106 enum _ecore_status_t ecore_mcp_gpio_read(struct ecore_hwfn *p_hwfn, 1107 struct ecore_ptt *p_ptt, 1108 u16 gpio, u32 *gpio_val); 1109 1110 /** 1111 * @brief Gpio write 1112 * 1113 * @param p_hwfn - hw function 1114 * @param p_ptt - PTT required for register access 1115 * @param gpio - gpio number 1116 * @param gpio_val - value to write to gpio 1117 * 1118 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful. 1119 */ 1120 enum _ecore_status_t ecore_mcp_gpio_write(struct ecore_hwfn *p_hwfn, 1121 struct ecore_ptt *p_ptt, 1122 u16 gpio, u16 gpio_val); 1123 1124 /** 1125 * @brief Gpio get information 1126 * 1127 * @param p_hwfn - hw function 1128 * @param p_ptt - PTT required for register access 1129 * @param gpio - gpio number 1130 * @param gpio_direction - gpio is output (0) or input (1) 1131 * @param gpio_ctrl - gpio control is uninitialized (0), 1132 * path 0 (1), path 1 (2) or shared(3) 1133 * 1134 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful. 1135 */ 1136 enum _ecore_status_t ecore_mcp_gpio_info(struct ecore_hwfn *p_hwfn, 1137 struct ecore_ptt *p_ptt, 1138 u16 gpio, u32 *gpio_direction, 1139 u32 *gpio_ctrl); 1140 1141 /** 1142 * @brief Bist register test 1143 * 1144 * @param p_hwfn - hw function 1145 * @param p_ptt - PTT required for register access 1146 * 1147 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful. 1148 */ 1149 enum _ecore_status_t ecore_mcp_bist_register_test(struct ecore_hwfn *p_hwfn, 1150 struct ecore_ptt *p_ptt); 1151 1152 /** 1153 * @brief Bist clock test 1154 * 1155 * @param p_hwfn - hw function 1156 * @param p_ptt - PTT required for register access 1157 * 1158 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful. 1159 */ 1160 enum _ecore_status_t ecore_mcp_bist_clock_test(struct ecore_hwfn *p_hwfn, 1161 struct ecore_ptt *p_ptt); 1162 1163 /** 1164 * @brief Bist nvm test - get number of images 1165 * 1166 * @param p_hwfn - hw function 1167 * @param p_ptt - PTT required for register access 1168 * @param num_images - number of images if operation was 1169 * successful. 0 if not. 1170 * 1171 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful. 1172 */ 1173 enum _ecore_status_t ecore_mcp_bist_nvm_test_get_num_images( 1174 struct ecore_hwfn *p_hwfn, 1175 struct ecore_ptt *p_ptt, 1176 u32 *num_images); 1177 1178 /** 1179 * @brief Bist nvm test - get image attributes by index 1180 * 1181 * @param p_hwfn - hw function 1182 * @param p_ptt - PTT required for register access 1183 * @param p_image_att - Attributes of image 1184 * @param image_index - Index of image to get information for 1185 * 1186 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful. 1187 */ 1188 enum _ecore_status_t ecore_mcp_bist_nvm_test_get_image_att( 1189 struct ecore_hwfn *p_hwfn, 1190 struct ecore_ptt *p_ptt, 1191 struct bist_nvm_image_att *p_image_att, 1192 u32 image_index); 1193 1194 /** 1195 * @brief ecore_mcp_get_temperature_info - get the status of the temperature 1196 * sensors 1197 * 1198 * @param p_hwfn - hw function 1199 * @param p_ptt - PTT required for register access 1200 * @param p_temp_status - A pointer to an ecore_temperature_info structure to 1201 * be filled with the temperature data 1202 * 1203 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful. 1204 */ 1205 enum _ecore_status_t 1206 ecore_mcp_get_temperature_info(struct ecore_hwfn *p_hwfn, 1207 struct ecore_ptt *p_ptt, 1208 struct ecore_temperature_info *p_temp_info); 1209 1210 /** 1211 * @brief Get MBA versions - get MBA sub images versions 1212 * 1213 * @param p_hwfn - hw function 1214 * @param p_ptt - PTT required for register access 1215 * @param p_mba_vers - MBA versions array to fill 1216 * 1217 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful. 1218 */ 1219 enum _ecore_status_t ecore_mcp_get_mba_versions( 1220 struct ecore_hwfn *p_hwfn, 1221 struct ecore_ptt *p_ptt, 1222 struct ecore_mba_vers *p_mba_vers); 1223 1224 /** 1225 * @brief Count memory ecc events 1226 * 1227 * @param p_hwfn - hw function 1228 * @param p_ptt - PTT required for register access 1229 * @param num_events - number of memory ecc events 1230 * 1231 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful. 1232 */ 1233 enum _ecore_status_t ecore_mcp_mem_ecc_events(struct ecore_hwfn *p_hwfn, 1234 struct ecore_ptt *p_ptt, 1235 u64 *num_events); 1236 1237 struct ecore_mdump_info { 1238 u32 reason; 1239 u32 version; 1240 u32 config; 1241 u32 epoch; 1242 u32 num_of_logs; 1243 u32 valid_logs; 1244 }; 1245 1246 /** 1247 * @brief - Gets the MFW crash dump configuration and logs info. 1248 * 1249 * @param p_hwfn 1250 * @param p_ptt 1251 * @param p_mdump_info 1252 * 1253 * @param return ECORE_SUCCESS upon success. 1254 */ 1255 enum _ecore_status_t 1256 ecore_mcp_mdump_get_info(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt, 1257 struct ecore_mdump_info *p_mdump_info); 1258 1259 /** 1260 * @brief - Clears the MFW crash dump logs. 1261 * 1262 * @param p_hwfn 1263 * @param p_ptt 1264 * 1265 * @param return ECORE_SUCCESS upon success. 1266 */ 1267 enum _ecore_status_t ecore_mcp_mdump_clear_logs(struct ecore_hwfn *p_hwfn, 1268 struct ecore_ptt *p_ptt); 1269 1270 /** 1271 * @brief - Clear the mdump retained data. 1272 * 1273 * @param p_hwfn 1274 * @param p_ptt 1275 * 1276 * @param return ECORE_SUCCESS upon success. 1277 */ 1278 enum _ecore_status_t ecore_mcp_mdump_clr_retain(struct ecore_hwfn *p_hwfn, 1279 struct ecore_ptt *p_ptt); 1280 1281 /** 1282 * @brief - Processes the TLV request from MFW i.e., get the required TLV info 1283 * from the ecore client and send it to the MFW. 1284 * 1285 * @param p_hwfn 1286 * @param p_ptt 1287 * 1288 * @param return ECORE_SUCCESS upon success. 1289 */ 1290 enum _ecore_status_t ecore_mfw_process_tlv_req(struct ecore_hwfn *p_hwfn, 1291 struct ecore_ptt *p_ptt); 1292 1293 1294 /** 1295 * @brief - Return whether management firmware support smart AN 1296 * 1297 * @param p_hwfn 1298 * 1299 * @return bool - true iff feature is supported. 1300 */ 1301 bool ecore_mcp_is_smart_an_supported(struct ecore_hwfn *p_hwfn); 1302 #endif 1303