1 /* 2 * Copyright (c) 2016 QLogic Corporation. 3 * All rights reserved. 4 * www.qlogic.com 5 * 6 * See LICENSE.qede_pmd for copyright and licensing details. 7 */ 8 9 #include "bcm_osal.h" 10 #include "reg_addr.h" 11 #include "ecore_gtt_reg_addr.h" 12 #include "ecore.h" 13 #include "ecore_chain.h" 14 #include "ecore_status.h" 15 #include "ecore_hw.h" 16 #include "ecore_rt_defs.h" 17 #include "ecore_init_ops.h" 18 #include "ecore_int.h" 19 #include "ecore_cxt.h" 20 #include "ecore_spq.h" 21 #include "ecore_init_fw_funcs.h" 22 #include "ecore_sp_commands.h" 23 #include "ecore_dev_api.h" 24 #include "ecore_sriov.h" 25 #include "ecore_vf.h" 26 #include "ecore_mcp.h" 27 #include "ecore_hw_defs.h" 28 #include "mcp_public.h" 29 #include "ecore_iro.h" 30 #include "nvm_cfg.h" 31 #include "ecore_dev_api.h" 32 #include "ecore_dcbx.h" 33 34 /* TODO - there's a bug in DCBx re-configuration flows in MF, as the QM 35 * registers involved are not split and thus configuration is a race where 36 * some of the PFs configuration might be lost. 37 * Eventually, this needs to move into a MFW-covered HW-lock as arbitration 38 * mechanism as this doesn't cover some cases [E.g., PDA or scenarios where 39 * there's more than a single compiled ecore component in system]. 40 */ 41 static osal_spinlock_t qm_lock; 42 static bool qm_lock_init; 43 44 /* Configurable */ 45 #define ECORE_MIN_DPIS (4) /* The minimal num of DPIs required to 46 * load the driver. The number was 47 * arbitrarily set. 48 */ 49 50 /* Derived */ 51 #define ECORE_MIN_PWM_REGION ((ECORE_WID_SIZE) * (ECORE_MIN_DPIS)) 52 53 enum BAR_ID { 54 BAR_ID_0, /* used for GRC */ 55 BAR_ID_1 /* Used for doorbells */ 56 }; 57 58 static u32 ecore_hw_bar_size(struct ecore_hwfn *p_hwfn, enum BAR_ID bar_id) 59 { 60 u32 bar_reg = (bar_id == BAR_ID_0 ? 61 PGLUE_B_REG_PF_BAR0_SIZE : PGLUE_B_REG_PF_BAR1_SIZE); 62 u32 val; 63 64 if (IS_VF(p_hwfn->p_dev)) { 65 /* TODO - assume each VF hwfn has 64Kb for Bar0; Bar1 can be 66 * read from actual register, but we're currently not using 67 * it for actual doorbelling. 68 */ 69 return 1 << 17; 70 } 71 72 val = ecore_rd(p_hwfn, p_hwfn->p_main_ptt, bar_reg); 73 74 /* The above registers were updated in the past only in CMT mode. Since 75 * they were found to be useful MFW started updating them from 8.7.7.0. 76 * In older MFW versions they are set to 0 which means disabled. 77 */ 78 if (!val) { 79 if (p_hwfn->p_dev->num_hwfns > 1) { 80 DP_NOTICE(p_hwfn, false, 81 "BAR size not configured. Assuming BAR size"); 82 DP_NOTICE(p_hwfn, false, 83 "of 256kB for GRC and 512kB for DB\n"); 84 return BAR_ID_0 ? 256 * 1024 : 512 * 1024; 85 } else { 86 DP_NOTICE(p_hwfn, false, 87 "BAR size not configured. Assuming BAR size"); 88 DP_NOTICE(p_hwfn, false, 89 "of 512kB for GRC and 512kB for DB\n"); 90 return 512 * 1024; 91 } 92 } 93 94 return 1 << (val + 15); 95 } 96 97 void ecore_init_dp(struct ecore_dev *p_dev, 98 u32 dp_module, u8 dp_level, void *dp_ctx) 99 { 100 u32 i; 101 102 p_dev->dp_level = dp_level; 103 p_dev->dp_module = dp_module; 104 p_dev->dp_ctx = dp_ctx; 105 for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) { 106 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i]; 107 108 p_hwfn->dp_level = dp_level; 109 p_hwfn->dp_module = dp_module; 110 p_hwfn->dp_ctx = dp_ctx; 111 } 112 } 113 114 void ecore_init_struct(struct ecore_dev *p_dev) 115 { 116 u8 i; 117 118 for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) { 119 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i]; 120 121 p_hwfn->p_dev = p_dev; 122 p_hwfn->my_id = i; 123 p_hwfn->b_active = false; 124 125 OSAL_MUTEX_ALLOC(p_hwfn, &p_hwfn->dmae_info.mutex); 126 OSAL_MUTEX_INIT(&p_hwfn->dmae_info.mutex); 127 } 128 129 /* hwfn 0 is always active */ 130 p_dev->hwfns[0].b_active = true; 131 132 /* set the default cache alignment to 128 (may be overridden later) */ 133 p_dev->cache_shift = 7; 134 } 135 136 static void ecore_qm_info_free(struct ecore_hwfn *p_hwfn) 137 { 138 struct ecore_qm_info *qm_info = &p_hwfn->qm_info; 139 140 OSAL_FREE(p_hwfn->p_dev, qm_info->qm_pq_params); 141 qm_info->qm_pq_params = OSAL_NULL; 142 OSAL_FREE(p_hwfn->p_dev, qm_info->qm_vport_params); 143 qm_info->qm_vport_params = OSAL_NULL; 144 OSAL_FREE(p_hwfn->p_dev, qm_info->qm_port_params); 145 qm_info->qm_port_params = OSAL_NULL; 146 OSAL_FREE(p_hwfn->p_dev, qm_info->wfq_data); 147 qm_info->wfq_data = OSAL_NULL; 148 } 149 150 void ecore_resc_free(struct ecore_dev *p_dev) 151 { 152 int i; 153 154 if (IS_VF(p_dev)) 155 return; 156 157 OSAL_FREE(p_dev, p_dev->fw_data); 158 p_dev->fw_data = OSAL_NULL; 159 160 OSAL_FREE(p_dev, p_dev->reset_stats); 161 162 for_each_hwfn(p_dev, i) { 163 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i]; 164 165 OSAL_FREE(p_dev, p_hwfn->p_tx_cids); 166 p_hwfn->p_tx_cids = OSAL_NULL; 167 OSAL_FREE(p_dev, p_hwfn->p_rx_cids); 168 p_hwfn->p_rx_cids = OSAL_NULL; 169 } 170 171 for_each_hwfn(p_dev, i) { 172 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i]; 173 174 ecore_cxt_mngr_free(p_hwfn); 175 ecore_qm_info_free(p_hwfn); 176 ecore_spq_free(p_hwfn); 177 ecore_eq_free(p_hwfn, p_hwfn->p_eq); 178 ecore_consq_free(p_hwfn, p_hwfn->p_consq); 179 ecore_int_free(p_hwfn); 180 #ifdef CONFIG_ECORE_LL2 181 ecore_ll2_free(p_hwfn, p_hwfn->p_ll2_info); 182 #endif 183 ecore_iov_free(p_hwfn); 184 ecore_dmae_info_free(p_hwfn); 185 ecore_dcbx_info_free(p_hwfn, p_hwfn->p_dcbx_info); 186 /* @@@TBD Flush work-queue ? */ 187 } 188 } 189 190 static enum _ecore_status_t ecore_init_qm_info(struct ecore_hwfn *p_hwfn, 191 bool b_sleepable) 192 { 193 u8 num_vports, vf_offset = 0, i, vport_id, num_ports, curr_queue; 194 struct ecore_qm_info *qm_info = &p_hwfn->qm_info; 195 struct init_qm_port_params *p_qm_port; 196 bool init_rdma_offload_pq = false; 197 bool init_pure_ack_pq = false; 198 bool init_ooo_pq = false; 199 u16 num_pqs, protocol_pqs; 200 u16 num_pf_rls = 0; 201 u16 num_vfs = 0; 202 u32 pf_rl; 203 u8 pf_wfq; 204 205 /* @TMP - saving the existing min/max bw config before resetting the 206 * qm_info to restore them. 207 */ 208 pf_rl = qm_info->pf_rl; 209 pf_wfq = qm_info->pf_wfq; 210 211 #ifdef CONFIG_ECORE_SRIOV 212 if (p_hwfn->p_dev->p_iov_info) 213 num_vfs = p_hwfn->p_dev->p_iov_info->total_vfs; 214 #endif 215 OSAL_MEM_ZERO(qm_info, sizeof(*qm_info)); 216 217 #ifndef ASIC_ONLY 218 /* @TMP - Don't allocate QM queues for VFs on emulation */ 219 if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) { 220 DP_NOTICE(p_hwfn, false, 221 "Emulation - skip configuring QM queues for VFs\n"); 222 num_vfs = 0; 223 } 224 #endif 225 226 /* ethernet PFs require a pq per tc. Even if only a subset of the TCs 227 * active, we want physical queues allocated for all of them, since we 228 * don't have a good recycle flow. Non ethernet PFs require only a 229 * single physical queue. 230 */ 231 if (p_hwfn->hw_info.personality == ECORE_PCI_ETH_ROCE || 232 p_hwfn->hw_info.personality == ECORE_PCI_IWARP || 233 p_hwfn->hw_info.personality == ECORE_PCI_ETH) 234 protocol_pqs = p_hwfn->hw_info.num_hw_tc; 235 else 236 protocol_pqs = 1; 237 238 num_pqs = protocol_pqs + num_vfs + 1; /* The '1' is for pure-LB */ 239 num_vports = (u8)RESC_NUM(p_hwfn, ECORE_VPORT); 240 241 if (p_hwfn->hw_info.personality == ECORE_PCI_ETH_ROCE) { 242 num_pqs++; /* for RoCE queue */ 243 init_rdma_offload_pq = true; 244 if (p_hwfn->pf_params.rdma_pf_params.enable_dcqcn) { 245 /* Due to FW assumption that rl==vport, we limit the 246 * number of rate limiters by the minimum between its 247 * allocated number and the allocated number of vports. 248 * Another limitation is the number of supported qps 249 * with rate limiters in FW. 250 */ 251 num_pf_rls = 252 (u16)OSAL_MIN_T(u32, RESC_NUM(p_hwfn, ECORE_RL), 253 RESC_NUM(p_hwfn, ECORE_VPORT)); 254 255 /* we subtract num_vfs because each one requires a rate 256 * limiter, and one default rate limiter. 257 */ 258 if (num_pf_rls < num_vfs + 1) { 259 DP_ERR(p_hwfn, "No RL for DCQCN"); 260 DP_ERR(p_hwfn, "[num_pf_rls %d num_vfs %d]\n", 261 num_pf_rls, num_vfs); 262 return ECORE_INVAL; 263 } 264 num_pf_rls -= num_vfs + 1; 265 } 266 267 num_pqs += num_pf_rls; 268 qm_info->num_pf_rls = (u8)num_pf_rls; 269 } 270 271 if (p_hwfn->hw_info.personality == ECORE_PCI_IWARP) { 272 num_pqs += 3; /* for iwarp queue / pure-ack / ooo */ 273 init_rdma_offload_pq = true; 274 init_pure_ack_pq = true; 275 init_ooo_pq = true; 276 } 277 278 if (p_hwfn->hw_info.personality == ECORE_PCI_ISCSI) { 279 num_pqs += 2; /* for iSCSI pure-ACK / OOO queue */ 280 init_pure_ack_pq = true; 281 init_ooo_pq = true; 282 } 283 284 /* Sanity checking that setup requires legal number of resources */ 285 if (num_pqs > RESC_NUM(p_hwfn, ECORE_PQ)) { 286 DP_ERR(p_hwfn, 287 "Need too many Physical queues - 0x%04x avail %04x", 288 num_pqs, RESC_NUM(p_hwfn, ECORE_PQ)); 289 return ECORE_INVAL; 290 } 291 292 /* PQs will be arranged as follows: First per-TC PQ, then pure-LB queue, 293 * then special queues (iSCSI pure-ACK / RoCE), then per-VF PQ. 294 */ 295 qm_info->qm_pq_params = OSAL_ZALLOC(p_hwfn->p_dev, 296 b_sleepable ? GFP_KERNEL : 297 GFP_ATOMIC, 298 sizeof(struct init_qm_pq_params) * 299 num_pqs); 300 if (!qm_info->qm_pq_params) 301 goto alloc_err; 302 303 qm_info->qm_vport_params = OSAL_ZALLOC(p_hwfn->p_dev, 304 b_sleepable ? GFP_KERNEL : 305 GFP_ATOMIC, 306 sizeof(struct 307 init_qm_vport_params) * 308 num_vports); 309 if (!qm_info->qm_vport_params) 310 goto alloc_err; 311 312 qm_info->qm_port_params = OSAL_ZALLOC(p_hwfn->p_dev, 313 b_sleepable ? GFP_KERNEL : 314 GFP_ATOMIC, 315 sizeof(struct init_qm_port_params) 316 * MAX_NUM_PORTS); 317 if (!qm_info->qm_port_params) 318 goto alloc_err; 319 320 qm_info->wfq_data = OSAL_ZALLOC(p_hwfn->p_dev, 321 b_sleepable ? GFP_KERNEL : 322 GFP_ATOMIC, 323 sizeof(struct ecore_wfq_data) * 324 num_vports); 325 326 if (!qm_info->wfq_data) 327 goto alloc_err; 328 329 vport_id = (u8)RESC_START(p_hwfn, ECORE_VPORT); 330 331 /* First init rate limited queues ( Due to RoCE assumption of 332 * qpid=rlid ) 333 */ 334 for (curr_queue = 0; curr_queue < num_pf_rls; curr_queue++) { 335 qm_info->qm_pq_params[curr_queue].vport_id = vport_id++; 336 qm_info->qm_pq_params[curr_queue].tc_id = 337 p_hwfn->hw_info.offload_tc; 338 qm_info->qm_pq_params[curr_queue].wrr_group = 1; 339 qm_info->qm_pq_params[curr_queue].rl_valid = 1; 340 }; 341 342 /* Protocol PQs */ 343 for (i = 0; i < protocol_pqs; i++) { 344 struct init_qm_pq_params *params = 345 &qm_info->qm_pq_params[curr_queue++]; 346 347 if (p_hwfn->hw_info.personality == ECORE_PCI_ETH_ROCE || 348 p_hwfn->hw_info.personality == ECORE_PCI_IWARP || 349 p_hwfn->hw_info.personality == ECORE_PCI_ETH) { 350 params->vport_id = vport_id; 351 params->tc_id = i; 352 /* Note: this assumes that if we had a configuration 353 * with N tcs and subsequently another configuration 354 * With Fewer TCs, the in flight traffic (in QM queues, 355 * in FW, from driver to FW) will still trickle out and 356 * not get "stuck" in the QM. This is determined by the 357 * NIG_REG_TX_ARB_CLIENT_IS_SUBJECT2WFQ. Unused TCs are 358 * supposed to be cleared in this map, allowing traffic 359 * to flush out. If this is not the case, we would need 360 * to set the TC of unused queues to 0, and reconfigure 361 * QM every time num of TCs changes. Unused queues in 362 * this context would mean those intended for TCs where 363 * tc_id > hw_info.num_active_tcs. 364 */ 365 params->wrr_group = 1; /* @@@TBD ECORE_WRR_MEDIUM */ 366 } else { 367 params->vport_id = vport_id; 368 params->tc_id = p_hwfn->hw_info.offload_tc; 369 params->wrr_group = 1; /* @@@TBD ECORE_WRR_MEDIUM */ 370 } 371 } 372 373 /* Then init pure-LB PQ */ 374 qm_info->pure_lb_pq = curr_queue; 375 qm_info->qm_pq_params[curr_queue].vport_id = 376 (u8)RESC_START(p_hwfn, ECORE_VPORT); 377 qm_info->qm_pq_params[curr_queue].tc_id = PURE_LB_TC; 378 qm_info->qm_pq_params[curr_queue].wrr_group = 1; 379 curr_queue++; 380 381 qm_info->offload_pq = 0; /* Already initialized for iSCSI/FCoE */ 382 if (init_rdma_offload_pq) { 383 qm_info->offload_pq = curr_queue; 384 qm_info->qm_pq_params[curr_queue].vport_id = vport_id; 385 qm_info->qm_pq_params[curr_queue].tc_id = 386 p_hwfn->hw_info.offload_tc; 387 qm_info->qm_pq_params[curr_queue].wrr_group = 1; 388 curr_queue++; 389 } 390 391 if (init_pure_ack_pq) { 392 qm_info->pure_ack_pq = curr_queue; 393 qm_info->qm_pq_params[curr_queue].vport_id = vport_id; 394 qm_info->qm_pq_params[curr_queue].tc_id = 395 p_hwfn->hw_info.offload_tc; 396 qm_info->qm_pq_params[curr_queue].wrr_group = 1; 397 curr_queue++; 398 } 399 400 if (init_ooo_pq) { 401 qm_info->ooo_pq = curr_queue; 402 qm_info->qm_pq_params[curr_queue].vport_id = vport_id; 403 qm_info->qm_pq_params[curr_queue].tc_id = DCBX_ISCSI_OOO_TC; 404 qm_info->qm_pq_params[curr_queue].wrr_group = 1; 405 curr_queue++; 406 } 407 408 /* Then init per-VF PQs */ 409 vf_offset = curr_queue; 410 for (i = 0; i < num_vfs; i++) { 411 /* First vport is used by the PF */ 412 qm_info->qm_pq_params[curr_queue].vport_id = vport_id + i + 1; 413 /* @@@TBD VF Multi-cos */ 414 qm_info->qm_pq_params[curr_queue].tc_id = 0; 415 qm_info->qm_pq_params[curr_queue].wrr_group = 1; 416 qm_info->qm_pq_params[curr_queue].rl_valid = 1; 417 curr_queue++; 418 }; 419 420 qm_info->vf_queues_offset = vf_offset; 421 qm_info->num_pqs = num_pqs; 422 qm_info->num_vports = num_vports; 423 424 /* Initialize qm port parameters */ 425 num_ports = p_hwfn->p_dev->num_ports_in_engines; 426 for (i = 0; i < num_ports; i++) { 427 p_qm_port = &qm_info->qm_port_params[i]; 428 p_qm_port->active = 1; 429 /* @@@TMP - was NUM_OF_PHYS_TCS; Changed until dcbx will 430 * be in place 431 */ 432 if (num_ports == 4) 433 p_qm_port->active_phys_tcs = 0xf; 434 else 435 p_qm_port->active_phys_tcs = 0x9f; 436 p_qm_port->num_pbf_cmd_lines = PBF_MAX_CMD_LINES / num_ports; 437 p_qm_port->num_btb_blocks = BTB_MAX_BLOCKS / num_ports; 438 } 439 440 if (ECORE_IS_AH(p_hwfn->p_dev) && (num_ports == 4)) 441 qm_info->max_phys_tcs_per_port = NUM_PHYS_TCS_4PORT_K2; 442 else 443 qm_info->max_phys_tcs_per_port = NUM_OF_PHYS_TCS; 444 445 qm_info->start_pq = (u16)RESC_START(p_hwfn, ECORE_PQ); 446 447 qm_info->num_vf_pqs = num_vfs; 448 qm_info->start_vport = (u8)RESC_START(p_hwfn, ECORE_VPORT); 449 450 for (i = 0; i < qm_info->num_vports; i++) 451 qm_info->qm_vport_params[i].vport_wfq = 1; 452 453 qm_info->vport_rl_en = 1; 454 qm_info->vport_wfq_en = 1; 455 qm_info->pf_rl = pf_rl; 456 qm_info->pf_wfq = pf_wfq; 457 458 return ECORE_SUCCESS; 459 460 alloc_err: 461 DP_NOTICE(p_hwfn, false, "Failed to allocate memory for QM params\n"); 462 ecore_qm_info_free(p_hwfn); 463 return ECORE_NOMEM; 464 } 465 466 /* This function reconfigures the QM pf on the fly. 467 * For this purpose we: 468 * 1. reconfigure the QM database 469 * 2. set new values to runtime arrat 470 * 3. send an sdm_qm_cmd through the rbc interface to stop the QM 471 * 4. activate init tool in QM_PF stage 472 * 5. send an sdm_qm_cmd through rbc interface to release the QM 473 */ 474 enum _ecore_status_t ecore_qm_reconf(struct ecore_hwfn *p_hwfn, 475 struct ecore_ptt *p_ptt) 476 { 477 struct ecore_qm_info *qm_info = &p_hwfn->qm_info; 478 bool b_rc; 479 enum _ecore_status_t rc; 480 481 /* qm_info is allocated in ecore_init_qm_info() which is already called 482 * from ecore_resc_alloc() or previous call of ecore_qm_reconf(). 483 * The allocated size may change each init, so we free it before next 484 * allocation. 485 */ 486 ecore_qm_info_free(p_hwfn); 487 488 /* initialize ecore's qm data structure */ 489 rc = ecore_init_qm_info(p_hwfn, false); 490 if (rc != ECORE_SUCCESS) 491 return rc; 492 493 /* stop PF's qm queues */ 494 OSAL_SPIN_LOCK(&qm_lock); 495 b_rc = ecore_send_qm_stop_cmd(p_hwfn, p_ptt, false, true, 496 qm_info->start_pq, qm_info->num_pqs); 497 OSAL_SPIN_UNLOCK(&qm_lock); 498 if (!b_rc) 499 return ECORE_INVAL; 500 501 /* clear the QM_PF runtime phase leftovers from previous init */ 502 ecore_init_clear_rt_data(p_hwfn); 503 504 /* prepare QM portion of runtime array */ 505 ecore_qm_init_pf(p_hwfn); 506 507 /* activate init tool on runtime array */ 508 rc = ecore_init_run(p_hwfn, p_ptt, PHASE_QM_PF, p_hwfn->rel_pf_id, 509 p_hwfn->hw_info.hw_mode); 510 if (rc != ECORE_SUCCESS) 511 return rc; 512 513 /* start PF's qm queues */ 514 OSAL_SPIN_LOCK(&qm_lock); 515 b_rc = ecore_send_qm_stop_cmd(p_hwfn, p_ptt, true, true, 516 qm_info->start_pq, qm_info->num_pqs); 517 OSAL_SPIN_UNLOCK(&qm_lock); 518 if (!b_rc) 519 return ECORE_INVAL; 520 521 return ECORE_SUCCESS; 522 } 523 524 enum _ecore_status_t ecore_resc_alloc(struct ecore_dev *p_dev) 525 { 526 struct ecore_consq *p_consq; 527 struct ecore_eq *p_eq; 528 #ifdef CONFIG_ECORE_LL2 529 struct ecore_ll2_info *p_ll2_info; 530 #endif 531 enum _ecore_status_t rc = ECORE_SUCCESS; 532 int i; 533 534 if (IS_VF(p_dev)) 535 return rc; 536 537 p_dev->fw_data = OSAL_ZALLOC(p_dev, GFP_KERNEL, 538 sizeof(*p_dev->fw_data)); 539 if (!p_dev->fw_data) 540 return ECORE_NOMEM; 541 542 /* Allocate Memory for the Queue->CID mapping */ 543 for_each_hwfn(p_dev, i) { 544 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i]; 545 546 /* @@@TMP - resc management, change to actual required size */ 547 int tx_size = sizeof(struct ecore_hw_cid_data) * 548 RESC_NUM(p_hwfn, ECORE_L2_QUEUE); 549 int rx_size = sizeof(struct ecore_hw_cid_data) * 550 RESC_NUM(p_hwfn, ECORE_L2_QUEUE); 551 552 p_hwfn->p_tx_cids = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL, 553 tx_size); 554 if (!p_hwfn->p_tx_cids) { 555 DP_NOTICE(p_hwfn, true, 556 "Failed to allocate memory for Tx Cids\n"); 557 goto alloc_no_mem; 558 } 559 560 p_hwfn->p_rx_cids = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL, 561 rx_size); 562 if (!p_hwfn->p_rx_cids) { 563 DP_NOTICE(p_hwfn, true, 564 "Failed to allocate memory for Rx Cids\n"); 565 goto alloc_no_mem; 566 } 567 } 568 569 for_each_hwfn(p_dev, i) { 570 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i]; 571 u32 n_eqes, num_cons; 572 573 /* First allocate the context manager structure */ 574 rc = ecore_cxt_mngr_alloc(p_hwfn); 575 if (rc) 576 goto alloc_err; 577 578 /* Set the HW cid/tid numbers (in the contest manager) 579 * Must be done prior to any further computations. 580 */ 581 rc = ecore_cxt_set_pf_params(p_hwfn); 582 if (rc) 583 goto alloc_err; 584 585 /* Prepare and process QM requirements */ 586 rc = ecore_init_qm_info(p_hwfn, true); 587 if (rc) 588 goto alloc_err; 589 590 /* Compute the ILT client partition */ 591 rc = ecore_cxt_cfg_ilt_compute(p_hwfn); 592 if (rc) 593 goto alloc_err; 594 595 /* CID map / ILT shadow table / T2 596 * The talbes sizes are determined by the computations above 597 */ 598 rc = ecore_cxt_tables_alloc(p_hwfn); 599 if (rc) 600 goto alloc_err; 601 602 /* SPQ, must follow ILT because initializes SPQ context */ 603 rc = ecore_spq_alloc(p_hwfn); 604 if (rc) 605 goto alloc_err; 606 607 /* SP status block allocation */ 608 p_hwfn->p_dpc_ptt = ecore_get_reserved_ptt(p_hwfn, 609 RESERVED_PTT_DPC); 610 611 rc = ecore_int_alloc(p_hwfn, p_hwfn->p_main_ptt); 612 if (rc) 613 goto alloc_err; 614 615 rc = ecore_iov_alloc(p_hwfn); 616 if (rc) 617 goto alloc_err; 618 619 /* EQ */ 620 n_eqes = ecore_chain_get_capacity(&p_hwfn->p_spq->chain); 621 if ((p_hwfn->hw_info.personality == ECORE_PCI_ETH_ROCE) || 622 (p_hwfn->hw_info.personality == ECORE_PCI_IWARP)) { 623 /* Calculate the EQ size 624 * --------------------- 625 * Each ICID may generate up to one event at a time i.e. 626 * the event must be handled/cleared before a new one 627 * can be generated. We calculate the sum of events per 628 * protocol and create an EQ deep enough to handle the 629 * worst case: 630 * - Core - according to SPQ. 631 * - RoCE - per QP there are a couple of ICIDs, one 632 * responder and one requester, each can 633 * generate an EQE => n_eqes_qp = 2 * n_qp. 634 * Each CQ can generate an EQE. There are 2 CQs 635 * per QP => n_eqes_cq = 2 * n_qp. 636 * Hence the RoCE total is 4 * n_qp or 637 * 2 * num_cons. 638 * - ENet - There can be up to two events per VF. One 639 * for VF-PF channel and another for VF FLR 640 * initial cleanup. The number of VFs is 641 * bounded by MAX_NUM_VFS_BB, and is much 642 * smaller than RoCE's so we avoid exact 643 * calculation. 644 */ 645 if (p_hwfn->hw_info.personality == ECORE_PCI_ETH_ROCE) { 646 num_cons = 647 ecore_cxt_get_proto_cid_count( 648 p_hwfn, 649 PROTOCOLID_ROCE, 650 0); 651 num_cons *= 2; 652 } else { 653 num_cons = ecore_cxt_get_proto_cid_count( 654 p_hwfn, 655 PROTOCOLID_IWARP, 656 0); 657 } 658 n_eqes += num_cons + 2 * MAX_NUM_VFS_BB; 659 } else if (p_hwfn->hw_info.personality == ECORE_PCI_ISCSI) { 660 num_cons = 661 ecore_cxt_get_proto_cid_count(p_hwfn, 662 PROTOCOLID_ISCSI, 0); 663 n_eqes += 2 * num_cons; 664 } 665 666 if (n_eqes > 0xFFFF) { 667 DP_ERR(p_hwfn, "Cannot allocate 0x%x EQ elements." 668 "The maximum of a u16 chain is 0x%x\n", 669 n_eqes, 0xFFFF); 670 goto alloc_err; 671 } 672 673 p_eq = ecore_eq_alloc(p_hwfn, (u16)n_eqes); 674 if (!p_eq) 675 goto alloc_no_mem; 676 p_hwfn->p_eq = p_eq; 677 678 p_consq = ecore_consq_alloc(p_hwfn); 679 if (!p_consq) 680 goto alloc_no_mem; 681 p_hwfn->p_consq = p_consq; 682 683 #ifdef CONFIG_ECORE_LL2 684 if (p_hwfn->using_ll2) { 685 p_ll2_info = ecore_ll2_alloc(p_hwfn); 686 if (!p_ll2_info) 687 goto alloc_no_mem; 688 p_hwfn->p_ll2_info = p_ll2_info; 689 } 690 #endif 691 692 /* DMA info initialization */ 693 rc = ecore_dmae_info_alloc(p_hwfn); 694 if (rc) { 695 DP_NOTICE(p_hwfn, true, 696 "Failed to allocate memory for dmae_info structure\n"); 697 goto alloc_err; 698 } 699 700 /* DCBX initialization */ 701 rc = ecore_dcbx_info_alloc(p_hwfn); 702 if (rc) { 703 DP_NOTICE(p_hwfn, true, 704 "Failed to allocate memory for dcbx structure\n"); 705 goto alloc_err; 706 } 707 } 708 709 p_dev->reset_stats = OSAL_ZALLOC(p_dev, GFP_KERNEL, 710 sizeof(struct ecore_eth_stats)); 711 if (!p_dev->reset_stats) { 712 DP_NOTICE(p_dev, true, "Failed to allocate reset statistics\n"); 713 goto alloc_no_mem; 714 } 715 716 return ECORE_SUCCESS; 717 718 alloc_no_mem: 719 rc = ECORE_NOMEM; 720 alloc_err: 721 ecore_resc_free(p_dev); 722 return rc; 723 } 724 725 void ecore_resc_setup(struct ecore_dev *p_dev) 726 { 727 int i; 728 729 if (IS_VF(p_dev)) 730 return; 731 732 for_each_hwfn(p_dev, i) { 733 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i]; 734 735 ecore_cxt_mngr_setup(p_hwfn); 736 ecore_spq_setup(p_hwfn); 737 ecore_eq_setup(p_hwfn, p_hwfn->p_eq); 738 ecore_consq_setup(p_hwfn, p_hwfn->p_consq); 739 740 /* Read shadow of current MFW mailbox */ 741 ecore_mcp_read_mb(p_hwfn, p_hwfn->p_main_ptt); 742 OSAL_MEMCPY(p_hwfn->mcp_info->mfw_mb_shadow, 743 p_hwfn->mcp_info->mfw_mb_cur, 744 p_hwfn->mcp_info->mfw_mb_length); 745 746 ecore_int_setup(p_hwfn, p_hwfn->p_main_ptt); 747 748 ecore_iov_setup(p_hwfn, p_hwfn->p_main_ptt); 749 #ifdef CONFIG_ECORE_LL2 750 if (p_hwfn->using_ll2) 751 ecore_ll2_setup(p_hwfn, p_hwfn->p_ll2_info); 752 #endif 753 } 754 } 755 756 #define FINAL_CLEANUP_POLL_CNT (100) 757 #define FINAL_CLEANUP_POLL_TIME (10) 758 enum _ecore_status_t ecore_final_cleanup(struct ecore_hwfn *p_hwfn, 759 struct ecore_ptt *p_ptt, 760 u16 id, bool is_vf) 761 { 762 u32 command = 0, addr, count = FINAL_CLEANUP_POLL_CNT; 763 enum _ecore_status_t rc = ECORE_TIMEOUT; 764 765 #ifndef ASIC_ONLY 766 if (CHIP_REV_IS_TEDIBEAR(p_hwfn->p_dev) || 767 CHIP_REV_IS_SLOW(p_hwfn->p_dev)) { 768 DP_INFO(p_hwfn, "Skipping final cleanup for non-ASIC\n"); 769 return ECORE_SUCCESS; 770 } 771 #endif 772 773 addr = GTT_BAR0_MAP_REG_USDM_RAM + 774 USTORM_FLR_FINAL_ACK_OFFSET(p_hwfn->rel_pf_id); 775 776 if (is_vf) 777 id += 0x10; 778 779 command |= X_FINAL_CLEANUP_AGG_INT << 780 SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_SHIFT; 781 command |= 1 << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_SHIFT; 782 command |= id << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_SHIFT; 783 command |= SDM_COMP_TYPE_AGG_INT << SDM_OP_GEN_COMP_TYPE_SHIFT; 784 785 /* Make sure notification is not set before initiating final cleanup */ 786 787 if (REG_RD(p_hwfn, addr)) { 788 DP_NOTICE(p_hwfn, false, 789 "Unexpected; Found final cleanup notification"); 790 DP_NOTICE(p_hwfn, false, 791 " before initiating final cleanup\n"); 792 REG_WR(p_hwfn, addr, 0); 793 } 794 795 DP_VERBOSE(p_hwfn, ECORE_MSG_IOV, 796 "Sending final cleanup for PFVF[%d] [Command %08x\n]", 797 id, OSAL_CPU_TO_LE32(command)); 798 799 ecore_wr(p_hwfn, p_ptt, XSDM_REG_OPERATION_GEN, 800 OSAL_CPU_TO_LE32(command)); 801 802 /* Poll until completion */ 803 while (!REG_RD(p_hwfn, addr) && count--) 804 OSAL_MSLEEP(FINAL_CLEANUP_POLL_TIME); 805 806 if (REG_RD(p_hwfn, addr)) 807 rc = ECORE_SUCCESS; 808 else 809 DP_NOTICE(p_hwfn, true, 810 "Failed to receive FW final cleanup notification\n"); 811 812 /* Cleanup afterwards */ 813 REG_WR(p_hwfn, addr, 0); 814 815 return rc; 816 } 817 818 static enum _ecore_status_t ecore_calc_hw_mode(struct ecore_hwfn *p_hwfn) 819 { 820 int hw_mode = 0; 821 822 if (ECORE_IS_BB_A0(p_hwfn->p_dev)) { 823 hw_mode |= 1 << MODE_BB_A0; 824 } else if (ECORE_IS_BB_B0(p_hwfn->p_dev)) { 825 hw_mode |= 1 << MODE_BB_B0; 826 } else if (ECORE_IS_AH(p_hwfn->p_dev)) { 827 hw_mode |= 1 << MODE_K2; 828 } else { 829 DP_NOTICE(p_hwfn, true, "Unknown chip type %#x\n", 830 p_hwfn->p_dev->type); 831 return ECORE_INVAL; 832 } 833 834 /* Ports per engine is based on the values in CNIG_REG_NW_PORT_MODE */ 835 switch (p_hwfn->p_dev->num_ports_in_engines) { 836 case 1: 837 hw_mode |= 1 << MODE_PORTS_PER_ENG_1; 838 break; 839 case 2: 840 hw_mode |= 1 << MODE_PORTS_PER_ENG_2; 841 break; 842 case 4: 843 hw_mode |= 1 << MODE_PORTS_PER_ENG_4; 844 break; 845 default: 846 DP_NOTICE(p_hwfn, true, 847 "num_ports_in_engine = %d not supported\n", 848 p_hwfn->p_dev->num_ports_in_engines); 849 return ECORE_INVAL; 850 } 851 852 switch (p_hwfn->p_dev->mf_mode) { 853 case ECORE_MF_DEFAULT: 854 case ECORE_MF_NPAR: 855 hw_mode |= 1 << MODE_MF_SI; 856 break; 857 case ECORE_MF_OVLAN: 858 hw_mode |= 1 << MODE_MF_SD; 859 break; 860 default: 861 DP_NOTICE(p_hwfn, true, 862 "Unsupported MF mode, init as DEFAULT\n"); 863 hw_mode |= 1 << MODE_MF_SI; 864 } 865 866 #ifndef ASIC_ONLY 867 if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) { 868 if (CHIP_REV_IS_FPGA(p_hwfn->p_dev)) { 869 hw_mode |= 1 << MODE_FPGA; 870 } else { 871 if (p_hwfn->p_dev->b_is_emul_full) 872 hw_mode |= 1 << MODE_EMUL_FULL; 873 else 874 hw_mode |= 1 << MODE_EMUL_REDUCED; 875 } 876 } else 877 #endif 878 hw_mode |= 1 << MODE_ASIC; 879 880 #ifndef REAL_ASIC_ONLY 881 if (ENABLE_EAGLE_ENG1_WORKAROUND(p_hwfn)) 882 hw_mode |= 1 << MODE_EAGLE_ENG1_WORKAROUND; 883 #endif 884 885 if (p_hwfn->p_dev->num_hwfns > 1) 886 hw_mode |= 1 << MODE_100G; 887 888 p_hwfn->hw_info.hw_mode = hw_mode; 889 890 DP_VERBOSE(p_hwfn, (ECORE_MSG_PROBE | ECORE_MSG_IFUP), 891 "Configuring function for hw_mode: 0x%08x\n", 892 p_hwfn->hw_info.hw_mode); 893 894 return ECORE_SUCCESS; 895 } 896 897 #ifndef ASIC_ONLY 898 /* MFW-replacement initializations for non-ASIC */ 899 static enum _ecore_status_t ecore_hw_init_chip(struct ecore_hwfn *p_hwfn, 900 struct ecore_ptt *p_ptt) 901 { 902 u32 pl_hv = 1; 903 int i; 904 905 if (CHIP_REV_IS_EMUL(p_hwfn->p_dev) && ECORE_IS_AH(p_hwfn->p_dev)) 906 pl_hv |= 0x600; 907 908 ecore_wr(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV + 4, pl_hv); 909 910 if (CHIP_REV_IS_EMUL(p_hwfn->p_dev) && ECORE_IS_AH(p_hwfn->p_dev)) 911 ecore_wr(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV_2, 0x3ffffff); 912 913 /* initialize port mode to 4x10G_E (10G with 4x10 SERDES) */ 914 /* CNIG_REG_NW_PORT_MODE is same for A0 and B0 */ 915 if (!CHIP_REV_IS_EMUL(p_hwfn->p_dev) || !ECORE_IS_AH(p_hwfn->p_dev)) 916 ecore_wr(p_hwfn, p_ptt, CNIG_REG_NW_PORT_MODE_BB_B0, 4); 917 918 if (CHIP_REV_IS_EMUL(p_hwfn->p_dev) && ECORE_IS_AH(p_hwfn->p_dev)) { 919 /* 2 for 4-port, 1 for 2-port, 0 for 1-port */ 920 ecore_wr(p_hwfn, p_ptt, MISC_REG_PORT_MODE, 921 (p_hwfn->p_dev->num_ports_in_engines >> 1)); 922 923 ecore_wr(p_hwfn, p_ptt, MISC_REG_BLOCK_256B_EN, 924 p_hwfn->p_dev->num_ports_in_engines == 4 ? 0 : 3); 925 } 926 927 /* Poll on RBC */ 928 ecore_wr(p_hwfn, p_ptt, PSWRQ2_REG_RBC_DONE, 1); 929 for (i = 0; i < 100; i++) { 930 OSAL_UDELAY(50); 931 if (ecore_rd(p_hwfn, p_ptt, PSWRQ2_REG_CFG_DONE) == 1) 932 break; 933 } 934 if (i == 100) 935 DP_NOTICE(p_hwfn, true, 936 "RBC done failed to complete in PSWRQ2\n"); 937 938 return ECORE_SUCCESS; 939 } 940 #endif 941 942 /* Init run time data for all PFs and their VFs on an engine. 943 * TBD - for VFs - Once we have parent PF info for each VF in 944 * shmem available as CAU requires knowledge of parent PF for each VF. 945 */ 946 static void ecore_init_cau_rt_data(struct ecore_dev *p_dev) 947 { 948 u32 offset = CAU_REG_SB_VAR_MEMORY_RT_OFFSET; 949 int i, sb_id; 950 951 for_each_hwfn(p_dev, i) { 952 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i]; 953 struct ecore_igu_info *p_igu_info; 954 struct ecore_igu_block *p_block; 955 struct cau_sb_entry sb_entry; 956 957 p_igu_info = p_hwfn->hw_info.p_igu_info; 958 959 for (sb_id = 0; sb_id < ECORE_MAPPING_MEMORY_SIZE(p_dev); 960 sb_id++) { 961 p_block = &p_igu_info->igu_map.igu_blocks[sb_id]; 962 963 if (!p_block->is_pf) 964 continue; 965 966 ecore_init_cau_sb_entry(p_hwfn, &sb_entry, 967 p_block->function_id, 0, 0); 968 STORE_RT_REG_AGG(p_hwfn, offset + sb_id * 2, sb_entry); 969 } 970 } 971 } 972 973 static enum _ecore_status_t ecore_hw_init_common(struct ecore_hwfn *p_hwfn, 974 struct ecore_ptt *p_ptt, 975 int hw_mode) 976 { 977 struct ecore_qm_info *qm_info = &p_hwfn->qm_info; 978 struct ecore_dev *p_dev = p_hwfn->p_dev; 979 u8 vf_id, max_num_vfs; 980 u16 num_pfs, pf_id; 981 u32 concrete_fid; 982 enum _ecore_status_t rc = ECORE_SUCCESS; 983 984 ecore_init_cau_rt_data(p_dev); 985 986 /* Program GTT windows */ 987 ecore_gtt_init(p_hwfn); 988 989 #ifndef ASIC_ONLY 990 if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) { 991 rc = ecore_hw_init_chip(p_hwfn, p_hwfn->p_main_ptt); 992 if (rc != ECORE_SUCCESS) 993 return rc; 994 } 995 #endif 996 997 if (p_hwfn->mcp_info) { 998 if (p_hwfn->mcp_info->func_info.bandwidth_max) 999 qm_info->pf_rl_en = 1; 1000 if (p_hwfn->mcp_info->func_info.bandwidth_min) 1001 qm_info->pf_wfq_en = 1; 1002 } 1003 1004 ecore_qm_common_rt_init(p_hwfn, 1005 p_hwfn->p_dev->num_ports_in_engines, 1006 qm_info->max_phys_tcs_per_port, 1007 qm_info->pf_rl_en, qm_info->pf_wfq_en, 1008 qm_info->vport_rl_en, qm_info->vport_wfq_en, 1009 qm_info->qm_port_params); 1010 1011 ecore_cxt_hw_init_common(p_hwfn); 1012 1013 /* Close gate from NIG to BRB/Storm; By default they are open, but 1014 * we close them to prevent NIG from passing data to reset blocks. 1015 * Should have been done in the ENGINE phase, but init-tool lacks 1016 * proper port-pretend capabilities. 1017 */ 1018 ecore_wr(p_hwfn, p_ptt, NIG_REG_RX_BRB_OUT_EN, 0); 1019 ecore_wr(p_hwfn, p_ptt, NIG_REG_STORM_OUT_EN, 0); 1020 ecore_port_pretend(p_hwfn, p_ptt, p_hwfn->port_id ^ 1); 1021 ecore_wr(p_hwfn, p_ptt, NIG_REG_RX_BRB_OUT_EN, 0); 1022 ecore_wr(p_hwfn, p_ptt, NIG_REG_STORM_OUT_EN, 0); 1023 ecore_port_unpretend(p_hwfn, p_ptt); 1024 1025 rc = ecore_init_run(p_hwfn, p_ptt, PHASE_ENGINE, ANY_PHASE_ID, hw_mode); 1026 if (rc != ECORE_SUCCESS) 1027 return rc; 1028 1029 /* @@TBD MichalK - should add VALIDATE_VFID to init tool... 1030 * need to decide with which value, maybe runtime 1031 */ 1032 ecore_wr(p_hwfn, p_ptt, PSWRQ2_REG_L2P_VALIDATE_VFID, 0); 1033 ecore_wr(p_hwfn, p_ptt, PGLUE_B_REG_USE_CLIENTID_IN_TAG, 1); 1034 1035 if (ECORE_IS_BB(p_hwfn->p_dev)) { 1036 /* Workaround clears ROCE search for all functions to prevent 1037 * involving non initialized function in processing ROCE packet. 1038 */ 1039 num_pfs = NUM_OF_ENG_PFS(p_hwfn->p_dev); 1040 for (pf_id = 0; pf_id < num_pfs; pf_id++) { 1041 ecore_fid_pretend(p_hwfn, p_ptt, pf_id); 1042 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0); 1043 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0); 1044 } 1045 /* pretend to original PF */ 1046 ecore_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id); 1047 } 1048 1049 /* Workaround for avoiding CCFC execution error when getting packets 1050 * with CRC errors, and allowing instead the invoking of the FW error 1051 * handler. 1052 * This is not done inside the init tool since it currently can't 1053 * perform a pretending to VFs. 1054 */ 1055 max_num_vfs = ECORE_IS_AH(p_hwfn->p_dev) ? MAX_NUM_VFS_K2 1056 : MAX_NUM_VFS_BB; 1057 for (vf_id = 0; vf_id < max_num_vfs; vf_id++) { 1058 concrete_fid = ecore_vfid_to_concrete(p_hwfn, vf_id); 1059 ecore_fid_pretend(p_hwfn, p_ptt, (u16)concrete_fid); 1060 ecore_wr(p_hwfn, p_ptt, CCFC_REG_STRONG_ENABLE_VF, 0x1); 1061 ecore_wr(p_hwfn, p_ptt, CCFC_REG_WEAK_ENABLE_VF, 0x0); 1062 ecore_wr(p_hwfn, p_ptt, TCFC_REG_STRONG_ENABLE_VF, 0x1); 1063 ecore_wr(p_hwfn, p_ptt, TCFC_REG_WEAK_ENABLE_VF, 0x0); 1064 } 1065 /* pretend to original PF */ 1066 ecore_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id); 1067 1068 return rc; 1069 } 1070 1071 #ifndef ASIC_ONLY 1072 #define MISC_REG_RESET_REG_2_XMAC_BIT (1 << 4) 1073 #define MISC_REG_RESET_REG_2_XMAC_SOFT_BIT (1 << 5) 1074 1075 #define PMEG_IF_BYTE_COUNT 8 1076 1077 static void ecore_wr_nw_port(struct ecore_hwfn *p_hwfn, 1078 struct ecore_ptt *p_ptt, 1079 u32 addr, u64 data, u8 reg_type, u8 port) 1080 { 1081 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK, 1082 "CMD: %08x, ADDR: 0x%08x, DATA: %08x:%08x\n", 1083 ecore_rd(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_CMD_BB_B0) | 1084 (8 << PMEG_IF_BYTE_COUNT), 1085 (reg_type << 25) | (addr << 8) | port, 1086 (u32)((data >> 32) & 0xffffffff), 1087 (u32)(data & 0xffffffff)); 1088 1089 ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_CMD_BB_B0, 1090 (ecore_rd(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_CMD_BB_B0) & 1091 0xffff00fe) | (8 << PMEG_IF_BYTE_COUNT)); 1092 ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_ADDR_BB_B0, 1093 (reg_type << 25) | (addr << 8) | port); 1094 ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_WRDATA_BB_B0, 1095 data & 0xffffffff); 1096 ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_WRDATA_BB_B0, 1097 (data >> 32) & 0xffffffff); 1098 } 1099 1100 #define XLPORT_MODE_REG (0x20a) 1101 #define XLPORT_MAC_CONTROL (0x210) 1102 #define XLPORT_FLOW_CONTROL_CONFIG (0x207) 1103 #define XLPORT_ENABLE_REG (0x20b) 1104 1105 #define XLMAC_CTRL (0x600) 1106 #define XLMAC_MODE (0x601) 1107 #define XLMAC_RX_MAX_SIZE (0x608) 1108 #define XLMAC_TX_CTRL (0x604) 1109 #define XLMAC_PAUSE_CTRL (0x60d) 1110 #define XLMAC_PFC_CTRL (0x60e) 1111 1112 static void ecore_emul_link_init_ah(struct ecore_hwfn *p_hwfn, 1113 struct ecore_ptt *p_ptt) 1114 { 1115 u8 port = p_hwfn->port_id; 1116 u32 mac_base = NWM_REG_MAC0 + (port << 2) * NWM_REG_MAC0_SIZE; 1117 1118 ecore_wr(p_hwfn, p_ptt, CNIG_REG_NIG_PORT0_CONF_K2 + (port << 2), 1119 (1 << CNIG_REG_NIG_PORT0_CONF_NIG_PORT_ENABLE_0_SHIFT) | 1120 (port << CNIG_REG_NIG_PORT0_CONF_NIG_PORT_NWM_PORT_MAP_0_SHIFT) 1121 | (0 << CNIG_REG_NIG_PORT0_CONF_NIG_PORT_RATE_0_SHIFT)); 1122 1123 ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_XIF_MODE, 1124 1 << ETH_MAC_REG_XIF_MODE_XGMII_SHIFT); 1125 1126 ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_FRM_LENGTH, 1127 9018 << ETH_MAC_REG_FRM_LENGTH_FRM_LENGTH_SHIFT); 1128 1129 ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_TX_IPG_LENGTH, 1130 0xc << ETH_MAC_REG_TX_IPG_LENGTH_TXIPG_SHIFT); 1131 1132 ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_RX_FIFO_SECTIONS, 1133 8 << ETH_MAC_REG_RX_FIFO_SECTIONS_RX_SECTION_FULL_SHIFT); 1134 1135 ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_TX_FIFO_SECTIONS, 1136 (0xA << ETH_MAC_REG_TX_FIFO_SECTIONS_TX_SECTION_EMPTY_SHIFT) | 1137 (8 << ETH_MAC_REG_TX_FIFO_SECTIONS_TX_SECTION_FULL_SHIFT)); 1138 1139 ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_COMMAND_CONFIG, 0xa853); 1140 } 1141 1142 static void ecore_emul_link_init(struct ecore_hwfn *p_hwfn, 1143 struct ecore_ptt *p_ptt) 1144 { 1145 u8 loopback = 0, port = p_hwfn->port_id * 2; 1146 1147 DP_INFO(p_hwfn->p_dev, "Configurating Emulation Link %02x\n", port); 1148 1149 if (ECORE_IS_AH(p_hwfn->p_dev)) { 1150 ecore_emul_link_init_ah(p_hwfn, p_ptt); 1151 return; 1152 } 1153 1154 /* XLPORT MAC MODE *//* 0 Quad, 4 Single... */ 1155 ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_MODE_REG, (0x4 << 4) | 0x4, 1, 1156 port); 1157 ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_MAC_CONTROL, 0, 1, port); 1158 /* XLMAC: SOFT RESET */ 1159 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_CTRL, 0x40, 0, port); 1160 /* XLMAC: Port Speed >= 10Gbps */ 1161 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_MODE, 0x40, 0, port); 1162 /* XLMAC: Max Size */ 1163 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_RX_MAX_SIZE, 0x3fff, 0, port); 1164 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_TX_CTRL, 1165 0x01000000800ULL | (0xa << 12) | ((u64)1 << 38), 1166 0, port); 1167 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_PAUSE_CTRL, 0x7c000, 0, port); 1168 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_PFC_CTRL, 1169 0x30ffffc000ULL, 0, port); 1170 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_CTRL, 0x3 | (loopback << 2), 0, 1171 port); /* XLMAC: TX_EN, RX_EN */ 1172 /* XLMAC: TX_EN, RX_EN, SW_LINK_STATUS */ 1173 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_CTRL, 1174 0x1003 | (loopback << 2), 0, port); 1175 /* Enabled Parallel PFC interface */ 1176 ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_FLOW_CONTROL_CONFIG, 1, 0, port); 1177 1178 /* XLPORT port enable */ 1179 ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_ENABLE_REG, 0xf, 1, port); 1180 } 1181 1182 static void ecore_link_init(struct ecore_hwfn *p_hwfn, 1183 struct ecore_ptt *p_ptt, u8 port) 1184 { 1185 int port_offset = port ? 0x800 : 0; 1186 u32 xmac_rxctrl = 0; 1187 1188 /* Reset of XMAC */ 1189 /* FIXME: move to common start */ 1190 ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + 2 * sizeof(u32), 1191 MISC_REG_RESET_REG_2_XMAC_BIT); /* Clear */ 1192 OSAL_MSLEEP(1); 1193 ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + sizeof(u32), 1194 MISC_REG_RESET_REG_2_XMAC_BIT); /* Set */ 1195 1196 ecore_wr(p_hwfn, p_ptt, MISC_REG_XMAC_CORE_PORT_MODE, 1); 1197 1198 /* Set the number of ports on the Warp Core to 10G */ 1199 ecore_wr(p_hwfn, p_ptt, MISC_REG_XMAC_PHY_PORT_MODE, 3); 1200 1201 /* Soft reset of XMAC */ 1202 ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + 2 * sizeof(u32), 1203 MISC_REG_RESET_REG_2_XMAC_SOFT_BIT); 1204 OSAL_MSLEEP(1); 1205 ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + sizeof(u32), 1206 MISC_REG_RESET_REG_2_XMAC_SOFT_BIT); 1207 1208 /* FIXME: move to common end */ 1209 if (CHIP_REV_IS_FPGA(p_hwfn->p_dev)) 1210 ecore_wr(p_hwfn, p_ptt, XMAC_REG_MODE + port_offset, 0x20); 1211 1212 /* Set Max packet size: initialize XMAC block register for port 0 */ 1213 ecore_wr(p_hwfn, p_ptt, XMAC_REG_RX_MAX_SIZE + port_offset, 0x2710); 1214 1215 /* CRC append for Tx packets: init XMAC block register for port 1 */ 1216 ecore_wr(p_hwfn, p_ptt, XMAC_REG_TX_CTRL_LO + port_offset, 0xC800); 1217 1218 /* Enable TX and RX: initialize XMAC block register for port 1 */ 1219 ecore_wr(p_hwfn, p_ptt, XMAC_REG_CTRL + port_offset, 1220 XMAC_REG_CTRL_TX_EN | XMAC_REG_CTRL_RX_EN); 1221 xmac_rxctrl = ecore_rd(p_hwfn, p_ptt, XMAC_REG_RX_CTRL + port_offset); 1222 xmac_rxctrl |= XMAC_REG_RX_CTRL_PROCESS_VARIABLE_PREAMBLE; 1223 ecore_wr(p_hwfn, p_ptt, XMAC_REG_RX_CTRL + port_offset, xmac_rxctrl); 1224 } 1225 #endif 1226 1227 static enum _ecore_status_t ecore_hw_init_port(struct ecore_hwfn *p_hwfn, 1228 struct ecore_ptt *p_ptt, 1229 int hw_mode) 1230 { 1231 enum _ecore_status_t rc = ECORE_SUCCESS; 1232 1233 rc = ecore_init_run(p_hwfn, p_ptt, PHASE_PORT, p_hwfn->port_id, 1234 hw_mode); 1235 if (rc != ECORE_SUCCESS) 1236 return rc; 1237 #ifndef ASIC_ONLY 1238 if (CHIP_REV_IS_ASIC(p_hwfn->p_dev)) 1239 return ECORE_SUCCESS; 1240 1241 if (CHIP_REV_IS_FPGA(p_hwfn->p_dev)) { 1242 if (ECORE_IS_AH(p_hwfn->p_dev)) 1243 return ECORE_SUCCESS; 1244 ecore_link_init(p_hwfn, p_ptt, p_hwfn->port_id); 1245 } else if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) { 1246 if (p_hwfn->p_dev->num_hwfns > 1) { 1247 /* Activate OPTE in CMT */ 1248 u32 val; 1249 1250 val = ecore_rd(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV); 1251 val |= 0x10; 1252 ecore_wr(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV, val); 1253 ecore_wr(p_hwfn, p_ptt, MISC_REG_CLK_100G_MODE, 1); 1254 ecore_wr(p_hwfn, p_ptt, MISCS_REG_CLK_100G_MODE, 1); 1255 ecore_wr(p_hwfn, p_ptt, MISC_REG_OPTE_MODE, 1); 1256 ecore_wr(p_hwfn, p_ptt, 1257 NIG_REG_LLH_ENG_CLS_TCP_4_TUPLE_SEARCH, 1); 1258 ecore_wr(p_hwfn, p_ptt, 1259 NIG_REG_LLH_ENG_CLS_ENG_ID_TBL, 0x55555555); 1260 ecore_wr(p_hwfn, p_ptt, 1261 NIG_REG_LLH_ENG_CLS_ENG_ID_TBL + 0x4, 1262 0x55555555); 1263 } 1264 1265 ecore_emul_link_init(p_hwfn, p_ptt); 1266 } else { 1267 DP_INFO(p_hwfn->p_dev, "link is not being configured\n"); 1268 } 1269 #endif 1270 1271 return rc; 1272 } 1273 1274 static enum _ecore_status_t 1275 ecore_hw_init_dpi_size(struct ecore_hwfn *p_hwfn, 1276 struct ecore_ptt *p_ptt, u32 pwm_region_size, u32 n_cpus) 1277 { 1278 u32 dpi_page_size_1, dpi_page_size_2, dpi_page_size; 1279 u32 dpi_bit_shift, dpi_count; 1280 u32 min_dpis; 1281 1282 /* Calculate DPI size 1283 * ------------------ 1284 * The PWM region contains Doorbell Pages. The first is reserverd for 1285 * the kernel for, e.g, L2. The others are free to be used by non- 1286 * trusted applications, typically from user space. Each page, called a 1287 * doorbell page is sectioned into windows that allow doorbells to be 1288 * issued in parallel by the kernel/application. The size of such a 1289 * window (a.k.a. WID) is 1kB. 1290 * Summary: 1291 * 1kB WID x N WIDS = DPI page size 1292 * DPI page size x N DPIs = PWM region size 1293 * Notes: 1294 * The size of the DPI page size must be in multiples of OSAL_PAGE_SIZE 1295 * in order to ensure that two applications won't share the same page. 1296 * It also must contain at least one WID per CPU to allow parallelism. 1297 * It also must be a power of 2, since it is stored as a bit shift. 1298 * 1299 * The DPI page size is stored in a register as 'dpi_bit_shift' so that 1300 * 0 is 4kB, 1 is 8kB and etc. Hence the minimum size is 4,096 1301 * containing 4 WIDs. 1302 */ 1303 dpi_page_size_1 = ECORE_WID_SIZE * n_cpus; 1304 dpi_page_size_2 = OSAL_MAX_T(u32, ECORE_WID_SIZE, OSAL_PAGE_SIZE); 1305 dpi_page_size = OSAL_MAX_T(u32, dpi_page_size_1, dpi_page_size_2); 1306 dpi_page_size = OSAL_ROUNDUP_POW_OF_TWO(dpi_page_size); 1307 dpi_bit_shift = OSAL_LOG2(dpi_page_size / 4096); 1308 1309 dpi_count = pwm_region_size / dpi_page_size; 1310 1311 min_dpis = p_hwfn->pf_params.rdma_pf_params.min_dpis; 1312 min_dpis = OSAL_MAX_T(u32, ECORE_MIN_DPIS, min_dpis); 1313 1314 /* Update hwfn */ 1315 p_hwfn->dpi_size = dpi_page_size; 1316 p_hwfn->dpi_count = dpi_count; 1317 1318 /* Update registers */ 1319 ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_DPI_BIT_SHIFT, dpi_bit_shift); 1320 1321 if (dpi_count < min_dpis) 1322 return ECORE_NORESOURCES; 1323 1324 return ECORE_SUCCESS; 1325 } 1326 1327 enum ECORE_ROCE_EDPM_MODE { 1328 ECORE_ROCE_EDPM_MODE_ENABLE = 0, 1329 ECORE_ROCE_EDPM_MODE_FORCE_ON = 1, 1330 ECORE_ROCE_EDPM_MODE_DISABLE = 2, 1331 }; 1332 1333 static enum _ecore_status_t 1334 ecore_hw_init_pf_doorbell_bar(struct ecore_hwfn *p_hwfn, 1335 struct ecore_ptt *p_ptt) 1336 { 1337 u32 pwm_regsize, norm_regsize; 1338 u32 non_pwm_conn, min_addr_reg1; 1339 u32 db_bar_size, n_cpus; 1340 u32 roce_edpm_mode; 1341 u32 pf_dems_shift; 1342 int rc = ECORE_SUCCESS; 1343 u8 cond; 1344 1345 db_bar_size = ecore_hw_bar_size(p_hwfn, BAR_ID_1); 1346 if (p_hwfn->p_dev->num_hwfns > 1) 1347 db_bar_size /= 2; 1348 1349 /* Calculate doorbell regions 1350 * ----------------------------------- 1351 * The doorbell BAR is made of two regions. The first is called normal 1352 * region and the second is called PWM region. In the normal region 1353 * each ICID has its own set of addresses so that writing to that 1354 * specific address identifies the ICID. In the Process Window Mode 1355 * region the ICID is given in the data written to the doorbell. The 1356 * above per PF register denotes the offset in the doorbell BAR in which 1357 * the PWM region begins. 1358 * The normal region has ECORE_PF_DEMS_SIZE bytes per ICID, that is per 1359 * non-PWM connection. The calculation below computes the total non-PWM 1360 * connections. The DORQ_REG_PF_MIN_ADDR_REG1 register is 1361 * in units of 4,096 bytes. 1362 */ 1363 non_pwm_conn = ecore_cxt_get_proto_cid_start(p_hwfn, PROTOCOLID_CORE) + 1364 ecore_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_CORE, 1365 OSAL_NULL) + 1366 ecore_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_ETH, OSAL_NULL); 1367 norm_regsize = ROUNDUP(ECORE_PF_DEMS_SIZE * non_pwm_conn, 4096); 1368 min_addr_reg1 = norm_regsize / 4096; 1369 pwm_regsize = db_bar_size - norm_regsize; 1370 1371 /* Check that the normal and PWM sizes are valid */ 1372 if (db_bar_size < norm_regsize) { 1373 DP_ERR(p_hwfn->p_dev, 1374 "Doorbell BAR size 0x%x is too small (normal region is 0x%0x )\n", 1375 db_bar_size, norm_regsize); 1376 return ECORE_NORESOURCES; 1377 } 1378 if (pwm_regsize < ECORE_MIN_PWM_REGION) { 1379 DP_ERR(p_hwfn->p_dev, 1380 "PWM region size 0x%0x is too small. Should be at least 0x%0x (Doorbell BAR size is 0x%x and normal region size is 0x%0x)\n", 1381 pwm_regsize, ECORE_MIN_PWM_REGION, db_bar_size, 1382 norm_regsize); 1383 return ECORE_NORESOURCES; 1384 } 1385 1386 /* Calculate number of DPIs */ 1387 roce_edpm_mode = p_hwfn->pf_params.rdma_pf_params.roce_edpm_mode; 1388 if ((roce_edpm_mode == ECORE_ROCE_EDPM_MODE_ENABLE) || 1389 ((roce_edpm_mode == ECORE_ROCE_EDPM_MODE_FORCE_ON))) { 1390 /* Either EDPM is mandatory, or we are attempting to allocate a 1391 * WID per CPU. 1392 */ 1393 n_cpus = OSAL_NUM_ACTIVE_CPU(); 1394 rc = ecore_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus); 1395 } 1396 1397 cond = ((rc) && (roce_edpm_mode == ECORE_ROCE_EDPM_MODE_ENABLE)) || 1398 (roce_edpm_mode == ECORE_ROCE_EDPM_MODE_DISABLE); 1399 if (cond || p_hwfn->dcbx_no_edpm) { 1400 /* Either EDPM is disabled from user configuration, or it is 1401 * disabled via DCBx, or it is not mandatory and we failed to 1402 * allocated a WID per CPU. 1403 */ 1404 n_cpus = 1; 1405 rc = ecore_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus); 1406 1407 /* If we entered this flow due to DCBX then the DPM register is 1408 * already configured. 1409 */ 1410 } 1411 1412 DP_INFO(p_hwfn, 1413 "doorbell bar: normal_region_size=%d, pwm_region_size=%d", 1414 norm_regsize, pwm_regsize); 1415 DP_INFO(p_hwfn, 1416 " dpi_size=%d, dpi_count=%d, roce_edpm=%s\n", 1417 p_hwfn->dpi_size, p_hwfn->dpi_count, 1418 ((p_hwfn->dcbx_no_edpm) || (p_hwfn->db_bar_no_edpm)) ? 1419 "disabled" : "enabled"); 1420 1421 /* Check return codes from above calls */ 1422 if (rc) { 1423 DP_ERR(p_hwfn, 1424 "Failed to allocate enough DPIs\n"); 1425 return ECORE_NORESOURCES; 1426 } 1427 1428 /* Update hwfn */ 1429 p_hwfn->dpi_start_offset = norm_regsize; 1430 1431 /* Update registers */ 1432 /* DEMS size is configured log2 of DWORDs, hence the division by 4 */ 1433 pf_dems_shift = OSAL_LOG2(ECORE_PF_DEMS_SIZE / 4); 1434 ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_ICID_BIT_SHIFT_NORM, pf_dems_shift); 1435 ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_MIN_ADDR_REG1, min_addr_reg1); 1436 1437 return ECORE_SUCCESS; 1438 } 1439 1440 static enum _ecore_status_t 1441 ecore_hw_init_pf(struct ecore_hwfn *p_hwfn, 1442 struct ecore_ptt *p_ptt, 1443 struct ecore_tunn_start_params *p_tunn, 1444 int hw_mode, 1445 bool b_hw_start, 1446 enum ecore_int_mode int_mode, bool allow_npar_tx_switch) 1447 { 1448 u8 rel_pf_id = p_hwfn->rel_pf_id; 1449 u32 prs_reg; 1450 enum _ecore_status_t rc = ECORE_SUCCESS; 1451 u16 ctrl; 1452 int pos; 1453 1454 if (p_hwfn->mcp_info) { 1455 struct ecore_mcp_function_info *p_info; 1456 1457 p_info = &p_hwfn->mcp_info->func_info; 1458 if (p_info->bandwidth_min) 1459 p_hwfn->qm_info.pf_wfq = p_info->bandwidth_min; 1460 1461 /* Update rate limit once we'll actually have a link */ 1462 p_hwfn->qm_info.pf_rl = 100000; 1463 } 1464 ecore_cxt_hw_init_pf(p_hwfn); 1465 1466 ecore_int_igu_init_rt(p_hwfn); 1467 1468 /* Set VLAN in NIG if needed */ 1469 if (hw_mode & (1 << MODE_MF_SD)) { 1470 DP_VERBOSE(p_hwfn, ECORE_MSG_HW, "Configuring LLH_FUNC_TAG\n"); 1471 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_EN_RT_OFFSET, 1); 1472 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_VALUE_RT_OFFSET, 1473 p_hwfn->hw_info.ovlan); 1474 } 1475 1476 /* Enable classification by MAC if needed */ 1477 if (hw_mode & (1 << MODE_MF_SI)) { 1478 DP_VERBOSE(p_hwfn, ECORE_MSG_HW, 1479 "Configuring TAGMAC_CLS_TYPE\n"); 1480 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAGMAC_CLS_TYPE_RT_OFFSET, 1481 1); 1482 } 1483 1484 /* Protocl Configuration - @@@TBD - should we set 0 otherwise? */ 1485 STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_TCP_RT_OFFSET, 1486 (p_hwfn->hw_info.personality == ECORE_PCI_ISCSI) ? 1 : 0); 1487 STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_FCOE_RT_OFFSET, 1488 (p_hwfn->hw_info.personality == ECORE_PCI_FCOE) ? 1 : 0); 1489 STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_ROCE_RT_OFFSET, 0); 1490 1491 /* perform debug configuration when chip is out of reset */ 1492 OSAL_BEFORE_PF_START((void *)p_hwfn->p_dev, p_hwfn->my_id); 1493 1494 /* Cleanup chip from previous driver if such remains exist */ 1495 rc = ecore_final_cleanup(p_hwfn, p_ptt, rel_pf_id, false); 1496 if (rc != ECORE_SUCCESS) { 1497 ecore_hw_err_notify(p_hwfn, ECORE_HW_ERR_RAMROD_FAIL); 1498 return rc; 1499 } 1500 1501 /* PF Init sequence */ 1502 rc = ecore_init_run(p_hwfn, p_ptt, PHASE_PF, rel_pf_id, hw_mode); 1503 if (rc) 1504 return rc; 1505 1506 /* QM_PF Init sequence (may be invoked separately e.g. for DCB) */ 1507 rc = ecore_init_run(p_hwfn, p_ptt, PHASE_QM_PF, rel_pf_id, hw_mode); 1508 if (rc) 1509 return rc; 1510 1511 /* Pure runtime initializations - directly to the HW */ 1512 ecore_int_igu_init_pure_rt(p_hwfn, p_ptt, true, true); 1513 1514 /* PCI relaxed ordering causes a decrease in the performance on some 1515 * systems. Till a root cause is found, disable this attribute in the 1516 * PCI config space. 1517 */ 1518 /* Not in use @DPDK 1519 * pos = OSAL_PCI_FIND_CAPABILITY(p_hwfn->p_dev, PCI_CAP_ID_EXP); 1520 * if (!pos) { 1521 * DP_NOTICE(p_hwfn, true, 1522 * "Failed to find the PCIe Cap\n"); 1523 * return ECORE_IO; 1524 * } 1525 * OSAL_PCI_READ_CONFIG_WORD(p_hwfn->p_dev, pos + PCI_EXP_DEVCTL, &ctrl); 1526 * ctrl &= ~PCI_EXP_DEVCTL_RELAX_EN; 1527 * OSAL_PCI_WRITE_CONFIG_WORD(p_hwfn->p_dev, pos + PCI_EXP_DEVCTL, ctrl); 1528 */ 1529 1530 rc = ecore_hw_init_pf_doorbell_bar(p_hwfn, p_ptt); 1531 if (rc) 1532 return rc; 1533 if (b_hw_start) { 1534 /* enable interrupts */ 1535 ecore_int_igu_enable(p_hwfn, p_ptt, int_mode); 1536 1537 /* send function start command */ 1538 rc = ecore_sp_pf_start(p_hwfn, p_tunn, p_hwfn->p_dev->mf_mode, 1539 allow_npar_tx_switch); 1540 if (rc) { 1541 DP_NOTICE(p_hwfn, true, 1542 "Function start ramrod failed\n"); 1543 } else { 1544 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1); 1545 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE, 1546 "PRS_REG_SEARCH_TAG1: %x\n", prs_reg); 1547 1548 if (p_hwfn->hw_info.personality == ECORE_PCI_FCOE) { 1549 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1, 1550 (1 << 2)); 1551 ecore_wr(p_hwfn, p_ptt, 1552 PRS_REG_PKT_LEN_STAT_TAGS_NOT_COUNTED_FIRST, 1553 0x100); 1554 } 1555 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE, 1556 "PRS_REG_SEARCH registers after start PFn\n"); 1557 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP); 1558 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE, 1559 "PRS_REG_SEARCH_TCP: %x\n", prs_reg); 1560 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP); 1561 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE, 1562 "PRS_REG_SEARCH_UDP: %x\n", prs_reg); 1563 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE); 1564 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE, 1565 "PRS_REG_SEARCH_FCOE: %x\n", prs_reg); 1566 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE); 1567 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE, 1568 "PRS_REG_SEARCH_ROCE: %x\n", prs_reg); 1569 prs_reg = ecore_rd(p_hwfn, p_ptt, 1570 PRS_REG_SEARCH_TCP_FIRST_FRAG); 1571 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE, 1572 "PRS_REG_SEARCH_TCP_FIRST_FRAG: %x\n", 1573 prs_reg); 1574 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1); 1575 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE, 1576 "PRS_REG_SEARCH_TAG1: %x\n", prs_reg); 1577 } 1578 } 1579 return rc; 1580 } 1581 1582 static enum _ecore_status_t 1583 ecore_change_pci_hwfn(struct ecore_hwfn *p_hwfn, 1584 struct ecore_ptt *p_ptt, u8 enable) 1585 { 1586 u32 delay_idx = 0, val, set_val = enable ? 1 : 0; 1587 1588 /* Change PF in PXP */ 1589 ecore_wr(p_hwfn, p_ptt, 1590 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, set_val); 1591 1592 /* wait until value is set - try for 1 second every 50us */ 1593 for (delay_idx = 0; delay_idx < 20000; delay_idx++) { 1594 val = ecore_rd(p_hwfn, p_ptt, 1595 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER); 1596 if (val == set_val) 1597 break; 1598 1599 OSAL_UDELAY(50); 1600 } 1601 1602 if (val != set_val) { 1603 DP_NOTICE(p_hwfn, true, 1604 "PFID_ENABLE_MASTER wasn't changed after a second\n"); 1605 return ECORE_UNKNOWN_ERROR; 1606 } 1607 1608 return ECORE_SUCCESS; 1609 } 1610 1611 static void ecore_reset_mb_shadow(struct ecore_hwfn *p_hwfn, 1612 struct ecore_ptt *p_main_ptt) 1613 { 1614 /* Read shadow of current MFW mailbox */ 1615 ecore_mcp_read_mb(p_hwfn, p_main_ptt); 1616 OSAL_MEMCPY(p_hwfn->mcp_info->mfw_mb_shadow, 1617 p_hwfn->mcp_info->mfw_mb_cur, 1618 p_hwfn->mcp_info->mfw_mb_length); 1619 } 1620 1621 enum _ecore_status_t ecore_hw_init(struct ecore_dev *p_dev, 1622 struct ecore_hw_init_params *p_params) 1623 { 1624 enum _ecore_status_t rc, mfw_rc; 1625 u32 load_code, param; 1626 int i, j; 1627 1628 if (p_params->int_mode == ECORE_INT_MODE_MSI && p_dev->num_hwfns > 1) { 1629 DP_NOTICE(p_dev, false, 1630 "MSI mode is not supported for CMT devices\n"); 1631 return ECORE_INVAL; 1632 } 1633 1634 if (IS_PF(p_dev)) { 1635 rc = ecore_init_fw_data(p_dev, p_params->bin_fw_data); 1636 if (rc != ECORE_SUCCESS) 1637 return rc; 1638 } 1639 1640 for_each_hwfn(p_dev, i) { 1641 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i]; 1642 1643 if (IS_VF(p_dev)) { 1644 p_hwfn->b_int_enabled = 1; 1645 continue; 1646 } 1647 1648 /* Enable DMAE in PXP */ 1649 rc = ecore_change_pci_hwfn(p_hwfn, p_hwfn->p_main_ptt, true); 1650 if (rc != ECORE_SUCCESS) 1651 return rc; 1652 1653 rc = ecore_calc_hw_mode(p_hwfn); 1654 if (rc != ECORE_SUCCESS) 1655 return rc; 1656 1657 /* @@@TBD need to add here: 1658 * Check for fan failure 1659 * Prev_unload 1660 */ 1661 rc = ecore_mcp_load_req(p_hwfn, p_hwfn->p_main_ptt, &load_code); 1662 if (rc) { 1663 DP_NOTICE(p_hwfn, true, 1664 "Failed sending LOAD_REQ command\n"); 1665 return rc; 1666 } 1667 1668 /* CQ75580: 1669 * When coming back from hiberbate state, the registers from 1670 * which shadow is read initially are not initialized. It turns 1671 * out that these registers get initialized during the call to 1672 * ecore_mcp_load_req request. So we need to reread them here 1673 * to get the proper shadow register value. 1674 * Note: This is a workaround for the missinginig MFW 1675 * initialization. It may be removed once the implementation 1676 * is done. 1677 */ 1678 ecore_reset_mb_shadow(p_hwfn, p_hwfn->p_main_ptt); 1679 1680 DP_VERBOSE(p_hwfn, ECORE_MSG_SP, 1681 "Load request was sent. Resp:0x%x, Load code: 0x%x\n", 1682 rc, load_code); 1683 1684 /* Only relevant for recovery: 1685 * Clear the indication after the LOAD_REQ command is responded 1686 * by the MFW. 1687 */ 1688 p_dev->recov_in_prog = false; 1689 1690 p_hwfn->first_on_engine = (load_code == 1691 FW_MSG_CODE_DRV_LOAD_ENGINE); 1692 1693 if (!qm_lock_init) { 1694 OSAL_SPIN_LOCK_INIT(&qm_lock); 1695 qm_lock_init = true; 1696 } 1697 1698 switch (load_code) { 1699 case FW_MSG_CODE_DRV_LOAD_ENGINE: 1700 rc = ecore_hw_init_common(p_hwfn, p_hwfn->p_main_ptt, 1701 p_hwfn->hw_info.hw_mode); 1702 if (rc) 1703 break; 1704 /* Fall into */ 1705 case FW_MSG_CODE_DRV_LOAD_PORT: 1706 rc = ecore_hw_init_port(p_hwfn, p_hwfn->p_main_ptt, 1707 p_hwfn->hw_info.hw_mode); 1708 if (rc) 1709 break; 1710 1711 #ifndef REAL_ASIC_ONLY 1712 if (ENABLE_EAGLE_ENG1_WORKAROUND(p_hwfn)) { 1713 struct init_nig_pri_tc_map_req tc_map; 1714 1715 OSAL_MEM_ZERO(&tc_map, sizeof(tc_map)); 1716 1717 /* remove this once flow control is 1718 * implemented 1719 */ 1720 for (j = 0; j < NUM_OF_VLAN_PRIORITIES; j++) { 1721 tc_map.pri[j].tc_id = 0; 1722 tc_map.pri[j].valid = 1; 1723 } 1724 ecore_init_nig_pri_tc_map(p_hwfn, 1725 p_hwfn->p_main_ptt, 1726 &tc_map); 1727 } 1728 #endif 1729 /* Fall into */ 1730 case FW_MSG_CODE_DRV_LOAD_FUNCTION: 1731 rc = ecore_hw_init_pf(p_hwfn, p_hwfn->p_main_ptt, 1732 p_params->p_tunn, 1733 p_hwfn->hw_info.hw_mode, 1734 p_params->b_hw_start, 1735 p_params->int_mode, 1736 p_params->allow_npar_tx_switch); 1737 break; 1738 default: 1739 rc = ECORE_NOTIMPL; 1740 break; 1741 } 1742 1743 if (rc != ECORE_SUCCESS) 1744 DP_NOTICE(p_hwfn, true, 1745 "init phase failed for loadcode 0x%x (rc %d)\n", 1746 load_code, rc); 1747 1748 /* ACK mfw regardless of success or failure of initialization */ 1749 mfw_rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt, 1750 DRV_MSG_CODE_LOAD_DONE, 1751 0, &load_code, ¶m); 1752 if (rc != ECORE_SUCCESS) 1753 return rc; 1754 if (mfw_rc != ECORE_SUCCESS) { 1755 DP_NOTICE(p_hwfn, true, 1756 "Failed sending LOAD_DONE command\n"); 1757 return mfw_rc; 1758 } 1759 1760 ecore_mcp_mdump_get_info(p_hwfn, p_hwfn->p_main_ptt); 1761 ecore_mcp_mdump_set_values(p_hwfn, p_hwfn->p_main_ptt, 1762 p_params->epoch); 1763 1764 /* send DCBX attention request command */ 1765 DP_VERBOSE(p_hwfn, ECORE_MSG_DCB, 1766 "sending phony dcbx set command to trigger DCBx attention handling\n"); 1767 mfw_rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt, 1768 DRV_MSG_CODE_SET_DCBX, 1769 1 << DRV_MB_PARAM_DCBX_NOTIFY_SHIFT, 1770 &load_code, ¶m); 1771 if (mfw_rc != ECORE_SUCCESS) { 1772 DP_NOTICE(p_hwfn, true, 1773 "Failed to send DCBX attention request\n"); 1774 return mfw_rc; 1775 } 1776 1777 p_hwfn->hw_init_done = true; 1778 } 1779 1780 return ECORE_SUCCESS; 1781 } 1782 1783 #define ECORE_HW_STOP_RETRY_LIMIT (10) 1784 static void ecore_hw_timers_stop(struct ecore_dev *p_dev, 1785 struct ecore_hwfn *p_hwfn, 1786 struct ecore_ptt *p_ptt) 1787 { 1788 int i; 1789 1790 /* close timers */ 1791 ecore_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_CONN, 0x0); 1792 ecore_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_TASK, 0x0); 1793 for (i = 0; i < ECORE_HW_STOP_RETRY_LIMIT && !p_dev->recov_in_prog; 1794 i++) { 1795 if ((!ecore_rd(p_hwfn, p_ptt, 1796 TM_REG_PF_SCAN_ACTIVE_CONN)) && 1797 (!ecore_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK))) 1798 break; 1799 1800 /* Dependent on number of connection/tasks, possibly 1801 * 1ms sleep is required between polls 1802 */ 1803 OSAL_MSLEEP(1); 1804 } 1805 if (i == ECORE_HW_STOP_RETRY_LIMIT) 1806 DP_NOTICE(p_hwfn, true, 1807 "Timers linear scans are not over [Connection %02x Tasks %02x]\n", 1808 (u8)ecore_rd(p_hwfn, p_ptt, 1809 TM_REG_PF_SCAN_ACTIVE_CONN), 1810 (u8)ecore_rd(p_hwfn, p_ptt, 1811 TM_REG_PF_SCAN_ACTIVE_TASK)); 1812 } 1813 1814 void ecore_hw_timers_stop_all(struct ecore_dev *p_dev) 1815 { 1816 int j; 1817 1818 for_each_hwfn(p_dev, j) { 1819 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j]; 1820 struct ecore_ptt *p_ptt = p_hwfn->p_main_ptt; 1821 1822 ecore_hw_timers_stop(p_dev, p_hwfn, p_ptt); 1823 } 1824 } 1825 1826 enum _ecore_status_t ecore_hw_stop(struct ecore_dev *p_dev) 1827 { 1828 enum _ecore_status_t rc = ECORE_SUCCESS, t_rc; 1829 int j; 1830 1831 for_each_hwfn(p_dev, j) { 1832 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j]; 1833 struct ecore_ptt *p_ptt = p_hwfn->p_main_ptt; 1834 1835 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN, "Stopping hw/fw\n"); 1836 1837 if (IS_VF(p_dev)) { 1838 ecore_vf_pf_int_cleanup(p_hwfn); 1839 continue; 1840 } 1841 1842 /* mark the hw as uninitialized... */ 1843 p_hwfn->hw_init_done = false; 1844 1845 rc = ecore_sp_pf_stop(p_hwfn); 1846 if (rc) 1847 DP_NOTICE(p_hwfn, true, 1848 "Failed to close PF against FW. Continue to stop HW to prevent illegal host access by the device\n"); 1849 1850 /* perform debug action after PF stop was sent */ 1851 OSAL_AFTER_PF_STOP((void *)p_hwfn->p_dev, p_hwfn->my_id); 1852 1853 /* close NIG to BRB gate */ 1854 ecore_wr(p_hwfn, p_ptt, 1855 NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1); 1856 1857 /* close parser */ 1858 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0); 1859 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0); 1860 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0); 1861 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0); 1862 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0); 1863 1864 /* @@@TBD - clean transmission queues (5.b) */ 1865 /* @@@TBD - clean BTB (5.c) */ 1866 1867 ecore_hw_timers_stop(p_dev, p_hwfn, p_ptt); 1868 1869 /* @@@TBD - verify DMAE requests are done (8) */ 1870 1871 /* Disable Attention Generation */ 1872 ecore_int_igu_disable_int(p_hwfn, p_ptt); 1873 ecore_wr(p_hwfn, p_ptt, IGU_REG_LEADING_EDGE_LATCH, 0); 1874 ecore_wr(p_hwfn, p_ptt, IGU_REG_TRAILING_EDGE_LATCH, 0); 1875 ecore_int_igu_init_pure_rt(p_hwfn, p_ptt, false, true); 1876 /* Need to wait 1ms to guarantee SBs are cleared */ 1877 OSAL_MSLEEP(1); 1878 } 1879 1880 if (IS_PF(p_dev)) { 1881 /* Disable DMAE in PXP - in CMT, this should only be done for 1882 * first hw-function, and only after all transactions have 1883 * stopped for all active hw-functions. 1884 */ 1885 t_rc = ecore_change_pci_hwfn(&p_dev->hwfns[0], 1886 p_dev->hwfns[0].p_main_ptt, false); 1887 if (t_rc != ECORE_SUCCESS) 1888 rc = t_rc; 1889 } 1890 1891 return rc; 1892 } 1893 1894 void ecore_hw_stop_fastpath(struct ecore_dev *p_dev) 1895 { 1896 int j; 1897 1898 for_each_hwfn(p_dev, j) { 1899 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j]; 1900 struct ecore_ptt *p_ptt = p_hwfn->p_main_ptt; 1901 1902 if (IS_VF(p_dev)) { 1903 ecore_vf_pf_int_cleanup(p_hwfn); 1904 continue; 1905 } 1906 1907 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN, 1908 "Shutting down the fastpath\n"); 1909 1910 ecore_wr(p_hwfn, p_ptt, 1911 NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1); 1912 1913 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0); 1914 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0); 1915 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0); 1916 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0); 1917 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0); 1918 1919 /* @@@TBD - clean transmission queues (5.b) */ 1920 /* @@@TBD - clean BTB (5.c) */ 1921 1922 /* @@@TBD - verify DMAE requests are done (8) */ 1923 1924 ecore_int_igu_init_pure_rt(p_hwfn, p_ptt, false, false); 1925 /* Need to wait 1ms to guarantee SBs are cleared */ 1926 OSAL_MSLEEP(1); 1927 } 1928 } 1929 1930 void ecore_hw_start_fastpath(struct ecore_hwfn *p_hwfn) 1931 { 1932 struct ecore_ptt *p_ptt = p_hwfn->p_main_ptt; 1933 1934 if (IS_VF(p_hwfn->p_dev)) 1935 return; 1936 1937 /* If roce info is allocated it means roce is initialized and should 1938 * be enabled in searcher. 1939 */ 1940 if (p_hwfn->p_rdma_info) { 1941 if (p_hwfn->b_rdma_enabled_in_prs) 1942 ecore_wr(p_hwfn, p_ptt, 1943 p_hwfn->rdma_prs_search_reg, 0x1); 1944 ecore_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_CONN, 0x1); 1945 } 1946 1947 /* Re-open incoming traffic */ 1948 ecore_wr(p_hwfn, p_hwfn->p_main_ptt, 1949 NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x0); 1950 } 1951 1952 static enum _ecore_status_t ecore_reg_assert(struct ecore_hwfn *p_hwfn, 1953 struct ecore_ptt *p_ptt, u32 reg, 1954 bool expected) 1955 { 1956 u32 assert_val = ecore_rd(p_hwfn, p_ptt, reg); 1957 1958 if (assert_val != expected) { 1959 DP_NOTICE(p_hwfn, true, "Value at address 0x%08x != 0x%08x\n", 1960 reg, expected); 1961 return ECORE_UNKNOWN_ERROR; 1962 } 1963 1964 return 0; 1965 } 1966 1967 enum _ecore_status_t ecore_hw_reset(struct ecore_dev *p_dev) 1968 { 1969 enum _ecore_status_t rc = ECORE_SUCCESS; 1970 u32 unload_resp, unload_param; 1971 int i; 1972 1973 for_each_hwfn(p_dev, i) { 1974 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i]; 1975 1976 if (IS_VF(p_dev)) { 1977 rc = ecore_vf_pf_reset(p_hwfn); 1978 if (rc) 1979 return rc; 1980 continue; 1981 } 1982 1983 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN, "Resetting hw/fw\n"); 1984 1985 /* Check for incorrect states */ 1986 if (!p_dev->recov_in_prog) { 1987 ecore_reg_assert(p_hwfn, p_hwfn->p_main_ptt, 1988 QM_REG_USG_CNT_PF_TX, 0); 1989 ecore_reg_assert(p_hwfn, p_hwfn->p_main_ptt, 1990 QM_REG_USG_CNT_PF_OTHER, 0); 1991 /* @@@TBD - assert on incorrect xCFC values (10.b) */ 1992 } 1993 1994 /* Disable PF in HW blocks */ 1995 ecore_wr(p_hwfn, p_hwfn->p_main_ptt, DORQ_REG_PF_DB_ENABLE, 0); 1996 ecore_wr(p_hwfn, p_hwfn->p_main_ptt, QM_REG_PF_EN, 0); 1997 1998 if (p_dev->recov_in_prog) { 1999 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN, 2000 "Recovery is in progress -> skip sending unload_req/done\n"); 2001 break; 2002 } 2003 2004 /* Send unload command to MCP */ 2005 rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt, 2006 DRV_MSG_CODE_UNLOAD_REQ, 2007 DRV_MB_PARAM_UNLOAD_WOL_MCP, 2008 &unload_resp, &unload_param); 2009 if (rc != ECORE_SUCCESS) { 2010 DP_NOTICE(p_hwfn, true, 2011 "ecore_hw_reset: UNLOAD_REQ failed\n"); 2012 /* @@TBD - what to do? for now, assume ENG. */ 2013 unload_resp = FW_MSG_CODE_DRV_UNLOAD_ENGINE; 2014 } 2015 2016 rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt, 2017 DRV_MSG_CODE_UNLOAD_DONE, 2018 0, &unload_resp, &unload_param); 2019 if (rc != ECORE_SUCCESS) { 2020 DP_NOTICE(p_hwfn, 2021 true, "ecore_hw_reset: UNLOAD_DONE failed\n"); 2022 /* @@@TBD - Should it really ASSERT here ? */ 2023 return rc; 2024 } 2025 } 2026 2027 return rc; 2028 } 2029 2030 /* Free hwfn memory and resources acquired in hw_hwfn_prepare */ 2031 static void ecore_hw_hwfn_free(struct ecore_hwfn *p_hwfn) 2032 { 2033 ecore_ptt_pool_free(p_hwfn); 2034 OSAL_FREE(p_hwfn->p_dev, p_hwfn->hw_info.p_igu_info); 2035 } 2036 2037 /* Setup bar access */ 2038 static void ecore_hw_hwfn_prepare(struct ecore_hwfn *p_hwfn) 2039 { 2040 /* clear indirect access */ 2041 if (ECORE_IS_AH(p_hwfn->p_dev)) { 2042 ecore_wr(p_hwfn, p_hwfn->p_main_ptt, 2043 PGLUE_B_REG_PGL_ADDR_E8_F0, 0); 2044 ecore_wr(p_hwfn, p_hwfn->p_main_ptt, 2045 PGLUE_B_REG_PGL_ADDR_EC_F0, 0); 2046 ecore_wr(p_hwfn, p_hwfn->p_main_ptt, 2047 PGLUE_B_REG_PGL_ADDR_F0_F0, 0); 2048 ecore_wr(p_hwfn, p_hwfn->p_main_ptt, 2049 PGLUE_B_REG_PGL_ADDR_F4_F0, 0); 2050 } else { 2051 ecore_wr(p_hwfn, p_hwfn->p_main_ptt, 2052 PGLUE_B_REG_PGL_ADDR_88_F0, 0); 2053 ecore_wr(p_hwfn, p_hwfn->p_main_ptt, 2054 PGLUE_B_REG_PGL_ADDR_8C_F0, 0); 2055 ecore_wr(p_hwfn, p_hwfn->p_main_ptt, 2056 PGLUE_B_REG_PGL_ADDR_90_F0, 0); 2057 ecore_wr(p_hwfn, p_hwfn->p_main_ptt, 2058 PGLUE_B_REG_PGL_ADDR_94_F0, 0); 2059 } 2060 2061 /* Clean Previous errors if such exist */ 2062 ecore_wr(p_hwfn, p_hwfn->p_main_ptt, 2063 PGLUE_B_REG_WAS_ERROR_PF_31_0_CLR, 1 << p_hwfn->abs_pf_id); 2064 2065 /* enable internal target-read */ 2066 ecore_wr(p_hwfn, p_hwfn->p_main_ptt, 2067 PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1); 2068 } 2069 2070 static void get_function_id(struct ecore_hwfn *p_hwfn) 2071 { 2072 /* ME Register */ 2073 p_hwfn->hw_info.opaque_fid = (u16)REG_RD(p_hwfn, 2074 PXP_PF_ME_OPAQUE_ADDR); 2075 2076 p_hwfn->hw_info.concrete_fid = REG_RD(p_hwfn, PXP_PF_ME_CONCRETE_ADDR); 2077 2078 /* Bits 16-19 from the ME registers are the pf_num */ 2079 p_hwfn->abs_pf_id = (p_hwfn->hw_info.concrete_fid >> 16) & 0xf; 2080 p_hwfn->rel_pf_id = GET_FIELD(p_hwfn->hw_info.concrete_fid, 2081 PXP_CONCRETE_FID_PFID); 2082 p_hwfn->port_id = GET_FIELD(p_hwfn->hw_info.concrete_fid, 2083 PXP_CONCRETE_FID_PORT); 2084 2085 DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE, 2086 "Read ME register: Concrete 0x%08x Opaque 0x%04x\n", 2087 p_hwfn->hw_info.concrete_fid, p_hwfn->hw_info.opaque_fid); 2088 } 2089 2090 static void ecore_hw_set_feat(struct ecore_hwfn *p_hwfn) 2091 { 2092 u32 *feat_num = p_hwfn->hw_info.feat_num; 2093 int num_features = 1; 2094 2095 /* L2 Queues require each: 1 status block. 1 L2 queue */ 2096 feat_num[ECORE_PF_L2_QUE] = 2097 OSAL_MIN_T(u32, 2098 RESC_NUM(p_hwfn, ECORE_SB) / num_features, 2099 RESC_NUM(p_hwfn, ECORE_L2_QUEUE)); 2100 2101 DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE, 2102 "#PF_L2_QUEUES=%d #ROCE_CNQ=%d #SBS=%d num_features=%d\n", 2103 feat_num[ECORE_PF_L2_QUE], 2104 feat_num[ECORE_RDMA_CNQ], 2105 RESC_NUM(p_hwfn, ECORE_SB), num_features); 2106 } 2107 2108 static enum resource_id_enum 2109 ecore_hw_get_mfw_res_id(enum ecore_resources res_id) 2110 { 2111 enum resource_id_enum mfw_res_id = RESOURCE_NUM_INVALID; 2112 2113 switch (res_id) { 2114 case ECORE_SB: 2115 mfw_res_id = RESOURCE_NUM_SB_E; 2116 break; 2117 case ECORE_L2_QUEUE: 2118 mfw_res_id = RESOURCE_NUM_L2_QUEUE_E; 2119 break; 2120 case ECORE_VPORT: 2121 mfw_res_id = RESOURCE_NUM_VPORT_E; 2122 break; 2123 case ECORE_RSS_ENG: 2124 mfw_res_id = RESOURCE_NUM_RSS_ENGINES_E; 2125 break; 2126 case ECORE_PQ: 2127 mfw_res_id = RESOURCE_NUM_PQ_E; 2128 break; 2129 case ECORE_RL: 2130 mfw_res_id = RESOURCE_NUM_RL_E; 2131 break; 2132 case ECORE_MAC: 2133 case ECORE_VLAN: 2134 /* Each VFC resource can accommodate both a MAC and a VLAN */ 2135 mfw_res_id = RESOURCE_VFC_FILTER_E; 2136 break; 2137 case ECORE_ILT: 2138 mfw_res_id = RESOURCE_ILT_E; 2139 break; 2140 case ECORE_LL2_QUEUE: 2141 mfw_res_id = RESOURCE_LL2_QUEUE_E; 2142 break; 2143 case ECORE_RDMA_CNQ_RAM: 2144 case ECORE_CMDQS_CQS: 2145 /* CNQ/CMDQS are the same resource */ 2146 mfw_res_id = RESOURCE_CQS_E; 2147 break; 2148 case ECORE_RDMA_STATS_QUEUE: 2149 mfw_res_id = RESOURCE_RDMA_STATS_QUEUE_E; 2150 break; 2151 default: 2152 break; 2153 } 2154 2155 return mfw_res_id; 2156 } 2157 2158 static u32 ecore_hw_get_dflt_resc_num(struct ecore_hwfn *p_hwfn, 2159 enum ecore_resources res_id) 2160 { 2161 u8 num_funcs = p_hwfn->num_funcs_on_engine; 2162 bool b_ah = ECORE_IS_AH(p_hwfn->p_dev); 2163 struct ecore_sb_cnt_info sb_cnt_info; 2164 u32 dflt_resc_num = 0; 2165 2166 switch (res_id) { 2167 case ECORE_SB: 2168 OSAL_MEM_ZERO(&sb_cnt_info, sizeof(sb_cnt_info)); 2169 ecore_int_get_num_sbs(p_hwfn, &sb_cnt_info); 2170 dflt_resc_num = sb_cnt_info.sb_cnt; 2171 break; 2172 case ECORE_L2_QUEUE: 2173 dflt_resc_num = (b_ah ? MAX_NUM_L2_QUEUES_K2 : 2174 MAX_NUM_L2_QUEUES_BB) / num_funcs; 2175 break; 2176 case ECORE_VPORT: 2177 dflt_resc_num = (b_ah ? MAX_NUM_VPORTS_K2 : 2178 MAX_NUM_VPORTS_BB) / num_funcs; 2179 break; 2180 case ECORE_RSS_ENG: 2181 dflt_resc_num = (b_ah ? ETH_RSS_ENGINE_NUM_K2 : 2182 ETH_RSS_ENGINE_NUM_BB) / num_funcs; 2183 break; 2184 case ECORE_PQ: 2185 dflt_resc_num = (b_ah ? MAX_QM_TX_QUEUES_K2 : 2186 MAX_QM_TX_QUEUES_BB) / num_funcs; 2187 break; 2188 case ECORE_RL: 2189 dflt_resc_num = MAX_QM_GLOBAL_RLS / num_funcs; 2190 break; 2191 case ECORE_MAC: 2192 case ECORE_VLAN: 2193 /* Each VFC resource can accommodate both a MAC and a VLAN */ 2194 dflt_resc_num = ETH_NUM_MAC_FILTERS / num_funcs; 2195 break; 2196 case ECORE_ILT: 2197 dflt_resc_num = (b_ah ? PXP_NUM_ILT_RECORDS_K2 : 2198 PXP_NUM_ILT_RECORDS_BB) / num_funcs; 2199 break; 2200 case ECORE_LL2_QUEUE: 2201 dflt_resc_num = MAX_NUM_LL2_RX_QUEUES / num_funcs; 2202 break; 2203 case ECORE_RDMA_CNQ_RAM: 2204 case ECORE_CMDQS_CQS: 2205 /* CNQ/CMDQS are the same resource */ 2206 /* @DPDK */ 2207 dflt_resc_num = (NUM_OF_GLOBAL_QUEUES / 2) / num_funcs; 2208 break; 2209 case ECORE_RDMA_STATS_QUEUE: 2210 /* @DPDK */ 2211 dflt_resc_num = (b_ah ? MAX_NUM_VPORTS_K2 : 2212 MAX_NUM_VPORTS_BB) / num_funcs; 2213 break; 2214 default: 2215 break; 2216 } 2217 2218 return dflt_resc_num; 2219 } 2220 2221 static enum _ecore_status_t ecore_hw_set_resc_info(struct ecore_hwfn *p_hwfn, 2222 enum ecore_resources res_id, 2223 bool drv_resc_alloc) 2224 { 2225 u32 dflt_resc_num = 0, dflt_resc_start = 0, mcp_resp, mcp_param; 2226 u32 *p_resc_num, *p_resc_start; 2227 struct resource_info resc_info; 2228 enum _ecore_status_t rc; 2229 2230 p_resc_num = &RESC_NUM(p_hwfn, res_id); 2231 p_resc_start = &RESC_START(p_hwfn, res_id); 2232 2233 dflt_resc_num = ecore_hw_get_dflt_resc_num(p_hwfn, res_id); 2234 if (!dflt_resc_num) { 2235 DP_ERR(p_hwfn, "Failed to get default amount for resource %d\n", 2236 res_id); 2237 return ECORE_INVAL; 2238 } 2239 dflt_resc_start = dflt_resc_num * p_hwfn->enabled_func_idx; 2240 2241 #ifndef ASIC_ONLY 2242 if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) { 2243 *p_resc_num = dflt_resc_num; 2244 *p_resc_start = dflt_resc_start; 2245 goto out; 2246 } 2247 #endif 2248 2249 OSAL_MEM_ZERO(&resc_info, sizeof(resc_info)); 2250 resc_info.res_id = ecore_hw_get_mfw_res_id(res_id); 2251 if (resc_info.res_id == RESOURCE_NUM_INVALID) { 2252 DP_ERR(p_hwfn, 2253 "Failed to match resource %d with MFW resources\n", 2254 res_id); 2255 return ECORE_INVAL; 2256 } 2257 2258 rc = ecore_mcp_get_resc_info(p_hwfn, p_hwfn->p_main_ptt, &resc_info, 2259 &mcp_resp, &mcp_param); 2260 if (rc != ECORE_SUCCESS) { 2261 DP_NOTICE(p_hwfn, true, 2262 "MFW resp failure for a resc alloc req [res_id %d]\n", 2263 res_id); 2264 return rc; 2265 } 2266 2267 /* Default driver values are applied in the following cases: 2268 * - The resource allocation MB command is not supported by the MFW 2269 * - There is an internal error in the MFW while processing the request 2270 * - The resource ID is unknown to the MFW 2271 */ 2272 if (mcp_resp != FW_MSG_CODE_RESOURCE_ALLOC_OK && 2273 mcp_resp != FW_MSG_CODE_RESOURCE_ALLOC_DEPRECATED) { 2274 /* @DPDK */ 2275 DP_INFO(p_hwfn, 2276 "No allocation info for resc %d [mcp_resp 0x%x].", 2277 res_id, mcp_resp); 2278 DP_INFO(p_hwfn, 2279 "Applying default values [num %d, start %d].\n", 2280 dflt_resc_num, dflt_resc_start); 2281 2282 *p_resc_num = dflt_resc_num; 2283 *p_resc_start = dflt_resc_start; 2284 goto out; 2285 } 2286 2287 /* TBD - remove this when revising the handling of the SB resource */ 2288 if (res_id == ECORE_SB) { 2289 /* Excluding the slowpath SB */ 2290 resc_info.size -= 1; 2291 resc_info.offset -= p_hwfn->enabled_func_idx; 2292 } 2293 2294 *p_resc_num = resc_info.size; 2295 *p_resc_start = resc_info.offset; 2296 2297 if (*p_resc_num != dflt_resc_num || *p_resc_start != dflt_resc_start) { 2298 DP_NOTICE(p_hwfn, false, 2299 "Resource %d: MFW allocation [num %d, start %d]", 2300 res_id, *p_resc_num, *p_resc_start); 2301 DP_NOTICE(p_hwfn, false, 2302 "differs from default values [num %d, start %d]%s\n", 2303 dflt_resc_num, 2304 dflt_resc_start, 2305 drv_resc_alloc ? " - applying default values" : ""); 2306 if (drv_resc_alloc) { 2307 *p_resc_num = dflt_resc_num; 2308 *p_resc_start = dflt_resc_start; 2309 } 2310 } 2311 out: 2312 return ECORE_SUCCESS; 2313 } 2314 2315 static const char *ecore_hw_get_resc_name(enum ecore_resources res_id) 2316 { 2317 switch (res_id) { 2318 case ECORE_SB: 2319 return "SB"; 2320 case ECORE_L2_QUEUE: 2321 return "L2_QUEUE"; 2322 case ECORE_VPORT: 2323 return "VPORT"; 2324 case ECORE_RSS_ENG: 2325 return "RSS_ENG"; 2326 case ECORE_PQ: 2327 return "PQ"; 2328 case ECORE_RL: 2329 return "RL"; 2330 case ECORE_MAC: 2331 return "MAC"; 2332 case ECORE_VLAN: 2333 return "VLAN"; 2334 case ECORE_RDMA_CNQ_RAM: 2335 return "RDMA_CNQ_RAM"; 2336 case ECORE_ILT: 2337 return "ILT"; 2338 case ECORE_LL2_QUEUE: 2339 return "LL2_QUEUE"; 2340 case ECORE_CMDQS_CQS: 2341 return "CMDQS_CQS"; 2342 case ECORE_RDMA_STATS_QUEUE: 2343 return "RDMA_STATS_QUEUE"; 2344 default: 2345 return "UNKNOWN_RESOURCE"; 2346 } 2347 } 2348 2349 static enum _ecore_status_t ecore_hw_get_resc(struct ecore_hwfn *p_hwfn, 2350 bool drv_resc_alloc) 2351 { 2352 bool b_ah = ECORE_IS_AH(p_hwfn->p_dev); 2353 enum _ecore_status_t rc; 2354 u8 res_id; 2355 #ifndef ASIC_ONLY 2356 u32 *resc_start = p_hwfn->hw_info.resc_start; 2357 u32 *resc_num = p_hwfn->hw_info.resc_num; 2358 /* For AH, an equal share of the ILT lines between the maximal number of 2359 * PFs is not enough for RoCE. This would be solved by the future 2360 * resource allocation scheme, but isn't currently present for 2361 * FPGA/emulation. For now we keep a number that is sufficient for RoCE 2362 * to work - the BB number of ILT lines divided by its max PFs number. 2363 */ 2364 u32 roce_min_ilt_lines = PXP_NUM_ILT_RECORDS_BB / MAX_NUM_PFS_BB; 2365 #endif 2366 2367 for (res_id = 0; res_id < ECORE_MAX_RESC; res_id++) { 2368 rc = ecore_hw_set_resc_info(p_hwfn, res_id, drv_resc_alloc); 2369 if (rc != ECORE_SUCCESS) 2370 return rc; 2371 } 2372 2373 #ifndef ASIC_ONLY 2374 if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) { 2375 /* Reduced build contains less PQs */ 2376 if (!(p_hwfn->p_dev->b_is_emul_full)) { 2377 resc_num[ECORE_PQ] = 32; 2378 resc_start[ECORE_PQ] = resc_num[ECORE_PQ] * 2379 p_hwfn->enabled_func_idx; 2380 } 2381 2382 /* For AH emulation, since we have a possible maximal number of 2383 * 16 enabled PFs, in case there are not enough ILT lines - 2384 * allocate only first PF as RoCE and have all the other ETH 2385 * only with less ILT lines. 2386 */ 2387 if (!p_hwfn->rel_pf_id && p_hwfn->p_dev->b_is_emul_full) 2388 resc_num[ECORE_ILT] = OSAL_MAX_T(u32, 2389 resc_num[ECORE_ILT], 2390 roce_min_ilt_lines); 2391 } 2392 2393 /* Correct the common ILT calculation if PF0 has more */ 2394 if (CHIP_REV_IS_SLOW(p_hwfn->p_dev) && 2395 p_hwfn->p_dev->b_is_emul_full && 2396 p_hwfn->rel_pf_id && resc_num[ECORE_ILT] < roce_min_ilt_lines) 2397 resc_start[ECORE_ILT] += roce_min_ilt_lines - 2398 resc_num[ECORE_ILT]; 2399 #endif 2400 2401 /* Sanity for ILT */ 2402 if ((b_ah && (RESC_END(p_hwfn, ECORE_ILT) > PXP_NUM_ILT_RECORDS_K2)) || 2403 (!b_ah && (RESC_END(p_hwfn, ECORE_ILT) > PXP_NUM_ILT_RECORDS_BB))) { 2404 DP_NOTICE(p_hwfn, true, 2405 "Can't assign ILT pages [%08x,...,%08x]\n", 2406 RESC_START(p_hwfn, ECORE_ILT), RESC_END(p_hwfn, 2407 ECORE_ILT) - 2408 1); 2409 return ECORE_INVAL; 2410 } 2411 2412 ecore_hw_set_feat(p_hwfn); 2413 2414 DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE, 2415 "The numbers for each resource are:\n"); 2416 for (res_id = 0; res_id < ECORE_MAX_RESC; res_id++) 2417 DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE, "%s = %d start = %d\n", 2418 ecore_hw_get_resc_name(res_id), 2419 RESC_NUM(p_hwfn, res_id), 2420 RESC_START(p_hwfn, res_id)); 2421 2422 return ECORE_SUCCESS; 2423 } 2424 2425 static enum _ecore_status_t ecore_hw_get_nvm_info(struct ecore_hwfn *p_hwfn, 2426 struct ecore_ptt *p_ptt) 2427 { 2428 u32 nvm_cfg1_offset, mf_mode, addr, generic_cont0, core_cfg; 2429 u32 port_cfg_addr, link_temp, nvm_cfg_addr, device_capabilities; 2430 struct ecore_mcp_link_params *link; 2431 2432 /* Read global nvm_cfg address */ 2433 nvm_cfg_addr = ecore_rd(p_hwfn, p_ptt, MISC_REG_GEN_PURP_CR0); 2434 2435 /* Verify MCP has initialized it */ 2436 if (!nvm_cfg_addr) { 2437 DP_NOTICE(p_hwfn, false, "Shared memory not initialized\n"); 2438 return ECORE_INVAL; 2439 } 2440 2441 /* Read nvm_cfg1 (Notice this is just offset, and not offsize (TBD) */ 2442 2443 nvm_cfg1_offset = ecore_rd(p_hwfn, p_ptt, nvm_cfg_addr + 4); 2444 2445 addr = MCP_REG_SCRATCH + nvm_cfg1_offset + 2446 OFFSETOF(struct nvm_cfg1, glob) + OFFSETOF(struct nvm_cfg1_glob, 2447 core_cfg); 2448 2449 core_cfg = ecore_rd(p_hwfn, p_ptt, addr); 2450 2451 switch ((core_cfg & NVM_CFG1_GLOB_NETWORK_PORT_MODE_MASK) >> 2452 NVM_CFG1_GLOB_NETWORK_PORT_MODE_OFFSET) { 2453 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_2X40G: 2454 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X40G; 2455 break; 2456 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X50G: 2457 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X50G; 2458 break; 2459 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_1X100G: 2460 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_1X100G; 2461 break; 2462 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X10G_F: 2463 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X10G_F; 2464 break; 2465 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X10G_E: 2466 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X10G_E; 2467 break; 2468 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X20G: 2469 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X20G; 2470 break; 2471 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X40G: 2472 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_1X40G; 2473 break; 2474 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X25G: 2475 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X25G; 2476 break; 2477 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X25G: 2478 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_1X25G; 2479 break; 2480 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X25G: 2481 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X25G; 2482 break; 2483 default: 2484 DP_NOTICE(p_hwfn, true, "Unknown port mode in 0x%08x\n", 2485 core_cfg); 2486 break; 2487 } 2488 2489 /* Read default link configuration */ 2490 link = &p_hwfn->mcp_info->link_input; 2491 port_cfg_addr = MCP_REG_SCRATCH + nvm_cfg1_offset + 2492 OFFSETOF(struct nvm_cfg1, port[MFW_PORT(p_hwfn)]); 2493 link_temp = ecore_rd(p_hwfn, p_ptt, 2494 port_cfg_addr + 2495 OFFSETOF(struct nvm_cfg1_port, speed_cap_mask)); 2496 link_temp &= NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_MASK; 2497 link->speed.advertised_speeds = link_temp; 2498 2499 link_temp = link->speed.advertised_speeds; 2500 p_hwfn->mcp_info->link_capabilities.speed_capabilities = link_temp; 2501 2502 link_temp = ecore_rd(p_hwfn, p_ptt, 2503 port_cfg_addr + 2504 OFFSETOF(struct nvm_cfg1_port, link_settings)); 2505 switch ((link_temp & NVM_CFG1_PORT_DRV_LINK_SPEED_MASK) >> 2506 NVM_CFG1_PORT_DRV_LINK_SPEED_OFFSET) { 2507 case NVM_CFG1_PORT_DRV_LINK_SPEED_AUTONEG: 2508 link->speed.autoneg = true; 2509 break; 2510 case NVM_CFG1_PORT_DRV_LINK_SPEED_1G: 2511 link->speed.forced_speed = 1000; 2512 break; 2513 case NVM_CFG1_PORT_DRV_LINK_SPEED_10G: 2514 link->speed.forced_speed = 10000; 2515 break; 2516 case NVM_CFG1_PORT_DRV_LINK_SPEED_25G: 2517 link->speed.forced_speed = 25000; 2518 break; 2519 case NVM_CFG1_PORT_DRV_LINK_SPEED_40G: 2520 link->speed.forced_speed = 40000; 2521 break; 2522 case NVM_CFG1_PORT_DRV_LINK_SPEED_50G: 2523 link->speed.forced_speed = 50000; 2524 break; 2525 case NVM_CFG1_PORT_DRV_LINK_SPEED_BB_100G: 2526 link->speed.forced_speed = 100000; 2527 break; 2528 default: 2529 DP_NOTICE(p_hwfn, true, "Unknown Speed in 0x%08x\n", link_temp); 2530 } 2531 2532 p_hwfn->mcp_info->link_capabilities.default_speed = 2533 link->speed.forced_speed; 2534 p_hwfn->mcp_info->link_capabilities.default_speed_autoneg = 2535 link->speed.autoneg; 2536 2537 link_temp &= NVM_CFG1_PORT_DRV_FLOW_CONTROL_MASK; 2538 link_temp >>= NVM_CFG1_PORT_DRV_FLOW_CONTROL_OFFSET; 2539 link->pause.autoneg = !!(link_temp & 2540 NVM_CFG1_PORT_DRV_FLOW_CONTROL_AUTONEG); 2541 link->pause.forced_rx = !!(link_temp & 2542 NVM_CFG1_PORT_DRV_FLOW_CONTROL_RX); 2543 link->pause.forced_tx = !!(link_temp & 2544 NVM_CFG1_PORT_DRV_FLOW_CONTROL_TX); 2545 link->loopback_mode = 0; 2546 2547 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK, 2548 "Read default link: Speed 0x%08x, Adv. Speed 0x%08x, AN: 0x%02x, PAUSE AN: 0x%02x\n", 2549 link->speed.forced_speed, link->speed.advertised_speeds, 2550 link->speed.autoneg, link->pause.autoneg); 2551 2552 /* Read Multi-function information from shmem */ 2553 addr = MCP_REG_SCRATCH + nvm_cfg1_offset + 2554 OFFSETOF(struct nvm_cfg1, glob) + 2555 OFFSETOF(struct nvm_cfg1_glob, generic_cont0); 2556 2557 generic_cont0 = ecore_rd(p_hwfn, p_ptt, addr); 2558 2559 mf_mode = (generic_cont0 & NVM_CFG1_GLOB_MF_MODE_MASK) >> 2560 NVM_CFG1_GLOB_MF_MODE_OFFSET; 2561 2562 switch (mf_mode) { 2563 case NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED: 2564 p_hwfn->p_dev->mf_mode = ECORE_MF_OVLAN; 2565 break; 2566 case NVM_CFG1_GLOB_MF_MODE_NPAR1_0: 2567 p_hwfn->p_dev->mf_mode = ECORE_MF_NPAR; 2568 break; 2569 case NVM_CFG1_GLOB_MF_MODE_DEFAULT: 2570 p_hwfn->p_dev->mf_mode = ECORE_MF_DEFAULT; 2571 break; 2572 } 2573 DP_INFO(p_hwfn, "Multi function mode is %08x\n", 2574 p_hwfn->p_dev->mf_mode); 2575 2576 /* Read Multi-function information from shmem */ 2577 addr = MCP_REG_SCRATCH + nvm_cfg1_offset + 2578 OFFSETOF(struct nvm_cfg1, glob) + 2579 OFFSETOF(struct nvm_cfg1_glob, device_capabilities); 2580 2581 device_capabilities = ecore_rd(p_hwfn, p_ptt, addr); 2582 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ETHERNET) 2583 OSAL_SET_BIT(ECORE_DEV_CAP_ETH, 2584 &p_hwfn->hw_info.device_capabilities); 2585 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_FCOE) 2586 OSAL_SET_BIT(ECORE_DEV_CAP_FCOE, 2587 &p_hwfn->hw_info.device_capabilities); 2588 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ISCSI) 2589 OSAL_SET_BIT(ECORE_DEV_CAP_ISCSI, 2590 &p_hwfn->hw_info.device_capabilities); 2591 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ROCE) 2592 OSAL_SET_BIT(ECORE_DEV_CAP_ROCE, 2593 &p_hwfn->hw_info.device_capabilities); 2594 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_IWARP) 2595 OSAL_SET_BIT(ECORE_DEV_CAP_IWARP, 2596 &p_hwfn->hw_info.device_capabilities); 2597 2598 return ecore_mcp_fill_shmem_func_info(p_hwfn, p_ptt); 2599 } 2600 2601 static void ecore_get_num_funcs(struct ecore_hwfn *p_hwfn, 2602 struct ecore_ptt *p_ptt) 2603 { 2604 u8 num_funcs, enabled_func_idx = p_hwfn->rel_pf_id; 2605 u32 reg_function_hide, tmp, eng_mask, low_pfs_mask; 2606 struct ecore_dev *p_dev = p_hwfn->p_dev; 2607 2608 num_funcs = ECORE_IS_AH(p_dev) ? MAX_NUM_PFS_K2 : MAX_NUM_PFS_BB; 2609 2610 /* Bit 0 of MISCS_REG_FUNCTION_HIDE indicates whether the bypass values 2611 * in the other bits are selected. 2612 * Bits 1-15 are for functions 1-15, respectively, and their value is 2613 * '0' only for enabled functions (function 0 always exists and 2614 * enabled). 2615 * In case of CMT in BB, only the "even" functions are enabled, and thus 2616 * the number of functions for both hwfns is learnt from the same bits. 2617 */ 2618 reg_function_hide = ecore_rd(p_hwfn, p_ptt, MISCS_REG_FUNCTION_HIDE); 2619 2620 if (reg_function_hide & 0x1) { 2621 if (ECORE_IS_BB(p_dev)) { 2622 if (ECORE_PATH_ID(p_hwfn) && p_dev->num_hwfns == 1) { 2623 num_funcs = 0; 2624 eng_mask = 0xaaaa; 2625 } else { 2626 num_funcs = 1; 2627 eng_mask = 0x5554; 2628 } 2629 } else { 2630 num_funcs = 1; 2631 eng_mask = 0xfffe; 2632 } 2633 2634 /* Get the number of the enabled functions on the engine */ 2635 tmp = (reg_function_hide ^ 0xffffffff) & eng_mask; 2636 while (tmp) { 2637 if (tmp & 0x1) 2638 num_funcs++; 2639 tmp >>= 0x1; 2640 } 2641 2642 /* Get the PF index within the enabled functions */ 2643 low_pfs_mask = (0x1 << p_hwfn->abs_pf_id) - 1; 2644 tmp = reg_function_hide & eng_mask & low_pfs_mask; 2645 while (tmp) { 2646 if (tmp & 0x1) 2647 enabled_func_idx--; 2648 tmp >>= 0x1; 2649 } 2650 } 2651 2652 p_hwfn->num_funcs_on_engine = num_funcs; 2653 p_hwfn->enabled_func_idx = enabled_func_idx; 2654 2655 #ifndef ASIC_ONLY 2656 if (CHIP_REV_IS_FPGA(p_dev)) { 2657 DP_NOTICE(p_hwfn, false, 2658 "FPGA: Limit number of PFs to 4 [would affect resource allocation, needed for IOV]\n"); 2659 p_hwfn->num_funcs_on_engine = 4; 2660 } 2661 #endif 2662 2663 DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE, 2664 "PF [rel_id %d, abs_id %d] occupies index %d within the %d enabled functions on the engine\n", 2665 p_hwfn->rel_pf_id, p_hwfn->abs_pf_id, 2666 p_hwfn->enabled_func_idx, p_hwfn->num_funcs_on_engine); 2667 } 2668 2669 static void ecore_hw_info_port_num_bb(struct ecore_hwfn *p_hwfn, 2670 struct ecore_ptt *p_ptt) 2671 { 2672 u32 port_mode; 2673 2674 #ifndef ASIC_ONLY 2675 /* Read the port mode */ 2676 if (CHIP_REV_IS_FPGA(p_hwfn->p_dev)) 2677 port_mode = 4; 2678 else if (CHIP_REV_IS_EMUL(p_hwfn->p_dev) && 2679 (p_hwfn->p_dev->num_hwfns > 1)) 2680 /* In CMT on emulation, assume 1 port */ 2681 port_mode = 1; 2682 else 2683 #endif 2684 port_mode = ecore_rd(p_hwfn, p_ptt, 2685 CNIG_REG_NW_PORT_MODE_BB_B0); 2686 2687 if (port_mode < 3) { 2688 p_hwfn->p_dev->num_ports_in_engines = 1; 2689 } else if (port_mode <= 5) { 2690 p_hwfn->p_dev->num_ports_in_engines = 2; 2691 } else { 2692 DP_NOTICE(p_hwfn, true, "PORT MODE: %d not supported\n", 2693 p_hwfn->p_dev->num_ports_in_engines); 2694 2695 /* Default num_ports_in_engines to something */ 2696 p_hwfn->p_dev->num_ports_in_engines = 1; 2697 } 2698 } 2699 2700 static void ecore_hw_info_port_num_ah(struct ecore_hwfn *p_hwfn, 2701 struct ecore_ptt *p_ptt) 2702 { 2703 u32 port; 2704 int i; 2705 2706 p_hwfn->p_dev->num_ports_in_engines = 0; 2707 2708 #ifndef ASIC_ONLY 2709 if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) { 2710 port = ecore_rd(p_hwfn, p_ptt, MISCS_REG_ECO_RESERVED); 2711 switch ((port & 0xf000) >> 12) { 2712 case 1: 2713 p_hwfn->p_dev->num_ports_in_engines = 1; 2714 break; 2715 case 3: 2716 p_hwfn->p_dev->num_ports_in_engines = 2; 2717 break; 2718 case 0xf: 2719 p_hwfn->p_dev->num_ports_in_engines = 4; 2720 break; 2721 default: 2722 DP_NOTICE(p_hwfn, false, 2723 "Unknown port mode in ECO_RESERVED %08x\n", 2724 port); 2725 } 2726 } else 2727 #endif 2728 for (i = 0; i < MAX_NUM_PORTS_K2; i++) { 2729 port = ecore_rd(p_hwfn, p_ptt, 2730 CNIG_REG_NIG_PORT0_CONF_K2 + (i * 4)); 2731 if (port & 1) 2732 p_hwfn->p_dev->num_ports_in_engines++; 2733 } 2734 } 2735 2736 static void ecore_hw_info_port_num(struct ecore_hwfn *p_hwfn, 2737 struct ecore_ptt *p_ptt) 2738 { 2739 if (ECORE_IS_BB(p_hwfn->p_dev)) 2740 ecore_hw_info_port_num_bb(p_hwfn, p_ptt); 2741 else 2742 ecore_hw_info_port_num_ah(p_hwfn, p_ptt); 2743 } 2744 2745 static enum _ecore_status_t 2746 ecore_get_hw_info(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt, 2747 enum ecore_pci_personality personality, bool drv_resc_alloc) 2748 { 2749 enum _ecore_status_t rc; 2750 2751 /* Since all information is common, only first hwfns should do this */ 2752 if (IS_LEAD_HWFN(p_hwfn)) { 2753 rc = ecore_iov_hw_info(p_hwfn); 2754 if (rc) 2755 return rc; 2756 } 2757 2758 /* TODO In get_hw_info, amoungst others: 2759 * Get MCP FW revision and determine according to it the supported 2760 * featrues (e.g. DCB) 2761 * Get boot mode 2762 * ecore_get_pcie_width_speed, WOL capability. 2763 * Number of global CQ-s (for storage 2764 */ 2765 ecore_hw_info_port_num(p_hwfn, p_ptt); 2766 2767 #ifndef ASIC_ONLY 2768 if (CHIP_REV_IS_ASIC(p_hwfn->p_dev)) 2769 #endif 2770 ecore_hw_get_nvm_info(p_hwfn, p_ptt); 2771 2772 rc = ecore_int_igu_read_cam(p_hwfn, p_ptt); 2773 if (rc) 2774 return rc; 2775 2776 #ifndef ASIC_ONLY 2777 if (CHIP_REV_IS_ASIC(p_hwfn->p_dev) && ecore_mcp_is_init(p_hwfn)) { 2778 #endif 2779 OSAL_MEMCPY(p_hwfn->hw_info.hw_mac_addr, 2780 p_hwfn->mcp_info->func_info.mac, ETH_ALEN); 2781 #ifndef ASIC_ONLY 2782 } else { 2783 static u8 mcp_hw_mac[6] = { 0, 2, 3, 4, 5, 6 }; 2784 2785 OSAL_MEMCPY(p_hwfn->hw_info.hw_mac_addr, mcp_hw_mac, ETH_ALEN); 2786 p_hwfn->hw_info.hw_mac_addr[5] = p_hwfn->abs_pf_id; 2787 } 2788 #endif 2789 2790 if (ecore_mcp_is_init(p_hwfn)) { 2791 if (p_hwfn->mcp_info->func_info.ovlan != ECORE_MCP_VLAN_UNSET) 2792 p_hwfn->hw_info.ovlan = 2793 p_hwfn->mcp_info->func_info.ovlan; 2794 2795 ecore_mcp_cmd_port_init(p_hwfn, p_ptt); 2796 } 2797 2798 if (personality != ECORE_PCI_DEFAULT) 2799 p_hwfn->hw_info.personality = personality; 2800 else if (ecore_mcp_is_init(p_hwfn)) 2801 p_hwfn->hw_info.personality = 2802 p_hwfn->mcp_info->func_info.protocol; 2803 2804 #ifndef ASIC_ONLY 2805 /* To overcome ILT lack for emulation, until at least until we'll have 2806 * a definite answer from system about it, allow only PF0 to be RoCE. 2807 */ 2808 if (CHIP_REV_IS_EMUL(p_hwfn->p_dev) && ECORE_IS_AH(p_hwfn->p_dev)) { 2809 if (!p_hwfn->rel_pf_id) 2810 p_hwfn->hw_info.personality = ECORE_PCI_ETH_ROCE; 2811 else 2812 p_hwfn->hw_info.personality = ECORE_PCI_ETH; 2813 } 2814 #endif 2815 2816 /* although in BB some constellations may support more than 4 tcs, 2817 * that can result in performance penalty in some cases. 4 2818 * represents a good tradeoff between performance and flexibility. 2819 */ 2820 p_hwfn->hw_info.num_hw_tc = NUM_PHYS_TCS_4PORT_K2; 2821 2822 /* start out with a single active tc. This can be increased either 2823 * by dcbx negotiation or by upper layer driver 2824 */ 2825 p_hwfn->hw_info.num_active_tc = 1; 2826 2827 ecore_get_num_funcs(p_hwfn, p_ptt); 2828 2829 /* In case of forcing the driver's default resource allocation, calling 2830 * ecore_hw_get_resc() should come after initializing the personality 2831 * and after getting the number of functions, since the calculation of 2832 * the resources/features depends on them. 2833 * This order is not harmful if not forcing. 2834 */ 2835 return ecore_hw_get_resc(p_hwfn, drv_resc_alloc); 2836 } 2837 2838 #define ECORE_DEV_ID_MASK 0xff00 2839 #define ECORE_DEV_ID_MASK_BB 0x1600 2840 #define ECORE_DEV_ID_MASK_AH 0x8000 2841 2842 static enum _ecore_status_t ecore_get_dev_info(struct ecore_dev *p_dev) 2843 { 2844 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev); 2845 u32 tmp; 2846 2847 /* Read Vendor Id / Device Id */ 2848 OSAL_PCI_READ_CONFIG_WORD(p_dev, PCICFG_VENDOR_ID_OFFSET, 2849 &p_dev->vendor_id); 2850 OSAL_PCI_READ_CONFIG_WORD(p_dev, PCICFG_DEVICE_ID_OFFSET, 2851 &p_dev->device_id); 2852 2853 /* Determine type */ 2854 if ((p_dev->device_id & ECORE_DEV_ID_MASK) == ECORE_DEV_ID_MASK_AH) 2855 p_dev->type = ECORE_DEV_TYPE_AH; 2856 else 2857 p_dev->type = ECORE_DEV_TYPE_BB; 2858 2859 p_dev->chip_num = (u16)ecore_rd(p_hwfn, p_hwfn->p_main_ptt, 2860 MISCS_REG_CHIP_NUM); 2861 p_dev->chip_rev = (u16)ecore_rd(p_hwfn, p_hwfn->p_main_ptt, 2862 MISCS_REG_CHIP_REV); 2863 2864 MASK_FIELD(CHIP_REV, p_dev->chip_rev); 2865 2866 /* Learn number of HW-functions */ 2867 tmp = ecore_rd(p_hwfn, p_hwfn->p_main_ptt, 2868 MISCS_REG_CMT_ENABLED_FOR_PAIR); 2869 2870 if (tmp & (1 << p_hwfn->rel_pf_id)) { 2871 DP_NOTICE(p_dev->hwfns, false, "device in CMT mode\n"); 2872 p_dev->num_hwfns = 2; 2873 } else { 2874 p_dev->num_hwfns = 1; 2875 } 2876 2877 #ifndef ASIC_ONLY 2878 if (CHIP_REV_IS_EMUL(p_dev)) { 2879 /* For some reason we have problems with this register 2880 * in B0 emulation; Simply assume no CMT 2881 */ 2882 DP_NOTICE(p_dev->hwfns, false, 2883 "device on emul - assume no CMT\n"); 2884 p_dev->num_hwfns = 1; 2885 } 2886 #endif 2887 2888 p_dev->chip_bond_id = ecore_rd(p_hwfn, p_hwfn->p_main_ptt, 2889 MISCS_REG_CHIP_TEST_REG) >> 4; 2890 MASK_FIELD(CHIP_BOND_ID, p_dev->chip_bond_id); 2891 p_dev->chip_metal = (u16)ecore_rd(p_hwfn, p_hwfn->p_main_ptt, 2892 MISCS_REG_CHIP_METAL); 2893 MASK_FIELD(CHIP_METAL, p_dev->chip_metal); 2894 DP_INFO(p_dev->hwfns, 2895 "Chip details - %s%d, Num: %04x Rev: %04x Bond id: %04x Metal: %04x\n", 2896 ECORE_IS_BB(p_dev) ? "BB" : "AH", 2897 CHIP_REV_IS_A0(p_dev) ? 0 : 1, 2898 p_dev->chip_num, p_dev->chip_rev, p_dev->chip_bond_id, 2899 p_dev->chip_metal); 2900 2901 if (ECORE_IS_BB(p_dev) && CHIP_REV_IS_A0(p_dev)) { 2902 DP_NOTICE(p_dev->hwfns, false, 2903 "The chip type/rev (BB A0) is not supported!\n"); 2904 return ECORE_ABORTED; 2905 } 2906 #ifndef ASIC_ONLY 2907 if (CHIP_REV_IS_EMUL(p_dev) && ECORE_IS_AH(p_dev)) 2908 ecore_wr(p_hwfn, p_hwfn->p_main_ptt, 2909 MISCS_REG_PLL_MAIN_CTRL_4, 0x1); 2910 2911 if (CHIP_REV_IS_EMUL(p_dev)) { 2912 tmp = ecore_rd(p_hwfn, p_hwfn->p_main_ptt, 2913 MISCS_REG_ECO_RESERVED); 2914 if (tmp & (1 << 29)) { 2915 DP_NOTICE(p_hwfn, false, 2916 "Emulation: Running on a FULL build\n"); 2917 p_dev->b_is_emul_full = true; 2918 } else { 2919 DP_NOTICE(p_hwfn, false, 2920 "Emulation: Running on a REDUCED build\n"); 2921 } 2922 } 2923 #endif 2924 2925 return ECORE_SUCCESS; 2926 } 2927 2928 #ifndef LINUX_REMOVE 2929 void ecore_prepare_hibernate(struct ecore_dev *p_dev) 2930 { 2931 int j; 2932 2933 if (IS_VF(p_dev)) 2934 return; 2935 2936 for_each_hwfn(p_dev, j) { 2937 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j]; 2938 2939 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN, 2940 "Mark hw/fw uninitialized\n"); 2941 2942 p_hwfn->hw_init_done = false; 2943 p_hwfn->first_on_engine = false; 2944 2945 ecore_ptt_invalidate(p_hwfn); 2946 } 2947 } 2948 #endif 2949 2950 static enum _ecore_status_t 2951 ecore_hw_prepare_single(struct ecore_hwfn *p_hwfn, void OSAL_IOMEM *p_regview, 2952 void OSAL_IOMEM *p_doorbells, 2953 struct ecore_hw_prepare_params *p_params) 2954 { 2955 struct ecore_dev *p_dev = p_hwfn->p_dev; 2956 enum _ecore_status_t rc = ECORE_SUCCESS; 2957 2958 /* Split PCI bars evenly between hwfns */ 2959 p_hwfn->regview = p_regview; 2960 p_hwfn->doorbells = p_doorbells; 2961 2962 if (IS_VF(p_dev)) 2963 return ecore_vf_hw_prepare(p_hwfn); 2964 2965 /* Validate that chip access is feasible */ 2966 if (REG_RD(p_hwfn, PXP_PF_ME_OPAQUE_ADDR) == 0xffffffff) { 2967 DP_ERR(p_hwfn, 2968 "Reading the ME register returns all Fs; Preventing further chip access\n"); 2969 return ECORE_INVAL; 2970 } 2971 2972 get_function_id(p_hwfn); 2973 2974 /* Allocate PTT pool */ 2975 rc = ecore_ptt_pool_alloc(p_hwfn); 2976 if (rc) { 2977 DP_NOTICE(p_hwfn, true, "Failed to prepare hwfn's hw\n"); 2978 goto err0; 2979 } 2980 2981 /* Allocate the main PTT */ 2982 p_hwfn->p_main_ptt = ecore_get_reserved_ptt(p_hwfn, RESERVED_PTT_MAIN); 2983 2984 /* First hwfn learns basic information, e.g., number of hwfns */ 2985 if (!p_hwfn->my_id) { 2986 rc = ecore_get_dev_info(p_dev); 2987 if (rc != ECORE_SUCCESS) 2988 goto err1; 2989 } 2990 2991 ecore_hw_hwfn_prepare(p_hwfn); 2992 2993 /* Initialize MCP structure */ 2994 rc = ecore_mcp_cmd_init(p_hwfn, p_hwfn->p_main_ptt); 2995 if (rc) { 2996 DP_NOTICE(p_hwfn, true, "Failed initializing mcp command\n"); 2997 goto err1; 2998 } 2999 3000 if (p_hwfn == ECORE_LEADING_HWFN(p_dev) && !p_dev->recov_in_prog) { 3001 rc = ecore_mcp_initiate_pf_flr(p_hwfn, p_hwfn->p_main_ptt); 3002 if (rc != ECORE_SUCCESS) 3003 DP_NOTICE(p_hwfn, false, "Failed to initiate PF FLR\n"); 3004 } 3005 3006 /* Read the device configuration information from the HW and SHMEM */ 3007 rc = ecore_get_hw_info(p_hwfn, p_hwfn->p_main_ptt, 3008 p_params->personality, p_params->drv_resc_alloc); 3009 if (rc) { 3010 DP_NOTICE(p_hwfn, true, "Failed to get HW information\n"); 3011 goto err2; 3012 } 3013 3014 /* Allocate the init RT array and initialize the init-ops engine */ 3015 rc = ecore_init_alloc(p_hwfn); 3016 if (rc) { 3017 DP_NOTICE(p_hwfn, true, "Failed to allocate the init array\n"); 3018 goto err2; 3019 } 3020 #ifndef ASIC_ONLY 3021 if (CHIP_REV_IS_FPGA(p_dev)) { 3022 DP_NOTICE(p_hwfn, false, 3023 "FPGA: workaround; Prevent DMAE parities\n"); 3024 ecore_wr(p_hwfn, p_hwfn->p_main_ptt, PCIE_REG_PRTY_MASK, 7); 3025 3026 DP_NOTICE(p_hwfn, false, 3027 "FPGA: workaround: Set VF bar0 size\n"); 3028 ecore_wr(p_hwfn, p_hwfn->p_main_ptt, 3029 PGLUE_B_REG_VF_BAR0_SIZE, 4); 3030 } 3031 #endif 3032 3033 return rc; 3034 err2: 3035 if (IS_LEAD_HWFN(p_hwfn)) 3036 ecore_iov_free_hw_info(p_dev); 3037 ecore_mcp_free(p_hwfn); 3038 err1: 3039 ecore_hw_hwfn_free(p_hwfn); 3040 err0: 3041 return rc; 3042 } 3043 3044 enum _ecore_status_t ecore_hw_prepare(struct ecore_dev *p_dev, 3045 struct ecore_hw_prepare_params *p_params) 3046 { 3047 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev); 3048 enum _ecore_status_t rc; 3049 3050 p_dev->chk_reg_fifo = p_params->chk_reg_fifo; 3051 3052 /* Store the precompiled init data ptrs */ 3053 if (IS_PF(p_dev)) 3054 ecore_init_iro_array(p_dev); 3055 3056 /* Initialize the first hwfn - will learn number of hwfns */ 3057 rc = ecore_hw_prepare_single(p_hwfn, 3058 p_dev->regview, 3059 p_dev->doorbells, p_params); 3060 if (rc != ECORE_SUCCESS) 3061 return rc; 3062 3063 p_params->personality = p_hwfn->hw_info.personality; 3064 3065 /* initilalize 2nd hwfn if necessary */ 3066 if (p_dev->num_hwfns > 1) { 3067 void OSAL_IOMEM *p_regview, *p_doorbell; 3068 u8 OSAL_IOMEM *addr; 3069 3070 /* adjust bar offset for second engine */ 3071 addr = (u8 OSAL_IOMEM *)p_dev->regview + 3072 ecore_hw_bar_size(p_hwfn, BAR_ID_0) / 2; 3073 p_regview = (void OSAL_IOMEM *)addr; 3074 3075 addr = (u8 OSAL_IOMEM *)p_dev->doorbells + 3076 ecore_hw_bar_size(p_hwfn, BAR_ID_1) / 2; 3077 p_doorbell = (void OSAL_IOMEM *)addr; 3078 3079 /* prepare second hw function */ 3080 rc = ecore_hw_prepare_single(&p_dev->hwfns[1], p_regview, 3081 p_doorbell, p_params); 3082 3083 /* in case of error, need to free the previously 3084 * initiliazed hwfn 0. 3085 */ 3086 if (rc != ECORE_SUCCESS) { 3087 if (IS_PF(p_dev)) { 3088 ecore_init_free(p_hwfn); 3089 ecore_mcp_free(p_hwfn); 3090 ecore_hw_hwfn_free(p_hwfn); 3091 } else { 3092 DP_NOTICE(p_dev, true, 3093 "What do we need to free when VF hwfn1 init fails\n"); 3094 } 3095 return rc; 3096 } 3097 } 3098 3099 return ECORE_SUCCESS; 3100 } 3101 3102 void ecore_hw_remove(struct ecore_dev *p_dev) 3103 { 3104 int i; 3105 3106 for_each_hwfn(p_dev, i) { 3107 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i]; 3108 3109 if (IS_VF(p_dev)) { 3110 ecore_vf_pf_release(p_hwfn); 3111 continue; 3112 } 3113 3114 ecore_init_free(p_hwfn); 3115 ecore_hw_hwfn_free(p_hwfn); 3116 ecore_mcp_free(p_hwfn); 3117 3118 OSAL_MUTEX_DEALLOC(&p_hwfn->dmae_info.mutex); 3119 } 3120 3121 ecore_iov_free_hw_info(p_dev); 3122 } 3123 3124 static void ecore_chain_free_next_ptr(struct ecore_dev *p_dev, 3125 struct ecore_chain *p_chain) 3126 { 3127 void *p_virt = p_chain->p_virt_addr, *p_virt_next = OSAL_NULL; 3128 dma_addr_t p_phys = p_chain->p_phys_addr, p_phys_next = 0; 3129 struct ecore_chain_next *p_next; 3130 u32 size, i; 3131 3132 if (!p_virt) 3133 return; 3134 3135 size = p_chain->elem_size * p_chain->usable_per_page; 3136 3137 for (i = 0; i < p_chain->page_cnt; i++) { 3138 if (!p_virt) 3139 break; 3140 3141 p_next = (struct ecore_chain_next *)((u8 *)p_virt + size); 3142 p_virt_next = p_next->next_virt; 3143 p_phys_next = HILO_DMA_REGPAIR(p_next->next_phys); 3144 3145 OSAL_DMA_FREE_COHERENT(p_dev, p_virt, p_phys, 3146 ECORE_CHAIN_PAGE_SIZE); 3147 3148 p_virt = p_virt_next; 3149 p_phys = p_phys_next; 3150 } 3151 } 3152 3153 static void ecore_chain_free_single(struct ecore_dev *p_dev, 3154 struct ecore_chain *p_chain) 3155 { 3156 if (!p_chain->p_virt_addr) 3157 return; 3158 3159 OSAL_DMA_FREE_COHERENT(p_dev, p_chain->p_virt_addr, 3160 p_chain->p_phys_addr, ECORE_CHAIN_PAGE_SIZE); 3161 } 3162 3163 static void ecore_chain_free_pbl(struct ecore_dev *p_dev, 3164 struct ecore_chain *p_chain) 3165 { 3166 void **pp_virt_addr_tbl = p_chain->pbl.pp_virt_addr_tbl; 3167 u8 *p_pbl_virt = (u8 *)p_chain->pbl.p_virt_table; 3168 u32 page_cnt = p_chain->page_cnt, i, pbl_size; 3169 3170 if (!pp_virt_addr_tbl) 3171 return; 3172 3173 if (!p_chain->pbl.p_virt_table) 3174 goto out; 3175 3176 for (i = 0; i < page_cnt; i++) { 3177 if (!pp_virt_addr_tbl[i]) 3178 break; 3179 3180 OSAL_DMA_FREE_COHERENT(p_dev, pp_virt_addr_tbl[i], 3181 *(dma_addr_t *)p_pbl_virt, 3182 ECORE_CHAIN_PAGE_SIZE); 3183 3184 p_pbl_virt += ECORE_CHAIN_PBL_ENTRY_SIZE; 3185 } 3186 3187 pbl_size = page_cnt * ECORE_CHAIN_PBL_ENTRY_SIZE; 3188 OSAL_DMA_FREE_COHERENT(p_dev, p_chain->pbl.p_virt_table, 3189 p_chain->pbl.p_phys_table, pbl_size); 3190 out: 3191 OSAL_VFREE(p_dev, p_chain->pbl.pp_virt_addr_tbl); 3192 } 3193 3194 void ecore_chain_free(struct ecore_dev *p_dev, struct ecore_chain *p_chain) 3195 { 3196 switch (p_chain->mode) { 3197 case ECORE_CHAIN_MODE_NEXT_PTR: 3198 ecore_chain_free_next_ptr(p_dev, p_chain); 3199 break; 3200 case ECORE_CHAIN_MODE_SINGLE: 3201 ecore_chain_free_single(p_dev, p_chain); 3202 break; 3203 case ECORE_CHAIN_MODE_PBL: 3204 ecore_chain_free_pbl(p_dev, p_chain); 3205 break; 3206 } 3207 } 3208 3209 static enum _ecore_status_t 3210 ecore_chain_alloc_sanity_check(struct ecore_dev *p_dev, 3211 enum ecore_chain_cnt_type cnt_type, 3212 osal_size_t elem_size, u32 page_cnt) 3213 { 3214 u64 chain_size = ELEMS_PER_PAGE(elem_size) * page_cnt; 3215 3216 /* The actual chain size can be larger than the maximal possible value 3217 * after rounding up the requested elements number to pages, and after 3218 * taking into acount the unusuable elements (next-ptr elements). 3219 * The size of a "u16" chain can be (U16_MAX + 1) since the chain 3220 * size/capacity fields are of a u32 type. 3221 */ 3222 if ((cnt_type == ECORE_CHAIN_CNT_TYPE_U16 && 3223 chain_size > ((u32)ECORE_U16_MAX + 1)) || 3224 (cnt_type == ECORE_CHAIN_CNT_TYPE_U32 && 3225 chain_size > ECORE_U32_MAX)) { 3226 DP_NOTICE(p_dev, true, 3227 "The actual chain size (0x%lx) is larger than the maximal possible value\n", 3228 (unsigned long)chain_size); 3229 return ECORE_INVAL; 3230 } 3231 3232 return ECORE_SUCCESS; 3233 } 3234 3235 static enum _ecore_status_t 3236 ecore_chain_alloc_next_ptr(struct ecore_dev *p_dev, struct ecore_chain *p_chain) 3237 { 3238 void *p_virt = OSAL_NULL, *p_virt_prev = OSAL_NULL; 3239 dma_addr_t p_phys = 0; 3240 u32 i; 3241 3242 for (i = 0; i < p_chain->page_cnt; i++) { 3243 p_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_phys, 3244 ECORE_CHAIN_PAGE_SIZE); 3245 if (!p_virt) { 3246 DP_NOTICE(p_dev, true, 3247 "Failed to allocate chain memory\n"); 3248 return ECORE_NOMEM; 3249 } 3250 3251 if (i == 0) { 3252 ecore_chain_init_mem(p_chain, p_virt, p_phys); 3253 ecore_chain_reset(p_chain); 3254 } else { 3255 ecore_chain_init_next_ptr_elem(p_chain, p_virt_prev, 3256 p_virt, p_phys); 3257 } 3258 3259 p_virt_prev = p_virt; 3260 } 3261 /* Last page's next element should point to the beginning of the 3262 * chain. 3263 */ 3264 ecore_chain_init_next_ptr_elem(p_chain, p_virt_prev, 3265 p_chain->p_virt_addr, 3266 p_chain->p_phys_addr); 3267 3268 return ECORE_SUCCESS; 3269 } 3270 3271 static enum _ecore_status_t 3272 ecore_chain_alloc_single(struct ecore_dev *p_dev, struct ecore_chain *p_chain) 3273 { 3274 void *p_virt = OSAL_NULL; 3275 dma_addr_t p_phys = 0; 3276 3277 p_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_phys, ECORE_CHAIN_PAGE_SIZE); 3278 if (!p_virt) { 3279 DP_NOTICE(p_dev, true, "Failed to allocate chain memory\n"); 3280 return ECORE_NOMEM; 3281 } 3282 3283 ecore_chain_init_mem(p_chain, p_virt, p_phys); 3284 ecore_chain_reset(p_chain); 3285 3286 return ECORE_SUCCESS; 3287 } 3288 3289 static enum _ecore_status_t ecore_chain_alloc_pbl(struct ecore_dev *p_dev, 3290 struct ecore_chain *p_chain) 3291 { 3292 void *p_virt = OSAL_NULL; 3293 u8 *p_pbl_virt = OSAL_NULL; 3294 void **pp_virt_addr_tbl = OSAL_NULL; 3295 dma_addr_t p_phys = 0, p_pbl_phys = 0; 3296 u32 page_cnt = p_chain->page_cnt, size, i; 3297 3298 size = page_cnt * sizeof(*pp_virt_addr_tbl); 3299 pp_virt_addr_tbl = (void **)OSAL_VALLOC(p_dev, size); 3300 if (!pp_virt_addr_tbl) { 3301 DP_NOTICE(p_dev, true, 3302 "Failed to allocate memory for the chain virtual addresses table\n"); 3303 return ECORE_NOMEM; 3304 } 3305 OSAL_MEM_ZERO(pp_virt_addr_tbl, size); 3306 3307 /* The allocation of the PBL table is done with its full size, since it 3308 * is expected to be successive. 3309 * ecore_chain_init_pbl_mem() is called even in a case of an allocation 3310 * failure, since pp_virt_addr_tbl was previously allocated, and it 3311 * should be saved to allow its freeing during the error flow. 3312 */ 3313 size = page_cnt * ECORE_CHAIN_PBL_ENTRY_SIZE; 3314 p_pbl_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_pbl_phys, size); 3315 ecore_chain_init_pbl_mem(p_chain, p_pbl_virt, p_pbl_phys, 3316 pp_virt_addr_tbl); 3317 if (!p_pbl_virt) { 3318 DP_NOTICE(p_dev, true, "Failed to allocate chain pbl memory\n"); 3319 return ECORE_NOMEM; 3320 } 3321 3322 for (i = 0; i < page_cnt; i++) { 3323 p_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_phys, 3324 ECORE_CHAIN_PAGE_SIZE); 3325 if (!p_virt) { 3326 DP_NOTICE(p_dev, true, 3327 "Failed to allocate chain memory\n"); 3328 return ECORE_NOMEM; 3329 } 3330 3331 if (i == 0) { 3332 ecore_chain_init_mem(p_chain, p_virt, p_phys); 3333 ecore_chain_reset(p_chain); 3334 } 3335 3336 /* Fill the PBL table with the physical address of the page */ 3337 *(dma_addr_t *)p_pbl_virt = p_phys; 3338 /* Keep the virtual address of the page */ 3339 p_chain->pbl.pp_virt_addr_tbl[i] = p_virt; 3340 3341 p_pbl_virt += ECORE_CHAIN_PBL_ENTRY_SIZE; 3342 } 3343 3344 return ECORE_SUCCESS; 3345 } 3346 3347 enum _ecore_status_t ecore_chain_alloc(struct ecore_dev *p_dev, 3348 enum ecore_chain_use_mode intended_use, 3349 enum ecore_chain_mode mode, 3350 enum ecore_chain_cnt_type cnt_type, 3351 u32 num_elems, osal_size_t elem_size, 3352 struct ecore_chain *p_chain) 3353 { 3354 u32 page_cnt; 3355 enum _ecore_status_t rc = ECORE_SUCCESS; 3356 3357 if (mode == ECORE_CHAIN_MODE_SINGLE) 3358 page_cnt = 1; 3359 else 3360 page_cnt = ECORE_CHAIN_PAGE_CNT(num_elems, elem_size, mode); 3361 3362 rc = ecore_chain_alloc_sanity_check(p_dev, cnt_type, elem_size, 3363 page_cnt); 3364 if (rc) { 3365 DP_NOTICE(p_dev, true, 3366 "Cannot allocate a chain with the given arguments:\n" 3367 "[use_mode %d, mode %d, cnt_type %d, num_elems %d, elem_size %zu]\n", 3368 intended_use, mode, cnt_type, num_elems, elem_size); 3369 return rc; 3370 } 3371 3372 ecore_chain_init_params(p_chain, page_cnt, (u8)elem_size, intended_use, 3373 mode, cnt_type, p_dev->dp_ctx); 3374 3375 switch (mode) { 3376 case ECORE_CHAIN_MODE_NEXT_PTR: 3377 rc = ecore_chain_alloc_next_ptr(p_dev, p_chain); 3378 break; 3379 case ECORE_CHAIN_MODE_SINGLE: 3380 rc = ecore_chain_alloc_single(p_dev, p_chain); 3381 break; 3382 case ECORE_CHAIN_MODE_PBL: 3383 rc = ecore_chain_alloc_pbl(p_dev, p_chain); 3384 break; 3385 } 3386 if (rc) 3387 goto nomem; 3388 3389 return ECORE_SUCCESS; 3390 3391 nomem: 3392 ecore_chain_free(p_dev, p_chain); 3393 return rc; 3394 } 3395 3396 enum _ecore_status_t ecore_fw_l2_queue(struct ecore_hwfn *p_hwfn, 3397 u16 src_id, u16 *dst_id) 3398 { 3399 if (src_id >= RESC_NUM(p_hwfn, ECORE_L2_QUEUE)) { 3400 u16 min, max; 3401 3402 min = (u16)RESC_START(p_hwfn, ECORE_L2_QUEUE); 3403 max = min + RESC_NUM(p_hwfn, ECORE_L2_QUEUE); 3404 DP_NOTICE(p_hwfn, true, 3405 "l2_queue id [%d] is not valid, available indices [%d - %d]\n", 3406 src_id, min, max); 3407 3408 return ECORE_INVAL; 3409 } 3410 3411 *dst_id = RESC_START(p_hwfn, ECORE_L2_QUEUE) + src_id; 3412 3413 return ECORE_SUCCESS; 3414 } 3415 3416 enum _ecore_status_t ecore_fw_vport(struct ecore_hwfn *p_hwfn, 3417 u8 src_id, u8 *dst_id) 3418 { 3419 if (src_id >= RESC_NUM(p_hwfn, ECORE_VPORT)) { 3420 u8 min, max; 3421 3422 min = (u8)RESC_START(p_hwfn, ECORE_VPORT); 3423 max = min + RESC_NUM(p_hwfn, ECORE_VPORT); 3424 DP_NOTICE(p_hwfn, true, 3425 "vport id [%d] is not valid, available indices [%d - %d]\n", 3426 src_id, min, max); 3427 3428 return ECORE_INVAL; 3429 } 3430 3431 *dst_id = RESC_START(p_hwfn, ECORE_VPORT) + src_id; 3432 3433 return ECORE_SUCCESS; 3434 } 3435 3436 enum _ecore_status_t ecore_fw_rss_eng(struct ecore_hwfn *p_hwfn, 3437 u8 src_id, u8 *dst_id) 3438 { 3439 if (src_id >= RESC_NUM(p_hwfn, ECORE_RSS_ENG)) { 3440 u8 min, max; 3441 3442 min = (u8)RESC_START(p_hwfn, ECORE_RSS_ENG); 3443 max = min + RESC_NUM(p_hwfn, ECORE_RSS_ENG); 3444 DP_NOTICE(p_hwfn, true, 3445 "rss_eng id [%d] is not valid, available indices [%d - %d]\n", 3446 src_id, min, max); 3447 3448 return ECORE_INVAL; 3449 } 3450 3451 *dst_id = RESC_START(p_hwfn, ECORE_RSS_ENG) + src_id; 3452 3453 return ECORE_SUCCESS; 3454 } 3455 3456 enum _ecore_status_t ecore_llh_add_mac_filter(struct ecore_hwfn *p_hwfn, 3457 struct ecore_ptt *p_ptt, 3458 u8 *p_filter) 3459 { 3460 u32 high, low, en; 3461 int i; 3462 3463 if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn))) 3464 return ECORE_SUCCESS; 3465 3466 high = p_filter[1] | (p_filter[0] << 8); 3467 low = p_filter[5] | (p_filter[4] << 8) | 3468 (p_filter[3] << 16) | (p_filter[2] << 24); 3469 3470 /* Find a free entry and utilize it */ 3471 for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) { 3472 en = ecore_rd(p_hwfn, p_ptt, 3473 NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32)); 3474 if (en) 3475 continue; 3476 ecore_wr(p_hwfn, p_ptt, 3477 NIG_REG_LLH_FUNC_FILTER_VALUE + 3478 2 * i * sizeof(u32), low); 3479 ecore_wr(p_hwfn, p_ptt, 3480 NIG_REG_LLH_FUNC_FILTER_VALUE + 3481 (2 * i + 1) * sizeof(u32), high); 3482 ecore_wr(p_hwfn, p_ptt, 3483 NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32), 0); 3484 ecore_wr(p_hwfn, p_ptt, 3485 NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE + 3486 i * sizeof(u32), 0); 3487 ecore_wr(p_hwfn, p_ptt, 3488 NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 1); 3489 break; 3490 } 3491 if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE) { 3492 DP_NOTICE(p_hwfn, false, 3493 "Failed to find an empty LLH filter to utilize\n"); 3494 return ECORE_INVAL; 3495 } 3496 3497 DP_VERBOSE(p_hwfn, ECORE_MSG_HW, 3498 "MAC: %x:%x:%x:%x:%x:%x is added at %d\n", 3499 p_filter[0], p_filter[1], p_filter[2], 3500 p_filter[3], p_filter[4], p_filter[5], i); 3501 3502 return ECORE_SUCCESS; 3503 } 3504 3505 void ecore_llh_remove_mac_filter(struct ecore_hwfn *p_hwfn, 3506 struct ecore_ptt *p_ptt, u8 *p_filter) 3507 { 3508 u32 high, low; 3509 int i; 3510 3511 if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn))) 3512 return; 3513 3514 high = p_filter[1] | (p_filter[0] << 8); 3515 low = p_filter[5] | (p_filter[4] << 8) | 3516 (p_filter[3] << 16) | (p_filter[2] << 24); 3517 3518 /* Find the entry and clean it */ 3519 for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) { 3520 if (ecore_rd(p_hwfn, p_ptt, 3521 NIG_REG_LLH_FUNC_FILTER_VALUE + 3522 2 * i * sizeof(u32)) != low) 3523 continue; 3524 if (ecore_rd(p_hwfn, p_ptt, 3525 NIG_REG_LLH_FUNC_FILTER_VALUE + 3526 (2 * i + 1) * sizeof(u32)) != high) 3527 continue; 3528 3529 ecore_wr(p_hwfn, p_ptt, 3530 NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 0); 3531 ecore_wr(p_hwfn, p_ptt, 3532 NIG_REG_LLH_FUNC_FILTER_VALUE + 3533 2 * i * sizeof(u32), 0); 3534 ecore_wr(p_hwfn, p_ptt, 3535 NIG_REG_LLH_FUNC_FILTER_VALUE + 3536 (2 * i + 1) * sizeof(u32), 0); 3537 break; 3538 } 3539 if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE) 3540 DP_NOTICE(p_hwfn, false, 3541 "Tried to remove a non-configured filter\n"); 3542 } 3543 3544 enum _ecore_status_t 3545 ecore_llh_add_protocol_filter(struct ecore_hwfn *p_hwfn, 3546 struct ecore_ptt *p_ptt, 3547 u16 source_port_or_eth_type, 3548 u16 dest_port, 3549 enum ecore_llh_port_filter_type_t type) 3550 { 3551 u32 high, low, en; 3552 int i; 3553 3554 if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn))) 3555 return ECORE_SUCCESS; 3556 3557 high = 0; 3558 low = 0; 3559 switch (type) { 3560 case ECORE_LLH_FILTER_ETHERTYPE: 3561 high = source_port_or_eth_type; 3562 break; 3563 case ECORE_LLH_FILTER_TCP_SRC_PORT: 3564 case ECORE_LLH_FILTER_UDP_SRC_PORT: 3565 low = source_port_or_eth_type << 16; 3566 break; 3567 case ECORE_LLH_FILTER_TCP_DEST_PORT: 3568 case ECORE_LLH_FILTER_UDP_DEST_PORT: 3569 low = dest_port; 3570 break; 3571 case ECORE_LLH_FILTER_TCP_SRC_AND_DEST_PORT: 3572 case ECORE_LLH_FILTER_UDP_SRC_AND_DEST_PORT: 3573 low = (source_port_or_eth_type << 16) | dest_port; 3574 break; 3575 default: 3576 DP_NOTICE(p_hwfn, true, 3577 "Non valid LLH protocol filter type %d\n", type); 3578 return ECORE_INVAL; 3579 } 3580 /* Find a free entry and utilize it */ 3581 for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) { 3582 en = ecore_rd(p_hwfn, p_ptt, 3583 NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32)); 3584 if (en) 3585 continue; 3586 ecore_wr(p_hwfn, p_ptt, 3587 NIG_REG_LLH_FUNC_FILTER_VALUE + 3588 2 * i * sizeof(u32), low); 3589 ecore_wr(p_hwfn, p_ptt, 3590 NIG_REG_LLH_FUNC_FILTER_VALUE + 3591 (2 * i + 1) * sizeof(u32), high); 3592 ecore_wr(p_hwfn, p_ptt, 3593 NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32), 1); 3594 ecore_wr(p_hwfn, p_ptt, 3595 NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE + 3596 i * sizeof(u32), 1 << type); 3597 ecore_wr(p_hwfn, p_ptt, 3598 NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 1); 3599 break; 3600 } 3601 if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE) { 3602 DP_NOTICE(p_hwfn, false, 3603 "Failed to find an empty LLH filter to utilize\n"); 3604 return ECORE_NORESOURCES; 3605 } 3606 switch (type) { 3607 case ECORE_LLH_FILTER_ETHERTYPE: 3608 DP_VERBOSE(p_hwfn, ECORE_MSG_HW, 3609 "ETH type %x is added at %d\n", 3610 source_port_or_eth_type, i); 3611 break; 3612 case ECORE_LLH_FILTER_TCP_SRC_PORT: 3613 DP_VERBOSE(p_hwfn, ECORE_MSG_HW, 3614 "TCP src port %x is added at %d\n", 3615 source_port_or_eth_type, i); 3616 break; 3617 case ECORE_LLH_FILTER_UDP_SRC_PORT: 3618 DP_VERBOSE(p_hwfn, ECORE_MSG_HW, 3619 "UDP src port %x is added at %d\n", 3620 source_port_or_eth_type, i); 3621 break; 3622 case ECORE_LLH_FILTER_TCP_DEST_PORT: 3623 DP_VERBOSE(p_hwfn, ECORE_MSG_HW, 3624 "TCP dst port %x is added at %d\n", dest_port, i); 3625 break; 3626 case ECORE_LLH_FILTER_UDP_DEST_PORT: 3627 DP_VERBOSE(p_hwfn, ECORE_MSG_HW, 3628 "UDP dst port %x is added at %d\n", dest_port, i); 3629 break; 3630 case ECORE_LLH_FILTER_TCP_SRC_AND_DEST_PORT: 3631 DP_VERBOSE(p_hwfn, ECORE_MSG_HW, 3632 "TCP src/dst ports %x/%x are added at %d\n", 3633 source_port_or_eth_type, dest_port, i); 3634 break; 3635 case ECORE_LLH_FILTER_UDP_SRC_AND_DEST_PORT: 3636 DP_VERBOSE(p_hwfn, ECORE_MSG_HW, 3637 "UDP src/dst ports %x/%x are added at %d\n", 3638 source_port_or_eth_type, dest_port, i); 3639 break; 3640 } 3641 return ECORE_SUCCESS; 3642 } 3643 3644 void 3645 ecore_llh_remove_protocol_filter(struct ecore_hwfn *p_hwfn, 3646 struct ecore_ptt *p_ptt, 3647 u16 source_port_or_eth_type, 3648 u16 dest_port, 3649 enum ecore_llh_port_filter_type_t type) 3650 { 3651 u32 high, low; 3652 int i; 3653 3654 if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn))) 3655 return; 3656 3657 high = 0; 3658 low = 0; 3659 switch (type) { 3660 case ECORE_LLH_FILTER_ETHERTYPE: 3661 high = source_port_or_eth_type; 3662 break; 3663 case ECORE_LLH_FILTER_TCP_SRC_PORT: 3664 case ECORE_LLH_FILTER_UDP_SRC_PORT: 3665 low = source_port_or_eth_type << 16; 3666 break; 3667 case ECORE_LLH_FILTER_TCP_DEST_PORT: 3668 case ECORE_LLH_FILTER_UDP_DEST_PORT: 3669 low = dest_port; 3670 break; 3671 case ECORE_LLH_FILTER_TCP_SRC_AND_DEST_PORT: 3672 case ECORE_LLH_FILTER_UDP_SRC_AND_DEST_PORT: 3673 low = (source_port_or_eth_type << 16) | dest_port; 3674 break; 3675 default: 3676 DP_NOTICE(p_hwfn, true, 3677 "Non valid LLH protocol filter type %d\n", type); 3678 return; 3679 } 3680 3681 for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) { 3682 if (!ecore_rd(p_hwfn, p_ptt, 3683 NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32))) 3684 continue; 3685 if (!ecore_rd(p_hwfn, p_ptt, 3686 NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32))) 3687 continue; 3688 if (!(ecore_rd(p_hwfn, p_ptt, 3689 NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE + 3690 i * sizeof(u32)) & (1 << type))) 3691 continue; 3692 if (ecore_rd(p_hwfn, p_ptt, 3693 NIG_REG_LLH_FUNC_FILTER_VALUE + 3694 2 * i * sizeof(u32)) != low) 3695 continue; 3696 if (ecore_rd(p_hwfn, p_ptt, 3697 NIG_REG_LLH_FUNC_FILTER_VALUE + 3698 (2 * i + 1) * sizeof(u32)) != high) 3699 continue; 3700 3701 ecore_wr(p_hwfn, p_ptt, 3702 NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 0); 3703 ecore_wr(p_hwfn, p_ptt, 3704 NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32), 0); 3705 ecore_wr(p_hwfn, p_ptt, 3706 NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE + 3707 i * sizeof(u32), 0); 3708 ecore_wr(p_hwfn, p_ptt, 3709 NIG_REG_LLH_FUNC_FILTER_VALUE + 3710 2 * i * sizeof(u32), 0); 3711 ecore_wr(p_hwfn, p_ptt, 3712 NIG_REG_LLH_FUNC_FILTER_VALUE + 3713 (2 * i + 1) * sizeof(u32), 0); 3714 break; 3715 } 3716 3717 if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE) 3718 DP_NOTICE(p_hwfn, false, 3719 "Tried to remove a non-configured filter\n"); 3720 } 3721 3722 void ecore_llh_clear_all_filters(struct ecore_hwfn *p_hwfn, 3723 struct ecore_ptt *p_ptt) 3724 { 3725 int i; 3726 3727 if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn))) 3728 return; 3729 3730 for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) { 3731 ecore_wr(p_hwfn, p_ptt, 3732 NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 0); 3733 ecore_wr(p_hwfn, p_ptt, 3734 NIG_REG_LLH_FUNC_FILTER_VALUE + 3735 2 * i * sizeof(u32), 0); 3736 ecore_wr(p_hwfn, p_ptt, 3737 NIG_REG_LLH_FUNC_FILTER_VALUE + 3738 (2 * i + 1) * sizeof(u32), 0); 3739 } 3740 } 3741 3742 enum _ecore_status_t 3743 ecore_llh_set_function_as_default(struct ecore_hwfn *p_hwfn, 3744 struct ecore_ptt *p_ptt) 3745 { 3746 if (IS_MF_DEFAULT(p_hwfn) && ECORE_IS_BB(p_hwfn->p_dev)) { 3747 ecore_wr(p_hwfn, p_ptt, 3748 NIG_REG_LLH_TAGMAC_DEF_PF_VECTOR, 3749 1 << p_hwfn->abs_pf_id / 2); 3750 ecore_wr(p_hwfn, p_ptt, PRS_REG_MSG_INFO, 0); 3751 return ECORE_SUCCESS; 3752 } 3753 3754 DP_NOTICE(p_hwfn, false, 3755 "This function can't be set as default\n"); 3756 return ECORE_INVAL; 3757 } 3758 3759 static enum _ecore_status_t ecore_set_coalesce(struct ecore_hwfn *p_hwfn, 3760 struct ecore_ptt *p_ptt, 3761 u32 hw_addr, void *p_eth_qzone, 3762 osal_size_t eth_qzone_size, 3763 u8 timeset) 3764 { 3765 struct coalescing_timeset *p_coal_timeset; 3766 3767 if (IS_VF(p_hwfn->p_dev)) { 3768 DP_NOTICE(p_hwfn, true, "VF coalescing config not supported\n"); 3769 return ECORE_INVAL; 3770 } 3771 3772 if (p_hwfn->p_dev->int_coalescing_mode != ECORE_COAL_MODE_ENABLE) { 3773 DP_NOTICE(p_hwfn, true, 3774 "Coalescing configuration not enabled\n"); 3775 return ECORE_INVAL; 3776 } 3777 3778 OSAL_MEMSET(p_eth_qzone, 0, eth_qzone_size); 3779 p_coal_timeset = p_eth_qzone; 3780 SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_TIMESET, timeset); 3781 SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_VALID, 1); 3782 ecore_memcpy_to(p_hwfn, p_ptt, hw_addr, p_eth_qzone, eth_qzone_size); 3783 3784 return ECORE_SUCCESS; 3785 } 3786 3787 enum _ecore_status_t ecore_set_rxq_coalesce(struct ecore_hwfn *p_hwfn, 3788 struct ecore_ptt *p_ptt, 3789 u16 coalesce, u8 qid, u16 sb_id) 3790 { 3791 struct ustorm_eth_queue_zone eth_qzone; 3792 u16 fw_qid = 0; 3793 u32 address; 3794 enum _ecore_status_t rc; 3795 u8 timeset, timer_res; 3796 3797 /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */ 3798 if (coalesce <= 0x7F) { 3799 timer_res = 0; 3800 } else if (coalesce <= 0xFF) { 3801 timer_res = 1; 3802 } else if (coalesce <= 0x1FF) { 3803 timer_res = 2; 3804 } else { 3805 DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce); 3806 return ECORE_INVAL; 3807 } 3808 timeset = (u8)(coalesce >> timer_res); 3809 3810 rc = ecore_fw_l2_queue(p_hwfn, (u16)qid, &fw_qid); 3811 if (rc != ECORE_SUCCESS) 3812 return rc; 3813 3814 rc = ecore_int_set_timer_res(p_hwfn, p_ptt, timer_res, sb_id, false); 3815 if (rc != ECORE_SUCCESS) 3816 goto out; 3817 3818 address = BAR0_MAP_REG_USDM_RAM + USTORM_ETH_QUEUE_ZONE_OFFSET(fw_qid); 3819 3820 rc = ecore_set_coalesce(p_hwfn, p_ptt, address, ð_qzone, 3821 sizeof(struct ustorm_eth_queue_zone), timeset); 3822 if (rc != ECORE_SUCCESS) 3823 goto out; 3824 3825 p_hwfn->p_dev->rx_coalesce_usecs = coalesce; 3826 out: 3827 return rc; 3828 } 3829 3830 enum _ecore_status_t ecore_set_txq_coalesce(struct ecore_hwfn *p_hwfn, 3831 struct ecore_ptt *p_ptt, 3832 u16 coalesce, u8 qid, u16 sb_id) 3833 { 3834 struct xstorm_eth_queue_zone eth_qzone; 3835 u16 fw_qid = 0; 3836 u32 address; 3837 enum _ecore_status_t rc; 3838 u8 timeset, timer_res; 3839 3840 /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */ 3841 if (coalesce <= 0x7F) { 3842 timer_res = 0; 3843 } else if (coalesce <= 0xFF) { 3844 timer_res = 1; 3845 } else if (coalesce <= 0x1FF) { 3846 timer_res = 2; 3847 } else { 3848 DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce); 3849 return ECORE_INVAL; 3850 } 3851 3852 timeset = (u8)(coalesce >> timer_res); 3853 3854 rc = ecore_fw_l2_queue(p_hwfn, (u16)qid, &fw_qid); 3855 if (rc != ECORE_SUCCESS) 3856 return rc; 3857 3858 rc = ecore_int_set_timer_res(p_hwfn, p_ptt, timer_res, sb_id, true); 3859 if (rc != ECORE_SUCCESS) 3860 goto out; 3861 3862 address = BAR0_MAP_REG_XSDM_RAM + XSTORM_ETH_QUEUE_ZONE_OFFSET(fw_qid); 3863 3864 rc = ecore_set_coalesce(p_hwfn, p_ptt, address, ð_qzone, 3865 sizeof(struct xstorm_eth_queue_zone), timeset); 3866 if (rc != ECORE_SUCCESS) 3867 goto out; 3868 3869 p_hwfn->p_dev->tx_coalesce_usecs = coalesce; 3870 out: 3871 return rc; 3872 } 3873 3874 /* Calculate final WFQ values for all vports and configure it. 3875 * After this configuration each vport must have 3876 * approx min rate = vport_wfq * min_pf_rate / ECORE_WFQ_UNIT 3877 */ 3878 static void ecore_configure_wfq_for_all_vports(struct ecore_hwfn *p_hwfn, 3879 struct ecore_ptt *p_ptt, 3880 u32 min_pf_rate) 3881 { 3882 struct init_qm_vport_params *vport_params; 3883 int i; 3884 3885 vport_params = p_hwfn->qm_info.qm_vport_params; 3886 3887 for (i = 0; i < p_hwfn->qm_info.num_vports; i++) { 3888 u32 wfq_speed = p_hwfn->qm_info.wfq_data[i].min_speed; 3889 3890 vport_params[i].vport_wfq = (wfq_speed * ECORE_WFQ_UNIT) / 3891 min_pf_rate; 3892 ecore_init_vport_wfq(p_hwfn, p_ptt, 3893 vport_params[i].first_tx_pq_id, 3894 vport_params[i].vport_wfq); 3895 } 3896 } 3897 3898 static void 3899 ecore_init_wfq_default_param(struct ecore_hwfn *p_hwfn, u32 min_pf_rate) 3900 { 3901 int i; 3902 3903 for (i = 0; i < p_hwfn->qm_info.num_vports; i++) 3904 p_hwfn->qm_info.qm_vport_params[i].vport_wfq = 1; 3905 } 3906 3907 static void ecore_disable_wfq_for_all_vports(struct ecore_hwfn *p_hwfn, 3908 struct ecore_ptt *p_ptt, 3909 u32 min_pf_rate) 3910 { 3911 struct init_qm_vport_params *vport_params; 3912 int i; 3913 3914 vport_params = p_hwfn->qm_info.qm_vport_params; 3915 3916 for (i = 0; i < p_hwfn->qm_info.num_vports; i++) { 3917 ecore_init_wfq_default_param(p_hwfn, min_pf_rate); 3918 ecore_init_vport_wfq(p_hwfn, p_ptt, 3919 vport_params[i].first_tx_pq_id, 3920 vport_params[i].vport_wfq); 3921 } 3922 } 3923 3924 /* This function performs several validations for WFQ 3925 * configuration and required min rate for a given vport 3926 * 1. req_rate must be greater than one percent of min_pf_rate. 3927 * 2. req_rate should not cause other vports [not configured for WFQ explicitly] 3928 * rates to get less than one percent of min_pf_rate. 3929 * 3. total_req_min_rate [all vports min rate sum] shouldn't exceed min_pf_rate. 3930 */ 3931 static enum _ecore_status_t ecore_init_wfq_param(struct ecore_hwfn *p_hwfn, 3932 u16 vport_id, u32 req_rate, 3933 u32 min_pf_rate) 3934 { 3935 u32 total_req_min_rate = 0, total_left_rate = 0, left_rate_per_vp = 0; 3936 int non_requested_count = 0, req_count = 0, i, num_vports; 3937 3938 num_vports = p_hwfn->qm_info.num_vports; 3939 3940 /* Accounting for the vports which are configured for WFQ explicitly */ 3941 3942 for (i = 0; i < num_vports; i++) { 3943 u32 tmp_speed; 3944 3945 if ((i != vport_id) && p_hwfn->qm_info.wfq_data[i].configured) { 3946 req_count++; 3947 tmp_speed = p_hwfn->qm_info.wfq_data[i].min_speed; 3948 total_req_min_rate += tmp_speed; 3949 } 3950 } 3951 3952 /* Include current vport data as well */ 3953 req_count++; 3954 total_req_min_rate += req_rate; 3955 non_requested_count = num_vports - req_count; 3956 3957 /* validate possible error cases */ 3958 if (req_rate > min_pf_rate) { 3959 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK, 3960 "Vport [%d] - Requested rate[%d Mbps] is greater than configured PF min rate[%d Mbps]\n", 3961 vport_id, req_rate, min_pf_rate); 3962 return ECORE_INVAL; 3963 } 3964 3965 if (req_rate < min_pf_rate / ECORE_WFQ_UNIT) { 3966 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK, 3967 "Vport [%d] - Requested rate[%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n", 3968 vport_id, req_rate, min_pf_rate); 3969 return ECORE_INVAL; 3970 } 3971 3972 /* TBD - for number of vports greater than 100 */ 3973 if (num_vports > ECORE_WFQ_UNIT) { 3974 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK, 3975 "Number of vports is greater than %d\n", 3976 ECORE_WFQ_UNIT); 3977 return ECORE_INVAL; 3978 } 3979 3980 if (total_req_min_rate > min_pf_rate) { 3981 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK, 3982 "Total requested min rate for all vports[%d Mbps] is greater than configured PF min rate[%d Mbps]\n", 3983 total_req_min_rate, min_pf_rate); 3984 return ECORE_INVAL; 3985 } 3986 3987 /* Data left for non requested vports */ 3988 total_left_rate = min_pf_rate - total_req_min_rate; 3989 left_rate_per_vp = total_left_rate / non_requested_count; 3990 3991 /* validate if non requested get < 1% of min bw */ 3992 if (left_rate_per_vp < min_pf_rate / ECORE_WFQ_UNIT) { 3993 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK, 3994 "Non WFQ configured vports rate [%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n", 3995 left_rate_per_vp, min_pf_rate); 3996 return ECORE_INVAL; 3997 } 3998 3999 /* now req_rate for given vport passes all scenarios. 4000 * assign final wfq rates to all vports. 4001 */ 4002 p_hwfn->qm_info.wfq_data[vport_id].min_speed = req_rate; 4003 p_hwfn->qm_info.wfq_data[vport_id].configured = true; 4004 4005 for (i = 0; i < num_vports; i++) { 4006 if (p_hwfn->qm_info.wfq_data[i].configured) 4007 continue; 4008 4009 p_hwfn->qm_info.wfq_data[i].min_speed = left_rate_per_vp; 4010 } 4011 4012 return ECORE_SUCCESS; 4013 } 4014 4015 static int __ecore_configure_vport_wfq(struct ecore_hwfn *p_hwfn, 4016 struct ecore_ptt *p_ptt, 4017 u16 vp_id, u32 rate) 4018 { 4019 struct ecore_mcp_link_state *p_link; 4020 int rc = ECORE_SUCCESS; 4021 4022 p_link = &p_hwfn->p_dev->hwfns[0].mcp_info->link_output; 4023 4024 if (!p_link->min_pf_rate) { 4025 p_hwfn->qm_info.wfq_data[vp_id].min_speed = rate; 4026 p_hwfn->qm_info.wfq_data[vp_id].configured = true; 4027 return rc; 4028 } 4029 4030 rc = ecore_init_wfq_param(p_hwfn, vp_id, rate, p_link->min_pf_rate); 4031 4032 if (rc == ECORE_SUCCESS) 4033 ecore_configure_wfq_for_all_vports(p_hwfn, p_ptt, 4034 p_link->min_pf_rate); 4035 else 4036 DP_NOTICE(p_hwfn, false, 4037 "Validation failed while configuring min rate\n"); 4038 4039 return rc; 4040 } 4041 4042 static int __ecore_configure_vp_wfq_on_link_change(struct ecore_hwfn *p_hwfn, 4043 struct ecore_ptt *p_ptt, 4044 u32 min_pf_rate) 4045 { 4046 bool use_wfq = false; 4047 int rc = ECORE_SUCCESS; 4048 u16 i; 4049 4050 /* Validate all pre configured vports for wfq */ 4051 for (i = 0; i < p_hwfn->qm_info.num_vports; i++) { 4052 u32 rate; 4053 4054 if (!p_hwfn->qm_info.wfq_data[i].configured) 4055 continue; 4056 4057 rate = p_hwfn->qm_info.wfq_data[i].min_speed; 4058 use_wfq = true; 4059 4060 rc = ecore_init_wfq_param(p_hwfn, i, rate, min_pf_rate); 4061 if (rc != ECORE_SUCCESS) { 4062 DP_NOTICE(p_hwfn, false, 4063 "WFQ validation failed while configuring min rate\n"); 4064 break; 4065 } 4066 } 4067 4068 if (rc == ECORE_SUCCESS && use_wfq) 4069 ecore_configure_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate); 4070 else 4071 ecore_disable_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate); 4072 4073 return rc; 4074 } 4075 4076 /* Main API for ecore clients to configure vport min rate. 4077 * vp_id - vport id in PF Range[0 - (total_num_vports_per_pf - 1)] 4078 * rate - Speed in Mbps needs to be assigned to a given vport. 4079 */ 4080 int ecore_configure_vport_wfq(struct ecore_dev *p_dev, u16 vp_id, u32 rate) 4081 { 4082 int i, rc = ECORE_INVAL; 4083 4084 /* TBD - for multiple hardware functions - that is 100 gig */ 4085 if (p_dev->num_hwfns > 1) { 4086 DP_NOTICE(p_dev, false, 4087 "WFQ configuration is not supported for this device\n"); 4088 return rc; 4089 } 4090 4091 for_each_hwfn(p_dev, i) { 4092 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i]; 4093 struct ecore_ptt *p_ptt; 4094 4095 p_ptt = ecore_ptt_acquire(p_hwfn); 4096 if (!p_ptt) 4097 return ECORE_TIMEOUT; 4098 4099 rc = __ecore_configure_vport_wfq(p_hwfn, p_ptt, vp_id, rate); 4100 4101 if (rc != ECORE_SUCCESS) { 4102 ecore_ptt_release(p_hwfn, p_ptt); 4103 return rc; 4104 } 4105 4106 ecore_ptt_release(p_hwfn, p_ptt); 4107 } 4108 4109 return rc; 4110 } 4111 4112 /* API to configure WFQ from mcp link change */ 4113 void ecore_configure_vp_wfq_on_link_change(struct ecore_dev *p_dev, 4114 u32 min_pf_rate) 4115 { 4116 int i; 4117 4118 /* TBD - for multiple hardware functions - that is 100 gig */ 4119 if (p_dev->num_hwfns > 1) { 4120 DP_VERBOSE(p_dev, ECORE_MSG_LINK, 4121 "WFQ configuration is not supported for this device\n"); 4122 return; 4123 } 4124 4125 for_each_hwfn(p_dev, i) { 4126 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i]; 4127 4128 __ecore_configure_vp_wfq_on_link_change(p_hwfn, 4129 p_hwfn->p_dpc_ptt, 4130 min_pf_rate); 4131 } 4132 } 4133 4134 int __ecore_configure_pf_max_bandwidth(struct ecore_hwfn *p_hwfn, 4135 struct ecore_ptt *p_ptt, 4136 struct ecore_mcp_link_state *p_link, 4137 u8 max_bw) 4138 { 4139 int rc = ECORE_SUCCESS; 4140 4141 p_hwfn->mcp_info->func_info.bandwidth_max = max_bw; 4142 4143 if (!p_link->line_speed && (max_bw != 100)) 4144 return rc; 4145 4146 p_link->speed = (p_link->line_speed * max_bw) / 100; 4147 p_hwfn->qm_info.pf_rl = p_link->speed; 4148 4149 /* Since the limiter also affects Tx-switched traffic, we don't want it 4150 * to limit such traffic in case there's no actual limit. 4151 * In that case, set limit to imaginary high boundary. 4152 */ 4153 if (max_bw == 100) 4154 p_hwfn->qm_info.pf_rl = 100000; 4155 4156 rc = ecore_init_pf_rl(p_hwfn, p_ptt, p_hwfn->rel_pf_id, 4157 p_hwfn->qm_info.pf_rl); 4158 4159 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK, 4160 "Configured MAX bandwidth to be %08x Mb/sec\n", 4161 p_link->speed); 4162 4163 return rc; 4164 } 4165 4166 /* Main API to configure PF max bandwidth where bw range is [1 - 100] */ 4167 int ecore_configure_pf_max_bandwidth(struct ecore_dev *p_dev, u8 max_bw) 4168 { 4169 int i, rc = ECORE_INVAL; 4170 4171 if (max_bw < 1 || max_bw > 100) { 4172 DP_NOTICE(p_dev, false, "PF max bw valid range is [1-100]\n"); 4173 return rc; 4174 } 4175 4176 for_each_hwfn(p_dev, i) { 4177 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i]; 4178 struct ecore_hwfn *p_lead = ECORE_LEADING_HWFN(p_dev); 4179 struct ecore_mcp_link_state *p_link; 4180 struct ecore_ptt *p_ptt; 4181 4182 p_link = &p_lead->mcp_info->link_output; 4183 4184 p_ptt = ecore_ptt_acquire(p_hwfn); 4185 if (!p_ptt) 4186 return ECORE_TIMEOUT; 4187 4188 rc = __ecore_configure_pf_max_bandwidth(p_hwfn, p_ptt, 4189 p_link, max_bw); 4190 4191 ecore_ptt_release(p_hwfn, p_ptt); 4192 4193 if (rc != ECORE_SUCCESS) 4194 break; 4195 } 4196 4197 return rc; 4198 } 4199 4200 int __ecore_configure_pf_min_bandwidth(struct ecore_hwfn *p_hwfn, 4201 struct ecore_ptt *p_ptt, 4202 struct ecore_mcp_link_state *p_link, 4203 u8 min_bw) 4204 { 4205 int rc = ECORE_SUCCESS; 4206 4207 p_hwfn->mcp_info->func_info.bandwidth_min = min_bw; 4208 p_hwfn->qm_info.pf_wfq = min_bw; 4209 4210 if (!p_link->line_speed) 4211 return rc; 4212 4213 p_link->min_pf_rate = (p_link->line_speed * min_bw) / 100; 4214 4215 rc = ecore_init_pf_wfq(p_hwfn, p_ptt, p_hwfn->rel_pf_id, min_bw); 4216 4217 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK, 4218 "Configured MIN bandwidth to be %d Mb/sec\n", 4219 p_link->min_pf_rate); 4220 4221 return rc; 4222 } 4223 4224 /* Main API to configure PF min bandwidth where bw range is [1-100] */ 4225 int ecore_configure_pf_min_bandwidth(struct ecore_dev *p_dev, u8 min_bw) 4226 { 4227 int i, rc = ECORE_INVAL; 4228 4229 if (min_bw < 1 || min_bw > 100) { 4230 DP_NOTICE(p_dev, false, "PF min bw valid range is [1-100]\n"); 4231 return rc; 4232 } 4233 4234 for_each_hwfn(p_dev, i) { 4235 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i]; 4236 struct ecore_hwfn *p_lead = ECORE_LEADING_HWFN(p_dev); 4237 struct ecore_mcp_link_state *p_link; 4238 struct ecore_ptt *p_ptt; 4239 4240 p_link = &p_lead->mcp_info->link_output; 4241 4242 p_ptt = ecore_ptt_acquire(p_hwfn); 4243 if (!p_ptt) 4244 return ECORE_TIMEOUT; 4245 4246 rc = __ecore_configure_pf_min_bandwidth(p_hwfn, p_ptt, 4247 p_link, min_bw); 4248 if (rc != ECORE_SUCCESS) { 4249 ecore_ptt_release(p_hwfn, p_ptt); 4250 return rc; 4251 } 4252 4253 if (p_link->min_pf_rate) { 4254 u32 min_rate = p_link->min_pf_rate; 4255 4256 rc = __ecore_configure_vp_wfq_on_link_change(p_hwfn, 4257 p_ptt, 4258 min_rate); 4259 } 4260 4261 ecore_ptt_release(p_hwfn, p_ptt); 4262 } 4263 4264 return rc; 4265 } 4266 4267 void ecore_clean_wfq_db(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt) 4268 { 4269 struct ecore_mcp_link_state *p_link; 4270 4271 p_link = &p_hwfn->mcp_info->link_output; 4272 4273 if (p_link->min_pf_rate) 4274 ecore_disable_wfq_for_all_vports(p_hwfn, p_ptt, 4275 p_link->min_pf_rate); 4276 4277 OSAL_MEMSET(p_hwfn->qm_info.wfq_data, 0, 4278 sizeof(*p_hwfn->qm_info.wfq_data) * 4279 p_hwfn->qm_info.num_vports); 4280 } 4281 4282 int ecore_device_num_engines(struct ecore_dev *p_dev) 4283 { 4284 return ECORE_IS_BB(p_dev) ? 2 : 1; 4285 } 4286 4287 int ecore_device_num_ports(struct ecore_dev *p_dev) 4288 { 4289 /* in CMT always only one port */ 4290 if (p_dev->num_hwfns > 1) 4291 return 1; 4292 4293 return p_dev->num_ports_in_engines * ecore_device_num_engines(p_dev); 4294 } 4295