1 /* 2 * Copyright (c) 2016 QLogic Corporation. 3 * All rights reserved. 4 * www.qlogic.com 5 * 6 * See LICENSE.qede_pmd for copyright and licensing details. 7 */ 8 9 #include "bcm_osal.h" 10 #include "reg_addr.h" 11 #include "ecore_gtt_reg_addr.h" 12 #include "ecore.h" 13 #include "ecore_chain.h" 14 #include "ecore_status.h" 15 #include "ecore_hw.h" 16 #include "ecore_rt_defs.h" 17 #include "ecore_init_ops.h" 18 #include "ecore_int.h" 19 #include "ecore_cxt.h" 20 #include "ecore_spq.h" 21 #include "ecore_init_fw_funcs.h" 22 #include "ecore_sp_commands.h" 23 #include "ecore_dev_api.h" 24 #include "ecore_sriov.h" 25 #include "ecore_vf.h" 26 #include "ecore_mcp.h" 27 #include "ecore_hw_defs.h" 28 #include "mcp_public.h" 29 #include "ecore_iro.h" 30 #include "nvm_cfg.h" 31 #include "ecore_dev_api.h" 32 #include "ecore_dcbx.h" 33 34 /* TODO - there's a bug in DCBx re-configuration flows in MF, as the QM 35 * registers involved are not split and thus configuration is a race where 36 * some of the PFs configuration might be lost. 37 * Eventually, this needs to move into a MFW-covered HW-lock as arbitration 38 * mechanism as this doesn't cover some cases [E.g., PDA or scenarios where 39 * there's more than a single compiled ecore component in system]. 40 */ 41 static osal_spinlock_t qm_lock; 42 static bool qm_lock_init; 43 44 /* Configurable */ 45 #define ECORE_MIN_DPIS (4) /* The minimal num of DPIs required to 46 * load the driver. The number was 47 * arbitrarily set. 48 */ 49 50 /* Derived */ 51 #define ECORE_MIN_PWM_REGION ((ECORE_WID_SIZE) * (ECORE_MIN_DPIS)) 52 53 enum BAR_ID { 54 BAR_ID_0, /* used for GRC */ 55 BAR_ID_1 /* Used for doorbells */ 56 }; 57 58 static u32 ecore_hw_bar_size(struct ecore_hwfn *p_hwfn, enum BAR_ID bar_id) 59 { 60 u32 bar_reg = (bar_id == BAR_ID_0 ? 61 PGLUE_B_REG_PF_BAR0_SIZE : PGLUE_B_REG_PF_BAR1_SIZE); 62 u32 val; 63 64 if (IS_VF(p_hwfn->p_dev)) { 65 /* TODO - assume each VF hwfn has 64Kb for Bar0; Bar1 can be 66 * read from actual register, but we're currently not using 67 * it for actual doorbelling. 68 */ 69 return 1 << 17; 70 } 71 72 val = ecore_rd(p_hwfn, p_hwfn->p_main_ptt, bar_reg); 73 if (val) 74 return 1 << (val + 15); 75 76 /* The above registers were updated in the past only in CMT mode. Since 77 * they were found to be useful MFW started updating them from 8.7.7.0. 78 * In older MFW versions they are set to 0 which means disabled. 79 */ 80 if (p_hwfn->p_dev->num_hwfns > 1) { 81 DP_NOTICE(p_hwfn, false, 82 "BAR size not configured. Assuming BAR size of 256kB" 83 " for GRC and 512kB for DB\n"); 84 val = BAR_ID_0 ? 256 * 1024 : 512 * 1024; 85 } else { 86 DP_NOTICE(p_hwfn, false, 87 "BAR size not configured. Assuming BAR size of 512kB" 88 " for GRC and 512kB for DB\n"); 89 val = 512 * 1024; 90 } 91 92 return val; 93 } 94 95 void ecore_init_dp(struct ecore_dev *p_dev, 96 u32 dp_module, u8 dp_level, void *dp_ctx) 97 { 98 u32 i; 99 100 p_dev->dp_level = dp_level; 101 p_dev->dp_module = dp_module; 102 p_dev->dp_ctx = dp_ctx; 103 for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) { 104 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i]; 105 106 p_hwfn->dp_level = dp_level; 107 p_hwfn->dp_module = dp_module; 108 p_hwfn->dp_ctx = dp_ctx; 109 } 110 } 111 112 void ecore_init_struct(struct ecore_dev *p_dev) 113 { 114 u8 i; 115 116 for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) { 117 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i]; 118 119 p_hwfn->p_dev = p_dev; 120 p_hwfn->my_id = i; 121 p_hwfn->b_active = false; 122 123 OSAL_MUTEX_ALLOC(p_hwfn, &p_hwfn->dmae_info.mutex); 124 OSAL_MUTEX_INIT(&p_hwfn->dmae_info.mutex); 125 } 126 127 /* hwfn 0 is always active */ 128 p_dev->hwfns[0].b_active = true; 129 130 /* set the default cache alignment to 128 (may be overridden later) */ 131 p_dev->cache_shift = 7; 132 } 133 134 static void ecore_qm_info_free(struct ecore_hwfn *p_hwfn) 135 { 136 struct ecore_qm_info *qm_info = &p_hwfn->qm_info; 137 138 OSAL_FREE(p_hwfn->p_dev, qm_info->qm_pq_params); 139 qm_info->qm_pq_params = OSAL_NULL; 140 OSAL_FREE(p_hwfn->p_dev, qm_info->qm_vport_params); 141 qm_info->qm_vport_params = OSAL_NULL; 142 OSAL_FREE(p_hwfn->p_dev, qm_info->qm_port_params); 143 qm_info->qm_port_params = OSAL_NULL; 144 OSAL_FREE(p_hwfn->p_dev, qm_info->wfq_data); 145 qm_info->wfq_data = OSAL_NULL; 146 } 147 148 void ecore_resc_free(struct ecore_dev *p_dev) 149 { 150 int i; 151 152 if (IS_VF(p_dev)) 153 return; 154 155 OSAL_FREE(p_dev, p_dev->fw_data); 156 p_dev->fw_data = OSAL_NULL; 157 158 OSAL_FREE(p_dev, p_dev->reset_stats); 159 160 for_each_hwfn(p_dev, i) { 161 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i]; 162 163 OSAL_FREE(p_dev, p_hwfn->p_tx_cids); 164 p_hwfn->p_tx_cids = OSAL_NULL; 165 OSAL_FREE(p_dev, p_hwfn->p_rx_cids); 166 p_hwfn->p_rx_cids = OSAL_NULL; 167 } 168 169 for_each_hwfn(p_dev, i) { 170 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i]; 171 172 ecore_cxt_mngr_free(p_hwfn); 173 ecore_qm_info_free(p_hwfn); 174 ecore_spq_free(p_hwfn); 175 ecore_eq_free(p_hwfn, p_hwfn->p_eq); 176 ecore_consq_free(p_hwfn, p_hwfn->p_consq); 177 ecore_int_free(p_hwfn); 178 #ifdef CONFIG_ECORE_LL2 179 ecore_ll2_free(p_hwfn, p_hwfn->p_ll2_info); 180 #endif 181 ecore_iov_free(p_hwfn); 182 ecore_dmae_info_free(p_hwfn); 183 ecore_dcbx_info_free(p_hwfn, p_hwfn->p_dcbx_info); 184 /* @@@TBD Flush work-queue ? */ 185 } 186 } 187 188 static enum _ecore_status_t ecore_init_qm_info(struct ecore_hwfn *p_hwfn, 189 bool b_sleepable) 190 { 191 u8 num_vports, vf_offset = 0, i, vport_id, num_ports, curr_queue; 192 struct ecore_qm_info *qm_info = &p_hwfn->qm_info; 193 struct init_qm_port_params *p_qm_port; 194 bool init_rdma_offload_pq = false; 195 bool init_pure_ack_pq = false; 196 bool init_ooo_pq = false; 197 u16 num_pqs, protocol_pqs; 198 u16 num_pf_rls = 0; 199 u16 num_vfs = 0; 200 u32 pf_rl; 201 u8 pf_wfq; 202 203 /* @TMP - saving the existing min/max bw config before resetting the 204 * qm_info to restore them. 205 */ 206 pf_rl = qm_info->pf_rl; 207 pf_wfq = qm_info->pf_wfq; 208 209 #ifdef CONFIG_ECORE_SRIOV 210 if (p_hwfn->p_dev->p_iov_info) 211 num_vfs = p_hwfn->p_dev->p_iov_info->total_vfs; 212 #endif 213 OSAL_MEM_ZERO(qm_info, sizeof(*qm_info)); 214 215 #ifndef ASIC_ONLY 216 /* @TMP - Don't allocate QM queues for VFs on emulation */ 217 if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) { 218 DP_NOTICE(p_hwfn, false, 219 "Emulation - skip configuring QM queues for VFs\n"); 220 num_vfs = 0; 221 } 222 #endif 223 224 /* ethernet PFs require a pq per tc. Even if only a subset of the TCs 225 * active, we want physical queues allocated for all of them, since we 226 * don't have a good recycle flow. Non ethernet PFs require only a 227 * single physical queue. 228 */ 229 if (p_hwfn->hw_info.personality == ECORE_PCI_ETH_ROCE || 230 p_hwfn->hw_info.personality == ECORE_PCI_IWARP || 231 p_hwfn->hw_info.personality == ECORE_PCI_ETH) 232 protocol_pqs = p_hwfn->hw_info.num_hw_tc; 233 else 234 protocol_pqs = 1; 235 236 num_pqs = protocol_pqs + num_vfs + 1; /* The '1' is for pure-LB */ 237 num_vports = (u8)RESC_NUM(p_hwfn, ECORE_VPORT); 238 239 if (p_hwfn->hw_info.personality == ECORE_PCI_ETH_ROCE) { 240 num_pqs++; /* for RoCE queue */ 241 init_rdma_offload_pq = true; 242 if (p_hwfn->pf_params.rdma_pf_params.enable_dcqcn) { 243 /* Due to FW assumption that rl==vport, we limit the 244 * number of rate limiters by the minimum between its 245 * allocated number and the allocated number of vports. 246 * Another limitation is the number of supported qps 247 * with rate limiters in FW. 248 */ 249 num_pf_rls = 250 (u16)OSAL_MIN_T(u32, RESC_NUM(p_hwfn, ECORE_RL), 251 RESC_NUM(p_hwfn, ECORE_VPORT)); 252 253 /* we subtract num_vfs because each one requires a rate 254 * limiter, and one default rate limiter. 255 */ 256 if (num_pf_rls < num_vfs + 1) { 257 DP_ERR(p_hwfn, "No RL for DCQCN"); 258 DP_ERR(p_hwfn, "[num_pf_rls %d num_vfs %d]\n", 259 num_pf_rls, num_vfs); 260 return ECORE_INVAL; 261 } 262 num_pf_rls -= num_vfs + 1; 263 } 264 265 num_pqs += num_pf_rls; 266 qm_info->num_pf_rls = (u8)num_pf_rls; 267 } 268 269 if (p_hwfn->hw_info.personality == ECORE_PCI_IWARP) { 270 num_pqs += 3; /* for iwarp queue / pure-ack / ooo */ 271 init_rdma_offload_pq = true; 272 init_pure_ack_pq = true; 273 init_ooo_pq = true; 274 } 275 276 if (p_hwfn->hw_info.personality == ECORE_PCI_ISCSI) { 277 num_pqs += 2; /* for iSCSI pure-ACK / OOO queue */ 278 init_pure_ack_pq = true; 279 init_ooo_pq = true; 280 } 281 282 /* Sanity checking that setup requires legal number of resources */ 283 if (num_pqs > RESC_NUM(p_hwfn, ECORE_PQ)) { 284 DP_ERR(p_hwfn, 285 "Need too many Physical queues - 0x%04x avail %04x", 286 num_pqs, RESC_NUM(p_hwfn, ECORE_PQ)); 287 return ECORE_INVAL; 288 } 289 290 /* PQs will be arranged as follows: First per-TC PQ, then pure-LB queue, 291 * then special queues (iSCSI pure-ACK / RoCE), then per-VF PQ. 292 */ 293 qm_info->qm_pq_params = OSAL_ZALLOC(p_hwfn->p_dev, 294 b_sleepable ? GFP_KERNEL : 295 GFP_ATOMIC, 296 sizeof(struct init_qm_pq_params) * 297 num_pqs); 298 if (!qm_info->qm_pq_params) 299 goto alloc_err; 300 301 qm_info->qm_vport_params = OSAL_ZALLOC(p_hwfn->p_dev, 302 b_sleepable ? GFP_KERNEL : 303 GFP_ATOMIC, 304 sizeof(struct 305 init_qm_vport_params) * 306 num_vports); 307 if (!qm_info->qm_vport_params) 308 goto alloc_err; 309 310 qm_info->qm_port_params = OSAL_ZALLOC(p_hwfn->p_dev, 311 b_sleepable ? GFP_KERNEL : 312 GFP_ATOMIC, 313 sizeof(struct init_qm_port_params) 314 * MAX_NUM_PORTS); 315 if (!qm_info->qm_port_params) 316 goto alloc_err; 317 318 qm_info->wfq_data = OSAL_ZALLOC(p_hwfn->p_dev, 319 b_sleepable ? GFP_KERNEL : 320 GFP_ATOMIC, 321 sizeof(struct ecore_wfq_data) * 322 num_vports); 323 324 if (!qm_info->wfq_data) 325 goto alloc_err; 326 327 vport_id = (u8)RESC_START(p_hwfn, ECORE_VPORT); 328 329 /* First init rate limited queues ( Due to RoCE assumption of 330 * qpid=rlid ) 331 */ 332 for (curr_queue = 0; curr_queue < num_pf_rls; curr_queue++) { 333 qm_info->qm_pq_params[curr_queue].vport_id = vport_id++; 334 qm_info->qm_pq_params[curr_queue].tc_id = 335 p_hwfn->hw_info.offload_tc; 336 qm_info->qm_pq_params[curr_queue].wrr_group = 1; 337 qm_info->qm_pq_params[curr_queue].rl_valid = 1; 338 }; 339 340 /* Protocol PQs */ 341 for (i = 0; i < protocol_pqs; i++) { 342 struct init_qm_pq_params *params = 343 &qm_info->qm_pq_params[curr_queue++]; 344 345 if (p_hwfn->hw_info.personality == ECORE_PCI_ETH_ROCE || 346 p_hwfn->hw_info.personality == ECORE_PCI_IWARP || 347 p_hwfn->hw_info.personality == ECORE_PCI_ETH) { 348 params->vport_id = vport_id; 349 params->tc_id = i; 350 /* Note: this assumes that if we had a configuration 351 * with N tcs and subsequently another configuration 352 * With Fewer TCs, the in flight traffic (in QM queues, 353 * in FW, from driver to FW) will still trickle out and 354 * not get "stuck" in the QM. This is determined by the 355 * NIG_REG_TX_ARB_CLIENT_IS_SUBJECT2WFQ. Unused TCs are 356 * supposed to be cleared in this map, allowing traffic 357 * to flush out. If this is not the case, we would need 358 * to set the TC of unused queues to 0, and reconfigure 359 * QM every time num of TCs changes. Unused queues in 360 * this context would mean those intended for TCs where 361 * tc_id > hw_info.num_active_tcs. 362 */ 363 params->wrr_group = 1; /* @@@TBD ECORE_WRR_MEDIUM */ 364 } else { 365 params->vport_id = vport_id; 366 params->tc_id = p_hwfn->hw_info.offload_tc; 367 params->wrr_group = 1; /* @@@TBD ECORE_WRR_MEDIUM */ 368 } 369 } 370 371 /* Then init pure-LB PQ */ 372 qm_info->pure_lb_pq = curr_queue; 373 qm_info->qm_pq_params[curr_queue].vport_id = 374 (u8)RESC_START(p_hwfn, ECORE_VPORT); 375 qm_info->qm_pq_params[curr_queue].tc_id = PURE_LB_TC; 376 qm_info->qm_pq_params[curr_queue].wrr_group = 1; 377 curr_queue++; 378 379 qm_info->offload_pq = 0; /* Already initialized for iSCSI/FCoE */ 380 if (init_rdma_offload_pq) { 381 qm_info->offload_pq = curr_queue; 382 qm_info->qm_pq_params[curr_queue].vport_id = vport_id; 383 qm_info->qm_pq_params[curr_queue].tc_id = 384 p_hwfn->hw_info.offload_tc; 385 qm_info->qm_pq_params[curr_queue].wrr_group = 1; 386 curr_queue++; 387 } 388 389 if (init_pure_ack_pq) { 390 qm_info->pure_ack_pq = curr_queue; 391 qm_info->qm_pq_params[curr_queue].vport_id = vport_id; 392 qm_info->qm_pq_params[curr_queue].tc_id = 393 p_hwfn->hw_info.offload_tc; 394 qm_info->qm_pq_params[curr_queue].wrr_group = 1; 395 curr_queue++; 396 } 397 398 if (init_ooo_pq) { 399 qm_info->ooo_pq = curr_queue; 400 qm_info->qm_pq_params[curr_queue].vport_id = vport_id; 401 qm_info->qm_pq_params[curr_queue].tc_id = DCBX_ISCSI_OOO_TC; 402 qm_info->qm_pq_params[curr_queue].wrr_group = 1; 403 curr_queue++; 404 } 405 406 /* Then init per-VF PQs */ 407 vf_offset = curr_queue; 408 for (i = 0; i < num_vfs; i++) { 409 /* First vport is used by the PF */ 410 qm_info->qm_pq_params[curr_queue].vport_id = vport_id + i + 1; 411 /* @@@TBD VF Multi-cos */ 412 qm_info->qm_pq_params[curr_queue].tc_id = 0; 413 qm_info->qm_pq_params[curr_queue].wrr_group = 1; 414 qm_info->qm_pq_params[curr_queue].rl_valid = 1; 415 curr_queue++; 416 }; 417 418 qm_info->vf_queues_offset = vf_offset; 419 qm_info->num_pqs = num_pqs; 420 qm_info->num_vports = num_vports; 421 422 /* Initialize qm port parameters */ 423 num_ports = p_hwfn->p_dev->num_ports_in_engines; 424 for (i = 0; i < num_ports; i++) { 425 p_qm_port = &qm_info->qm_port_params[i]; 426 p_qm_port->active = 1; 427 /* @@@TMP - was NUM_OF_PHYS_TCS; Changed until dcbx will 428 * be in place 429 */ 430 if (num_ports == 4) 431 p_qm_port->active_phys_tcs = 0xf; 432 else 433 p_qm_port->active_phys_tcs = 0x9f; 434 p_qm_port->num_pbf_cmd_lines = PBF_MAX_CMD_LINES / num_ports; 435 p_qm_port->num_btb_blocks = BTB_MAX_BLOCKS / num_ports; 436 } 437 438 if (ECORE_IS_AH(p_hwfn->p_dev) && (num_ports == 4)) 439 qm_info->max_phys_tcs_per_port = NUM_PHYS_TCS_4PORT_K2; 440 else 441 qm_info->max_phys_tcs_per_port = NUM_OF_PHYS_TCS; 442 443 qm_info->start_pq = (u16)RESC_START(p_hwfn, ECORE_PQ); 444 445 qm_info->num_vf_pqs = num_vfs; 446 qm_info->start_vport = (u8)RESC_START(p_hwfn, ECORE_VPORT); 447 448 for (i = 0; i < qm_info->num_vports; i++) 449 qm_info->qm_vport_params[i].vport_wfq = 1; 450 451 qm_info->vport_rl_en = 1; 452 qm_info->vport_wfq_en = 1; 453 qm_info->pf_rl = pf_rl; 454 qm_info->pf_wfq = pf_wfq; 455 456 return ECORE_SUCCESS; 457 458 alloc_err: 459 DP_NOTICE(p_hwfn, false, "Failed to allocate memory for QM params\n"); 460 ecore_qm_info_free(p_hwfn); 461 return ECORE_NOMEM; 462 } 463 464 /* This function reconfigures the QM pf on the fly. 465 * For this purpose we: 466 * 1. reconfigure the QM database 467 * 2. set new values to runtime arrat 468 * 3. send an sdm_qm_cmd through the rbc interface to stop the QM 469 * 4. activate init tool in QM_PF stage 470 * 5. send an sdm_qm_cmd through rbc interface to release the QM 471 */ 472 enum _ecore_status_t ecore_qm_reconf(struct ecore_hwfn *p_hwfn, 473 struct ecore_ptt *p_ptt) 474 { 475 struct ecore_qm_info *qm_info = &p_hwfn->qm_info; 476 bool b_rc; 477 enum _ecore_status_t rc; 478 479 /* qm_info is allocated in ecore_init_qm_info() which is already called 480 * from ecore_resc_alloc() or previous call of ecore_qm_reconf(). 481 * The allocated size may change each init, so we free it before next 482 * allocation. 483 */ 484 ecore_qm_info_free(p_hwfn); 485 486 /* initialize ecore's qm data structure */ 487 rc = ecore_init_qm_info(p_hwfn, false); 488 if (rc != ECORE_SUCCESS) 489 return rc; 490 491 /* stop PF's qm queues */ 492 OSAL_SPIN_LOCK(&qm_lock); 493 b_rc = ecore_send_qm_stop_cmd(p_hwfn, p_ptt, false, true, 494 qm_info->start_pq, qm_info->num_pqs); 495 OSAL_SPIN_UNLOCK(&qm_lock); 496 if (!b_rc) 497 return ECORE_INVAL; 498 499 /* clear the QM_PF runtime phase leftovers from previous init */ 500 ecore_init_clear_rt_data(p_hwfn); 501 502 /* prepare QM portion of runtime array */ 503 ecore_qm_init_pf(p_hwfn); 504 505 /* activate init tool on runtime array */ 506 rc = ecore_init_run(p_hwfn, p_ptt, PHASE_QM_PF, p_hwfn->rel_pf_id, 507 p_hwfn->hw_info.hw_mode); 508 if (rc != ECORE_SUCCESS) 509 return rc; 510 511 /* start PF's qm queues */ 512 OSAL_SPIN_LOCK(&qm_lock); 513 b_rc = ecore_send_qm_stop_cmd(p_hwfn, p_ptt, true, true, 514 qm_info->start_pq, qm_info->num_pqs); 515 OSAL_SPIN_UNLOCK(&qm_lock); 516 if (!b_rc) 517 return ECORE_INVAL; 518 519 return ECORE_SUCCESS; 520 } 521 522 enum _ecore_status_t ecore_resc_alloc(struct ecore_dev *p_dev) 523 { 524 struct ecore_consq *p_consq; 525 struct ecore_eq *p_eq; 526 #ifdef CONFIG_ECORE_LL2 527 struct ecore_ll2_info *p_ll2_info; 528 #endif 529 enum _ecore_status_t rc = ECORE_SUCCESS; 530 int i; 531 532 if (IS_VF(p_dev)) 533 return rc; 534 535 p_dev->fw_data = OSAL_ZALLOC(p_dev, GFP_KERNEL, 536 sizeof(*p_dev->fw_data)); 537 if (!p_dev->fw_data) 538 return ECORE_NOMEM; 539 540 /* Allocate Memory for the Queue->CID mapping */ 541 for_each_hwfn(p_dev, i) { 542 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i]; 543 u32 num_tx_conns = RESC_NUM(p_hwfn, ECORE_L2_QUEUE); 544 int tx_size, rx_size; 545 546 /* @@@TMP - resc management, change to actual required size */ 547 if (p_hwfn->pf_params.eth_pf_params.num_cons > num_tx_conns) 548 num_tx_conns = p_hwfn->pf_params.eth_pf_params.num_cons; 549 tx_size = sizeof(struct ecore_hw_cid_data) * num_tx_conns; 550 rx_size = sizeof(struct ecore_hw_cid_data) * 551 RESC_NUM(p_hwfn, ECORE_L2_QUEUE); 552 553 p_hwfn->p_tx_cids = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL, 554 tx_size); 555 if (!p_hwfn->p_tx_cids) { 556 DP_NOTICE(p_hwfn, true, 557 "Failed to allocate memory for Tx Cids\n"); 558 goto alloc_no_mem; 559 } 560 561 p_hwfn->p_rx_cids = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL, 562 rx_size); 563 if (!p_hwfn->p_rx_cids) { 564 DP_NOTICE(p_hwfn, true, 565 "Failed to allocate memory for Rx Cids\n"); 566 goto alloc_no_mem; 567 } 568 } 569 570 for_each_hwfn(p_dev, i) { 571 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i]; 572 u32 n_eqes, num_cons; 573 574 /* First allocate the context manager structure */ 575 rc = ecore_cxt_mngr_alloc(p_hwfn); 576 if (rc) 577 goto alloc_err; 578 579 /* Set the HW cid/tid numbers (in the contest manager) 580 * Must be done prior to any further computations. 581 */ 582 rc = ecore_cxt_set_pf_params(p_hwfn); 583 if (rc) 584 goto alloc_err; 585 586 /* Prepare and process QM requirements */ 587 rc = ecore_init_qm_info(p_hwfn, true); 588 if (rc) 589 goto alloc_err; 590 591 /* Compute the ILT client partition */ 592 rc = ecore_cxt_cfg_ilt_compute(p_hwfn); 593 if (rc) 594 goto alloc_err; 595 596 /* CID map / ILT shadow table / T2 597 * The talbes sizes are determined by the computations above 598 */ 599 rc = ecore_cxt_tables_alloc(p_hwfn); 600 if (rc) 601 goto alloc_err; 602 603 /* SPQ, must follow ILT because initializes SPQ context */ 604 rc = ecore_spq_alloc(p_hwfn); 605 if (rc) 606 goto alloc_err; 607 608 /* SP status block allocation */ 609 p_hwfn->p_dpc_ptt = ecore_get_reserved_ptt(p_hwfn, 610 RESERVED_PTT_DPC); 611 612 rc = ecore_int_alloc(p_hwfn, p_hwfn->p_main_ptt); 613 if (rc) 614 goto alloc_err; 615 616 rc = ecore_iov_alloc(p_hwfn); 617 if (rc) 618 goto alloc_err; 619 620 /* EQ */ 621 n_eqes = ecore_chain_get_capacity(&p_hwfn->p_spq->chain); 622 if ((p_hwfn->hw_info.personality == ECORE_PCI_ETH_ROCE) || 623 (p_hwfn->hw_info.personality == ECORE_PCI_IWARP)) { 624 /* Calculate the EQ size 625 * --------------------- 626 * Each ICID may generate up to one event at a time i.e. 627 * the event must be handled/cleared before a new one 628 * can be generated. We calculate the sum of events per 629 * protocol and create an EQ deep enough to handle the 630 * worst case: 631 * - Core - according to SPQ. 632 * - RoCE - per QP there are a couple of ICIDs, one 633 * responder and one requester, each can 634 * generate an EQE => n_eqes_qp = 2 * n_qp. 635 * Each CQ can generate an EQE. There are 2 CQs 636 * per QP => n_eqes_cq = 2 * n_qp. 637 * Hence the RoCE total is 4 * n_qp or 638 * 2 * num_cons. 639 * - ENet - There can be up to two events per VF. One 640 * for VF-PF channel and another for VF FLR 641 * initial cleanup. The number of VFs is 642 * bounded by MAX_NUM_VFS_BB, and is much 643 * smaller than RoCE's so we avoid exact 644 * calculation. 645 */ 646 if (p_hwfn->hw_info.personality == ECORE_PCI_ETH_ROCE) { 647 num_cons = 648 ecore_cxt_get_proto_cid_count( 649 p_hwfn, 650 PROTOCOLID_ROCE, 651 0); 652 num_cons *= 2; 653 } else { 654 num_cons = ecore_cxt_get_proto_cid_count( 655 p_hwfn, 656 PROTOCOLID_IWARP, 657 0); 658 } 659 n_eqes += num_cons + 2 * MAX_NUM_VFS_BB; 660 } else if (p_hwfn->hw_info.personality == ECORE_PCI_ISCSI) { 661 num_cons = 662 ecore_cxt_get_proto_cid_count(p_hwfn, 663 PROTOCOLID_ISCSI, 0); 664 n_eqes += 2 * num_cons; 665 } 666 667 if (n_eqes > 0xFFFF) { 668 DP_ERR(p_hwfn, "Cannot allocate 0x%x EQ elements." 669 "The maximum of a u16 chain is 0x%x\n", 670 n_eqes, 0xFFFF); 671 rc = ECORE_INVAL; 672 goto alloc_err; 673 } 674 675 p_eq = ecore_eq_alloc(p_hwfn, (u16)n_eqes); 676 if (!p_eq) 677 goto alloc_no_mem; 678 p_hwfn->p_eq = p_eq; 679 680 p_consq = ecore_consq_alloc(p_hwfn); 681 if (!p_consq) 682 goto alloc_no_mem; 683 p_hwfn->p_consq = p_consq; 684 685 #ifdef CONFIG_ECORE_LL2 686 if (p_hwfn->using_ll2) { 687 p_ll2_info = ecore_ll2_alloc(p_hwfn); 688 if (!p_ll2_info) 689 goto alloc_no_mem; 690 p_hwfn->p_ll2_info = p_ll2_info; 691 } 692 #endif 693 694 /* DMA info initialization */ 695 rc = ecore_dmae_info_alloc(p_hwfn); 696 if (rc) { 697 DP_NOTICE(p_hwfn, true, 698 "Failed to allocate memory for dmae_info structure\n"); 699 goto alloc_err; 700 } 701 702 /* DCBX initialization */ 703 rc = ecore_dcbx_info_alloc(p_hwfn); 704 if (rc) { 705 DP_NOTICE(p_hwfn, true, 706 "Failed to allocate memory for dcbx structure\n"); 707 goto alloc_err; 708 } 709 } 710 711 p_dev->reset_stats = OSAL_ZALLOC(p_dev, GFP_KERNEL, 712 sizeof(*p_dev->reset_stats)); 713 if (!p_dev->reset_stats) { 714 DP_NOTICE(p_dev, true, "Failed to allocate reset statistics\n"); 715 goto alloc_no_mem; 716 } 717 718 return ECORE_SUCCESS; 719 720 alloc_no_mem: 721 rc = ECORE_NOMEM; 722 alloc_err: 723 ecore_resc_free(p_dev); 724 return rc; 725 } 726 727 void ecore_resc_setup(struct ecore_dev *p_dev) 728 { 729 int i; 730 731 if (IS_VF(p_dev)) 732 return; 733 734 for_each_hwfn(p_dev, i) { 735 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i]; 736 737 ecore_cxt_mngr_setup(p_hwfn); 738 ecore_spq_setup(p_hwfn); 739 ecore_eq_setup(p_hwfn, p_hwfn->p_eq); 740 ecore_consq_setup(p_hwfn, p_hwfn->p_consq); 741 742 /* Read shadow of current MFW mailbox */ 743 ecore_mcp_read_mb(p_hwfn, p_hwfn->p_main_ptt); 744 OSAL_MEMCPY(p_hwfn->mcp_info->mfw_mb_shadow, 745 p_hwfn->mcp_info->mfw_mb_cur, 746 p_hwfn->mcp_info->mfw_mb_length); 747 748 ecore_int_setup(p_hwfn, p_hwfn->p_main_ptt); 749 750 ecore_iov_setup(p_hwfn, p_hwfn->p_main_ptt); 751 #ifdef CONFIG_ECORE_LL2 752 if (p_hwfn->using_ll2) 753 ecore_ll2_setup(p_hwfn, p_hwfn->p_ll2_info); 754 #endif 755 } 756 } 757 758 #define FINAL_CLEANUP_POLL_CNT (100) 759 #define FINAL_CLEANUP_POLL_TIME (10) 760 enum _ecore_status_t ecore_final_cleanup(struct ecore_hwfn *p_hwfn, 761 struct ecore_ptt *p_ptt, 762 u16 id, bool is_vf) 763 { 764 u32 command = 0, addr, count = FINAL_CLEANUP_POLL_CNT; 765 enum _ecore_status_t rc = ECORE_TIMEOUT; 766 767 #ifndef ASIC_ONLY 768 if (CHIP_REV_IS_TEDIBEAR(p_hwfn->p_dev) || 769 CHIP_REV_IS_SLOW(p_hwfn->p_dev)) { 770 DP_INFO(p_hwfn, "Skipping final cleanup for non-ASIC\n"); 771 return ECORE_SUCCESS; 772 } 773 #endif 774 775 addr = GTT_BAR0_MAP_REG_USDM_RAM + 776 USTORM_FLR_FINAL_ACK_OFFSET(p_hwfn->rel_pf_id); 777 778 if (is_vf) 779 id += 0x10; 780 781 command |= X_FINAL_CLEANUP_AGG_INT << 782 SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_SHIFT; 783 command |= 1 << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_SHIFT; 784 command |= id << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_SHIFT; 785 command |= SDM_COMP_TYPE_AGG_INT << SDM_OP_GEN_COMP_TYPE_SHIFT; 786 787 /* Make sure notification is not set before initiating final cleanup */ 788 789 if (REG_RD(p_hwfn, addr)) { 790 DP_NOTICE(p_hwfn, false, 791 "Unexpected; Found final cleanup notification"); 792 DP_NOTICE(p_hwfn, false, 793 " before initiating final cleanup\n"); 794 REG_WR(p_hwfn, addr, 0); 795 } 796 797 DP_VERBOSE(p_hwfn, ECORE_MSG_IOV, 798 "Sending final cleanup for PFVF[%d] [Command %08x\n]", 799 id, OSAL_CPU_TO_LE32(command)); 800 801 ecore_wr(p_hwfn, p_ptt, XSDM_REG_OPERATION_GEN, 802 OSAL_CPU_TO_LE32(command)); 803 804 /* Poll until completion */ 805 while (!REG_RD(p_hwfn, addr) && count--) 806 OSAL_MSLEEP(FINAL_CLEANUP_POLL_TIME); 807 808 if (REG_RD(p_hwfn, addr)) 809 rc = ECORE_SUCCESS; 810 else 811 DP_NOTICE(p_hwfn, true, 812 "Failed to receive FW final cleanup notification\n"); 813 814 /* Cleanup afterwards */ 815 REG_WR(p_hwfn, addr, 0); 816 817 return rc; 818 } 819 820 static enum _ecore_status_t ecore_calc_hw_mode(struct ecore_hwfn *p_hwfn) 821 { 822 int hw_mode = 0; 823 824 if (ECORE_IS_BB_B0(p_hwfn->p_dev)) { 825 hw_mode |= 1 << MODE_BB_B0; 826 } else if (ECORE_IS_AH(p_hwfn->p_dev)) { 827 hw_mode |= 1 << MODE_K2; 828 } else { 829 DP_NOTICE(p_hwfn, true, "Unknown chip type %#x\n", 830 p_hwfn->p_dev->type); 831 return ECORE_INVAL; 832 } 833 834 /* Ports per engine is based on the values in CNIG_REG_NW_PORT_MODE */ 835 switch (p_hwfn->p_dev->num_ports_in_engines) { 836 case 1: 837 hw_mode |= 1 << MODE_PORTS_PER_ENG_1; 838 break; 839 case 2: 840 hw_mode |= 1 << MODE_PORTS_PER_ENG_2; 841 break; 842 case 4: 843 hw_mode |= 1 << MODE_PORTS_PER_ENG_4; 844 break; 845 default: 846 DP_NOTICE(p_hwfn, true, 847 "num_ports_in_engine = %d not supported\n", 848 p_hwfn->p_dev->num_ports_in_engines); 849 return ECORE_INVAL; 850 } 851 852 switch (p_hwfn->p_dev->mf_mode) { 853 case ECORE_MF_DEFAULT: 854 case ECORE_MF_NPAR: 855 hw_mode |= 1 << MODE_MF_SI; 856 break; 857 case ECORE_MF_OVLAN: 858 hw_mode |= 1 << MODE_MF_SD; 859 break; 860 default: 861 DP_NOTICE(p_hwfn, true, 862 "Unsupported MF mode, init as DEFAULT\n"); 863 hw_mode |= 1 << MODE_MF_SI; 864 } 865 866 #ifndef ASIC_ONLY 867 if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) { 868 if (CHIP_REV_IS_FPGA(p_hwfn->p_dev)) { 869 hw_mode |= 1 << MODE_FPGA; 870 } else { 871 if (p_hwfn->p_dev->b_is_emul_full) 872 hw_mode |= 1 << MODE_EMUL_FULL; 873 else 874 hw_mode |= 1 << MODE_EMUL_REDUCED; 875 } 876 } else 877 #endif 878 hw_mode |= 1 << MODE_ASIC; 879 880 if (p_hwfn->p_dev->num_hwfns > 1) 881 hw_mode |= 1 << MODE_100G; 882 883 p_hwfn->hw_info.hw_mode = hw_mode; 884 885 DP_VERBOSE(p_hwfn, (ECORE_MSG_PROBE | ECORE_MSG_IFUP), 886 "Configuring function for hw_mode: 0x%08x\n", 887 p_hwfn->hw_info.hw_mode); 888 889 return ECORE_SUCCESS; 890 } 891 892 #ifndef ASIC_ONLY 893 /* MFW-replacement initializations for non-ASIC */ 894 static enum _ecore_status_t ecore_hw_init_chip(struct ecore_hwfn *p_hwfn, 895 struct ecore_ptt *p_ptt) 896 { 897 u32 pl_hv = 1; 898 int i; 899 900 if (CHIP_REV_IS_EMUL(p_hwfn->p_dev) && ECORE_IS_AH(p_hwfn->p_dev)) 901 pl_hv |= 0x600; 902 903 ecore_wr(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV + 4, pl_hv); 904 905 if (CHIP_REV_IS_EMUL(p_hwfn->p_dev) && ECORE_IS_AH(p_hwfn->p_dev)) 906 ecore_wr(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV_2, 0x3ffffff); 907 908 /* initialize port mode to 4x10G_E (10G with 4x10 SERDES) */ 909 /* CNIG_REG_NW_PORT_MODE is same for A0 and B0 */ 910 if (!CHIP_REV_IS_EMUL(p_hwfn->p_dev) || !ECORE_IS_AH(p_hwfn->p_dev)) 911 ecore_wr(p_hwfn, p_ptt, CNIG_REG_NW_PORT_MODE_BB_B0, 4); 912 913 if (CHIP_REV_IS_EMUL(p_hwfn->p_dev) && ECORE_IS_AH(p_hwfn->p_dev)) { 914 /* 2 for 4-port, 1 for 2-port, 0 for 1-port */ 915 ecore_wr(p_hwfn, p_ptt, MISC_REG_PORT_MODE, 916 (p_hwfn->p_dev->num_ports_in_engines >> 1)); 917 918 ecore_wr(p_hwfn, p_ptt, MISC_REG_BLOCK_256B_EN, 919 p_hwfn->p_dev->num_ports_in_engines == 4 ? 0 : 3); 920 } 921 922 /* Poll on RBC */ 923 ecore_wr(p_hwfn, p_ptt, PSWRQ2_REG_RBC_DONE, 1); 924 for (i = 0; i < 100; i++) { 925 OSAL_UDELAY(50); 926 if (ecore_rd(p_hwfn, p_ptt, PSWRQ2_REG_CFG_DONE) == 1) 927 break; 928 } 929 if (i == 100) 930 DP_NOTICE(p_hwfn, true, 931 "RBC done failed to complete in PSWRQ2\n"); 932 933 return ECORE_SUCCESS; 934 } 935 #endif 936 937 /* Init run time data for all PFs and their VFs on an engine. 938 * TBD - for VFs - Once we have parent PF info for each VF in 939 * shmem available as CAU requires knowledge of parent PF for each VF. 940 */ 941 static void ecore_init_cau_rt_data(struct ecore_dev *p_dev) 942 { 943 u32 offset = CAU_REG_SB_VAR_MEMORY_RT_OFFSET; 944 int i, sb_id; 945 946 for_each_hwfn(p_dev, i) { 947 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i]; 948 struct ecore_igu_info *p_igu_info; 949 struct ecore_igu_block *p_block; 950 struct cau_sb_entry sb_entry; 951 952 p_igu_info = p_hwfn->hw_info.p_igu_info; 953 954 for (sb_id = 0; sb_id < ECORE_MAPPING_MEMORY_SIZE(p_dev); 955 sb_id++) { 956 p_block = &p_igu_info->igu_map.igu_blocks[sb_id]; 957 958 if (!p_block->is_pf) 959 continue; 960 961 ecore_init_cau_sb_entry(p_hwfn, &sb_entry, 962 p_block->function_id, 0, 0); 963 STORE_RT_REG_AGG(p_hwfn, offset + sb_id * 2, sb_entry); 964 } 965 } 966 } 967 968 static enum _ecore_status_t ecore_hw_init_common(struct ecore_hwfn *p_hwfn, 969 struct ecore_ptt *p_ptt, 970 int hw_mode) 971 { 972 struct ecore_qm_info *qm_info = &p_hwfn->qm_info; 973 struct ecore_dev *p_dev = p_hwfn->p_dev; 974 u8 vf_id, max_num_vfs; 975 u16 num_pfs, pf_id; 976 u32 concrete_fid; 977 enum _ecore_status_t rc = ECORE_SUCCESS; 978 979 ecore_init_cau_rt_data(p_dev); 980 981 /* Program GTT windows */ 982 ecore_gtt_init(p_hwfn); 983 984 #ifndef ASIC_ONLY 985 if (CHIP_REV_IS_EMUL(p_dev)) { 986 rc = ecore_hw_init_chip(p_hwfn, p_hwfn->p_main_ptt); 987 if (rc != ECORE_SUCCESS) 988 return rc; 989 } 990 #endif 991 992 if (p_hwfn->mcp_info) { 993 if (p_hwfn->mcp_info->func_info.bandwidth_max) 994 qm_info->pf_rl_en = 1; 995 if (p_hwfn->mcp_info->func_info.bandwidth_min) 996 qm_info->pf_wfq_en = 1; 997 } 998 999 ecore_qm_common_rt_init(p_hwfn, 1000 p_dev->num_ports_in_engines, 1001 qm_info->max_phys_tcs_per_port, 1002 qm_info->pf_rl_en, qm_info->pf_wfq_en, 1003 qm_info->vport_rl_en, qm_info->vport_wfq_en, 1004 qm_info->qm_port_params); 1005 1006 ecore_cxt_hw_init_common(p_hwfn); 1007 1008 /* Close gate from NIG to BRB/Storm; By default they are open, but 1009 * we close them to prevent NIG from passing data to reset blocks. 1010 * Should have been done in the ENGINE phase, but init-tool lacks 1011 * proper port-pretend capabilities. 1012 */ 1013 ecore_wr(p_hwfn, p_ptt, NIG_REG_RX_BRB_OUT_EN, 0); 1014 ecore_wr(p_hwfn, p_ptt, NIG_REG_STORM_OUT_EN, 0); 1015 ecore_port_pretend(p_hwfn, p_ptt, p_hwfn->port_id ^ 1); 1016 ecore_wr(p_hwfn, p_ptt, NIG_REG_RX_BRB_OUT_EN, 0); 1017 ecore_wr(p_hwfn, p_ptt, NIG_REG_STORM_OUT_EN, 0); 1018 ecore_port_unpretend(p_hwfn, p_ptt); 1019 1020 rc = ecore_init_run(p_hwfn, p_ptt, PHASE_ENGINE, ANY_PHASE_ID, hw_mode); 1021 if (rc != ECORE_SUCCESS) 1022 return rc; 1023 1024 /* @@TBD MichalK - should add VALIDATE_VFID to init tool... 1025 * need to decide with which value, maybe runtime 1026 */ 1027 ecore_wr(p_hwfn, p_ptt, PSWRQ2_REG_L2P_VALIDATE_VFID, 0); 1028 ecore_wr(p_hwfn, p_ptt, PGLUE_B_REG_USE_CLIENTID_IN_TAG, 1); 1029 1030 if (ECORE_IS_BB(p_dev)) { 1031 /* Workaround clears ROCE search for all functions to prevent 1032 * involving non initialized function in processing ROCE packet. 1033 */ 1034 num_pfs = NUM_OF_ENG_PFS(p_dev); 1035 for (pf_id = 0; pf_id < num_pfs; pf_id++) { 1036 ecore_fid_pretend(p_hwfn, p_ptt, pf_id); 1037 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0); 1038 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0); 1039 } 1040 /* pretend to original PF */ 1041 ecore_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id); 1042 } 1043 1044 /* Workaround for avoiding CCFC execution error when getting packets 1045 * with CRC errors, and allowing instead the invoking of the FW error 1046 * handler. 1047 * This is not done inside the init tool since it currently can't 1048 * perform a pretending to VFs. 1049 */ 1050 max_num_vfs = ECORE_IS_AH(p_dev) ? MAX_NUM_VFS_K2 : MAX_NUM_VFS_BB; 1051 for (vf_id = 0; vf_id < max_num_vfs; vf_id++) { 1052 concrete_fid = ecore_vfid_to_concrete(p_hwfn, vf_id); 1053 ecore_fid_pretend(p_hwfn, p_ptt, (u16)concrete_fid); 1054 ecore_wr(p_hwfn, p_ptt, CCFC_REG_STRONG_ENABLE_VF, 0x1); 1055 ecore_wr(p_hwfn, p_ptt, CCFC_REG_WEAK_ENABLE_VF, 0x0); 1056 ecore_wr(p_hwfn, p_ptt, TCFC_REG_STRONG_ENABLE_VF, 0x1); 1057 ecore_wr(p_hwfn, p_ptt, TCFC_REG_WEAK_ENABLE_VF, 0x0); 1058 } 1059 /* pretend to original PF */ 1060 ecore_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id); 1061 1062 return rc; 1063 } 1064 1065 #ifndef ASIC_ONLY 1066 #define MISC_REG_RESET_REG_2_XMAC_BIT (1 << 4) 1067 #define MISC_REG_RESET_REG_2_XMAC_SOFT_BIT (1 << 5) 1068 1069 #define PMEG_IF_BYTE_COUNT 8 1070 1071 static void ecore_wr_nw_port(struct ecore_hwfn *p_hwfn, 1072 struct ecore_ptt *p_ptt, 1073 u32 addr, u64 data, u8 reg_type, u8 port) 1074 { 1075 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK, 1076 "CMD: %08x, ADDR: 0x%08x, DATA: %08x:%08x\n", 1077 ecore_rd(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_CMD_BB_B0) | 1078 (8 << PMEG_IF_BYTE_COUNT), 1079 (reg_type << 25) | (addr << 8) | port, 1080 (u32)((data >> 32) & 0xffffffff), 1081 (u32)(data & 0xffffffff)); 1082 1083 ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_CMD_BB_B0, 1084 (ecore_rd(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_CMD_BB_B0) & 1085 0xffff00fe) | (8 << PMEG_IF_BYTE_COUNT)); 1086 ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_ADDR_BB_B0, 1087 (reg_type << 25) | (addr << 8) | port); 1088 ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_WRDATA_BB_B0, 1089 data & 0xffffffff); 1090 ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_WRDATA_BB_B0, 1091 (data >> 32) & 0xffffffff); 1092 } 1093 1094 #define XLPORT_MODE_REG (0x20a) 1095 #define XLPORT_MAC_CONTROL (0x210) 1096 #define XLPORT_FLOW_CONTROL_CONFIG (0x207) 1097 #define XLPORT_ENABLE_REG (0x20b) 1098 1099 #define XLMAC_CTRL (0x600) 1100 #define XLMAC_MODE (0x601) 1101 #define XLMAC_RX_MAX_SIZE (0x608) 1102 #define XLMAC_TX_CTRL (0x604) 1103 #define XLMAC_PAUSE_CTRL (0x60d) 1104 #define XLMAC_PFC_CTRL (0x60e) 1105 1106 static void ecore_emul_link_init_ah(struct ecore_hwfn *p_hwfn, 1107 struct ecore_ptt *p_ptt) 1108 { 1109 u8 port = p_hwfn->port_id; 1110 u32 mac_base = NWM_REG_MAC0 + (port << 2) * NWM_REG_MAC0_SIZE; 1111 1112 ecore_wr(p_hwfn, p_ptt, CNIG_REG_NIG_PORT0_CONF_K2 + (port << 2), 1113 (1 << CNIG_REG_NIG_PORT0_CONF_NIG_PORT_ENABLE_0_SHIFT) | 1114 (port << CNIG_REG_NIG_PORT0_CONF_NIG_PORT_NWM_PORT_MAP_0_SHIFT) 1115 | (0 << CNIG_REG_NIG_PORT0_CONF_NIG_PORT_RATE_0_SHIFT)); 1116 1117 ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_XIF_MODE, 1118 1 << ETH_MAC_REG_XIF_MODE_XGMII_SHIFT); 1119 1120 ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_FRM_LENGTH, 1121 9018 << ETH_MAC_REG_FRM_LENGTH_FRM_LENGTH_SHIFT); 1122 1123 ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_TX_IPG_LENGTH, 1124 0xc << ETH_MAC_REG_TX_IPG_LENGTH_TXIPG_SHIFT); 1125 1126 ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_RX_FIFO_SECTIONS, 1127 8 << ETH_MAC_REG_RX_FIFO_SECTIONS_RX_SECTION_FULL_SHIFT); 1128 1129 ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_TX_FIFO_SECTIONS, 1130 (0xA << ETH_MAC_REG_TX_FIFO_SECTIONS_TX_SECTION_EMPTY_SHIFT) | 1131 (8 << ETH_MAC_REG_TX_FIFO_SECTIONS_TX_SECTION_FULL_SHIFT)); 1132 1133 ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_COMMAND_CONFIG, 0xa853); 1134 } 1135 1136 static void ecore_emul_link_init(struct ecore_hwfn *p_hwfn, 1137 struct ecore_ptt *p_ptt) 1138 { 1139 u8 loopback = 0, port = p_hwfn->port_id * 2; 1140 1141 DP_INFO(p_hwfn->p_dev, "Configurating Emulation Link %02x\n", port); 1142 1143 if (ECORE_IS_AH(p_hwfn->p_dev)) { 1144 ecore_emul_link_init_ah(p_hwfn, p_ptt); 1145 return; 1146 } 1147 1148 /* XLPORT MAC MODE *//* 0 Quad, 4 Single... */ 1149 ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_MODE_REG, (0x4 << 4) | 0x4, 1, 1150 port); 1151 ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_MAC_CONTROL, 0, 1, port); 1152 /* XLMAC: SOFT RESET */ 1153 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_CTRL, 0x40, 0, port); 1154 /* XLMAC: Port Speed >= 10Gbps */ 1155 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_MODE, 0x40, 0, port); 1156 /* XLMAC: Max Size */ 1157 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_RX_MAX_SIZE, 0x3fff, 0, port); 1158 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_TX_CTRL, 1159 0x01000000800ULL | (0xa << 12) | ((u64)1 << 38), 1160 0, port); 1161 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_PAUSE_CTRL, 0x7c000, 0, port); 1162 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_PFC_CTRL, 1163 0x30ffffc000ULL, 0, port); 1164 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_CTRL, 0x3 | (loopback << 2), 0, 1165 port); /* XLMAC: TX_EN, RX_EN */ 1166 /* XLMAC: TX_EN, RX_EN, SW_LINK_STATUS */ 1167 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_CTRL, 1168 0x1003 | (loopback << 2), 0, port); 1169 /* Enabled Parallel PFC interface */ 1170 ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_FLOW_CONTROL_CONFIG, 1, 0, port); 1171 1172 /* XLPORT port enable */ 1173 ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_ENABLE_REG, 0xf, 1, port); 1174 } 1175 1176 static void ecore_link_init(struct ecore_hwfn *p_hwfn, 1177 struct ecore_ptt *p_ptt, u8 port) 1178 { 1179 int port_offset = port ? 0x800 : 0; 1180 u32 xmac_rxctrl = 0; 1181 1182 /* Reset of XMAC */ 1183 /* FIXME: move to common start */ 1184 ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + 2 * sizeof(u32), 1185 MISC_REG_RESET_REG_2_XMAC_BIT); /* Clear */ 1186 OSAL_MSLEEP(1); 1187 ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + sizeof(u32), 1188 MISC_REG_RESET_REG_2_XMAC_BIT); /* Set */ 1189 1190 ecore_wr(p_hwfn, p_ptt, MISC_REG_XMAC_CORE_PORT_MODE, 1); 1191 1192 /* Set the number of ports on the Warp Core to 10G */ 1193 ecore_wr(p_hwfn, p_ptt, MISC_REG_XMAC_PHY_PORT_MODE, 3); 1194 1195 /* Soft reset of XMAC */ 1196 ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + 2 * sizeof(u32), 1197 MISC_REG_RESET_REG_2_XMAC_SOFT_BIT); 1198 OSAL_MSLEEP(1); 1199 ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + sizeof(u32), 1200 MISC_REG_RESET_REG_2_XMAC_SOFT_BIT); 1201 1202 /* FIXME: move to common end */ 1203 if (CHIP_REV_IS_FPGA(p_hwfn->p_dev)) 1204 ecore_wr(p_hwfn, p_ptt, XMAC_REG_MODE + port_offset, 0x20); 1205 1206 /* Set Max packet size: initialize XMAC block register for port 0 */ 1207 ecore_wr(p_hwfn, p_ptt, XMAC_REG_RX_MAX_SIZE + port_offset, 0x2710); 1208 1209 /* CRC append for Tx packets: init XMAC block register for port 1 */ 1210 ecore_wr(p_hwfn, p_ptt, XMAC_REG_TX_CTRL_LO + port_offset, 0xC800); 1211 1212 /* Enable TX and RX: initialize XMAC block register for port 1 */ 1213 ecore_wr(p_hwfn, p_ptt, XMAC_REG_CTRL + port_offset, 1214 XMAC_REG_CTRL_TX_EN | XMAC_REG_CTRL_RX_EN); 1215 xmac_rxctrl = ecore_rd(p_hwfn, p_ptt, XMAC_REG_RX_CTRL + port_offset); 1216 xmac_rxctrl |= XMAC_REG_RX_CTRL_PROCESS_VARIABLE_PREAMBLE; 1217 ecore_wr(p_hwfn, p_ptt, XMAC_REG_RX_CTRL + port_offset, xmac_rxctrl); 1218 } 1219 #endif 1220 1221 static enum _ecore_status_t ecore_hw_init_port(struct ecore_hwfn *p_hwfn, 1222 struct ecore_ptt *p_ptt, 1223 int hw_mode) 1224 { 1225 enum _ecore_status_t rc = ECORE_SUCCESS; 1226 1227 rc = ecore_init_run(p_hwfn, p_ptt, PHASE_PORT, p_hwfn->port_id, 1228 hw_mode); 1229 if (rc != ECORE_SUCCESS) 1230 return rc; 1231 #ifndef ASIC_ONLY 1232 if (CHIP_REV_IS_ASIC(p_hwfn->p_dev)) 1233 return ECORE_SUCCESS; 1234 1235 if (CHIP_REV_IS_FPGA(p_hwfn->p_dev)) { 1236 if (ECORE_IS_AH(p_hwfn->p_dev)) 1237 return ECORE_SUCCESS; 1238 ecore_link_init(p_hwfn, p_ptt, p_hwfn->port_id); 1239 } else if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) { 1240 if (p_hwfn->p_dev->num_hwfns > 1) { 1241 /* Activate OPTE in CMT */ 1242 u32 val; 1243 1244 val = ecore_rd(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV); 1245 val |= 0x10; 1246 ecore_wr(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV, val); 1247 ecore_wr(p_hwfn, p_ptt, MISC_REG_CLK_100G_MODE, 1); 1248 ecore_wr(p_hwfn, p_ptt, MISCS_REG_CLK_100G_MODE, 1); 1249 ecore_wr(p_hwfn, p_ptt, MISC_REG_OPTE_MODE, 1); 1250 ecore_wr(p_hwfn, p_ptt, 1251 NIG_REG_LLH_ENG_CLS_TCP_4_TUPLE_SEARCH, 1); 1252 ecore_wr(p_hwfn, p_ptt, 1253 NIG_REG_LLH_ENG_CLS_ENG_ID_TBL, 0x55555555); 1254 ecore_wr(p_hwfn, p_ptt, 1255 NIG_REG_LLH_ENG_CLS_ENG_ID_TBL + 0x4, 1256 0x55555555); 1257 } 1258 1259 ecore_emul_link_init(p_hwfn, p_ptt); 1260 } else { 1261 DP_INFO(p_hwfn->p_dev, "link is not being configured\n"); 1262 } 1263 #endif 1264 1265 return rc; 1266 } 1267 1268 static enum _ecore_status_t 1269 ecore_hw_init_dpi_size(struct ecore_hwfn *p_hwfn, 1270 struct ecore_ptt *p_ptt, u32 pwm_region_size, u32 n_cpus) 1271 { 1272 u32 dpi_page_size_1, dpi_page_size_2, dpi_page_size; 1273 u32 dpi_bit_shift, dpi_count; 1274 u32 min_dpis; 1275 1276 /* Calculate DPI size 1277 * ------------------ 1278 * The PWM region contains Doorbell Pages. The first is reserverd for 1279 * the kernel for, e.g, L2. The others are free to be used by non- 1280 * trusted applications, typically from user space. Each page, called a 1281 * doorbell page is sectioned into windows that allow doorbells to be 1282 * issued in parallel by the kernel/application. The size of such a 1283 * window (a.k.a. WID) is 1kB. 1284 * Summary: 1285 * 1kB WID x N WIDS = DPI page size 1286 * DPI page size x N DPIs = PWM region size 1287 * Notes: 1288 * The size of the DPI page size must be in multiples of OSAL_PAGE_SIZE 1289 * in order to ensure that two applications won't share the same page. 1290 * It also must contain at least one WID per CPU to allow parallelism. 1291 * It also must be a power of 2, since it is stored as a bit shift. 1292 * 1293 * The DPI page size is stored in a register as 'dpi_bit_shift' so that 1294 * 0 is 4kB, 1 is 8kB and etc. Hence the minimum size is 4,096 1295 * containing 4 WIDs. 1296 */ 1297 dpi_page_size_1 = ECORE_WID_SIZE * n_cpus; 1298 dpi_page_size_2 = OSAL_MAX_T(u32, ECORE_WID_SIZE, OSAL_PAGE_SIZE); 1299 dpi_page_size = OSAL_MAX_T(u32, dpi_page_size_1, dpi_page_size_2); 1300 dpi_page_size = OSAL_ROUNDUP_POW_OF_TWO(dpi_page_size); 1301 dpi_bit_shift = OSAL_LOG2(dpi_page_size / 4096); 1302 1303 dpi_count = pwm_region_size / dpi_page_size; 1304 1305 min_dpis = p_hwfn->pf_params.rdma_pf_params.min_dpis; 1306 min_dpis = OSAL_MAX_T(u32, ECORE_MIN_DPIS, min_dpis); 1307 1308 /* Update hwfn */ 1309 p_hwfn->dpi_size = dpi_page_size; 1310 p_hwfn->dpi_count = dpi_count; 1311 1312 /* Update registers */ 1313 ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_DPI_BIT_SHIFT, dpi_bit_shift); 1314 1315 if (dpi_count < min_dpis) 1316 return ECORE_NORESOURCES; 1317 1318 return ECORE_SUCCESS; 1319 } 1320 1321 enum ECORE_ROCE_EDPM_MODE { 1322 ECORE_ROCE_EDPM_MODE_ENABLE = 0, 1323 ECORE_ROCE_EDPM_MODE_FORCE_ON = 1, 1324 ECORE_ROCE_EDPM_MODE_DISABLE = 2, 1325 }; 1326 1327 static enum _ecore_status_t 1328 ecore_hw_init_pf_doorbell_bar(struct ecore_hwfn *p_hwfn, 1329 struct ecore_ptt *p_ptt) 1330 { 1331 u32 pwm_regsize, norm_regsize; 1332 u32 non_pwm_conn, min_addr_reg1; 1333 u32 db_bar_size, n_cpus; 1334 u32 roce_edpm_mode; 1335 u32 pf_dems_shift; 1336 int rc = ECORE_SUCCESS; 1337 u8 cond; 1338 1339 db_bar_size = ecore_hw_bar_size(p_hwfn, BAR_ID_1); 1340 if (p_hwfn->p_dev->num_hwfns > 1) 1341 db_bar_size /= 2; 1342 1343 /* Calculate doorbell regions 1344 * ----------------------------------- 1345 * The doorbell BAR is made of two regions. The first is called normal 1346 * region and the second is called PWM region. In the normal region 1347 * each ICID has its own set of addresses so that writing to that 1348 * specific address identifies the ICID. In the Process Window Mode 1349 * region the ICID is given in the data written to the doorbell. The 1350 * above per PF register denotes the offset in the doorbell BAR in which 1351 * the PWM region begins. 1352 * The normal region has ECORE_PF_DEMS_SIZE bytes per ICID, that is per 1353 * non-PWM connection. The calculation below computes the total non-PWM 1354 * connections. The DORQ_REG_PF_MIN_ADDR_REG1 register is 1355 * in units of 4,096 bytes. 1356 */ 1357 non_pwm_conn = ecore_cxt_get_proto_cid_start(p_hwfn, PROTOCOLID_CORE) + 1358 ecore_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_CORE, 1359 OSAL_NULL) + 1360 ecore_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_ETH, OSAL_NULL); 1361 norm_regsize = ROUNDUP(ECORE_PF_DEMS_SIZE * non_pwm_conn, 4096); 1362 min_addr_reg1 = norm_regsize / 4096; 1363 pwm_regsize = db_bar_size - norm_regsize; 1364 1365 /* Check that the normal and PWM sizes are valid */ 1366 if (db_bar_size < norm_regsize) { 1367 DP_ERR(p_hwfn->p_dev, 1368 "Doorbell BAR size 0x%x is too small (normal region is 0x%0x )\n", 1369 db_bar_size, norm_regsize); 1370 return ECORE_NORESOURCES; 1371 } 1372 if (pwm_regsize < ECORE_MIN_PWM_REGION) { 1373 DP_ERR(p_hwfn->p_dev, 1374 "PWM region size 0x%0x is too small. Should be at least 0x%0x (Doorbell BAR size is 0x%x and normal region size is 0x%0x)\n", 1375 pwm_regsize, ECORE_MIN_PWM_REGION, db_bar_size, 1376 norm_regsize); 1377 return ECORE_NORESOURCES; 1378 } 1379 1380 /* Calculate number of DPIs */ 1381 roce_edpm_mode = p_hwfn->pf_params.rdma_pf_params.roce_edpm_mode; 1382 if ((roce_edpm_mode == ECORE_ROCE_EDPM_MODE_ENABLE) || 1383 ((roce_edpm_mode == ECORE_ROCE_EDPM_MODE_FORCE_ON))) { 1384 /* Either EDPM is mandatory, or we are attempting to allocate a 1385 * WID per CPU. 1386 */ 1387 n_cpus = OSAL_NUM_ACTIVE_CPU(); 1388 rc = ecore_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus); 1389 } 1390 1391 cond = ((rc) && (roce_edpm_mode == ECORE_ROCE_EDPM_MODE_ENABLE)) || 1392 (roce_edpm_mode == ECORE_ROCE_EDPM_MODE_DISABLE); 1393 if (cond || p_hwfn->dcbx_no_edpm) { 1394 /* Either EDPM is disabled from user configuration, or it is 1395 * disabled via DCBx, or it is not mandatory and we failed to 1396 * allocated a WID per CPU. 1397 */ 1398 n_cpus = 1; 1399 rc = ecore_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus); 1400 1401 /* If we entered this flow due to DCBX then the DPM register is 1402 * already configured. 1403 */ 1404 } 1405 1406 DP_INFO(p_hwfn, 1407 "doorbell bar: normal_region_size=%d, pwm_region_size=%d", 1408 norm_regsize, pwm_regsize); 1409 DP_INFO(p_hwfn, 1410 " dpi_size=%d, dpi_count=%d, roce_edpm=%s\n", 1411 p_hwfn->dpi_size, p_hwfn->dpi_count, 1412 ((p_hwfn->dcbx_no_edpm) || (p_hwfn->db_bar_no_edpm)) ? 1413 "disabled" : "enabled"); 1414 1415 /* Check return codes from above calls */ 1416 if (rc) { 1417 DP_ERR(p_hwfn, 1418 "Failed to allocate enough DPIs\n"); 1419 return ECORE_NORESOURCES; 1420 } 1421 1422 /* Update hwfn */ 1423 p_hwfn->dpi_start_offset = norm_regsize; 1424 1425 /* Update registers */ 1426 /* DEMS size is configured log2 of DWORDs, hence the division by 4 */ 1427 pf_dems_shift = OSAL_LOG2(ECORE_PF_DEMS_SIZE / 4); 1428 ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_ICID_BIT_SHIFT_NORM, pf_dems_shift); 1429 ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_MIN_ADDR_REG1, min_addr_reg1); 1430 1431 return ECORE_SUCCESS; 1432 } 1433 1434 static enum _ecore_status_t 1435 ecore_hw_init_pf(struct ecore_hwfn *p_hwfn, 1436 struct ecore_ptt *p_ptt, 1437 struct ecore_tunn_start_params *p_tunn, 1438 int hw_mode, 1439 bool b_hw_start, 1440 enum ecore_int_mode int_mode, bool allow_npar_tx_switch) 1441 { 1442 u8 rel_pf_id = p_hwfn->rel_pf_id; 1443 u32 prs_reg; 1444 enum _ecore_status_t rc = ECORE_SUCCESS; 1445 u16 ctrl; 1446 int pos; 1447 1448 if (p_hwfn->mcp_info) { 1449 struct ecore_mcp_function_info *p_info; 1450 1451 p_info = &p_hwfn->mcp_info->func_info; 1452 if (p_info->bandwidth_min) 1453 p_hwfn->qm_info.pf_wfq = p_info->bandwidth_min; 1454 1455 /* Update rate limit once we'll actually have a link */ 1456 p_hwfn->qm_info.pf_rl = 100000; 1457 } 1458 ecore_cxt_hw_init_pf(p_hwfn); 1459 1460 ecore_int_igu_init_rt(p_hwfn); 1461 1462 /* Set VLAN in NIG if needed */ 1463 if (hw_mode & (1 << MODE_MF_SD)) { 1464 DP_VERBOSE(p_hwfn, ECORE_MSG_HW, "Configuring LLH_FUNC_TAG\n"); 1465 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_EN_RT_OFFSET, 1); 1466 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_VALUE_RT_OFFSET, 1467 p_hwfn->hw_info.ovlan); 1468 } 1469 1470 /* Enable classification by MAC if needed */ 1471 if (hw_mode & (1 << MODE_MF_SI)) { 1472 DP_VERBOSE(p_hwfn, ECORE_MSG_HW, 1473 "Configuring TAGMAC_CLS_TYPE\n"); 1474 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAGMAC_CLS_TYPE_RT_OFFSET, 1475 1); 1476 } 1477 1478 /* Protocl Configuration - @@@TBD - should we set 0 otherwise? */ 1479 STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_TCP_RT_OFFSET, 1480 (p_hwfn->hw_info.personality == ECORE_PCI_ISCSI) ? 1 : 0); 1481 STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_FCOE_RT_OFFSET, 1482 (p_hwfn->hw_info.personality == ECORE_PCI_FCOE) ? 1 : 0); 1483 STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_ROCE_RT_OFFSET, 0); 1484 1485 /* perform debug configuration when chip is out of reset */ 1486 OSAL_BEFORE_PF_START((void *)p_hwfn->p_dev, p_hwfn->my_id); 1487 1488 /* Cleanup chip from previous driver if such remains exist */ 1489 rc = ecore_final_cleanup(p_hwfn, p_ptt, rel_pf_id, false); 1490 if (rc != ECORE_SUCCESS) { 1491 ecore_hw_err_notify(p_hwfn, ECORE_HW_ERR_RAMROD_FAIL); 1492 return rc; 1493 } 1494 1495 /* PF Init sequence */ 1496 rc = ecore_init_run(p_hwfn, p_ptt, PHASE_PF, rel_pf_id, hw_mode); 1497 if (rc) 1498 return rc; 1499 1500 /* QM_PF Init sequence (may be invoked separately e.g. for DCB) */ 1501 rc = ecore_init_run(p_hwfn, p_ptt, PHASE_QM_PF, rel_pf_id, hw_mode); 1502 if (rc) 1503 return rc; 1504 1505 /* Pure runtime initializations - directly to the HW */ 1506 ecore_int_igu_init_pure_rt(p_hwfn, p_ptt, true, true); 1507 1508 /* PCI relaxed ordering causes a decrease in the performance on some 1509 * systems. Till a root cause is found, disable this attribute in the 1510 * PCI config space. 1511 */ 1512 /* Not in use @DPDK 1513 * pos = OSAL_PCI_FIND_CAPABILITY(p_hwfn->p_dev, PCI_CAP_ID_EXP); 1514 * if (!pos) { 1515 * DP_NOTICE(p_hwfn, true, 1516 * "Failed to find the PCIe Cap\n"); 1517 * return ECORE_IO; 1518 * } 1519 * OSAL_PCI_READ_CONFIG_WORD(p_hwfn->p_dev, pos + PCI_EXP_DEVCTL, &ctrl); 1520 * ctrl &= ~PCI_EXP_DEVCTL_RELAX_EN; 1521 * OSAL_PCI_WRITE_CONFIG_WORD(p_hwfn->p_dev, pos + PCI_EXP_DEVCTL, ctrl); 1522 */ 1523 1524 rc = ecore_hw_init_pf_doorbell_bar(p_hwfn, p_ptt); 1525 if (rc) 1526 return rc; 1527 if (b_hw_start) { 1528 /* enable interrupts */ 1529 rc = ecore_int_igu_enable(p_hwfn, p_ptt, int_mode); 1530 if (rc != ECORE_SUCCESS) 1531 return rc; 1532 1533 /* send function start command */ 1534 rc = ecore_sp_pf_start(p_hwfn, p_tunn, p_hwfn->p_dev->mf_mode, 1535 allow_npar_tx_switch); 1536 if (rc) { 1537 DP_NOTICE(p_hwfn, true, 1538 "Function start ramrod failed\n"); 1539 } else { 1540 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1); 1541 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE, 1542 "PRS_REG_SEARCH_TAG1: %x\n", prs_reg); 1543 1544 if (p_hwfn->hw_info.personality == ECORE_PCI_FCOE) { 1545 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1, 1546 (1 << 2)); 1547 ecore_wr(p_hwfn, p_ptt, 1548 PRS_REG_PKT_LEN_STAT_TAGS_NOT_COUNTED_FIRST, 1549 0x100); 1550 } 1551 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE, 1552 "PRS_REG_SEARCH registers after start PFn\n"); 1553 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP); 1554 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE, 1555 "PRS_REG_SEARCH_TCP: %x\n", prs_reg); 1556 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP); 1557 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE, 1558 "PRS_REG_SEARCH_UDP: %x\n", prs_reg); 1559 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE); 1560 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE, 1561 "PRS_REG_SEARCH_FCOE: %x\n", prs_reg); 1562 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE); 1563 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE, 1564 "PRS_REG_SEARCH_ROCE: %x\n", prs_reg); 1565 prs_reg = ecore_rd(p_hwfn, p_ptt, 1566 PRS_REG_SEARCH_TCP_FIRST_FRAG); 1567 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE, 1568 "PRS_REG_SEARCH_TCP_FIRST_FRAG: %x\n", 1569 prs_reg); 1570 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1); 1571 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE, 1572 "PRS_REG_SEARCH_TAG1: %x\n", prs_reg); 1573 } 1574 } 1575 return rc; 1576 } 1577 1578 static enum _ecore_status_t 1579 ecore_change_pci_hwfn(struct ecore_hwfn *p_hwfn, 1580 struct ecore_ptt *p_ptt, u8 enable) 1581 { 1582 u32 delay_idx = 0, val, set_val = enable ? 1 : 0; 1583 1584 /* Change PF in PXP */ 1585 ecore_wr(p_hwfn, p_ptt, 1586 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, set_val); 1587 1588 /* wait until value is set - try for 1 second every 50us */ 1589 for (delay_idx = 0; delay_idx < 20000; delay_idx++) { 1590 val = ecore_rd(p_hwfn, p_ptt, 1591 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER); 1592 if (val == set_val) 1593 break; 1594 1595 OSAL_UDELAY(50); 1596 } 1597 1598 if (val != set_val) { 1599 DP_NOTICE(p_hwfn, true, 1600 "PFID_ENABLE_MASTER wasn't changed after a second\n"); 1601 return ECORE_UNKNOWN_ERROR; 1602 } 1603 1604 return ECORE_SUCCESS; 1605 } 1606 1607 static void ecore_reset_mb_shadow(struct ecore_hwfn *p_hwfn, 1608 struct ecore_ptt *p_main_ptt) 1609 { 1610 /* Read shadow of current MFW mailbox */ 1611 ecore_mcp_read_mb(p_hwfn, p_main_ptt); 1612 OSAL_MEMCPY(p_hwfn->mcp_info->mfw_mb_shadow, 1613 p_hwfn->mcp_info->mfw_mb_cur, 1614 p_hwfn->mcp_info->mfw_mb_length); 1615 } 1616 1617 enum _ecore_status_t ecore_hw_init(struct ecore_dev *p_dev, 1618 struct ecore_hw_init_params *p_params) 1619 { 1620 enum _ecore_status_t rc, mfw_rc; 1621 u32 load_code, param; 1622 int i; 1623 1624 if ((p_params->int_mode == ECORE_INT_MODE_MSI) && 1625 (p_dev->num_hwfns > 1)) { 1626 DP_NOTICE(p_dev, false, 1627 "MSI mode is not supported for CMT devices\n"); 1628 return ECORE_INVAL; 1629 } 1630 1631 if (IS_PF(p_dev)) { 1632 rc = ecore_init_fw_data(p_dev, p_params->bin_fw_data); 1633 if (rc != ECORE_SUCCESS) 1634 return rc; 1635 } 1636 1637 for_each_hwfn(p_dev, i) { 1638 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i]; 1639 1640 if (IS_VF(p_dev)) { 1641 p_hwfn->b_int_enabled = 1; 1642 continue; 1643 } 1644 1645 /* Enable DMAE in PXP */ 1646 rc = ecore_change_pci_hwfn(p_hwfn, p_hwfn->p_main_ptt, true); 1647 if (rc != ECORE_SUCCESS) 1648 return rc; 1649 1650 rc = ecore_calc_hw_mode(p_hwfn); 1651 if (rc != ECORE_SUCCESS) 1652 return rc; 1653 1654 /* @@@TBD need to add here: 1655 * Check for fan failure 1656 * Prev_unload 1657 */ 1658 rc = ecore_mcp_load_req(p_hwfn, p_hwfn->p_main_ptt, &load_code); 1659 if (rc) { 1660 DP_NOTICE(p_hwfn, true, 1661 "Failed sending LOAD_REQ command\n"); 1662 return rc; 1663 } 1664 1665 /* CQ75580: 1666 * When coming back from hiberbate state, the registers from 1667 * which shadow is read initially are not initialized. It turns 1668 * out that these registers get initialized during the call to 1669 * ecore_mcp_load_req request. So we need to reread them here 1670 * to get the proper shadow register value. 1671 * Note: This is a workaround for the missinginig MFW 1672 * initialization. It may be removed once the implementation 1673 * is done. 1674 */ 1675 ecore_reset_mb_shadow(p_hwfn, p_hwfn->p_main_ptt); 1676 1677 DP_VERBOSE(p_hwfn, ECORE_MSG_SP, 1678 "Load request was sent. Resp:0x%x, Load code: 0x%x\n", 1679 rc, load_code); 1680 1681 /* Only relevant for recovery: 1682 * Clear the indication after the LOAD_REQ command is responded 1683 * by the MFW. 1684 */ 1685 p_dev->recov_in_prog = false; 1686 1687 p_hwfn->first_on_engine = (load_code == 1688 FW_MSG_CODE_DRV_LOAD_ENGINE); 1689 1690 if (!qm_lock_init) { 1691 OSAL_SPIN_LOCK_INIT(&qm_lock); 1692 qm_lock_init = true; 1693 } 1694 1695 switch (load_code) { 1696 case FW_MSG_CODE_DRV_LOAD_ENGINE: 1697 rc = ecore_hw_init_common(p_hwfn, p_hwfn->p_main_ptt, 1698 p_hwfn->hw_info.hw_mode); 1699 if (rc) 1700 break; 1701 /* Fall into */ 1702 case FW_MSG_CODE_DRV_LOAD_PORT: 1703 rc = ecore_hw_init_port(p_hwfn, p_hwfn->p_main_ptt, 1704 p_hwfn->hw_info.hw_mode); 1705 if (rc) 1706 break; 1707 /* Fall into */ 1708 case FW_MSG_CODE_DRV_LOAD_FUNCTION: 1709 rc = ecore_hw_init_pf(p_hwfn, p_hwfn->p_main_ptt, 1710 p_params->p_tunn, 1711 p_hwfn->hw_info.hw_mode, 1712 p_params->b_hw_start, 1713 p_params->int_mode, 1714 p_params->allow_npar_tx_switch); 1715 break; 1716 default: 1717 rc = ECORE_NOTIMPL; 1718 break; 1719 } 1720 1721 if (rc != ECORE_SUCCESS) 1722 DP_NOTICE(p_hwfn, true, 1723 "init phase failed for loadcode 0x%x (rc %d)\n", 1724 load_code, rc); 1725 1726 /* ACK mfw regardless of success or failure of initialization */ 1727 mfw_rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt, 1728 DRV_MSG_CODE_LOAD_DONE, 1729 0, &load_code, ¶m); 1730 if (rc != ECORE_SUCCESS) 1731 return rc; 1732 if (mfw_rc != ECORE_SUCCESS) { 1733 DP_NOTICE(p_hwfn, true, 1734 "Failed sending LOAD_DONE command\n"); 1735 return mfw_rc; 1736 } 1737 1738 /* send DCBX attention request command */ 1739 DP_VERBOSE(p_hwfn, ECORE_MSG_DCB, 1740 "sending phony dcbx set command to trigger DCBx attention handling\n"); 1741 mfw_rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt, 1742 DRV_MSG_CODE_SET_DCBX, 1743 1 << DRV_MB_PARAM_DCBX_NOTIFY_SHIFT, 1744 &load_code, ¶m); 1745 if (mfw_rc != ECORE_SUCCESS) { 1746 DP_NOTICE(p_hwfn, true, 1747 "Failed to send DCBX attention request\n"); 1748 return mfw_rc; 1749 } 1750 1751 p_hwfn->hw_init_done = true; 1752 } 1753 1754 return ECORE_SUCCESS; 1755 } 1756 1757 #define ECORE_HW_STOP_RETRY_LIMIT (10) 1758 static void ecore_hw_timers_stop(struct ecore_dev *p_dev, 1759 struct ecore_hwfn *p_hwfn, 1760 struct ecore_ptt *p_ptt) 1761 { 1762 int i; 1763 1764 /* close timers */ 1765 ecore_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_CONN, 0x0); 1766 ecore_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_TASK, 0x0); 1767 for (i = 0; i < ECORE_HW_STOP_RETRY_LIMIT && !p_dev->recov_in_prog; 1768 i++) { 1769 if ((!ecore_rd(p_hwfn, p_ptt, 1770 TM_REG_PF_SCAN_ACTIVE_CONN)) && 1771 (!ecore_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK))) 1772 break; 1773 1774 /* Dependent on number of connection/tasks, possibly 1775 * 1ms sleep is required between polls 1776 */ 1777 OSAL_MSLEEP(1); 1778 } 1779 1780 if (i < ECORE_HW_STOP_RETRY_LIMIT) 1781 return; 1782 1783 DP_NOTICE(p_hwfn, true, "Timers linear scans are not over" 1784 " [Connection %02x Tasks %02x]\n", 1785 (u8)ecore_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_CONN), 1786 (u8)ecore_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK)); 1787 } 1788 1789 void ecore_hw_timers_stop_all(struct ecore_dev *p_dev) 1790 { 1791 int j; 1792 1793 for_each_hwfn(p_dev, j) { 1794 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j]; 1795 struct ecore_ptt *p_ptt = p_hwfn->p_main_ptt; 1796 1797 ecore_hw_timers_stop(p_dev, p_hwfn, p_ptt); 1798 } 1799 } 1800 1801 enum _ecore_status_t ecore_hw_stop(struct ecore_dev *p_dev) 1802 { 1803 enum _ecore_status_t rc = ECORE_SUCCESS, t_rc; 1804 int j; 1805 1806 for_each_hwfn(p_dev, j) { 1807 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j]; 1808 struct ecore_ptt *p_ptt = p_hwfn->p_main_ptt; 1809 1810 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN, "Stopping hw/fw\n"); 1811 1812 if (IS_VF(p_dev)) { 1813 ecore_vf_pf_int_cleanup(p_hwfn); 1814 continue; 1815 } 1816 1817 /* mark the hw as uninitialized... */ 1818 p_hwfn->hw_init_done = false; 1819 1820 rc = ecore_sp_pf_stop(p_hwfn); 1821 if (rc) 1822 DP_NOTICE(p_hwfn, true, 1823 "Failed to close PF against FW. Continue to stop HW to prevent illegal host access by the device\n"); 1824 1825 /* perform debug action after PF stop was sent */ 1826 OSAL_AFTER_PF_STOP((void *)p_hwfn->p_dev, p_hwfn->my_id); 1827 1828 /* close NIG to BRB gate */ 1829 ecore_wr(p_hwfn, p_ptt, 1830 NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1); 1831 1832 /* close parser */ 1833 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0); 1834 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0); 1835 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0); 1836 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0); 1837 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0); 1838 1839 /* @@@TBD - clean transmission queues (5.b) */ 1840 /* @@@TBD - clean BTB (5.c) */ 1841 1842 ecore_hw_timers_stop(p_dev, p_hwfn, p_ptt); 1843 1844 /* @@@TBD - verify DMAE requests are done (8) */ 1845 1846 /* Disable Attention Generation */ 1847 ecore_int_igu_disable_int(p_hwfn, p_ptt); 1848 ecore_wr(p_hwfn, p_ptt, IGU_REG_LEADING_EDGE_LATCH, 0); 1849 ecore_wr(p_hwfn, p_ptt, IGU_REG_TRAILING_EDGE_LATCH, 0); 1850 ecore_int_igu_init_pure_rt(p_hwfn, p_ptt, false, true); 1851 /* Need to wait 1ms to guarantee SBs are cleared */ 1852 OSAL_MSLEEP(1); 1853 } 1854 1855 if (IS_PF(p_dev)) { 1856 /* Disable DMAE in PXP - in CMT, this should only be done for 1857 * first hw-function, and only after all transactions have 1858 * stopped for all active hw-functions. 1859 */ 1860 t_rc = ecore_change_pci_hwfn(&p_dev->hwfns[0], 1861 p_dev->hwfns[0].p_main_ptt, false); 1862 if (t_rc != ECORE_SUCCESS) 1863 rc = t_rc; 1864 } 1865 1866 return rc; 1867 } 1868 1869 void ecore_hw_stop_fastpath(struct ecore_dev *p_dev) 1870 { 1871 int j; 1872 1873 for_each_hwfn(p_dev, j) { 1874 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j]; 1875 struct ecore_ptt *p_ptt = p_hwfn->p_main_ptt; 1876 1877 if (IS_VF(p_dev)) { 1878 ecore_vf_pf_int_cleanup(p_hwfn); 1879 continue; 1880 } 1881 1882 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN, 1883 "Shutting down the fastpath\n"); 1884 1885 ecore_wr(p_hwfn, p_ptt, 1886 NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1); 1887 1888 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0); 1889 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0); 1890 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0); 1891 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0); 1892 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0); 1893 1894 /* @@@TBD - clean transmission queues (5.b) */ 1895 /* @@@TBD - clean BTB (5.c) */ 1896 1897 /* @@@TBD - verify DMAE requests are done (8) */ 1898 1899 ecore_int_igu_init_pure_rt(p_hwfn, p_ptt, false, false); 1900 /* Need to wait 1ms to guarantee SBs are cleared */ 1901 OSAL_MSLEEP(1); 1902 } 1903 } 1904 1905 void ecore_hw_start_fastpath(struct ecore_hwfn *p_hwfn) 1906 { 1907 struct ecore_ptt *p_ptt = p_hwfn->p_main_ptt; 1908 1909 if (IS_VF(p_hwfn->p_dev)) 1910 return; 1911 1912 /* If roce info is allocated it means roce is initialized and should 1913 * be enabled in searcher. 1914 */ 1915 if (p_hwfn->p_rdma_info) { 1916 if (p_hwfn->b_rdma_enabled_in_prs) 1917 ecore_wr(p_hwfn, p_ptt, 1918 p_hwfn->rdma_prs_search_reg, 0x1); 1919 ecore_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_CONN, 0x1); 1920 } 1921 1922 /* Re-open incoming traffic */ 1923 ecore_wr(p_hwfn, p_hwfn->p_main_ptt, 1924 NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x0); 1925 } 1926 1927 static enum _ecore_status_t ecore_reg_assert(struct ecore_hwfn *p_hwfn, 1928 struct ecore_ptt *p_ptt, u32 reg, 1929 bool expected) 1930 { 1931 u32 assert_val = ecore_rd(p_hwfn, p_ptt, reg); 1932 1933 if (assert_val != expected) { 1934 DP_NOTICE(p_hwfn, true, "Value at address 0x%08x != 0x%08x\n", 1935 reg, expected); 1936 return ECORE_UNKNOWN_ERROR; 1937 } 1938 1939 return 0; 1940 } 1941 1942 enum _ecore_status_t ecore_hw_reset(struct ecore_dev *p_dev) 1943 { 1944 enum _ecore_status_t rc = ECORE_SUCCESS; 1945 u32 unload_resp, unload_param; 1946 int i; 1947 1948 for_each_hwfn(p_dev, i) { 1949 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i]; 1950 1951 if (IS_VF(p_dev)) { 1952 rc = ecore_vf_pf_reset(p_hwfn); 1953 if (rc) 1954 return rc; 1955 continue; 1956 } 1957 1958 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN, "Resetting hw/fw\n"); 1959 1960 /* Check for incorrect states */ 1961 if (!p_dev->recov_in_prog) { 1962 ecore_reg_assert(p_hwfn, p_hwfn->p_main_ptt, 1963 QM_REG_USG_CNT_PF_TX, 0); 1964 ecore_reg_assert(p_hwfn, p_hwfn->p_main_ptt, 1965 QM_REG_USG_CNT_PF_OTHER, 0); 1966 /* @@@TBD - assert on incorrect xCFC values (10.b) */ 1967 } 1968 1969 /* Disable PF in HW blocks */ 1970 ecore_wr(p_hwfn, p_hwfn->p_main_ptt, DORQ_REG_PF_DB_ENABLE, 0); 1971 ecore_wr(p_hwfn, p_hwfn->p_main_ptt, QM_REG_PF_EN, 0); 1972 1973 if (p_dev->recov_in_prog) { 1974 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN, 1975 "Recovery is in progress -> skip sending unload_req/done\n"); 1976 break; 1977 } 1978 1979 /* Send unload command to MCP */ 1980 rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt, 1981 DRV_MSG_CODE_UNLOAD_REQ, 1982 DRV_MB_PARAM_UNLOAD_WOL_MCP, 1983 &unload_resp, &unload_param); 1984 if (rc != ECORE_SUCCESS) { 1985 DP_NOTICE(p_hwfn, true, 1986 "ecore_hw_reset: UNLOAD_REQ failed\n"); 1987 /* @@TBD - what to do? for now, assume ENG. */ 1988 unload_resp = FW_MSG_CODE_DRV_UNLOAD_ENGINE; 1989 } 1990 1991 rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt, 1992 DRV_MSG_CODE_UNLOAD_DONE, 1993 0, &unload_resp, &unload_param); 1994 if (rc != ECORE_SUCCESS) { 1995 DP_NOTICE(p_hwfn, 1996 true, "ecore_hw_reset: UNLOAD_DONE failed\n"); 1997 /* @@@TBD - Should it really ASSERT here ? */ 1998 return rc; 1999 } 2000 } 2001 2002 return rc; 2003 } 2004 2005 /* Free hwfn memory and resources acquired in hw_hwfn_prepare */ 2006 static void ecore_hw_hwfn_free(struct ecore_hwfn *p_hwfn) 2007 { 2008 ecore_ptt_pool_free(p_hwfn); 2009 OSAL_FREE(p_hwfn->p_dev, p_hwfn->hw_info.p_igu_info); 2010 } 2011 2012 /* Setup bar access */ 2013 static void ecore_hw_hwfn_prepare(struct ecore_hwfn *p_hwfn) 2014 { 2015 /* clear indirect access */ 2016 if (ECORE_IS_AH(p_hwfn->p_dev)) { 2017 ecore_wr(p_hwfn, p_hwfn->p_main_ptt, 2018 PGLUE_B_REG_PGL_ADDR_E8_F0, 0); 2019 ecore_wr(p_hwfn, p_hwfn->p_main_ptt, 2020 PGLUE_B_REG_PGL_ADDR_EC_F0, 0); 2021 ecore_wr(p_hwfn, p_hwfn->p_main_ptt, 2022 PGLUE_B_REG_PGL_ADDR_F0_F0, 0); 2023 ecore_wr(p_hwfn, p_hwfn->p_main_ptt, 2024 PGLUE_B_REG_PGL_ADDR_F4_F0, 0); 2025 } else { 2026 ecore_wr(p_hwfn, p_hwfn->p_main_ptt, 2027 PGLUE_B_REG_PGL_ADDR_88_F0, 0); 2028 ecore_wr(p_hwfn, p_hwfn->p_main_ptt, 2029 PGLUE_B_REG_PGL_ADDR_8C_F0, 0); 2030 ecore_wr(p_hwfn, p_hwfn->p_main_ptt, 2031 PGLUE_B_REG_PGL_ADDR_90_F0, 0); 2032 ecore_wr(p_hwfn, p_hwfn->p_main_ptt, 2033 PGLUE_B_REG_PGL_ADDR_94_F0, 0); 2034 } 2035 2036 /* Clean Previous errors if such exist */ 2037 ecore_wr(p_hwfn, p_hwfn->p_main_ptt, 2038 PGLUE_B_REG_WAS_ERROR_PF_31_0_CLR, 1 << p_hwfn->abs_pf_id); 2039 2040 /* enable internal target-read */ 2041 ecore_wr(p_hwfn, p_hwfn->p_main_ptt, 2042 PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1); 2043 } 2044 2045 static void get_function_id(struct ecore_hwfn *p_hwfn) 2046 { 2047 /* ME Register */ 2048 p_hwfn->hw_info.opaque_fid = (u16)REG_RD(p_hwfn, 2049 PXP_PF_ME_OPAQUE_ADDR); 2050 2051 p_hwfn->hw_info.concrete_fid = REG_RD(p_hwfn, PXP_PF_ME_CONCRETE_ADDR); 2052 2053 /* Bits 16-19 from the ME registers are the pf_num */ 2054 p_hwfn->abs_pf_id = (p_hwfn->hw_info.concrete_fid >> 16) & 0xf; 2055 p_hwfn->rel_pf_id = GET_FIELD(p_hwfn->hw_info.concrete_fid, 2056 PXP_CONCRETE_FID_PFID); 2057 p_hwfn->port_id = GET_FIELD(p_hwfn->hw_info.concrete_fid, 2058 PXP_CONCRETE_FID_PORT); 2059 2060 DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE, 2061 "Read ME register: Concrete 0x%08x Opaque 0x%04x\n", 2062 p_hwfn->hw_info.concrete_fid, p_hwfn->hw_info.opaque_fid); 2063 } 2064 2065 static void ecore_hw_set_feat(struct ecore_hwfn *p_hwfn) 2066 { 2067 u32 *feat_num = p_hwfn->hw_info.feat_num; 2068 int num_features = 1; 2069 2070 /* L2 Queues require each: 1 status block. 1 L2 queue */ 2071 feat_num[ECORE_PF_L2_QUE] = 2072 OSAL_MIN_T(u32, 2073 RESC_NUM(p_hwfn, ECORE_SB) / num_features, 2074 RESC_NUM(p_hwfn, ECORE_L2_QUEUE)); 2075 2076 DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE, 2077 "#PF_L2_QUEUES=%d #ROCE_CNQ=%d #SBS=%d num_features=%d\n", 2078 feat_num[ECORE_PF_L2_QUE], 2079 feat_num[ECORE_RDMA_CNQ], 2080 RESC_NUM(p_hwfn, ECORE_SB), num_features); 2081 } 2082 2083 static enum resource_id_enum 2084 ecore_hw_get_mfw_res_id(enum ecore_resources res_id) 2085 { 2086 enum resource_id_enum mfw_res_id = RESOURCE_NUM_INVALID; 2087 2088 switch (res_id) { 2089 case ECORE_SB: 2090 mfw_res_id = RESOURCE_NUM_SB_E; 2091 break; 2092 case ECORE_L2_QUEUE: 2093 mfw_res_id = RESOURCE_NUM_L2_QUEUE_E; 2094 break; 2095 case ECORE_VPORT: 2096 mfw_res_id = RESOURCE_NUM_VPORT_E; 2097 break; 2098 case ECORE_RSS_ENG: 2099 mfw_res_id = RESOURCE_NUM_RSS_ENGINES_E; 2100 break; 2101 case ECORE_PQ: 2102 mfw_res_id = RESOURCE_NUM_PQ_E; 2103 break; 2104 case ECORE_RL: 2105 mfw_res_id = RESOURCE_NUM_RL_E; 2106 break; 2107 case ECORE_MAC: 2108 case ECORE_VLAN: 2109 /* Each VFC resource can accommodate both a MAC and a VLAN */ 2110 mfw_res_id = RESOURCE_VFC_FILTER_E; 2111 break; 2112 case ECORE_ILT: 2113 mfw_res_id = RESOURCE_ILT_E; 2114 break; 2115 case ECORE_LL2_QUEUE: 2116 mfw_res_id = RESOURCE_LL2_QUEUE_E; 2117 break; 2118 case ECORE_RDMA_CNQ_RAM: 2119 case ECORE_CMDQS_CQS: 2120 /* CNQ/CMDQS are the same resource */ 2121 mfw_res_id = RESOURCE_CQS_E; 2122 break; 2123 case ECORE_RDMA_STATS_QUEUE: 2124 mfw_res_id = RESOURCE_RDMA_STATS_QUEUE_E; 2125 break; 2126 default: 2127 break; 2128 } 2129 2130 return mfw_res_id; 2131 } 2132 2133 static u32 ecore_hw_get_dflt_resc_num(struct ecore_hwfn *p_hwfn, 2134 enum ecore_resources res_id) 2135 { 2136 u8 num_funcs = p_hwfn->num_funcs_on_engine; 2137 bool b_ah = ECORE_IS_AH(p_hwfn->p_dev); 2138 struct ecore_sb_cnt_info sb_cnt_info; 2139 u32 dflt_resc_num = 0; 2140 2141 switch (res_id) { 2142 case ECORE_SB: 2143 OSAL_MEM_ZERO(&sb_cnt_info, sizeof(sb_cnt_info)); 2144 ecore_int_get_num_sbs(p_hwfn, &sb_cnt_info); 2145 dflt_resc_num = sb_cnt_info.sb_cnt; 2146 break; 2147 case ECORE_L2_QUEUE: 2148 dflt_resc_num = (b_ah ? MAX_NUM_L2_QUEUES_K2 : 2149 MAX_NUM_L2_QUEUES_BB) / num_funcs; 2150 break; 2151 case ECORE_VPORT: 2152 dflt_resc_num = (b_ah ? MAX_NUM_VPORTS_K2 : 2153 MAX_NUM_VPORTS_BB) / num_funcs; 2154 break; 2155 case ECORE_RSS_ENG: 2156 dflt_resc_num = (b_ah ? ETH_RSS_ENGINE_NUM_K2 : 2157 ETH_RSS_ENGINE_NUM_BB) / num_funcs; 2158 break; 2159 case ECORE_PQ: 2160 dflt_resc_num = (b_ah ? MAX_QM_TX_QUEUES_K2 : 2161 MAX_QM_TX_QUEUES_BB) / num_funcs; 2162 break; 2163 case ECORE_RL: 2164 dflt_resc_num = MAX_QM_GLOBAL_RLS / num_funcs; 2165 break; 2166 case ECORE_MAC: 2167 case ECORE_VLAN: 2168 /* Each VFC resource can accommodate both a MAC and a VLAN */ 2169 dflt_resc_num = ETH_NUM_MAC_FILTERS / num_funcs; 2170 break; 2171 case ECORE_ILT: 2172 dflt_resc_num = (b_ah ? PXP_NUM_ILT_RECORDS_K2 : 2173 PXP_NUM_ILT_RECORDS_BB) / num_funcs; 2174 break; 2175 case ECORE_LL2_QUEUE: 2176 dflt_resc_num = MAX_NUM_LL2_RX_QUEUES / num_funcs; 2177 break; 2178 case ECORE_RDMA_CNQ_RAM: 2179 case ECORE_CMDQS_CQS: 2180 /* CNQ/CMDQS are the same resource */ 2181 /* @DPDK */ 2182 dflt_resc_num = (NUM_OF_GLOBAL_QUEUES / 2) / num_funcs; 2183 break; 2184 case ECORE_RDMA_STATS_QUEUE: 2185 /* @DPDK */ 2186 dflt_resc_num = (b_ah ? MAX_NUM_VPORTS_K2 : 2187 MAX_NUM_VPORTS_BB) / num_funcs; 2188 break; 2189 default: 2190 break; 2191 } 2192 2193 return dflt_resc_num; 2194 } 2195 2196 static const char *ecore_hw_get_resc_name(enum ecore_resources res_id) 2197 { 2198 switch (res_id) { 2199 case ECORE_SB: 2200 return "SB"; 2201 case ECORE_L2_QUEUE: 2202 return "L2_QUEUE"; 2203 case ECORE_VPORT: 2204 return "VPORT"; 2205 case ECORE_RSS_ENG: 2206 return "RSS_ENG"; 2207 case ECORE_PQ: 2208 return "PQ"; 2209 case ECORE_RL: 2210 return "RL"; 2211 case ECORE_MAC: 2212 return "MAC"; 2213 case ECORE_VLAN: 2214 return "VLAN"; 2215 case ECORE_RDMA_CNQ_RAM: 2216 return "RDMA_CNQ_RAM"; 2217 case ECORE_ILT: 2218 return "ILT"; 2219 case ECORE_LL2_QUEUE: 2220 return "LL2_QUEUE"; 2221 case ECORE_CMDQS_CQS: 2222 return "CMDQS_CQS"; 2223 case ECORE_RDMA_STATS_QUEUE: 2224 return "RDMA_STATS_QUEUE"; 2225 default: 2226 return "UNKNOWN_RESOURCE"; 2227 } 2228 } 2229 2230 static enum _ecore_status_t ecore_hw_set_resc_info(struct ecore_hwfn *p_hwfn, 2231 enum ecore_resources res_id, 2232 bool drv_resc_alloc) 2233 { 2234 u32 dflt_resc_num = 0, dflt_resc_start = 0, mcp_resp, mcp_param; 2235 u32 *p_resc_num, *p_resc_start; 2236 struct resource_info resc_info; 2237 enum _ecore_status_t rc; 2238 2239 p_resc_num = &RESC_NUM(p_hwfn, res_id); 2240 p_resc_start = &RESC_START(p_hwfn, res_id); 2241 2242 dflt_resc_num = ecore_hw_get_dflt_resc_num(p_hwfn, res_id); 2243 if (!dflt_resc_num) { 2244 DP_ERR(p_hwfn, 2245 "Failed to get default amount for resource %d [%s]\n", 2246 res_id, ecore_hw_get_resc_name(res_id)); 2247 return ECORE_INVAL; 2248 } 2249 dflt_resc_start = dflt_resc_num * p_hwfn->enabled_func_idx; 2250 2251 #ifndef ASIC_ONLY 2252 if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) { 2253 *p_resc_num = dflt_resc_num; 2254 *p_resc_start = dflt_resc_start; 2255 goto out; 2256 } 2257 #endif 2258 2259 OSAL_MEM_ZERO(&resc_info, sizeof(resc_info)); 2260 resc_info.res_id = ecore_hw_get_mfw_res_id(res_id); 2261 if (resc_info.res_id == RESOURCE_NUM_INVALID) { 2262 DP_ERR(p_hwfn, 2263 "Failed to match resource %d with MFW resources\n", 2264 res_id); 2265 return ECORE_INVAL; 2266 } 2267 2268 rc = ecore_mcp_get_resc_info(p_hwfn, p_hwfn->p_main_ptt, &resc_info, 2269 &mcp_resp, &mcp_param); 2270 if (rc != ECORE_SUCCESS) { 2271 DP_NOTICE(p_hwfn, true, 2272 "MFW response failure for an allocation request for" 2273 " resource %d [%s]\n", 2274 res_id, ecore_hw_get_resc_name(res_id)); 2275 return rc; 2276 } 2277 2278 /* Default driver values are applied in the following cases: 2279 * - The resource allocation MB command is not supported by the MFW 2280 * - There is an internal error in the MFW while processing the request 2281 * - The resource ID is unknown to the MFW 2282 */ 2283 if (mcp_resp != FW_MSG_CODE_RESOURCE_ALLOC_OK && 2284 mcp_resp != FW_MSG_CODE_RESOURCE_ALLOC_DEPRECATED) { 2285 /* @DPDK */ 2286 DP_INFO(p_hwfn, 2287 "Resource %d [%s]: No allocation info was received" 2288 " [mcp_resp 0x%x]. Applying default values" 2289 " [num %d, start %d].\n", 2290 res_id, ecore_hw_get_resc_name(res_id), mcp_resp, 2291 dflt_resc_num, dflt_resc_start); 2292 2293 *p_resc_num = dflt_resc_num; 2294 *p_resc_start = dflt_resc_start; 2295 goto out; 2296 } 2297 2298 /* TBD - remove this when revising the handling of the SB resource */ 2299 if (res_id == ECORE_SB) { 2300 /* Excluding the slowpath SB */ 2301 resc_info.size -= 1; 2302 resc_info.offset -= p_hwfn->enabled_func_idx; 2303 } 2304 2305 *p_resc_num = resc_info.size; 2306 *p_resc_start = resc_info.offset; 2307 2308 if (*p_resc_num != dflt_resc_num || *p_resc_start != dflt_resc_start) { 2309 DP_NOTICE(p_hwfn, false, 2310 "Resource %d [%s]: MFW allocation [num %d, start %d]" 2311 " differs from default values [num %d, start %d]%s\n", 2312 res_id, ecore_hw_get_resc_name(res_id), *p_resc_num, 2313 *p_resc_start, dflt_resc_num, dflt_resc_start, 2314 drv_resc_alloc ? " - Applying default values" : ""); 2315 if (drv_resc_alloc) { 2316 *p_resc_num = dflt_resc_num; 2317 *p_resc_start = dflt_resc_start; 2318 } 2319 } 2320 out: 2321 return ECORE_SUCCESS; 2322 } 2323 2324 static enum _ecore_status_t ecore_hw_get_resc(struct ecore_hwfn *p_hwfn, 2325 bool drv_resc_alloc) 2326 { 2327 bool b_ah = ECORE_IS_AH(p_hwfn->p_dev); 2328 enum _ecore_status_t rc; 2329 u8 res_id; 2330 #ifndef ASIC_ONLY 2331 u32 *resc_start = p_hwfn->hw_info.resc_start; 2332 u32 *resc_num = p_hwfn->hw_info.resc_num; 2333 /* For AH, an equal share of the ILT lines between the maximal number of 2334 * PFs is not enough for RoCE. This would be solved by the future 2335 * resource allocation scheme, but isn't currently present for 2336 * FPGA/emulation. For now we keep a number that is sufficient for RoCE 2337 * to work - the BB number of ILT lines divided by its max PFs number. 2338 */ 2339 u32 roce_min_ilt_lines = PXP_NUM_ILT_RECORDS_BB / MAX_NUM_PFS_BB; 2340 #endif 2341 2342 for (res_id = 0; res_id < ECORE_MAX_RESC; res_id++) { 2343 /* @@@TMP for AH: 2344 * Force the driver's default resource allocation in case there 2345 * is a diff with the MFW allocation value. 2346 */ 2347 rc = ecore_hw_set_resc_info(p_hwfn, res_id, 2348 b_ah || drv_resc_alloc); 2349 if (rc != ECORE_SUCCESS) 2350 return rc; 2351 } 2352 2353 #ifndef ASIC_ONLY 2354 if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) { 2355 /* Reduced build contains less PQs */ 2356 if (!(p_hwfn->p_dev->b_is_emul_full)) { 2357 resc_num[ECORE_PQ] = 32; 2358 resc_start[ECORE_PQ] = resc_num[ECORE_PQ] * 2359 p_hwfn->enabled_func_idx; 2360 } 2361 2362 /* For AH emulation, since we have a possible maximal number of 2363 * 16 enabled PFs, in case there are not enough ILT lines - 2364 * allocate only first PF as RoCE and have all the other ETH 2365 * only with less ILT lines. 2366 */ 2367 if (!p_hwfn->rel_pf_id && p_hwfn->p_dev->b_is_emul_full) 2368 resc_num[ECORE_ILT] = OSAL_MAX_T(u32, 2369 resc_num[ECORE_ILT], 2370 roce_min_ilt_lines); 2371 } 2372 2373 /* Correct the common ILT calculation if PF0 has more */ 2374 if (CHIP_REV_IS_SLOW(p_hwfn->p_dev) && 2375 p_hwfn->p_dev->b_is_emul_full && 2376 p_hwfn->rel_pf_id && resc_num[ECORE_ILT] < roce_min_ilt_lines) 2377 resc_start[ECORE_ILT] += roce_min_ilt_lines - 2378 resc_num[ECORE_ILT]; 2379 #endif 2380 2381 /* Sanity for ILT */ 2382 if ((b_ah && (RESC_END(p_hwfn, ECORE_ILT) > PXP_NUM_ILT_RECORDS_K2)) || 2383 (!b_ah && (RESC_END(p_hwfn, ECORE_ILT) > PXP_NUM_ILT_RECORDS_BB))) { 2384 DP_NOTICE(p_hwfn, true, 2385 "Can't assign ILT pages [%08x,...,%08x]\n", 2386 RESC_START(p_hwfn, ECORE_ILT), RESC_END(p_hwfn, 2387 ECORE_ILT) - 2388 1); 2389 return ECORE_INVAL; 2390 } 2391 2392 ecore_hw_set_feat(p_hwfn); 2393 2394 DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE, 2395 "The numbers for each resource are:\n"); 2396 for (res_id = 0; res_id < ECORE_MAX_RESC; res_id++) 2397 DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE, "%s = %d start = %d\n", 2398 ecore_hw_get_resc_name(res_id), 2399 RESC_NUM(p_hwfn, res_id), 2400 RESC_START(p_hwfn, res_id)); 2401 2402 return ECORE_SUCCESS; 2403 } 2404 2405 static enum _ecore_status_t ecore_hw_get_nvm_info(struct ecore_hwfn *p_hwfn, 2406 struct ecore_ptt *p_ptt) 2407 { 2408 u32 nvm_cfg1_offset, mf_mode, addr, generic_cont0, core_cfg, dcbx_mode; 2409 u32 port_cfg_addr, link_temp, nvm_cfg_addr, device_capabilities; 2410 struct ecore_mcp_link_params *link; 2411 2412 /* Read global nvm_cfg address */ 2413 nvm_cfg_addr = ecore_rd(p_hwfn, p_ptt, MISC_REG_GEN_PURP_CR0); 2414 2415 /* Verify MCP has initialized it */ 2416 if (!nvm_cfg_addr) { 2417 DP_NOTICE(p_hwfn, false, "Shared memory not initialized\n"); 2418 return ECORE_INVAL; 2419 } 2420 2421 /* Read nvm_cfg1 (Notice this is just offset, and not offsize (TBD) */ 2422 2423 nvm_cfg1_offset = ecore_rd(p_hwfn, p_ptt, nvm_cfg_addr + 4); 2424 2425 addr = MCP_REG_SCRATCH + nvm_cfg1_offset + 2426 OFFSETOF(struct nvm_cfg1, glob) + OFFSETOF(struct nvm_cfg1_glob, 2427 core_cfg); 2428 2429 core_cfg = ecore_rd(p_hwfn, p_ptt, addr); 2430 2431 switch ((core_cfg & NVM_CFG1_GLOB_NETWORK_PORT_MODE_MASK) >> 2432 NVM_CFG1_GLOB_NETWORK_PORT_MODE_OFFSET) { 2433 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_2X40G: 2434 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X40G; 2435 break; 2436 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X50G: 2437 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X50G; 2438 break; 2439 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_1X100G: 2440 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_1X100G; 2441 break; 2442 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X10G_F: 2443 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X10G_F; 2444 break; 2445 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X10G_E: 2446 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X10G_E; 2447 break; 2448 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X20G: 2449 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X20G; 2450 break; 2451 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X40G: 2452 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_1X40G; 2453 break; 2454 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X25G: 2455 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X25G; 2456 break; 2457 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X10G: 2458 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X10G; 2459 break; 2460 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X25G: 2461 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_1X25G; 2462 break; 2463 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X25G: 2464 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X25G; 2465 break; 2466 default: 2467 DP_NOTICE(p_hwfn, true, "Unknown port mode in 0x%08x\n", 2468 core_cfg); 2469 break; 2470 } 2471 2472 /* Read DCBX configuration */ 2473 port_cfg_addr = MCP_REG_SCRATCH + nvm_cfg1_offset + 2474 OFFSETOF(struct nvm_cfg1, port[MFW_PORT(p_hwfn)]); 2475 dcbx_mode = ecore_rd(p_hwfn, p_ptt, 2476 port_cfg_addr + 2477 OFFSETOF(struct nvm_cfg1_port, generic_cont0)); 2478 dcbx_mode = (dcbx_mode & NVM_CFG1_PORT_DCBX_MODE_MASK) 2479 >> NVM_CFG1_PORT_DCBX_MODE_OFFSET; 2480 switch (dcbx_mode) { 2481 case NVM_CFG1_PORT_DCBX_MODE_DYNAMIC: 2482 p_hwfn->hw_info.dcbx_mode = ECORE_DCBX_VERSION_DYNAMIC; 2483 break; 2484 case NVM_CFG1_PORT_DCBX_MODE_CEE: 2485 p_hwfn->hw_info.dcbx_mode = ECORE_DCBX_VERSION_CEE; 2486 break; 2487 case NVM_CFG1_PORT_DCBX_MODE_IEEE: 2488 p_hwfn->hw_info.dcbx_mode = ECORE_DCBX_VERSION_IEEE; 2489 break; 2490 default: 2491 p_hwfn->hw_info.dcbx_mode = ECORE_DCBX_VERSION_DISABLED; 2492 } 2493 2494 /* Read default link configuration */ 2495 link = &p_hwfn->mcp_info->link_input; 2496 port_cfg_addr = MCP_REG_SCRATCH + nvm_cfg1_offset + 2497 OFFSETOF(struct nvm_cfg1, port[MFW_PORT(p_hwfn)]); 2498 link_temp = ecore_rd(p_hwfn, p_ptt, 2499 port_cfg_addr + 2500 OFFSETOF(struct nvm_cfg1_port, speed_cap_mask)); 2501 link_temp &= NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_MASK; 2502 link->speed.advertised_speeds = link_temp; 2503 2504 link_temp = link->speed.advertised_speeds; 2505 p_hwfn->mcp_info->link_capabilities.speed_capabilities = link_temp; 2506 2507 link_temp = ecore_rd(p_hwfn, p_ptt, 2508 port_cfg_addr + 2509 OFFSETOF(struct nvm_cfg1_port, link_settings)); 2510 switch ((link_temp & NVM_CFG1_PORT_DRV_LINK_SPEED_MASK) >> 2511 NVM_CFG1_PORT_DRV_LINK_SPEED_OFFSET) { 2512 case NVM_CFG1_PORT_DRV_LINK_SPEED_AUTONEG: 2513 link->speed.autoneg = true; 2514 break; 2515 case NVM_CFG1_PORT_DRV_LINK_SPEED_1G: 2516 link->speed.forced_speed = 1000; 2517 break; 2518 case NVM_CFG1_PORT_DRV_LINK_SPEED_10G: 2519 link->speed.forced_speed = 10000; 2520 break; 2521 case NVM_CFG1_PORT_DRV_LINK_SPEED_25G: 2522 link->speed.forced_speed = 25000; 2523 break; 2524 case NVM_CFG1_PORT_DRV_LINK_SPEED_40G: 2525 link->speed.forced_speed = 40000; 2526 break; 2527 case NVM_CFG1_PORT_DRV_LINK_SPEED_50G: 2528 link->speed.forced_speed = 50000; 2529 break; 2530 case NVM_CFG1_PORT_DRV_LINK_SPEED_BB_100G: 2531 link->speed.forced_speed = 100000; 2532 break; 2533 default: 2534 DP_NOTICE(p_hwfn, true, "Unknown Speed in 0x%08x\n", link_temp); 2535 } 2536 2537 p_hwfn->mcp_info->link_capabilities.default_speed = 2538 link->speed.forced_speed; 2539 p_hwfn->mcp_info->link_capabilities.default_speed_autoneg = 2540 link->speed.autoneg; 2541 2542 link_temp &= NVM_CFG1_PORT_DRV_FLOW_CONTROL_MASK; 2543 link_temp >>= NVM_CFG1_PORT_DRV_FLOW_CONTROL_OFFSET; 2544 link->pause.autoneg = !!(link_temp & 2545 NVM_CFG1_PORT_DRV_FLOW_CONTROL_AUTONEG); 2546 link->pause.forced_rx = !!(link_temp & 2547 NVM_CFG1_PORT_DRV_FLOW_CONTROL_RX); 2548 link->pause.forced_tx = !!(link_temp & 2549 NVM_CFG1_PORT_DRV_FLOW_CONTROL_TX); 2550 link->loopback_mode = 0; 2551 2552 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK, 2553 "Read default link: Speed 0x%08x, Adv. Speed 0x%08x, AN: 0x%02x, PAUSE AN: 0x%02x\n", 2554 link->speed.forced_speed, link->speed.advertised_speeds, 2555 link->speed.autoneg, link->pause.autoneg); 2556 2557 /* Read Multi-function information from shmem */ 2558 addr = MCP_REG_SCRATCH + nvm_cfg1_offset + 2559 OFFSETOF(struct nvm_cfg1, glob) + 2560 OFFSETOF(struct nvm_cfg1_glob, generic_cont0); 2561 2562 generic_cont0 = ecore_rd(p_hwfn, p_ptt, addr); 2563 2564 mf_mode = (generic_cont0 & NVM_CFG1_GLOB_MF_MODE_MASK) >> 2565 NVM_CFG1_GLOB_MF_MODE_OFFSET; 2566 2567 switch (mf_mode) { 2568 case NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED: 2569 p_hwfn->p_dev->mf_mode = ECORE_MF_OVLAN; 2570 break; 2571 case NVM_CFG1_GLOB_MF_MODE_NPAR1_0: 2572 p_hwfn->p_dev->mf_mode = ECORE_MF_NPAR; 2573 break; 2574 case NVM_CFG1_GLOB_MF_MODE_DEFAULT: 2575 p_hwfn->p_dev->mf_mode = ECORE_MF_DEFAULT; 2576 break; 2577 } 2578 DP_INFO(p_hwfn, "Multi function mode is %08x\n", 2579 p_hwfn->p_dev->mf_mode); 2580 2581 /* Read Multi-function information from shmem */ 2582 addr = MCP_REG_SCRATCH + nvm_cfg1_offset + 2583 OFFSETOF(struct nvm_cfg1, glob) + 2584 OFFSETOF(struct nvm_cfg1_glob, device_capabilities); 2585 2586 device_capabilities = ecore_rd(p_hwfn, p_ptt, addr); 2587 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ETHERNET) 2588 OSAL_SET_BIT(ECORE_DEV_CAP_ETH, 2589 &p_hwfn->hw_info.device_capabilities); 2590 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_FCOE) 2591 OSAL_SET_BIT(ECORE_DEV_CAP_FCOE, 2592 &p_hwfn->hw_info.device_capabilities); 2593 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ISCSI) 2594 OSAL_SET_BIT(ECORE_DEV_CAP_ISCSI, 2595 &p_hwfn->hw_info.device_capabilities); 2596 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ROCE) 2597 OSAL_SET_BIT(ECORE_DEV_CAP_ROCE, 2598 &p_hwfn->hw_info.device_capabilities); 2599 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_IWARP) 2600 OSAL_SET_BIT(ECORE_DEV_CAP_IWARP, 2601 &p_hwfn->hw_info.device_capabilities); 2602 2603 return ecore_mcp_fill_shmem_func_info(p_hwfn, p_ptt); 2604 } 2605 2606 static void ecore_get_num_funcs(struct ecore_hwfn *p_hwfn, 2607 struct ecore_ptt *p_ptt) 2608 { 2609 u8 num_funcs, enabled_func_idx = p_hwfn->rel_pf_id; 2610 u32 reg_function_hide, tmp, eng_mask, low_pfs_mask; 2611 struct ecore_dev *p_dev = p_hwfn->p_dev; 2612 2613 num_funcs = ECORE_IS_AH(p_dev) ? MAX_NUM_PFS_K2 : MAX_NUM_PFS_BB; 2614 2615 /* Bit 0 of MISCS_REG_FUNCTION_HIDE indicates whether the bypass values 2616 * in the other bits are selected. 2617 * Bits 1-15 are for functions 1-15, respectively, and their value is 2618 * '0' only for enabled functions (function 0 always exists and 2619 * enabled). 2620 * In case of CMT in BB, only the "even" functions are enabled, and thus 2621 * the number of functions for both hwfns is learnt from the same bits. 2622 */ 2623 reg_function_hide = ecore_rd(p_hwfn, p_ptt, MISCS_REG_FUNCTION_HIDE); 2624 2625 if (reg_function_hide & 0x1) { 2626 if (ECORE_IS_BB(p_dev)) { 2627 if (ECORE_PATH_ID(p_hwfn) && p_dev->num_hwfns == 1) { 2628 num_funcs = 0; 2629 eng_mask = 0xaaaa; 2630 } else { 2631 num_funcs = 1; 2632 eng_mask = 0x5554; 2633 } 2634 } else { 2635 num_funcs = 1; 2636 eng_mask = 0xfffe; 2637 } 2638 2639 /* Get the number of the enabled functions on the engine */ 2640 tmp = (reg_function_hide ^ 0xffffffff) & eng_mask; 2641 while (tmp) { 2642 if (tmp & 0x1) 2643 num_funcs++; 2644 tmp >>= 0x1; 2645 } 2646 2647 /* Get the PF index within the enabled functions */ 2648 low_pfs_mask = (0x1 << p_hwfn->abs_pf_id) - 1; 2649 tmp = reg_function_hide & eng_mask & low_pfs_mask; 2650 while (tmp) { 2651 if (tmp & 0x1) 2652 enabled_func_idx--; 2653 tmp >>= 0x1; 2654 } 2655 } 2656 2657 p_hwfn->num_funcs_on_engine = num_funcs; 2658 p_hwfn->enabled_func_idx = enabled_func_idx; 2659 2660 #ifndef ASIC_ONLY 2661 if (CHIP_REV_IS_FPGA(p_dev)) { 2662 DP_NOTICE(p_hwfn, false, 2663 "FPGA: Limit number of PFs to 4 [would affect resource allocation, needed for IOV]\n"); 2664 p_hwfn->num_funcs_on_engine = 4; 2665 } 2666 #endif 2667 2668 DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE, 2669 "PF [rel_id %d, abs_id %d] occupies index %d within the %d enabled functions on the engine\n", 2670 p_hwfn->rel_pf_id, p_hwfn->abs_pf_id, 2671 p_hwfn->enabled_func_idx, p_hwfn->num_funcs_on_engine); 2672 } 2673 2674 static void ecore_hw_info_port_num_bb(struct ecore_hwfn *p_hwfn, 2675 struct ecore_ptt *p_ptt) 2676 { 2677 u32 port_mode; 2678 2679 #ifndef ASIC_ONLY 2680 /* Read the port mode */ 2681 if (CHIP_REV_IS_FPGA(p_hwfn->p_dev)) 2682 port_mode = 4; 2683 else if (CHIP_REV_IS_EMUL(p_hwfn->p_dev) && 2684 (p_hwfn->p_dev->num_hwfns > 1)) 2685 /* In CMT on emulation, assume 1 port */ 2686 port_mode = 1; 2687 else 2688 #endif 2689 port_mode = ecore_rd(p_hwfn, p_ptt, 2690 CNIG_REG_NW_PORT_MODE_BB_B0); 2691 2692 if (port_mode < 3) { 2693 p_hwfn->p_dev->num_ports_in_engines = 1; 2694 } else if (port_mode <= 5) { 2695 p_hwfn->p_dev->num_ports_in_engines = 2; 2696 } else { 2697 DP_NOTICE(p_hwfn, true, "PORT MODE: %d not supported\n", 2698 p_hwfn->p_dev->num_ports_in_engines); 2699 2700 /* Default num_ports_in_engines to something */ 2701 p_hwfn->p_dev->num_ports_in_engines = 1; 2702 } 2703 } 2704 2705 static void ecore_hw_info_port_num_ah(struct ecore_hwfn *p_hwfn, 2706 struct ecore_ptt *p_ptt) 2707 { 2708 u32 port; 2709 int i; 2710 2711 p_hwfn->p_dev->num_ports_in_engines = 0; 2712 2713 #ifndef ASIC_ONLY 2714 if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) { 2715 port = ecore_rd(p_hwfn, p_ptt, MISCS_REG_ECO_RESERVED); 2716 switch ((port & 0xf000) >> 12) { 2717 case 1: 2718 p_hwfn->p_dev->num_ports_in_engines = 1; 2719 break; 2720 case 3: 2721 p_hwfn->p_dev->num_ports_in_engines = 2; 2722 break; 2723 case 0xf: 2724 p_hwfn->p_dev->num_ports_in_engines = 4; 2725 break; 2726 default: 2727 DP_NOTICE(p_hwfn, false, 2728 "Unknown port mode in ECO_RESERVED %08x\n", 2729 port); 2730 } 2731 } else 2732 #endif 2733 for (i = 0; i < MAX_NUM_PORTS_K2; i++) { 2734 port = ecore_rd(p_hwfn, p_ptt, 2735 CNIG_REG_NIG_PORT0_CONF_K2 + (i * 4)); 2736 if (port & 1) 2737 p_hwfn->p_dev->num_ports_in_engines++; 2738 } 2739 } 2740 2741 static void ecore_hw_info_port_num(struct ecore_hwfn *p_hwfn, 2742 struct ecore_ptt *p_ptt) 2743 { 2744 if (ECORE_IS_BB(p_hwfn->p_dev)) 2745 ecore_hw_info_port_num_bb(p_hwfn, p_ptt); 2746 else 2747 ecore_hw_info_port_num_ah(p_hwfn, p_ptt); 2748 } 2749 2750 static enum _ecore_status_t 2751 ecore_get_hw_info(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt, 2752 enum ecore_pci_personality personality, bool drv_resc_alloc) 2753 { 2754 enum _ecore_status_t rc; 2755 2756 /* Since all information is common, only first hwfns should do this */ 2757 if (IS_LEAD_HWFN(p_hwfn)) { 2758 rc = ecore_iov_hw_info(p_hwfn); 2759 if (rc != ECORE_SUCCESS) 2760 return rc; 2761 } 2762 2763 /* TODO In get_hw_info, amoungst others: 2764 * Get MCP FW revision and determine according to it the supported 2765 * featrues (e.g. DCB) 2766 * Get boot mode 2767 * ecore_get_pcie_width_speed, WOL capability. 2768 * Number of global CQ-s (for storage 2769 */ 2770 ecore_hw_info_port_num(p_hwfn, p_ptt); 2771 2772 #ifndef ASIC_ONLY 2773 if (CHIP_REV_IS_ASIC(p_hwfn->p_dev)) { 2774 #endif 2775 rc = ecore_hw_get_nvm_info(p_hwfn, p_ptt); 2776 if (rc != ECORE_SUCCESS) 2777 return rc; 2778 #ifndef ASIC_ONLY 2779 } 2780 #endif 2781 2782 rc = ecore_int_igu_read_cam(p_hwfn, p_ptt); 2783 if (rc != ECORE_SUCCESS) 2784 return rc; 2785 2786 #ifndef ASIC_ONLY 2787 if (CHIP_REV_IS_ASIC(p_hwfn->p_dev) && ecore_mcp_is_init(p_hwfn)) { 2788 #endif 2789 OSAL_MEMCPY(p_hwfn->hw_info.hw_mac_addr, 2790 p_hwfn->mcp_info->func_info.mac, ETH_ALEN); 2791 #ifndef ASIC_ONLY 2792 } else { 2793 static u8 mcp_hw_mac[6] = { 0, 2, 3, 4, 5, 6 }; 2794 2795 OSAL_MEMCPY(p_hwfn->hw_info.hw_mac_addr, mcp_hw_mac, ETH_ALEN); 2796 p_hwfn->hw_info.hw_mac_addr[5] = p_hwfn->abs_pf_id; 2797 } 2798 #endif 2799 2800 if (ecore_mcp_is_init(p_hwfn)) { 2801 if (p_hwfn->mcp_info->func_info.ovlan != ECORE_MCP_VLAN_UNSET) 2802 p_hwfn->hw_info.ovlan = 2803 p_hwfn->mcp_info->func_info.ovlan; 2804 2805 ecore_mcp_cmd_port_init(p_hwfn, p_ptt); 2806 } 2807 2808 if (personality != ECORE_PCI_DEFAULT) { 2809 p_hwfn->hw_info.personality = personality; 2810 } else if (ecore_mcp_is_init(p_hwfn)) { 2811 enum ecore_pci_personality protocol; 2812 2813 protocol = p_hwfn->mcp_info->func_info.protocol; 2814 p_hwfn->hw_info.personality = protocol; 2815 } 2816 2817 #ifndef ASIC_ONLY 2818 /* To overcome ILT lack for emulation, until at least until we'll have 2819 * a definite answer from system about it, allow only PF0 to be RoCE. 2820 */ 2821 if (CHIP_REV_IS_EMUL(p_hwfn->p_dev) && ECORE_IS_AH(p_hwfn->p_dev)) { 2822 if (!p_hwfn->rel_pf_id) 2823 p_hwfn->hw_info.personality = ECORE_PCI_ETH_ROCE; 2824 else 2825 p_hwfn->hw_info.personality = ECORE_PCI_ETH; 2826 } 2827 #endif 2828 2829 /* although in BB some constellations may support more than 4 tcs, 2830 * that can result in performance penalty in some cases. 4 2831 * represents a good tradeoff between performance and flexibility. 2832 */ 2833 p_hwfn->hw_info.num_hw_tc = NUM_PHYS_TCS_4PORT_K2; 2834 2835 /* start out with a single active tc. This can be increased either 2836 * by dcbx negotiation or by upper layer driver 2837 */ 2838 p_hwfn->hw_info.num_active_tc = 1; 2839 2840 ecore_get_num_funcs(p_hwfn, p_ptt); 2841 2842 /* In case of forcing the driver's default resource allocation, calling 2843 * ecore_hw_get_resc() should come after initializing the personality 2844 * and after getting the number of functions, since the calculation of 2845 * the resources/features depends on them. 2846 * This order is not harmful if not forcing. 2847 */ 2848 return ecore_hw_get_resc(p_hwfn, drv_resc_alloc); 2849 } 2850 2851 #define ECORE_DEV_ID_MASK 0xff00 2852 #define ECORE_DEV_ID_MASK_BB 0x1600 2853 #define ECORE_DEV_ID_MASK_AH 0x8000 2854 2855 static enum _ecore_status_t ecore_get_dev_info(struct ecore_dev *p_dev) 2856 { 2857 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev); 2858 u32 tmp; 2859 2860 /* Read Vendor Id / Device Id */ 2861 OSAL_PCI_READ_CONFIG_WORD(p_dev, PCICFG_VENDOR_ID_OFFSET, 2862 &p_dev->vendor_id); 2863 OSAL_PCI_READ_CONFIG_WORD(p_dev, PCICFG_DEVICE_ID_OFFSET, 2864 &p_dev->device_id); 2865 2866 /* Determine type */ 2867 if ((p_dev->device_id & ECORE_DEV_ID_MASK) == ECORE_DEV_ID_MASK_AH) 2868 p_dev->type = ECORE_DEV_TYPE_AH; 2869 else 2870 p_dev->type = ECORE_DEV_TYPE_BB; 2871 2872 p_dev->chip_num = (u16)ecore_rd(p_hwfn, p_hwfn->p_main_ptt, 2873 MISCS_REG_CHIP_NUM); 2874 p_dev->chip_rev = (u16)ecore_rd(p_hwfn, p_hwfn->p_main_ptt, 2875 MISCS_REG_CHIP_REV); 2876 2877 MASK_FIELD(CHIP_REV, p_dev->chip_rev); 2878 2879 /* Learn number of HW-functions */ 2880 tmp = ecore_rd(p_hwfn, p_hwfn->p_main_ptt, 2881 MISCS_REG_CMT_ENABLED_FOR_PAIR); 2882 2883 if (tmp & (1 << p_hwfn->rel_pf_id)) { 2884 DP_NOTICE(p_dev->hwfns, false, "device in CMT mode\n"); 2885 p_dev->num_hwfns = 2; 2886 } else { 2887 p_dev->num_hwfns = 1; 2888 } 2889 2890 #ifndef ASIC_ONLY 2891 if (CHIP_REV_IS_EMUL(p_dev)) { 2892 /* For some reason we have problems with this register 2893 * in B0 emulation; Simply assume no CMT 2894 */ 2895 DP_NOTICE(p_dev->hwfns, false, 2896 "device on emul - assume no CMT\n"); 2897 p_dev->num_hwfns = 1; 2898 } 2899 #endif 2900 2901 p_dev->chip_bond_id = ecore_rd(p_hwfn, p_hwfn->p_main_ptt, 2902 MISCS_REG_CHIP_TEST_REG) >> 4; 2903 MASK_FIELD(CHIP_BOND_ID, p_dev->chip_bond_id); 2904 p_dev->chip_metal = (u16)ecore_rd(p_hwfn, p_hwfn->p_main_ptt, 2905 MISCS_REG_CHIP_METAL); 2906 MASK_FIELD(CHIP_METAL, p_dev->chip_metal); 2907 DP_INFO(p_dev->hwfns, 2908 "Chip details - %s%d, Num: %04x Rev: %04x Bond id: %04x Metal: %04x\n", 2909 ECORE_IS_BB(p_dev) ? "BB" : "AH", 2910 CHIP_REV_IS_A0(p_dev) ? 0 : 1, 2911 p_dev->chip_num, p_dev->chip_rev, p_dev->chip_bond_id, 2912 p_dev->chip_metal); 2913 2914 if (ECORE_IS_BB(p_dev) && CHIP_REV_IS_A0(p_dev)) { 2915 DP_NOTICE(p_dev->hwfns, false, 2916 "The chip type/rev (BB A0) is not supported!\n"); 2917 return ECORE_ABORTED; 2918 } 2919 #ifndef ASIC_ONLY 2920 if (CHIP_REV_IS_EMUL(p_dev) && ECORE_IS_AH(p_dev)) 2921 ecore_wr(p_hwfn, p_hwfn->p_main_ptt, 2922 MISCS_REG_PLL_MAIN_CTRL_4, 0x1); 2923 2924 if (CHIP_REV_IS_EMUL(p_dev)) { 2925 tmp = ecore_rd(p_hwfn, p_hwfn->p_main_ptt, 2926 MISCS_REG_ECO_RESERVED); 2927 if (tmp & (1 << 29)) { 2928 DP_NOTICE(p_hwfn, false, 2929 "Emulation: Running on a FULL build\n"); 2930 p_dev->b_is_emul_full = true; 2931 } else { 2932 DP_NOTICE(p_hwfn, false, 2933 "Emulation: Running on a REDUCED build\n"); 2934 } 2935 } 2936 #endif 2937 2938 return ECORE_SUCCESS; 2939 } 2940 2941 #ifndef LINUX_REMOVE 2942 void ecore_prepare_hibernate(struct ecore_dev *p_dev) 2943 { 2944 int j; 2945 2946 if (IS_VF(p_dev)) 2947 return; 2948 2949 for_each_hwfn(p_dev, j) { 2950 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j]; 2951 2952 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN, 2953 "Mark hw/fw uninitialized\n"); 2954 2955 p_hwfn->hw_init_done = false; 2956 p_hwfn->first_on_engine = false; 2957 2958 ecore_ptt_invalidate(p_hwfn); 2959 } 2960 } 2961 #endif 2962 2963 static enum _ecore_status_t 2964 ecore_hw_prepare_single(struct ecore_hwfn *p_hwfn, 2965 void OSAL_IOMEM * p_regview, 2966 void OSAL_IOMEM * p_doorbells, 2967 struct ecore_hw_prepare_params *p_params) 2968 { 2969 struct ecore_dev *p_dev = p_hwfn->p_dev; 2970 struct ecore_mdump_info mdump_info; 2971 enum _ecore_status_t rc = ECORE_SUCCESS; 2972 2973 /* Split PCI bars evenly between hwfns */ 2974 p_hwfn->regview = p_regview; 2975 p_hwfn->doorbells = p_doorbells; 2976 2977 if (IS_VF(p_dev)) 2978 return ecore_vf_hw_prepare(p_hwfn); 2979 2980 /* Validate that chip access is feasible */ 2981 if (REG_RD(p_hwfn, PXP_PF_ME_OPAQUE_ADDR) == 0xffffffff) { 2982 DP_ERR(p_hwfn, 2983 "Reading the ME register returns all Fs; Preventing further chip access\n"); 2984 return ECORE_INVAL; 2985 } 2986 2987 get_function_id(p_hwfn); 2988 2989 /* Allocate PTT pool */ 2990 rc = ecore_ptt_pool_alloc(p_hwfn); 2991 if (rc) { 2992 DP_NOTICE(p_hwfn, true, "Failed to prepare hwfn's hw\n"); 2993 goto err0; 2994 } 2995 2996 /* Allocate the main PTT */ 2997 p_hwfn->p_main_ptt = ecore_get_reserved_ptt(p_hwfn, RESERVED_PTT_MAIN); 2998 2999 /* First hwfn learns basic information, e.g., number of hwfns */ 3000 if (!p_hwfn->my_id) { 3001 rc = ecore_get_dev_info(p_dev); 3002 if (rc != ECORE_SUCCESS) 3003 goto err1; 3004 } 3005 3006 ecore_hw_hwfn_prepare(p_hwfn); 3007 3008 /* Initialize MCP structure */ 3009 rc = ecore_mcp_cmd_init(p_hwfn, p_hwfn->p_main_ptt); 3010 if (rc) { 3011 DP_NOTICE(p_hwfn, true, "Failed initializing mcp command\n"); 3012 goto err1; 3013 } 3014 3015 /* Read the device configuration information from the HW and SHMEM */ 3016 rc = ecore_get_hw_info(p_hwfn, p_hwfn->p_main_ptt, 3017 p_params->personality, p_params->drv_resc_alloc); 3018 if (rc) { 3019 DP_NOTICE(p_hwfn, true, "Failed to get HW information\n"); 3020 goto err2; 3021 } 3022 3023 /* Sending a mailbox to the MFW should be after ecore_get_hw_info() is 3024 * called, since among others it sets the ports number in an engine. 3025 */ 3026 if (p_params->initiate_pf_flr && p_hwfn == ECORE_LEADING_HWFN(p_dev) && 3027 !p_dev->recov_in_prog) { 3028 rc = ecore_mcp_initiate_pf_flr(p_hwfn, p_hwfn->p_main_ptt); 3029 if (rc != ECORE_SUCCESS) 3030 DP_NOTICE(p_hwfn, false, "Failed to initiate PF FLR\n"); 3031 } 3032 3033 /* Check if mdump logs are present and update the epoch value */ 3034 if (p_hwfn == ECORE_LEADING_HWFN(p_hwfn->p_dev)) { 3035 rc = ecore_mcp_mdump_get_info(p_hwfn, p_hwfn->p_main_ptt, 3036 &mdump_info); 3037 if (rc == ECORE_SUCCESS && mdump_info.num_of_logs > 0) { 3038 DP_NOTICE(p_hwfn, false, 3039 "* * * IMPORTANT - HW ERROR register dump captured by device * * *\n"); 3040 } 3041 3042 ecore_mcp_mdump_set_values(p_hwfn, p_hwfn->p_main_ptt, 3043 p_params->epoch); 3044 } 3045 3046 /* Allocate the init RT array and initialize the init-ops engine */ 3047 rc = ecore_init_alloc(p_hwfn); 3048 if (rc) { 3049 DP_NOTICE(p_hwfn, true, "Failed to allocate the init array\n"); 3050 goto err2; 3051 } 3052 #ifndef ASIC_ONLY 3053 if (CHIP_REV_IS_FPGA(p_dev)) { 3054 DP_NOTICE(p_hwfn, false, 3055 "FPGA: workaround; Prevent DMAE parities\n"); 3056 ecore_wr(p_hwfn, p_hwfn->p_main_ptt, PCIE_REG_PRTY_MASK, 7); 3057 3058 DP_NOTICE(p_hwfn, false, 3059 "FPGA: workaround: Set VF bar0 size\n"); 3060 ecore_wr(p_hwfn, p_hwfn->p_main_ptt, 3061 PGLUE_B_REG_VF_BAR0_SIZE, 4); 3062 } 3063 #endif 3064 3065 return rc; 3066 err2: 3067 if (IS_LEAD_HWFN(p_hwfn)) 3068 ecore_iov_free_hw_info(p_dev); 3069 ecore_mcp_free(p_hwfn); 3070 err1: 3071 ecore_hw_hwfn_free(p_hwfn); 3072 err0: 3073 return rc; 3074 } 3075 3076 enum _ecore_status_t ecore_hw_prepare(struct ecore_dev *p_dev, 3077 struct ecore_hw_prepare_params *p_params) 3078 { 3079 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev); 3080 enum _ecore_status_t rc; 3081 3082 p_dev->chk_reg_fifo = p_params->chk_reg_fifo; 3083 3084 /* Store the precompiled init data ptrs */ 3085 if (IS_PF(p_dev)) 3086 ecore_init_iro_array(p_dev); 3087 3088 /* Initialize the first hwfn - will learn number of hwfns */ 3089 rc = ecore_hw_prepare_single(p_hwfn, 3090 p_dev->regview, 3091 p_dev->doorbells, p_params); 3092 if (rc != ECORE_SUCCESS) 3093 return rc; 3094 3095 p_params->personality = p_hwfn->hw_info.personality; 3096 3097 /* initilalize 2nd hwfn if necessary */ 3098 if (p_dev->num_hwfns > 1) { 3099 void OSAL_IOMEM *p_regview, *p_doorbell; 3100 u8 OSAL_IOMEM *addr; 3101 3102 /* adjust bar offset for second engine */ 3103 addr = (u8 OSAL_IOMEM *)p_dev->regview + 3104 ecore_hw_bar_size(p_hwfn, BAR_ID_0) / 2; 3105 p_regview = (void OSAL_IOMEM *)addr; 3106 3107 addr = (u8 OSAL_IOMEM *)p_dev->doorbells + 3108 ecore_hw_bar_size(p_hwfn, BAR_ID_1) / 2; 3109 p_doorbell = (void OSAL_IOMEM *)addr; 3110 3111 /* prepare second hw function */ 3112 rc = ecore_hw_prepare_single(&p_dev->hwfns[1], p_regview, 3113 p_doorbell, p_params); 3114 3115 /* in case of error, need to free the previously 3116 * initiliazed hwfn 0. 3117 */ 3118 if (rc != ECORE_SUCCESS) { 3119 if (IS_PF(p_dev)) { 3120 ecore_init_free(p_hwfn); 3121 ecore_mcp_free(p_hwfn); 3122 ecore_hw_hwfn_free(p_hwfn); 3123 } else { 3124 DP_NOTICE(p_dev, true, 3125 "What do we need to free when VF hwfn1 init fails\n"); 3126 } 3127 return rc; 3128 } 3129 } 3130 3131 return rc; 3132 } 3133 3134 void ecore_hw_remove(struct ecore_dev *p_dev) 3135 { 3136 int i; 3137 3138 for_each_hwfn(p_dev, i) { 3139 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i]; 3140 3141 if (IS_VF(p_dev)) { 3142 ecore_vf_pf_release(p_hwfn); 3143 continue; 3144 } 3145 3146 ecore_init_free(p_hwfn); 3147 ecore_hw_hwfn_free(p_hwfn); 3148 ecore_mcp_free(p_hwfn); 3149 3150 OSAL_MUTEX_DEALLOC(&p_hwfn->dmae_info.mutex); 3151 } 3152 3153 ecore_iov_free_hw_info(p_dev); 3154 } 3155 3156 static void ecore_chain_free_next_ptr(struct ecore_dev *p_dev, 3157 struct ecore_chain *p_chain) 3158 { 3159 void *p_virt = p_chain->p_virt_addr, *p_virt_next = OSAL_NULL; 3160 dma_addr_t p_phys = p_chain->p_phys_addr, p_phys_next = 0; 3161 struct ecore_chain_next *p_next; 3162 u32 size, i; 3163 3164 if (!p_virt) 3165 return; 3166 3167 size = p_chain->elem_size * p_chain->usable_per_page; 3168 3169 for (i = 0; i < p_chain->page_cnt; i++) { 3170 if (!p_virt) 3171 break; 3172 3173 p_next = (struct ecore_chain_next *)((u8 *)p_virt + size); 3174 p_virt_next = p_next->next_virt; 3175 p_phys_next = HILO_DMA_REGPAIR(p_next->next_phys); 3176 3177 OSAL_DMA_FREE_COHERENT(p_dev, p_virt, p_phys, 3178 ECORE_CHAIN_PAGE_SIZE); 3179 3180 p_virt = p_virt_next; 3181 p_phys = p_phys_next; 3182 } 3183 } 3184 3185 static void ecore_chain_free_single(struct ecore_dev *p_dev, 3186 struct ecore_chain *p_chain) 3187 { 3188 if (!p_chain->p_virt_addr) 3189 return; 3190 3191 OSAL_DMA_FREE_COHERENT(p_dev, p_chain->p_virt_addr, 3192 p_chain->p_phys_addr, ECORE_CHAIN_PAGE_SIZE); 3193 } 3194 3195 static void ecore_chain_free_pbl(struct ecore_dev *p_dev, 3196 struct ecore_chain *p_chain) 3197 { 3198 void **pp_virt_addr_tbl = p_chain->pbl.pp_virt_addr_tbl; 3199 u8 *p_pbl_virt = (u8 *)p_chain->pbl.p_virt_table; 3200 u32 page_cnt = p_chain->page_cnt, i, pbl_size; 3201 3202 if (!pp_virt_addr_tbl) 3203 return; 3204 3205 if (!p_chain->pbl.p_virt_table) 3206 goto out; 3207 3208 for (i = 0; i < page_cnt; i++) { 3209 if (!pp_virt_addr_tbl[i]) 3210 break; 3211 3212 OSAL_DMA_FREE_COHERENT(p_dev, pp_virt_addr_tbl[i], 3213 *(dma_addr_t *)p_pbl_virt, 3214 ECORE_CHAIN_PAGE_SIZE); 3215 3216 p_pbl_virt += ECORE_CHAIN_PBL_ENTRY_SIZE; 3217 } 3218 3219 pbl_size = page_cnt * ECORE_CHAIN_PBL_ENTRY_SIZE; 3220 3221 if (!p_chain->pbl.external) 3222 OSAL_DMA_FREE_COHERENT(p_dev, p_chain->pbl.p_virt_table, 3223 p_chain->pbl.p_phys_table, pbl_size); 3224 out: 3225 OSAL_VFREE(p_dev, p_chain->pbl.pp_virt_addr_tbl); 3226 } 3227 3228 void ecore_chain_free(struct ecore_dev *p_dev, struct ecore_chain *p_chain) 3229 { 3230 switch (p_chain->mode) { 3231 case ECORE_CHAIN_MODE_NEXT_PTR: 3232 ecore_chain_free_next_ptr(p_dev, p_chain); 3233 break; 3234 case ECORE_CHAIN_MODE_SINGLE: 3235 ecore_chain_free_single(p_dev, p_chain); 3236 break; 3237 case ECORE_CHAIN_MODE_PBL: 3238 ecore_chain_free_pbl(p_dev, p_chain); 3239 break; 3240 } 3241 } 3242 3243 static enum _ecore_status_t 3244 ecore_chain_alloc_sanity_check(struct ecore_dev *p_dev, 3245 enum ecore_chain_cnt_type cnt_type, 3246 osal_size_t elem_size, u32 page_cnt) 3247 { 3248 u64 chain_size = ELEMS_PER_PAGE(elem_size) * page_cnt; 3249 3250 /* The actual chain size can be larger than the maximal possible value 3251 * after rounding up the requested elements number to pages, and after 3252 * taking into acount the unusuable elements (next-ptr elements). 3253 * The size of a "u16" chain can be (U16_MAX + 1) since the chain 3254 * size/capacity fields are of a u32 type. 3255 */ 3256 if ((cnt_type == ECORE_CHAIN_CNT_TYPE_U16 && 3257 chain_size > ((u32)ECORE_U16_MAX + 1)) || 3258 (cnt_type == ECORE_CHAIN_CNT_TYPE_U32 && 3259 chain_size > ECORE_U32_MAX)) { 3260 DP_NOTICE(p_dev, true, 3261 "The actual chain size (0x%lx) is larger than the maximal possible value\n", 3262 (unsigned long)chain_size); 3263 return ECORE_INVAL; 3264 } 3265 3266 return ECORE_SUCCESS; 3267 } 3268 3269 static enum _ecore_status_t 3270 ecore_chain_alloc_next_ptr(struct ecore_dev *p_dev, struct ecore_chain *p_chain) 3271 { 3272 void *p_virt = OSAL_NULL, *p_virt_prev = OSAL_NULL; 3273 dma_addr_t p_phys = 0; 3274 u32 i; 3275 3276 for (i = 0; i < p_chain->page_cnt; i++) { 3277 p_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_phys, 3278 ECORE_CHAIN_PAGE_SIZE); 3279 if (!p_virt) { 3280 DP_NOTICE(p_dev, true, 3281 "Failed to allocate chain memory\n"); 3282 return ECORE_NOMEM; 3283 } 3284 3285 if (i == 0) { 3286 ecore_chain_init_mem(p_chain, p_virt, p_phys); 3287 ecore_chain_reset(p_chain); 3288 } else { 3289 ecore_chain_init_next_ptr_elem(p_chain, p_virt_prev, 3290 p_virt, p_phys); 3291 } 3292 3293 p_virt_prev = p_virt; 3294 } 3295 /* Last page's next element should point to the beginning of the 3296 * chain. 3297 */ 3298 ecore_chain_init_next_ptr_elem(p_chain, p_virt_prev, 3299 p_chain->p_virt_addr, 3300 p_chain->p_phys_addr); 3301 3302 return ECORE_SUCCESS; 3303 } 3304 3305 static enum _ecore_status_t 3306 ecore_chain_alloc_single(struct ecore_dev *p_dev, struct ecore_chain *p_chain) 3307 { 3308 dma_addr_t p_phys = 0; 3309 void *p_virt = OSAL_NULL; 3310 3311 p_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_phys, ECORE_CHAIN_PAGE_SIZE); 3312 if (!p_virt) { 3313 DP_NOTICE(p_dev, true, "Failed to allocate chain memory\n"); 3314 return ECORE_NOMEM; 3315 } 3316 3317 ecore_chain_init_mem(p_chain, p_virt, p_phys); 3318 ecore_chain_reset(p_chain); 3319 3320 return ECORE_SUCCESS; 3321 } 3322 3323 static enum _ecore_status_t 3324 ecore_chain_alloc_pbl(struct ecore_dev *p_dev, 3325 struct ecore_chain *p_chain, 3326 struct ecore_chain_ext_pbl *ext_pbl) 3327 { 3328 void *p_virt = OSAL_NULL; 3329 u8 *p_pbl_virt = OSAL_NULL; 3330 void **pp_virt_addr_tbl = OSAL_NULL; 3331 dma_addr_t p_phys = 0, p_pbl_phys = 0; 3332 u32 page_cnt = p_chain->page_cnt, size, i; 3333 3334 size = page_cnt * sizeof(*pp_virt_addr_tbl); 3335 pp_virt_addr_tbl = (void **)OSAL_VALLOC(p_dev, size); 3336 if (!pp_virt_addr_tbl) { 3337 DP_NOTICE(p_dev, true, 3338 "Failed to allocate memory for the chain virtual addresses table\n"); 3339 return ECORE_NOMEM; 3340 } 3341 OSAL_MEM_ZERO(pp_virt_addr_tbl, size); 3342 3343 /* The allocation of the PBL table is done with its full size, since it 3344 * is expected to be successive. 3345 * ecore_chain_init_pbl_mem() is called even in a case of an allocation 3346 * failure, since pp_virt_addr_tbl was previously allocated, and it 3347 * should be saved to allow its freeing during the error flow. 3348 */ 3349 size = page_cnt * ECORE_CHAIN_PBL_ENTRY_SIZE; 3350 3351 if (ext_pbl == OSAL_NULL) { 3352 p_pbl_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_pbl_phys, size); 3353 } else { 3354 p_pbl_virt = ext_pbl->p_pbl_virt; 3355 p_pbl_phys = ext_pbl->p_pbl_phys; 3356 p_chain->pbl.external = true; 3357 } 3358 3359 ecore_chain_init_pbl_mem(p_chain, p_pbl_virt, p_pbl_phys, 3360 pp_virt_addr_tbl); 3361 if (!p_pbl_virt) { 3362 DP_NOTICE(p_dev, true, "Failed to allocate chain pbl memory\n"); 3363 return ECORE_NOMEM; 3364 } 3365 3366 for (i = 0; i < page_cnt; i++) { 3367 p_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_phys, 3368 ECORE_CHAIN_PAGE_SIZE); 3369 if (!p_virt) { 3370 DP_NOTICE(p_dev, true, 3371 "Failed to allocate chain memory\n"); 3372 return ECORE_NOMEM; 3373 } 3374 3375 if (i == 0) { 3376 ecore_chain_init_mem(p_chain, p_virt, p_phys); 3377 ecore_chain_reset(p_chain); 3378 } 3379 3380 /* Fill the PBL table with the physical address of the page */ 3381 *(dma_addr_t *)p_pbl_virt = p_phys; 3382 /* Keep the virtual address of the page */ 3383 p_chain->pbl.pp_virt_addr_tbl[i] = p_virt; 3384 3385 p_pbl_virt += ECORE_CHAIN_PBL_ENTRY_SIZE; 3386 } 3387 3388 return ECORE_SUCCESS; 3389 } 3390 3391 enum _ecore_status_t ecore_chain_alloc(struct ecore_dev *p_dev, 3392 enum ecore_chain_use_mode intended_use, 3393 enum ecore_chain_mode mode, 3394 enum ecore_chain_cnt_type cnt_type, 3395 u32 num_elems, osal_size_t elem_size, 3396 struct ecore_chain *p_chain, 3397 struct ecore_chain_ext_pbl *ext_pbl) 3398 { 3399 u32 page_cnt; 3400 enum _ecore_status_t rc = ECORE_SUCCESS; 3401 3402 if (mode == ECORE_CHAIN_MODE_SINGLE) 3403 page_cnt = 1; 3404 else 3405 page_cnt = ECORE_CHAIN_PAGE_CNT(num_elems, elem_size, mode); 3406 3407 rc = ecore_chain_alloc_sanity_check(p_dev, cnt_type, elem_size, 3408 page_cnt); 3409 if (rc) { 3410 DP_NOTICE(p_dev, true, 3411 "Cannot allocate a chain with the given arguments:\n" 3412 "[use_mode %d, mode %d, cnt_type %d, num_elems %d, elem_size %zu]\n", 3413 intended_use, mode, cnt_type, num_elems, elem_size); 3414 return rc; 3415 } 3416 3417 ecore_chain_init_params(p_chain, page_cnt, (u8)elem_size, intended_use, 3418 mode, cnt_type, p_dev->dp_ctx); 3419 3420 switch (mode) { 3421 case ECORE_CHAIN_MODE_NEXT_PTR: 3422 rc = ecore_chain_alloc_next_ptr(p_dev, p_chain); 3423 break; 3424 case ECORE_CHAIN_MODE_SINGLE: 3425 rc = ecore_chain_alloc_single(p_dev, p_chain); 3426 break; 3427 case ECORE_CHAIN_MODE_PBL: 3428 rc = ecore_chain_alloc_pbl(p_dev, p_chain, ext_pbl); 3429 break; 3430 } 3431 if (rc) 3432 goto nomem; 3433 3434 return ECORE_SUCCESS; 3435 3436 nomem: 3437 ecore_chain_free(p_dev, p_chain); 3438 return rc; 3439 } 3440 3441 enum _ecore_status_t ecore_fw_l2_queue(struct ecore_hwfn *p_hwfn, 3442 u16 src_id, u16 *dst_id) 3443 { 3444 if (src_id >= RESC_NUM(p_hwfn, ECORE_L2_QUEUE)) { 3445 u16 min, max; 3446 3447 min = (u16)RESC_START(p_hwfn, ECORE_L2_QUEUE); 3448 max = min + RESC_NUM(p_hwfn, ECORE_L2_QUEUE); 3449 DP_NOTICE(p_hwfn, true, 3450 "l2_queue id [%d] is not valid, available indices [%d - %d]\n", 3451 src_id, min, max); 3452 3453 return ECORE_INVAL; 3454 } 3455 3456 *dst_id = RESC_START(p_hwfn, ECORE_L2_QUEUE) + src_id; 3457 3458 return ECORE_SUCCESS; 3459 } 3460 3461 enum _ecore_status_t ecore_fw_vport(struct ecore_hwfn *p_hwfn, 3462 u8 src_id, u8 *dst_id) 3463 { 3464 if (src_id >= RESC_NUM(p_hwfn, ECORE_VPORT)) { 3465 u8 min, max; 3466 3467 min = (u8)RESC_START(p_hwfn, ECORE_VPORT); 3468 max = min + RESC_NUM(p_hwfn, ECORE_VPORT); 3469 DP_NOTICE(p_hwfn, true, 3470 "vport id [%d] is not valid, available indices [%d - %d]\n", 3471 src_id, min, max); 3472 3473 return ECORE_INVAL; 3474 } 3475 3476 *dst_id = RESC_START(p_hwfn, ECORE_VPORT) + src_id; 3477 3478 return ECORE_SUCCESS; 3479 } 3480 3481 enum _ecore_status_t ecore_fw_rss_eng(struct ecore_hwfn *p_hwfn, 3482 u8 src_id, u8 *dst_id) 3483 { 3484 if (src_id >= RESC_NUM(p_hwfn, ECORE_RSS_ENG)) { 3485 u8 min, max; 3486 3487 min = (u8)RESC_START(p_hwfn, ECORE_RSS_ENG); 3488 max = min + RESC_NUM(p_hwfn, ECORE_RSS_ENG); 3489 DP_NOTICE(p_hwfn, true, 3490 "rss_eng id [%d] is not valid, available indices [%d - %d]\n", 3491 src_id, min, max); 3492 3493 return ECORE_INVAL; 3494 } 3495 3496 *dst_id = RESC_START(p_hwfn, ECORE_RSS_ENG) + src_id; 3497 3498 return ECORE_SUCCESS; 3499 } 3500 3501 enum _ecore_status_t ecore_llh_add_mac_filter(struct ecore_hwfn *p_hwfn, 3502 struct ecore_ptt *p_ptt, 3503 u8 *p_filter) 3504 { 3505 u32 high, low, en; 3506 int i; 3507 3508 if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn))) 3509 return ECORE_SUCCESS; 3510 3511 high = p_filter[1] | (p_filter[0] << 8); 3512 low = p_filter[5] | (p_filter[4] << 8) | 3513 (p_filter[3] << 16) | (p_filter[2] << 24); 3514 3515 /* Find a free entry and utilize it */ 3516 for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) { 3517 en = ecore_rd(p_hwfn, p_ptt, 3518 NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32)); 3519 if (en) 3520 continue; 3521 ecore_wr(p_hwfn, p_ptt, 3522 NIG_REG_LLH_FUNC_FILTER_VALUE + 3523 2 * i * sizeof(u32), low); 3524 ecore_wr(p_hwfn, p_ptt, 3525 NIG_REG_LLH_FUNC_FILTER_VALUE + 3526 (2 * i + 1) * sizeof(u32), high); 3527 ecore_wr(p_hwfn, p_ptt, 3528 NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32), 0); 3529 ecore_wr(p_hwfn, p_ptt, 3530 NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE + 3531 i * sizeof(u32), 0); 3532 ecore_wr(p_hwfn, p_ptt, 3533 NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 1); 3534 break; 3535 } 3536 if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE) { 3537 DP_NOTICE(p_hwfn, false, 3538 "Failed to find an empty LLH filter to utilize\n"); 3539 return ECORE_INVAL; 3540 } 3541 3542 DP_VERBOSE(p_hwfn, ECORE_MSG_HW, 3543 "MAC: %x:%x:%x:%x:%x:%x is added at %d\n", 3544 p_filter[0], p_filter[1], p_filter[2], 3545 p_filter[3], p_filter[4], p_filter[5], i); 3546 3547 return ECORE_SUCCESS; 3548 } 3549 3550 void ecore_llh_remove_mac_filter(struct ecore_hwfn *p_hwfn, 3551 struct ecore_ptt *p_ptt, u8 *p_filter) 3552 { 3553 u32 high, low; 3554 int i; 3555 3556 if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn))) 3557 return; 3558 3559 high = p_filter[1] | (p_filter[0] << 8); 3560 low = p_filter[5] | (p_filter[4] << 8) | 3561 (p_filter[3] << 16) | (p_filter[2] << 24); 3562 3563 /* Find the entry and clean it */ 3564 for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) { 3565 if (ecore_rd(p_hwfn, p_ptt, 3566 NIG_REG_LLH_FUNC_FILTER_VALUE + 3567 2 * i * sizeof(u32)) != low) 3568 continue; 3569 if (ecore_rd(p_hwfn, p_ptt, 3570 NIG_REG_LLH_FUNC_FILTER_VALUE + 3571 (2 * i + 1) * sizeof(u32)) != high) 3572 continue; 3573 3574 ecore_wr(p_hwfn, p_ptt, 3575 NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 0); 3576 ecore_wr(p_hwfn, p_ptt, 3577 NIG_REG_LLH_FUNC_FILTER_VALUE + 3578 2 * i * sizeof(u32), 0); 3579 ecore_wr(p_hwfn, p_ptt, 3580 NIG_REG_LLH_FUNC_FILTER_VALUE + 3581 (2 * i + 1) * sizeof(u32), 0); 3582 break; 3583 } 3584 if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE) 3585 DP_NOTICE(p_hwfn, false, 3586 "Tried to remove a non-configured filter\n"); 3587 } 3588 3589 enum _ecore_status_t 3590 ecore_llh_add_protocol_filter(struct ecore_hwfn *p_hwfn, 3591 struct ecore_ptt *p_ptt, 3592 u16 source_port_or_eth_type, 3593 u16 dest_port, 3594 enum ecore_llh_port_filter_type_t type) 3595 { 3596 u32 high, low, en; 3597 int i; 3598 3599 if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn))) 3600 return ECORE_SUCCESS; 3601 3602 high = 0; 3603 low = 0; 3604 switch (type) { 3605 case ECORE_LLH_FILTER_ETHERTYPE: 3606 high = source_port_or_eth_type; 3607 break; 3608 case ECORE_LLH_FILTER_TCP_SRC_PORT: 3609 case ECORE_LLH_FILTER_UDP_SRC_PORT: 3610 low = source_port_or_eth_type << 16; 3611 break; 3612 case ECORE_LLH_FILTER_TCP_DEST_PORT: 3613 case ECORE_LLH_FILTER_UDP_DEST_PORT: 3614 low = dest_port; 3615 break; 3616 case ECORE_LLH_FILTER_TCP_SRC_AND_DEST_PORT: 3617 case ECORE_LLH_FILTER_UDP_SRC_AND_DEST_PORT: 3618 low = (source_port_or_eth_type << 16) | dest_port; 3619 break; 3620 default: 3621 DP_NOTICE(p_hwfn, true, 3622 "Non valid LLH protocol filter type %d\n", type); 3623 return ECORE_INVAL; 3624 } 3625 /* Find a free entry and utilize it */ 3626 for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) { 3627 en = ecore_rd(p_hwfn, p_ptt, 3628 NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32)); 3629 if (en) 3630 continue; 3631 ecore_wr(p_hwfn, p_ptt, 3632 NIG_REG_LLH_FUNC_FILTER_VALUE + 3633 2 * i * sizeof(u32), low); 3634 ecore_wr(p_hwfn, p_ptt, 3635 NIG_REG_LLH_FUNC_FILTER_VALUE + 3636 (2 * i + 1) * sizeof(u32), high); 3637 ecore_wr(p_hwfn, p_ptt, 3638 NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32), 1); 3639 ecore_wr(p_hwfn, p_ptt, 3640 NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE + 3641 i * sizeof(u32), 1 << type); 3642 ecore_wr(p_hwfn, p_ptt, 3643 NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 1); 3644 break; 3645 } 3646 if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE) { 3647 DP_NOTICE(p_hwfn, false, 3648 "Failed to find an empty LLH filter to utilize\n"); 3649 return ECORE_NORESOURCES; 3650 } 3651 switch (type) { 3652 case ECORE_LLH_FILTER_ETHERTYPE: 3653 DP_VERBOSE(p_hwfn, ECORE_MSG_HW, 3654 "ETH type %x is added at %d\n", 3655 source_port_or_eth_type, i); 3656 break; 3657 case ECORE_LLH_FILTER_TCP_SRC_PORT: 3658 DP_VERBOSE(p_hwfn, ECORE_MSG_HW, 3659 "TCP src port %x is added at %d\n", 3660 source_port_or_eth_type, i); 3661 break; 3662 case ECORE_LLH_FILTER_UDP_SRC_PORT: 3663 DP_VERBOSE(p_hwfn, ECORE_MSG_HW, 3664 "UDP src port %x is added at %d\n", 3665 source_port_or_eth_type, i); 3666 break; 3667 case ECORE_LLH_FILTER_TCP_DEST_PORT: 3668 DP_VERBOSE(p_hwfn, ECORE_MSG_HW, 3669 "TCP dst port %x is added at %d\n", dest_port, i); 3670 break; 3671 case ECORE_LLH_FILTER_UDP_DEST_PORT: 3672 DP_VERBOSE(p_hwfn, ECORE_MSG_HW, 3673 "UDP dst port %x is added at %d\n", dest_port, i); 3674 break; 3675 case ECORE_LLH_FILTER_TCP_SRC_AND_DEST_PORT: 3676 DP_VERBOSE(p_hwfn, ECORE_MSG_HW, 3677 "TCP src/dst ports %x/%x are added at %d\n", 3678 source_port_or_eth_type, dest_port, i); 3679 break; 3680 case ECORE_LLH_FILTER_UDP_SRC_AND_DEST_PORT: 3681 DP_VERBOSE(p_hwfn, ECORE_MSG_HW, 3682 "UDP src/dst ports %x/%x are added at %d\n", 3683 source_port_or_eth_type, dest_port, i); 3684 break; 3685 } 3686 return ECORE_SUCCESS; 3687 } 3688 3689 void 3690 ecore_llh_remove_protocol_filter(struct ecore_hwfn *p_hwfn, 3691 struct ecore_ptt *p_ptt, 3692 u16 source_port_or_eth_type, 3693 u16 dest_port, 3694 enum ecore_llh_port_filter_type_t type) 3695 { 3696 u32 high, low; 3697 int i; 3698 3699 if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn))) 3700 return; 3701 3702 high = 0; 3703 low = 0; 3704 switch (type) { 3705 case ECORE_LLH_FILTER_ETHERTYPE: 3706 high = source_port_or_eth_type; 3707 break; 3708 case ECORE_LLH_FILTER_TCP_SRC_PORT: 3709 case ECORE_LLH_FILTER_UDP_SRC_PORT: 3710 low = source_port_or_eth_type << 16; 3711 break; 3712 case ECORE_LLH_FILTER_TCP_DEST_PORT: 3713 case ECORE_LLH_FILTER_UDP_DEST_PORT: 3714 low = dest_port; 3715 break; 3716 case ECORE_LLH_FILTER_TCP_SRC_AND_DEST_PORT: 3717 case ECORE_LLH_FILTER_UDP_SRC_AND_DEST_PORT: 3718 low = (source_port_or_eth_type << 16) | dest_port; 3719 break; 3720 default: 3721 DP_NOTICE(p_hwfn, true, 3722 "Non valid LLH protocol filter type %d\n", type); 3723 return; 3724 } 3725 3726 for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) { 3727 if (!ecore_rd(p_hwfn, p_ptt, 3728 NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32))) 3729 continue; 3730 if (!ecore_rd(p_hwfn, p_ptt, 3731 NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32))) 3732 continue; 3733 if (!(ecore_rd(p_hwfn, p_ptt, 3734 NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE + 3735 i * sizeof(u32)) & (1 << type))) 3736 continue; 3737 if (ecore_rd(p_hwfn, p_ptt, 3738 NIG_REG_LLH_FUNC_FILTER_VALUE + 3739 2 * i * sizeof(u32)) != low) 3740 continue; 3741 if (ecore_rd(p_hwfn, p_ptt, 3742 NIG_REG_LLH_FUNC_FILTER_VALUE + 3743 (2 * i + 1) * sizeof(u32)) != high) 3744 continue; 3745 3746 ecore_wr(p_hwfn, p_ptt, 3747 NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 0); 3748 ecore_wr(p_hwfn, p_ptt, 3749 NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32), 0); 3750 ecore_wr(p_hwfn, p_ptt, 3751 NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE + 3752 i * sizeof(u32), 0); 3753 ecore_wr(p_hwfn, p_ptt, 3754 NIG_REG_LLH_FUNC_FILTER_VALUE + 3755 2 * i * sizeof(u32), 0); 3756 ecore_wr(p_hwfn, p_ptt, 3757 NIG_REG_LLH_FUNC_FILTER_VALUE + 3758 (2 * i + 1) * sizeof(u32), 0); 3759 break; 3760 } 3761 3762 if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE) 3763 DP_NOTICE(p_hwfn, false, 3764 "Tried to remove a non-configured filter\n"); 3765 } 3766 3767 void ecore_llh_clear_all_filters(struct ecore_hwfn *p_hwfn, 3768 struct ecore_ptt *p_ptt) 3769 { 3770 int i; 3771 3772 if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn))) 3773 return; 3774 3775 for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) { 3776 ecore_wr(p_hwfn, p_ptt, 3777 NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 0); 3778 ecore_wr(p_hwfn, p_ptt, 3779 NIG_REG_LLH_FUNC_FILTER_VALUE + 3780 2 * i * sizeof(u32), 0); 3781 ecore_wr(p_hwfn, p_ptt, 3782 NIG_REG_LLH_FUNC_FILTER_VALUE + 3783 (2 * i + 1) * sizeof(u32), 0); 3784 } 3785 } 3786 3787 enum _ecore_status_t 3788 ecore_llh_set_function_as_default(struct ecore_hwfn *p_hwfn, 3789 struct ecore_ptt *p_ptt) 3790 { 3791 if (IS_MF_DEFAULT(p_hwfn) && ECORE_IS_BB(p_hwfn->p_dev)) { 3792 ecore_wr(p_hwfn, p_ptt, 3793 NIG_REG_LLH_TAGMAC_DEF_PF_VECTOR, 3794 1 << p_hwfn->abs_pf_id / 2); 3795 ecore_wr(p_hwfn, p_ptt, PRS_REG_MSG_INFO, 0); 3796 return ECORE_SUCCESS; 3797 } 3798 3799 DP_NOTICE(p_hwfn, false, 3800 "This function can't be set as default\n"); 3801 return ECORE_INVAL; 3802 } 3803 3804 static enum _ecore_status_t ecore_set_coalesce(struct ecore_hwfn *p_hwfn, 3805 struct ecore_ptt *p_ptt, 3806 u32 hw_addr, void *p_eth_qzone, 3807 osal_size_t eth_qzone_size, 3808 u8 timeset) 3809 { 3810 struct coalescing_timeset *p_coal_timeset; 3811 3812 if (IS_VF(p_hwfn->p_dev)) { 3813 DP_NOTICE(p_hwfn, true, "VF coalescing config not supported\n"); 3814 return ECORE_INVAL; 3815 } 3816 3817 if (p_hwfn->p_dev->int_coalescing_mode != ECORE_COAL_MODE_ENABLE) { 3818 DP_NOTICE(p_hwfn, true, 3819 "Coalescing configuration not enabled\n"); 3820 return ECORE_INVAL; 3821 } 3822 3823 p_coal_timeset = p_eth_qzone; 3824 OSAL_MEMSET(p_eth_qzone, 0, eth_qzone_size); 3825 SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_TIMESET, timeset); 3826 SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_VALID, 1); 3827 ecore_memcpy_to(p_hwfn, p_ptt, hw_addr, p_eth_qzone, eth_qzone_size); 3828 3829 return ECORE_SUCCESS; 3830 } 3831 3832 enum _ecore_status_t ecore_set_rxq_coalesce(struct ecore_hwfn *p_hwfn, 3833 struct ecore_ptt *p_ptt, 3834 u16 coalesce, u8 qid, u16 sb_id) 3835 { 3836 struct ustorm_eth_queue_zone eth_qzone; 3837 u8 timeset, timer_res; 3838 u16 fw_qid = 0; 3839 u32 address; 3840 enum _ecore_status_t rc; 3841 3842 /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */ 3843 if (coalesce <= 0x7F) { 3844 timer_res = 0; 3845 } else if (coalesce <= 0xFF) { 3846 timer_res = 1; 3847 } else if (coalesce <= 0x1FF) { 3848 timer_res = 2; 3849 } else { 3850 DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce); 3851 return ECORE_INVAL; 3852 } 3853 timeset = (u8)(coalesce >> timer_res); 3854 3855 rc = ecore_fw_l2_queue(p_hwfn, (u16)qid, &fw_qid); 3856 if (rc != ECORE_SUCCESS) 3857 return rc; 3858 3859 rc = ecore_int_set_timer_res(p_hwfn, p_ptt, timer_res, sb_id, false); 3860 if (rc != ECORE_SUCCESS) 3861 goto out; 3862 3863 address = BAR0_MAP_REG_USDM_RAM + USTORM_ETH_QUEUE_ZONE_OFFSET(fw_qid); 3864 3865 rc = ecore_set_coalesce(p_hwfn, p_ptt, address, ð_qzone, 3866 sizeof(struct ustorm_eth_queue_zone), timeset); 3867 if (rc != ECORE_SUCCESS) 3868 goto out; 3869 3870 p_hwfn->p_dev->rx_coalesce_usecs = coalesce; 3871 out: 3872 return rc; 3873 } 3874 3875 enum _ecore_status_t ecore_set_txq_coalesce(struct ecore_hwfn *p_hwfn, 3876 struct ecore_ptt *p_ptt, 3877 u16 coalesce, u8 qid, u16 sb_id) 3878 { 3879 struct xstorm_eth_queue_zone eth_qzone; 3880 u8 timeset, timer_res; 3881 u16 fw_qid = 0; 3882 u32 address; 3883 enum _ecore_status_t rc; 3884 3885 /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */ 3886 if (coalesce <= 0x7F) { 3887 timer_res = 0; 3888 } else if (coalesce <= 0xFF) { 3889 timer_res = 1; 3890 } else if (coalesce <= 0x1FF) { 3891 timer_res = 2; 3892 } else { 3893 DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce); 3894 return ECORE_INVAL; 3895 } 3896 3897 timeset = (u8)(coalesce >> timer_res); 3898 3899 rc = ecore_fw_l2_queue(p_hwfn, (u16)qid, &fw_qid); 3900 if (rc != ECORE_SUCCESS) 3901 return rc; 3902 3903 rc = ecore_int_set_timer_res(p_hwfn, p_ptt, timer_res, sb_id, true); 3904 if (rc != ECORE_SUCCESS) 3905 goto out; 3906 3907 address = BAR0_MAP_REG_XSDM_RAM + XSTORM_ETH_QUEUE_ZONE_OFFSET(fw_qid); 3908 3909 rc = ecore_set_coalesce(p_hwfn, p_ptt, address, ð_qzone, 3910 sizeof(struct xstorm_eth_queue_zone), timeset); 3911 if (rc != ECORE_SUCCESS) 3912 goto out; 3913 3914 p_hwfn->p_dev->tx_coalesce_usecs = coalesce; 3915 out: 3916 return rc; 3917 } 3918 3919 /* Calculate final WFQ values for all vports and configure it. 3920 * After this configuration each vport must have 3921 * approx min rate = vport_wfq * min_pf_rate / ECORE_WFQ_UNIT 3922 */ 3923 static void ecore_configure_wfq_for_all_vports(struct ecore_hwfn *p_hwfn, 3924 struct ecore_ptt *p_ptt, 3925 u32 min_pf_rate) 3926 { 3927 struct init_qm_vport_params *vport_params; 3928 int i; 3929 3930 vport_params = p_hwfn->qm_info.qm_vport_params; 3931 3932 for (i = 0; i < p_hwfn->qm_info.num_vports; i++) { 3933 u32 wfq_speed = p_hwfn->qm_info.wfq_data[i].min_speed; 3934 3935 vport_params[i].vport_wfq = (wfq_speed * ECORE_WFQ_UNIT) / 3936 min_pf_rate; 3937 ecore_init_vport_wfq(p_hwfn, p_ptt, 3938 vport_params[i].first_tx_pq_id, 3939 vport_params[i].vport_wfq); 3940 } 3941 } 3942 3943 static void 3944 ecore_init_wfq_default_param(struct ecore_hwfn *p_hwfn, u32 min_pf_rate) 3945 { 3946 int i; 3947 3948 for (i = 0; i < p_hwfn->qm_info.num_vports; i++) 3949 p_hwfn->qm_info.qm_vport_params[i].vport_wfq = 1; 3950 } 3951 3952 static void ecore_disable_wfq_for_all_vports(struct ecore_hwfn *p_hwfn, 3953 struct ecore_ptt *p_ptt, 3954 u32 min_pf_rate) 3955 { 3956 struct init_qm_vport_params *vport_params; 3957 int i; 3958 3959 vport_params = p_hwfn->qm_info.qm_vport_params; 3960 3961 for (i = 0; i < p_hwfn->qm_info.num_vports; i++) { 3962 ecore_init_wfq_default_param(p_hwfn, min_pf_rate); 3963 ecore_init_vport_wfq(p_hwfn, p_ptt, 3964 vport_params[i].first_tx_pq_id, 3965 vport_params[i].vport_wfq); 3966 } 3967 } 3968 3969 /* This function performs several validations for WFQ 3970 * configuration and required min rate for a given vport 3971 * 1. req_rate must be greater than one percent of min_pf_rate. 3972 * 2. req_rate should not cause other vports [not configured for WFQ explicitly] 3973 * rates to get less than one percent of min_pf_rate. 3974 * 3. total_req_min_rate [all vports min rate sum] shouldn't exceed min_pf_rate. 3975 */ 3976 static enum _ecore_status_t ecore_init_wfq_param(struct ecore_hwfn *p_hwfn, 3977 u16 vport_id, u32 req_rate, 3978 u32 min_pf_rate) 3979 { 3980 u32 total_req_min_rate = 0, total_left_rate = 0, left_rate_per_vp = 0; 3981 int non_requested_count = 0, req_count = 0, i, num_vports; 3982 3983 num_vports = p_hwfn->qm_info.num_vports; 3984 3985 /* Accounting for the vports which are configured for WFQ explicitly */ 3986 3987 for (i = 0; i < num_vports; i++) { 3988 u32 tmp_speed; 3989 3990 if ((i != vport_id) && p_hwfn->qm_info.wfq_data[i].configured) { 3991 req_count++; 3992 tmp_speed = p_hwfn->qm_info.wfq_data[i].min_speed; 3993 total_req_min_rate += tmp_speed; 3994 } 3995 } 3996 3997 /* Include current vport data as well */ 3998 req_count++; 3999 total_req_min_rate += req_rate; 4000 non_requested_count = num_vports - req_count; 4001 4002 /* validate possible error cases */ 4003 if (req_rate > min_pf_rate) { 4004 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK, 4005 "Vport [%d] - Requested rate[%d Mbps] is greater than configured PF min rate[%d Mbps]\n", 4006 vport_id, req_rate, min_pf_rate); 4007 return ECORE_INVAL; 4008 } 4009 4010 if (req_rate < min_pf_rate / ECORE_WFQ_UNIT) { 4011 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK, 4012 "Vport [%d] - Requested rate[%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n", 4013 vport_id, req_rate, min_pf_rate); 4014 return ECORE_INVAL; 4015 } 4016 4017 /* TBD - for number of vports greater than 100 */ 4018 if (num_vports > ECORE_WFQ_UNIT) { 4019 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK, 4020 "Number of vports is greater than %d\n", 4021 ECORE_WFQ_UNIT); 4022 return ECORE_INVAL; 4023 } 4024 4025 if (total_req_min_rate > min_pf_rate) { 4026 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK, 4027 "Total requested min rate for all vports[%d Mbps] is greater than configured PF min rate[%d Mbps]\n", 4028 total_req_min_rate, min_pf_rate); 4029 return ECORE_INVAL; 4030 } 4031 4032 /* Data left for non requested vports */ 4033 total_left_rate = min_pf_rate - total_req_min_rate; 4034 left_rate_per_vp = total_left_rate / non_requested_count; 4035 4036 /* validate if non requested get < 1% of min bw */ 4037 if (left_rate_per_vp < min_pf_rate / ECORE_WFQ_UNIT) { 4038 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK, 4039 "Non WFQ configured vports rate [%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n", 4040 left_rate_per_vp, min_pf_rate); 4041 return ECORE_INVAL; 4042 } 4043 4044 /* now req_rate for given vport passes all scenarios. 4045 * assign final wfq rates to all vports. 4046 */ 4047 p_hwfn->qm_info.wfq_data[vport_id].min_speed = req_rate; 4048 p_hwfn->qm_info.wfq_data[vport_id].configured = true; 4049 4050 for (i = 0; i < num_vports; i++) { 4051 if (p_hwfn->qm_info.wfq_data[i].configured) 4052 continue; 4053 4054 p_hwfn->qm_info.wfq_data[i].min_speed = left_rate_per_vp; 4055 } 4056 4057 return ECORE_SUCCESS; 4058 } 4059 4060 static int __ecore_configure_vport_wfq(struct ecore_hwfn *p_hwfn, 4061 struct ecore_ptt *p_ptt, 4062 u16 vp_id, u32 rate) 4063 { 4064 struct ecore_mcp_link_state *p_link; 4065 int rc = ECORE_SUCCESS; 4066 4067 p_link = &p_hwfn->p_dev->hwfns[0].mcp_info->link_output; 4068 4069 if (!p_link->min_pf_rate) { 4070 p_hwfn->qm_info.wfq_data[vp_id].min_speed = rate; 4071 p_hwfn->qm_info.wfq_data[vp_id].configured = true; 4072 return rc; 4073 } 4074 4075 rc = ecore_init_wfq_param(p_hwfn, vp_id, rate, p_link->min_pf_rate); 4076 4077 if (rc == ECORE_SUCCESS) 4078 ecore_configure_wfq_for_all_vports(p_hwfn, p_ptt, 4079 p_link->min_pf_rate); 4080 else 4081 DP_NOTICE(p_hwfn, false, 4082 "Validation failed while configuring min rate\n"); 4083 4084 return rc; 4085 } 4086 4087 static int __ecore_configure_vp_wfq_on_link_change(struct ecore_hwfn *p_hwfn, 4088 struct ecore_ptt *p_ptt, 4089 u32 min_pf_rate) 4090 { 4091 bool use_wfq = false; 4092 int rc = ECORE_SUCCESS; 4093 u16 i; 4094 4095 /* Validate all pre configured vports for wfq */ 4096 for (i = 0; i < p_hwfn->qm_info.num_vports; i++) { 4097 u32 rate; 4098 4099 if (!p_hwfn->qm_info.wfq_data[i].configured) 4100 continue; 4101 4102 rate = p_hwfn->qm_info.wfq_data[i].min_speed; 4103 use_wfq = true; 4104 4105 rc = ecore_init_wfq_param(p_hwfn, i, rate, min_pf_rate); 4106 if (rc != ECORE_SUCCESS) { 4107 DP_NOTICE(p_hwfn, false, 4108 "WFQ validation failed while configuring min rate\n"); 4109 break; 4110 } 4111 } 4112 4113 if (rc == ECORE_SUCCESS && use_wfq) 4114 ecore_configure_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate); 4115 else 4116 ecore_disable_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate); 4117 4118 return rc; 4119 } 4120 4121 /* Main API for ecore clients to configure vport min rate. 4122 * vp_id - vport id in PF Range[0 - (total_num_vports_per_pf - 1)] 4123 * rate - Speed in Mbps needs to be assigned to a given vport. 4124 */ 4125 int ecore_configure_vport_wfq(struct ecore_dev *p_dev, u16 vp_id, u32 rate) 4126 { 4127 int i, rc = ECORE_INVAL; 4128 4129 /* TBD - for multiple hardware functions - that is 100 gig */ 4130 if (p_dev->num_hwfns > 1) { 4131 DP_NOTICE(p_dev, false, 4132 "WFQ configuration is not supported for this device\n"); 4133 return rc; 4134 } 4135 4136 for_each_hwfn(p_dev, i) { 4137 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i]; 4138 struct ecore_ptt *p_ptt; 4139 4140 p_ptt = ecore_ptt_acquire(p_hwfn); 4141 if (!p_ptt) 4142 return ECORE_TIMEOUT; 4143 4144 rc = __ecore_configure_vport_wfq(p_hwfn, p_ptt, vp_id, rate); 4145 4146 if (rc != ECORE_SUCCESS) { 4147 ecore_ptt_release(p_hwfn, p_ptt); 4148 return rc; 4149 } 4150 4151 ecore_ptt_release(p_hwfn, p_ptt); 4152 } 4153 4154 return rc; 4155 } 4156 4157 /* API to configure WFQ from mcp link change */ 4158 void ecore_configure_vp_wfq_on_link_change(struct ecore_dev *p_dev, 4159 u32 min_pf_rate) 4160 { 4161 int i; 4162 4163 /* TBD - for multiple hardware functions - that is 100 gig */ 4164 if (p_dev->num_hwfns > 1) { 4165 DP_VERBOSE(p_dev, ECORE_MSG_LINK, 4166 "WFQ configuration is not supported for this device\n"); 4167 return; 4168 } 4169 4170 for_each_hwfn(p_dev, i) { 4171 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i]; 4172 4173 __ecore_configure_vp_wfq_on_link_change(p_hwfn, 4174 p_hwfn->p_dpc_ptt, 4175 min_pf_rate); 4176 } 4177 } 4178 4179 int __ecore_configure_pf_max_bandwidth(struct ecore_hwfn *p_hwfn, 4180 struct ecore_ptt *p_ptt, 4181 struct ecore_mcp_link_state *p_link, 4182 u8 max_bw) 4183 { 4184 int rc = ECORE_SUCCESS; 4185 4186 p_hwfn->mcp_info->func_info.bandwidth_max = max_bw; 4187 4188 if (!p_link->line_speed && (max_bw != 100)) 4189 return rc; 4190 4191 p_link->speed = (p_link->line_speed * max_bw) / 100; 4192 p_hwfn->qm_info.pf_rl = p_link->speed; 4193 4194 /* Since the limiter also affects Tx-switched traffic, we don't want it 4195 * to limit such traffic in case there's no actual limit. 4196 * In that case, set limit to imaginary high boundary. 4197 */ 4198 if (max_bw == 100) 4199 p_hwfn->qm_info.pf_rl = 100000; 4200 4201 rc = ecore_init_pf_rl(p_hwfn, p_ptt, p_hwfn->rel_pf_id, 4202 p_hwfn->qm_info.pf_rl); 4203 4204 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK, 4205 "Configured MAX bandwidth to be %08x Mb/sec\n", 4206 p_link->speed); 4207 4208 return rc; 4209 } 4210 4211 /* Main API to configure PF max bandwidth where bw range is [1 - 100] */ 4212 int ecore_configure_pf_max_bandwidth(struct ecore_dev *p_dev, u8 max_bw) 4213 { 4214 int i, rc = ECORE_INVAL; 4215 4216 if (max_bw < 1 || max_bw > 100) { 4217 DP_NOTICE(p_dev, false, "PF max bw valid range is [1-100]\n"); 4218 return rc; 4219 } 4220 4221 for_each_hwfn(p_dev, i) { 4222 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i]; 4223 struct ecore_hwfn *p_lead = ECORE_LEADING_HWFN(p_dev); 4224 struct ecore_mcp_link_state *p_link; 4225 struct ecore_ptt *p_ptt; 4226 4227 p_link = &p_lead->mcp_info->link_output; 4228 4229 p_ptt = ecore_ptt_acquire(p_hwfn); 4230 if (!p_ptt) 4231 return ECORE_TIMEOUT; 4232 4233 rc = __ecore_configure_pf_max_bandwidth(p_hwfn, p_ptt, 4234 p_link, max_bw); 4235 4236 ecore_ptt_release(p_hwfn, p_ptt); 4237 4238 if (rc != ECORE_SUCCESS) 4239 break; 4240 } 4241 4242 return rc; 4243 } 4244 4245 int __ecore_configure_pf_min_bandwidth(struct ecore_hwfn *p_hwfn, 4246 struct ecore_ptt *p_ptt, 4247 struct ecore_mcp_link_state *p_link, 4248 u8 min_bw) 4249 { 4250 int rc = ECORE_SUCCESS; 4251 4252 p_hwfn->mcp_info->func_info.bandwidth_min = min_bw; 4253 p_hwfn->qm_info.pf_wfq = min_bw; 4254 4255 if (!p_link->line_speed) 4256 return rc; 4257 4258 p_link->min_pf_rate = (p_link->line_speed * min_bw) / 100; 4259 4260 rc = ecore_init_pf_wfq(p_hwfn, p_ptt, p_hwfn->rel_pf_id, min_bw); 4261 4262 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK, 4263 "Configured MIN bandwidth to be %d Mb/sec\n", 4264 p_link->min_pf_rate); 4265 4266 return rc; 4267 } 4268 4269 /* Main API to configure PF min bandwidth where bw range is [1-100] */ 4270 int ecore_configure_pf_min_bandwidth(struct ecore_dev *p_dev, u8 min_bw) 4271 { 4272 int i, rc = ECORE_INVAL; 4273 4274 if (min_bw < 1 || min_bw > 100) { 4275 DP_NOTICE(p_dev, false, "PF min bw valid range is [1-100]\n"); 4276 return rc; 4277 } 4278 4279 for_each_hwfn(p_dev, i) { 4280 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i]; 4281 struct ecore_hwfn *p_lead = ECORE_LEADING_HWFN(p_dev); 4282 struct ecore_mcp_link_state *p_link; 4283 struct ecore_ptt *p_ptt; 4284 4285 p_link = &p_lead->mcp_info->link_output; 4286 4287 p_ptt = ecore_ptt_acquire(p_hwfn); 4288 if (!p_ptt) 4289 return ECORE_TIMEOUT; 4290 4291 rc = __ecore_configure_pf_min_bandwidth(p_hwfn, p_ptt, 4292 p_link, min_bw); 4293 if (rc != ECORE_SUCCESS) { 4294 ecore_ptt_release(p_hwfn, p_ptt); 4295 return rc; 4296 } 4297 4298 if (p_link->min_pf_rate) { 4299 u32 min_rate = p_link->min_pf_rate; 4300 4301 rc = __ecore_configure_vp_wfq_on_link_change(p_hwfn, 4302 p_ptt, 4303 min_rate); 4304 } 4305 4306 ecore_ptt_release(p_hwfn, p_ptt); 4307 } 4308 4309 return rc; 4310 } 4311 4312 void ecore_clean_wfq_db(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt) 4313 { 4314 struct ecore_mcp_link_state *p_link; 4315 4316 p_link = &p_hwfn->mcp_info->link_output; 4317 4318 if (p_link->min_pf_rate) 4319 ecore_disable_wfq_for_all_vports(p_hwfn, p_ptt, 4320 p_link->min_pf_rate); 4321 4322 OSAL_MEMSET(p_hwfn->qm_info.wfq_data, 0, 4323 sizeof(*p_hwfn->qm_info.wfq_data) * 4324 p_hwfn->qm_info.num_vports); 4325 } 4326 4327 int ecore_device_num_engines(struct ecore_dev *p_dev) 4328 { 4329 return ECORE_IS_BB(p_dev) ? 2 : 1; 4330 } 4331 4332 int ecore_device_num_ports(struct ecore_dev *p_dev) 4333 { 4334 /* in CMT always only one port */ 4335 if (p_dev->num_hwfns > 1) 4336 return 1; 4337 4338 return p_dev->num_ports_in_engines * ecore_device_num_engines(p_dev); 4339 } 4340 4341 void ecore_set_fw_mac_addr(__le16 *fw_msb, 4342 __le16 *fw_mid, 4343 __le16 *fw_lsb, 4344 u8 *mac) 4345 { 4346 ((u8 *)fw_msb)[0] = mac[1]; 4347 ((u8 *)fw_msb)[1] = mac[0]; 4348 ((u8 *)fw_mid)[0] = mac[3]; 4349 ((u8 *)fw_mid)[1] = mac[2]; 4350 ((u8 *)fw_lsb)[0] = mac[5]; 4351 ((u8 *)fw_lsb)[1] = mac[4]; 4352 } 4353