1 /* 2 * Copyright (c) 2016 - 2018 Cavium Inc. 3 * All rights reserved. 4 * www.cavium.com 5 * 6 * See LICENSE.qede_pmd for copyright and licensing details. 7 */ 8 9 #ifndef __COMMON_HSI__ 10 #define __COMMON_HSI__ 11 /********************************/ 12 /* PROTOCOL COMMON FW CONSTANTS */ 13 /********************************/ 14 15 /* Temporarily here should be added to HSI automatically by resource allocation 16 * tool. 17 */ 18 #define T_TEST_AGG_INT_TEMP 6 19 #define M_TEST_AGG_INT_TEMP 8 20 #define U_TEST_AGG_INT_TEMP 6 21 #define X_TEST_AGG_INT_TEMP 14 22 #define Y_TEST_AGG_INT_TEMP 4 23 #define P_TEST_AGG_INT_TEMP 4 24 25 #define X_FINAL_CLEANUP_AGG_INT 1 26 27 #define EVENT_RING_PAGE_SIZE_BYTES 4096 28 29 #define NUM_OF_GLOBAL_QUEUES 128 30 #define COMMON_QUEUE_ENTRY_MAX_BYTE_SIZE 64 31 32 #define ISCSI_CDU_TASK_SEG_TYPE 0 33 #define FCOE_CDU_TASK_SEG_TYPE 0 34 #define RDMA_CDU_TASK_SEG_TYPE 1 35 36 #define FW_ASSERT_GENERAL_ATTN_IDX 32 37 38 #define MAX_PINNED_CCFC 32 39 40 #define EAGLE_ENG1_WORKAROUND_NIG_FLOWCTRL_MODE 3 41 42 /* Queue Zone sizes in bytes */ 43 #define TSTORM_QZONE_SIZE 8 /*tstorm_scsi_queue_zone*/ 44 #define MSTORM_QZONE_SIZE 16 /*mstorm_eth_queue_zone. Used only for RX 45 *producer of VFs in backward compatibility 46 *mode. 47 */ 48 #define USTORM_QZONE_SIZE 8 /*ustorm_eth_queue_zone*/ 49 #define XSTORM_QZONE_SIZE 8 /*xstorm_eth_queue_zone*/ 50 #define YSTORM_QZONE_SIZE 0 51 #define PSTORM_QZONE_SIZE 0 52 53 /*Log of mstorm default VF zone size.*/ 54 #define MSTORM_VF_ZONE_DEFAULT_SIZE_LOG 7 55 /*Maximum number of RX queues that can be allocated to VF by default*/ 56 #define ETH_MAX_NUM_RX_QUEUES_PER_VF_DEFAULT 16 57 /*Maximum number of RX queues that can be allocated to VF with doubled VF zone 58 * size. Up to 96 VF supported in this mode 59 */ 60 #define ETH_MAX_NUM_RX_QUEUES_PER_VF_DOUBLE 48 61 /*Maximum number of RX queues that can be allocated to VF with 4 VF zone size. 62 * Up to 48 VF supported in this mode 63 */ 64 #define ETH_MAX_NUM_RX_QUEUES_PER_VF_QUAD 112 65 66 67 /********************************/ 68 /* CORE (LIGHT L2) FW CONSTANTS */ 69 /********************************/ 70 71 #define CORE_LL2_MAX_RAMROD_PER_CON 8 72 #define CORE_LL2_TX_BD_PAGE_SIZE_BYTES 4096 73 #define CORE_LL2_RX_BD_PAGE_SIZE_BYTES 4096 74 #define CORE_LL2_RX_CQE_PAGE_SIZE_BYTES 4096 75 #define CORE_LL2_RX_NUM_NEXT_PAGE_BDS 1 76 77 #define CORE_LL2_TX_MAX_BDS_PER_PACKET 12 78 79 #define CORE_SPQE_PAGE_SIZE_BYTES 4096 80 81 /* 82 * Usually LL2 queues are opened in pairs TX-RX. 83 * There is a hard restriction on number of RX queues (limited by Tstorm RAM) 84 * and TX counters (Pstorm RAM). 85 * Number of TX queues is almost unlimited. 86 * The constants are different so as to allow asymmetric LL2 connections 87 */ 88 89 #define MAX_NUM_LL2_RX_QUEUES 48 90 #define MAX_NUM_LL2_TX_STATS_COUNTERS 48 91 92 93 /****************************************************************************/ 94 /* Include firmware version number only- do not add constants here to avoid */ 95 /* redundunt compilations */ 96 /****************************************************************************/ 97 98 99 #define FW_MAJOR_VERSION 8 100 #define FW_MINOR_VERSION 33 101 #define FW_REVISION_VERSION 12 102 #define FW_ENGINEERING_VERSION 0 103 104 /***********************/ 105 /* COMMON HW CONSTANTS */ 106 /***********************/ 107 108 /* PCI functions */ 109 #define MAX_NUM_PORTS_BB (2) 110 #define MAX_NUM_PORTS_K2 (4) 111 #define MAX_NUM_PORTS_E5 (4) 112 #define MAX_NUM_PORTS (MAX_NUM_PORTS_E5) 113 114 #define MAX_NUM_PFS_BB (8) 115 #define MAX_NUM_PFS_K2 (16) 116 #define MAX_NUM_PFS_E5 (16) 117 #define MAX_NUM_PFS (MAX_NUM_PFS_E5) 118 #define MAX_NUM_OF_PFS_IN_CHIP (16) /* On both engines */ 119 120 #define MAX_NUM_VFS_BB (120) 121 #define MAX_NUM_VFS_K2 (192) 122 #define MAX_NUM_VFS_E4 (MAX_NUM_VFS_K2) 123 #define MAX_NUM_VFS_E5 (240) 124 #define COMMON_MAX_NUM_VFS (MAX_NUM_VFS_E5) 125 126 #define MAX_NUM_FUNCTIONS_BB (MAX_NUM_PFS_BB + MAX_NUM_VFS_BB) 127 #define MAX_NUM_FUNCTIONS_K2 (MAX_NUM_PFS_K2 + MAX_NUM_VFS_K2) 128 #define MAX_NUM_FUNCTIONS (MAX_NUM_PFS + MAX_NUM_VFS_E4) 129 130 /* in both BB and K2, the VF number starts from 16. so for arrays containing all 131 * possible PFs and VFs - we need a constant for this size 132 */ 133 #define MAX_FUNCTION_NUMBER_BB (MAX_NUM_PFS + MAX_NUM_VFS_BB) 134 #define MAX_FUNCTION_NUMBER_K2 (MAX_NUM_PFS + MAX_NUM_VFS_K2) 135 #define MAX_FUNCTION_NUMBER_E4 (MAX_NUM_PFS + MAX_NUM_VFS_E4) 136 #define MAX_FUNCTION_NUMBER_E5 (MAX_NUM_PFS + MAX_NUM_VFS_E5) 137 #define COMMON_MAX_FUNCTION_NUMBER (MAX_NUM_PFS + MAX_NUM_VFS_E5) 138 139 #define MAX_NUM_VPORTS_K2 (208) 140 #define MAX_NUM_VPORTS_BB (160) 141 #define MAX_NUM_VPORTS_E4 (MAX_NUM_VPORTS_K2) 142 #define MAX_NUM_VPORTS_E5 (256) 143 #define COMMON_MAX_NUM_VPORTS (MAX_NUM_VPORTS_E5) 144 145 #define MAX_NUM_L2_QUEUES_BB (256) 146 #define MAX_NUM_L2_QUEUES_K2 (320) 147 #define MAX_NUM_L2_QUEUES_E5 (320) /* TODO_E5_VITALY - fix to 512 */ 148 #define MAX_NUM_L2_QUEUES (MAX_NUM_L2_QUEUES_E5) 149 150 /* Traffic classes in network-facing blocks (PBF, BTB, NIG, BRB, PRS and QM) */ 151 #define NUM_PHYS_TCS_4PORT_K2 4 152 #define NUM_PHYS_TCS_4PORT_TX_E5 6 153 #define NUM_PHYS_TCS_4PORT_RX_E5 4 154 #define NUM_OF_PHYS_TCS 8 155 #define PURE_LB_TC NUM_OF_PHYS_TCS 156 #define NUM_TCS_4PORT_K2 (NUM_PHYS_TCS_4PORT_K2 + 1) 157 #define NUM_TCS_4PORT_TX_E5 (NUM_PHYS_TCS_4PORT_TX_E5 + 1) 158 #define NUM_TCS_4PORT_RX_E5 (NUM_PHYS_TCS_4PORT_RX_E5 + 1) 159 #define NUM_OF_TCS (NUM_OF_PHYS_TCS + 1) 160 161 /* CIDs */ 162 #define NUM_OF_CONNECTION_TYPES_E4 (8) 163 #define NUM_OF_CONNECTION_TYPES_E5 (16) 164 #define NUM_OF_TASK_TYPES (8) 165 #define NUM_OF_LCIDS (320) 166 #define NUM_OF_LTIDS (320) 167 168 /* Global PXP windows (GTT) */ 169 #define NUM_OF_GTT 19 170 #define GTT_DWORD_SIZE_BITS 10 171 #define GTT_BYTE_SIZE_BITS (GTT_DWORD_SIZE_BITS + 2) 172 #define GTT_DWORD_SIZE (1 << GTT_DWORD_SIZE_BITS) 173 174 /* Tools Version */ 175 #define TOOLS_VERSION 10 176 /*****************/ 177 /* CDU CONSTANTS */ 178 /*****************/ 179 180 #define CDU_SEG_TYPE_OFFSET_REG_TYPE_SHIFT (17) 181 #define CDU_SEG_TYPE_OFFSET_REG_OFFSET_MASK (0x1ffff) 182 183 #define CDU_VF_FL_SEG_TYPE_OFFSET_REG_TYPE_SHIFT (12) 184 #define CDU_VF_FL_SEG_TYPE_OFFSET_REG_OFFSET_MASK (0xfff) 185 186 #define CDU_CONTEXT_VALIDATION_CFG_ENABLE_SHIFT (0) 187 #define CDU_CONTEXT_VALIDATION_CFG_VALIDATION_TYPE_SHIFT (1) 188 #define CDU_CONTEXT_VALIDATION_CFG_USE_TYPE (2) 189 #define CDU_CONTEXT_VALIDATION_CFG_USE_REGION (3) 190 #define CDU_CONTEXT_VALIDATION_CFG_USE_CID (4) 191 #define CDU_CONTEXT_VALIDATION_CFG_USE_ACTIVE (5) 192 193 194 /*****************/ 195 /* DQ CONSTANTS */ 196 /*****************/ 197 198 /* DEMS */ 199 #define DQ_DEMS_LEGACY 0 200 #define DQ_DEMS_TOE_MORE_TO_SEND 3 201 #define DQ_DEMS_TOE_LOCAL_ADV_WND 4 202 #define DQ_DEMS_ROCE_CQ_CONS 7 203 204 /* XCM agg val selection (HW) */ 205 #define DQ_XCM_AGG_VAL_SEL_WORD2 0 206 #define DQ_XCM_AGG_VAL_SEL_WORD3 1 207 #define DQ_XCM_AGG_VAL_SEL_WORD4 2 208 #define DQ_XCM_AGG_VAL_SEL_WORD5 3 209 #define DQ_XCM_AGG_VAL_SEL_REG3 4 210 #define DQ_XCM_AGG_VAL_SEL_REG4 5 211 #define DQ_XCM_AGG_VAL_SEL_REG5 6 212 #define DQ_XCM_AGG_VAL_SEL_REG6 7 213 214 /* XCM agg val selection (FW) */ 215 #define DQ_XCM_ETH_EDPM_NUM_BDS_CMD \ 216 DQ_XCM_AGG_VAL_SEL_WORD2 217 #define DQ_XCM_ETH_TX_BD_CONS_CMD \ 218 DQ_XCM_AGG_VAL_SEL_WORD3 219 #define DQ_XCM_CORE_TX_BD_CONS_CMD \ 220 DQ_XCM_AGG_VAL_SEL_WORD3 221 #define DQ_XCM_ETH_TX_BD_PROD_CMD \ 222 DQ_XCM_AGG_VAL_SEL_WORD4 223 #define DQ_XCM_CORE_TX_BD_PROD_CMD \ 224 DQ_XCM_AGG_VAL_SEL_WORD4 225 #define DQ_XCM_CORE_SPQ_PROD_CMD \ 226 DQ_XCM_AGG_VAL_SEL_WORD4 227 #define DQ_XCM_ETH_GO_TO_BD_CONS_CMD DQ_XCM_AGG_VAL_SEL_WORD5 228 #define DQ_XCM_FCOE_SQ_CONS_CMD DQ_XCM_AGG_VAL_SEL_WORD3 229 #define DQ_XCM_FCOE_SQ_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD4 230 #define DQ_XCM_FCOE_X_FERQ_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD5 231 #define DQ_XCM_ISCSI_SQ_CONS_CMD DQ_XCM_AGG_VAL_SEL_WORD3 232 #define DQ_XCM_ISCSI_SQ_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD4 233 #define DQ_XCM_ISCSI_MORE_TO_SEND_SEQ_CMD DQ_XCM_AGG_VAL_SEL_REG3 234 #define DQ_XCM_ISCSI_EXP_STAT_SN_CMD DQ_XCM_AGG_VAL_SEL_REG6 235 #define DQ_XCM_ROCE_SQ_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD4 236 #define DQ_XCM_TOE_TX_BD_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD4 237 #define DQ_XCM_TOE_MORE_TO_SEND_SEQ_CMD DQ_XCM_AGG_VAL_SEL_REG3 238 #define DQ_XCM_TOE_LOCAL_ADV_WND_SEQ_CMD DQ_XCM_AGG_VAL_SEL_REG4 239 240 /* UCM agg val selection (HW) */ 241 #define DQ_UCM_AGG_VAL_SEL_WORD0 0 242 #define DQ_UCM_AGG_VAL_SEL_WORD1 1 243 #define DQ_UCM_AGG_VAL_SEL_WORD2 2 244 #define DQ_UCM_AGG_VAL_SEL_WORD3 3 245 #define DQ_UCM_AGG_VAL_SEL_REG0 4 246 #define DQ_UCM_AGG_VAL_SEL_REG1 5 247 #define DQ_UCM_AGG_VAL_SEL_REG2 6 248 #define DQ_UCM_AGG_VAL_SEL_REG3 7 249 250 /* UCM agg val selection (FW) */ 251 #define DQ_UCM_ETH_PMD_TX_CONS_CMD DQ_UCM_AGG_VAL_SEL_WORD2 252 #define DQ_UCM_ETH_PMD_RX_CONS_CMD DQ_UCM_AGG_VAL_SEL_WORD3 253 #define DQ_UCM_ROCE_CQ_CONS_CMD DQ_UCM_AGG_VAL_SEL_REG0 254 #define DQ_UCM_ROCE_CQ_PROD_CMD DQ_UCM_AGG_VAL_SEL_REG2 255 256 /* TCM agg val selection (HW) */ 257 #define DQ_TCM_AGG_VAL_SEL_WORD0 0 258 #define DQ_TCM_AGG_VAL_SEL_WORD1 1 259 #define DQ_TCM_AGG_VAL_SEL_WORD2 2 260 #define DQ_TCM_AGG_VAL_SEL_WORD3 3 261 #define DQ_TCM_AGG_VAL_SEL_REG1 4 262 #define DQ_TCM_AGG_VAL_SEL_REG2 5 263 #define DQ_TCM_AGG_VAL_SEL_REG6 6 264 #define DQ_TCM_AGG_VAL_SEL_REG9 7 265 266 /* TCM agg val selection (FW) */ 267 #define DQ_TCM_L2B_BD_PROD_CMD DQ_TCM_AGG_VAL_SEL_WORD1 268 #define DQ_TCM_ROCE_RQ_PROD_CMD DQ_TCM_AGG_VAL_SEL_WORD0 269 270 /* XCM agg counter flag selection (HW) */ 271 #define DQ_XCM_AGG_FLG_SHIFT_BIT14 0 272 #define DQ_XCM_AGG_FLG_SHIFT_BIT15 1 273 #define DQ_XCM_AGG_FLG_SHIFT_CF12 2 274 #define DQ_XCM_AGG_FLG_SHIFT_CF13 3 275 #define DQ_XCM_AGG_FLG_SHIFT_CF18 4 276 #define DQ_XCM_AGG_FLG_SHIFT_CF19 5 277 #define DQ_XCM_AGG_FLG_SHIFT_CF22 6 278 #define DQ_XCM_AGG_FLG_SHIFT_CF23 7 279 280 /* XCM agg counter flag selection (FW) */ 281 #define DQ_XCM_ETH_DQ_CF_CMD (1 << \ 282 DQ_XCM_AGG_FLG_SHIFT_CF18) 283 #define DQ_XCM_CORE_DQ_CF_CMD (1 << \ 284 DQ_XCM_AGG_FLG_SHIFT_CF18) 285 #define DQ_XCM_ETH_TERMINATE_CMD (1 << \ 286 DQ_XCM_AGG_FLG_SHIFT_CF19) 287 #define DQ_XCM_CORE_TERMINATE_CMD (1 << \ 288 DQ_XCM_AGG_FLG_SHIFT_CF19) 289 #define DQ_XCM_ETH_SLOW_PATH_CMD (1 << \ 290 DQ_XCM_AGG_FLG_SHIFT_CF22) 291 #define DQ_XCM_CORE_SLOW_PATH_CMD (1 << \ 292 DQ_XCM_AGG_FLG_SHIFT_CF22) 293 #define DQ_XCM_ETH_TPH_EN_CMD (1 << \ 294 DQ_XCM_AGG_FLG_SHIFT_CF23) 295 #define DQ_XCM_FCOE_SLOW_PATH_CMD (1 << DQ_XCM_AGG_FLG_SHIFT_CF22) 296 #define DQ_XCM_ISCSI_DQ_FLUSH_CMD (1 << DQ_XCM_AGG_FLG_SHIFT_CF19) 297 #define DQ_XCM_ISCSI_SLOW_PATH_CMD (1 << DQ_XCM_AGG_FLG_SHIFT_CF22) 298 #define DQ_XCM_ISCSI_PROC_ONLY_CLEANUP_CMD (1 << DQ_XCM_AGG_FLG_SHIFT_CF23) 299 #define DQ_XCM_TOE_DQ_FLUSH_CMD (1 << DQ_XCM_AGG_FLG_SHIFT_CF19) 300 #define DQ_XCM_TOE_SLOW_PATH_CMD (1 << DQ_XCM_AGG_FLG_SHIFT_CF22) 301 302 /* UCM agg counter flag selection (HW) */ 303 #define DQ_UCM_AGG_FLG_SHIFT_CF0 0 304 #define DQ_UCM_AGG_FLG_SHIFT_CF1 1 305 #define DQ_UCM_AGG_FLG_SHIFT_CF3 2 306 #define DQ_UCM_AGG_FLG_SHIFT_CF4 3 307 #define DQ_UCM_AGG_FLG_SHIFT_CF5 4 308 #define DQ_UCM_AGG_FLG_SHIFT_CF6 5 309 #define DQ_UCM_AGG_FLG_SHIFT_RULE0EN 6 310 #define DQ_UCM_AGG_FLG_SHIFT_RULE1EN 7 311 312 /* UCM agg counter flag selection (FW) */ 313 #define DQ_UCM_ETH_PMD_TX_ARM_CMD (1 << DQ_UCM_AGG_FLG_SHIFT_CF4) 314 #define DQ_UCM_ETH_PMD_RX_ARM_CMD (1 << DQ_UCM_AGG_FLG_SHIFT_CF5) 315 #define DQ_UCM_ROCE_CQ_ARM_SE_CF_CMD (1 << DQ_UCM_AGG_FLG_SHIFT_CF4) 316 #define DQ_UCM_ROCE_CQ_ARM_CF_CMD (1 << DQ_UCM_AGG_FLG_SHIFT_CF5) 317 #define DQ_UCM_TOE_TIMER_STOP_ALL_CMD (1 << DQ_UCM_AGG_FLG_SHIFT_CF3) 318 #define DQ_UCM_TOE_SLOW_PATH_CF_CMD (1 << DQ_UCM_AGG_FLG_SHIFT_CF4) 319 #define DQ_UCM_TOE_DQ_CF_CMD (1 << DQ_UCM_AGG_FLG_SHIFT_CF5) 320 321 /* TCM agg counter flag selection (HW) */ 322 #define DQ_TCM_AGG_FLG_SHIFT_CF0 0 323 #define DQ_TCM_AGG_FLG_SHIFT_CF1 1 324 #define DQ_TCM_AGG_FLG_SHIFT_CF2 2 325 #define DQ_TCM_AGG_FLG_SHIFT_CF3 3 326 #define DQ_TCM_AGG_FLG_SHIFT_CF4 4 327 #define DQ_TCM_AGG_FLG_SHIFT_CF5 5 328 #define DQ_TCM_AGG_FLG_SHIFT_CF6 6 329 #define DQ_TCM_AGG_FLG_SHIFT_CF7 7 330 331 /* TCM agg counter flag selection (FW) */ 332 #define DQ_TCM_FCOE_FLUSH_Q0_CMD (1 << DQ_TCM_AGG_FLG_SHIFT_CF1) 333 #define DQ_TCM_FCOE_DUMMY_TIMER_CMD (1 << DQ_TCM_AGG_FLG_SHIFT_CF2) 334 #define DQ_TCM_FCOE_TIMER_STOP_ALL_CMD (1 << DQ_TCM_AGG_FLG_SHIFT_CF3) 335 #define DQ_TCM_ISCSI_FLUSH_Q0_CMD (1 << DQ_TCM_AGG_FLG_SHIFT_CF1) 336 #define DQ_TCM_ISCSI_TIMER_STOP_ALL_CMD (1 << DQ_TCM_AGG_FLG_SHIFT_CF3) 337 #define DQ_TCM_TOE_FLUSH_Q0_CMD (1 << DQ_TCM_AGG_FLG_SHIFT_CF1) 338 #define DQ_TCM_TOE_TIMER_STOP_ALL_CMD (1 << DQ_TCM_AGG_FLG_SHIFT_CF3) 339 #define DQ_TCM_IWARP_POST_RQ_CF_CMD (1 << DQ_TCM_AGG_FLG_SHIFT_CF1) 340 341 /* PWM address mapping */ 342 #define DQ_PWM_OFFSET_DPM_BASE 0x0 343 #define DQ_PWM_OFFSET_DPM_END 0x27 344 #define DQ_PWM_OFFSET_XCM16_BASE 0x40 345 #define DQ_PWM_OFFSET_XCM32_BASE 0x44 346 #define DQ_PWM_OFFSET_UCM16_BASE 0x48 347 #define DQ_PWM_OFFSET_UCM32_BASE 0x4C 348 #define DQ_PWM_OFFSET_UCM16_4 0x50 349 #define DQ_PWM_OFFSET_TCM16_BASE 0x58 350 #define DQ_PWM_OFFSET_TCM32_BASE 0x5C 351 #define DQ_PWM_OFFSET_XCM_FLAGS 0x68 352 #define DQ_PWM_OFFSET_UCM_FLAGS 0x69 353 #define DQ_PWM_OFFSET_TCM_FLAGS 0x6B 354 355 #define DQ_PWM_OFFSET_XCM_RDMA_SQ_PROD (DQ_PWM_OFFSET_XCM16_BASE + 2) 356 #define DQ_PWM_OFFSET_UCM_RDMA_CQ_CONS_32BIT (DQ_PWM_OFFSET_UCM32_BASE) 357 #define DQ_PWM_OFFSET_UCM_RDMA_CQ_CONS_16BIT (DQ_PWM_OFFSET_UCM16_4) 358 #define DQ_PWM_OFFSET_UCM_RDMA_INT_TIMEOUT (DQ_PWM_OFFSET_UCM16_BASE + 2) 359 #define DQ_PWM_OFFSET_UCM_RDMA_ARM_FLAGS (DQ_PWM_OFFSET_UCM_FLAGS) 360 #define DQ_PWM_OFFSET_TCM_ROCE_RQ_PROD (DQ_PWM_OFFSET_TCM16_BASE + 1) 361 #define DQ_PWM_OFFSET_TCM_IWARP_RQ_PROD (DQ_PWM_OFFSET_TCM16_BASE + 3) 362 363 #define DQ_REGION_SHIFT (12) 364 365 /* DPM */ 366 #define DQ_DPM_WQE_BUFF_SIZE (320) 367 368 /* Conn type ranges */ 369 #define DQ_CONN_TYPE_RANGE_SHIFT (4) 370 371 /*****************/ 372 /* QM CONSTANTS */ 373 /*****************/ 374 375 /* number of TX queues in the QM */ 376 #define MAX_QM_TX_QUEUES_K2 512 377 #define MAX_QM_TX_QUEUES_BB 448 378 #define MAX_QM_TX_QUEUES MAX_QM_TX_QUEUES_K2 379 380 /* number of Other queues in the QM */ 381 #define MAX_QM_OTHER_QUEUES_BB 64 382 #define MAX_QM_OTHER_QUEUES_K2 128 383 #define MAX_QM_OTHER_QUEUES MAX_QM_OTHER_QUEUES_K2 384 385 /* number of queues in a PF queue group */ 386 #define QM_PF_QUEUE_GROUP_SIZE 8 387 388 /* the size of a single queue element in bytes */ 389 #define QM_PQ_ELEMENT_SIZE 4 390 391 /* base number of Tx PQs in the CM PQ representation. 392 * should be used when storing PQ IDs in CM PQ registers and context 393 */ 394 #define CM_TX_PQ_BASE 0x200 395 396 /* number of global Vport/QCN rate limiters */ 397 #define MAX_QM_GLOBAL_RLS 256 398 399 /* QM registers data */ 400 #define QM_LINE_CRD_REG_WIDTH 16 401 #define QM_LINE_CRD_REG_SIGN_BIT (1 << (QM_LINE_CRD_REG_WIDTH - 1)) 402 #define QM_BYTE_CRD_REG_WIDTH 24 403 #define QM_BYTE_CRD_REG_SIGN_BIT (1 << (QM_BYTE_CRD_REG_WIDTH - 1)) 404 #define QM_WFQ_CRD_REG_WIDTH 32 405 #define QM_WFQ_CRD_REG_SIGN_BIT (1 << (QM_WFQ_CRD_REG_WIDTH - 1)) 406 #define QM_RL_CRD_REG_WIDTH 32 407 #define QM_RL_CRD_REG_SIGN_BIT (1 << (QM_RL_CRD_REG_WIDTH - 1)) 408 409 /*****************/ 410 /* CAU CONSTANTS */ 411 /*****************/ 412 413 #define CAU_FSM_ETH_RX 0 414 #define CAU_FSM_ETH_TX 1 415 416 /* Number of Protocol Indices per Status Block */ 417 #define PIS_PER_SB_E4 12 418 #define PIS_PER_SB_E5 8 419 #define MAX_PIS_PER_SB_E4 OSAL_MAX_T(PIS_PER_SB_E4, PIS_PER_SB_E5) 420 421 /* fsm is stopped or not valid for this sb */ 422 #define CAU_HC_STOPPED_STATE 3 423 /* fsm is working without interrupt coalescing for this sb*/ 424 #define CAU_HC_DISABLE_STATE 4 425 /* fsm is working with interrupt coalescing for this sb*/ 426 #define CAU_HC_ENABLE_STATE 0 427 428 429 /*****************/ 430 /* IGU CONSTANTS */ 431 /*****************/ 432 433 #define MAX_SB_PER_PATH_K2 (368) 434 #define MAX_SB_PER_PATH_BB (288) 435 #define MAX_SB_PER_PATH_E5 (512) 436 #define MAX_TOT_SB_PER_PATH MAX_SB_PER_PATH_E5 437 438 #define MAX_SB_PER_PF_MIMD 129 439 #define MAX_SB_PER_PF_SIMD 64 440 #define MAX_SB_PER_VF 64 441 442 /* Memory addresses on the BAR for the IGU Sub Block */ 443 #define IGU_MEM_BASE 0x0000 444 445 #define IGU_MEM_MSIX_BASE 0x0000 446 #define IGU_MEM_MSIX_UPPER 0x0101 447 #define IGU_MEM_MSIX_RESERVED_UPPER 0x01ff 448 449 #define IGU_MEM_PBA_MSIX_BASE 0x0200 450 #define IGU_MEM_PBA_MSIX_UPPER 0x0202 451 #define IGU_MEM_PBA_MSIX_RESERVED_UPPER 0x03ff 452 453 #define IGU_CMD_INT_ACK_BASE 0x0400 454 #define IGU_CMD_INT_ACK_UPPER (IGU_CMD_INT_ACK_BASE + \ 455 MAX_TOT_SB_PER_PATH - \ 456 1) 457 #define IGU_CMD_INT_ACK_RESERVED_UPPER 0x05ff 458 459 #define IGU_CMD_ATTN_BIT_UPD_UPPER 0x05f0 460 #define IGU_CMD_ATTN_BIT_SET_UPPER 0x05f1 461 #define IGU_CMD_ATTN_BIT_CLR_UPPER 0x05f2 462 463 #define IGU_REG_SISR_MDPC_WMASK_UPPER 0x05f3 464 #define IGU_REG_SISR_MDPC_WMASK_LSB_UPPER 0x05f4 465 #define IGU_REG_SISR_MDPC_WMASK_MSB_UPPER 0x05f5 466 #define IGU_REG_SISR_MDPC_WOMASK_UPPER 0x05f6 467 468 #define IGU_CMD_PROD_UPD_BASE 0x0600 469 #define IGU_CMD_PROD_UPD_UPPER (IGU_CMD_PROD_UPD_BASE + \ 470 MAX_TOT_SB_PER_PATH - \ 471 1) 472 #define IGU_CMD_PROD_UPD_RESERVED_UPPER 0x07ff 473 474 /*****************/ 475 /* PXP CONSTANTS */ 476 /*****************/ 477 478 /* Bars for Blocks */ 479 #define PXP_BAR_GRC 0 480 #define PXP_BAR_TSDM 0 481 #define PXP_BAR_USDM 0 482 #define PXP_BAR_XSDM 0 483 #define PXP_BAR_MSDM 0 484 #define PXP_BAR_YSDM 0 485 #define PXP_BAR_PSDM 0 486 #define PXP_BAR_IGU 0 487 #define PXP_BAR_DQ 1 488 489 /* PTT and GTT */ 490 #define PXP_PER_PF_ENTRY_SIZE 8 491 #define PXP_NUM_GLOBAL_WINDOWS 243 492 #define PXP_GLOBAL_ENTRY_SIZE 4 493 #define PXP_ADMIN_WINDOW_ALLOWED_LENGTH 4 494 #define PXP_PF_WINDOW_ADMIN_START 0 495 #define PXP_PF_WINDOW_ADMIN_LENGTH 0x1000 496 #define PXP_PF_WINDOW_ADMIN_END (PXP_PF_WINDOW_ADMIN_START + \ 497 PXP_PF_WINDOW_ADMIN_LENGTH - 1) 498 #define PXP_PF_WINDOW_ADMIN_PER_PF_START 0 499 #define PXP_PF_WINDOW_ADMIN_PER_PF_LENGTH (PXP_NUM_PF_WINDOWS * \ 500 PXP_PER_PF_ENTRY_SIZE) 501 #define PXP_PF_WINDOW_ADMIN_PER_PF_END (PXP_PF_WINDOW_ADMIN_PER_PF_START + \ 502 PXP_PF_WINDOW_ADMIN_PER_PF_LENGTH - 1) 503 #define PXP_PF_WINDOW_ADMIN_GLOBAL_START 0x200 504 #define PXP_PF_WINDOW_ADMIN_GLOBAL_LENGTH (PXP_NUM_GLOBAL_WINDOWS * \ 505 PXP_GLOBAL_ENTRY_SIZE) 506 #define PXP_PF_WINDOW_ADMIN_GLOBAL_END \ 507 (PXP_PF_WINDOW_ADMIN_GLOBAL_START + \ 508 PXP_PF_WINDOW_ADMIN_GLOBAL_LENGTH - 1) 509 #define PXP_PF_GLOBAL_PRETEND_ADDR 0x1f0 510 #define PXP_PF_ME_OPAQUE_MASK_ADDR 0xf4 511 #define PXP_PF_ME_OPAQUE_ADDR 0x1f8 512 #define PXP_PF_ME_CONCRETE_ADDR 0x1fc 513 514 #define PXP_NUM_PF_WINDOWS 12 515 516 #define PXP_EXTERNAL_BAR_PF_WINDOW_START 0x1000 517 #define PXP_EXTERNAL_BAR_PF_WINDOW_NUM PXP_NUM_PF_WINDOWS 518 #define PXP_EXTERNAL_BAR_PF_WINDOW_SINGLE_SIZE 0x1000 519 #define PXP_EXTERNAL_BAR_PF_WINDOW_LENGTH \ 520 (PXP_EXTERNAL_BAR_PF_WINDOW_NUM * \ 521 PXP_EXTERNAL_BAR_PF_WINDOW_SINGLE_SIZE) 522 #define PXP_EXTERNAL_BAR_PF_WINDOW_END \ 523 (PXP_EXTERNAL_BAR_PF_WINDOW_START + \ 524 PXP_EXTERNAL_BAR_PF_WINDOW_LENGTH - 1) 525 526 #define PXP_EXTERNAL_BAR_GLOBAL_WINDOW_START \ 527 (PXP_EXTERNAL_BAR_PF_WINDOW_END + 1) 528 #define PXP_EXTERNAL_BAR_GLOBAL_WINDOW_NUM PXP_NUM_GLOBAL_WINDOWS 529 #define PXP_EXTERNAL_BAR_GLOBAL_WINDOW_SINGLE_SIZE 0x1000 530 #define PXP_EXTERNAL_BAR_GLOBAL_WINDOW_LENGTH \ 531 (PXP_EXTERNAL_BAR_GLOBAL_WINDOW_NUM * \ 532 PXP_EXTERNAL_BAR_GLOBAL_WINDOW_SINGLE_SIZE) 533 #define PXP_EXTERNAL_BAR_GLOBAL_WINDOW_END \ 534 (PXP_EXTERNAL_BAR_GLOBAL_WINDOW_START + \ 535 PXP_EXTERNAL_BAR_GLOBAL_WINDOW_LENGTH - 1) 536 537 /* PF BAR */ 538 #define PXP_BAR0_START_GRC 0x0000 539 #define PXP_BAR0_GRC_LENGTH 0x1C00000 540 #define PXP_BAR0_END_GRC \ 541 (PXP_BAR0_START_GRC + PXP_BAR0_GRC_LENGTH - 1) 542 543 #define PXP_BAR0_START_IGU 0x1C00000 544 #define PXP_BAR0_IGU_LENGTH 0x10000 545 #define PXP_BAR0_END_IGU \ 546 (PXP_BAR0_START_IGU + PXP_BAR0_IGU_LENGTH - 1) 547 548 #define PXP_BAR0_START_TSDM 0x1C80000 549 #define PXP_BAR0_SDM_LENGTH 0x40000 550 #define PXP_BAR0_SDM_RESERVED_LENGTH 0x40000 551 #define PXP_BAR0_END_TSDM \ 552 (PXP_BAR0_START_TSDM + PXP_BAR0_SDM_LENGTH - 1) 553 554 #define PXP_BAR0_START_MSDM 0x1D00000 555 #define PXP_BAR0_END_MSDM \ 556 (PXP_BAR0_START_MSDM + PXP_BAR0_SDM_LENGTH - 1) 557 558 #define PXP_BAR0_START_USDM 0x1D80000 559 #define PXP_BAR0_END_USDM \ 560 (PXP_BAR0_START_USDM + PXP_BAR0_SDM_LENGTH - 1) 561 562 #define PXP_BAR0_START_XSDM 0x1E00000 563 #define PXP_BAR0_END_XSDM \ 564 (PXP_BAR0_START_XSDM + PXP_BAR0_SDM_LENGTH - 1) 565 566 #define PXP_BAR0_START_YSDM 0x1E80000 567 #define PXP_BAR0_END_YSDM \ 568 (PXP_BAR0_START_YSDM + PXP_BAR0_SDM_LENGTH - 1) 569 570 #define PXP_BAR0_START_PSDM 0x1F00000 571 #define PXP_BAR0_END_PSDM \ 572 (PXP_BAR0_START_PSDM + PXP_BAR0_SDM_LENGTH - 1) 573 574 #define PXP_BAR0_FIRST_INVALID_ADDRESS \ 575 (PXP_BAR0_END_PSDM + 1) 576 577 /* VF BAR */ 578 #define PXP_VF_BAR0 0 579 580 #define PXP_VF_BAR0_START_IGU 0 581 #define PXP_VF_BAR0_IGU_LENGTH 0x3000 582 #define PXP_VF_BAR0_END_IGU \ 583 (PXP_VF_BAR0_START_IGU + PXP_VF_BAR0_IGU_LENGTH - 1) 584 585 #define PXP_VF_BAR0_START_DQ 0x3000 586 #define PXP_VF_BAR0_DQ_LENGTH 0x200 587 #define PXP_VF_BAR0_DQ_OPAQUE_OFFSET 0 588 #define PXP_VF_BAR0_ME_OPAQUE_ADDRESS \ 589 (PXP_VF_BAR0_START_DQ + PXP_VF_BAR0_DQ_OPAQUE_OFFSET) 590 #define PXP_VF_BAR0_ME_CONCRETE_ADDRESS \ 591 (PXP_VF_BAR0_ME_OPAQUE_ADDRESS + 4) 592 #define PXP_VF_BAR0_END_DQ \ 593 (PXP_VF_BAR0_START_DQ + PXP_VF_BAR0_DQ_LENGTH - 1) 594 595 #define PXP_VF_BAR0_START_TSDM_ZONE_B 0x3200 596 #define PXP_VF_BAR0_SDM_LENGTH_ZONE_B 0x200 597 #define PXP_VF_BAR0_END_TSDM_ZONE_B \ 598 (PXP_VF_BAR0_START_TSDM_ZONE_B + PXP_VF_BAR0_SDM_LENGTH_ZONE_B - 1) 599 600 #define PXP_VF_BAR0_START_MSDM_ZONE_B 0x3400 601 #define PXP_VF_BAR0_END_MSDM_ZONE_B \ 602 (PXP_VF_BAR0_START_MSDM_ZONE_B + PXP_VF_BAR0_SDM_LENGTH_ZONE_B - 1) 603 604 #define PXP_VF_BAR0_START_USDM_ZONE_B 0x3600 605 #define PXP_VF_BAR0_END_USDM_ZONE_B \ 606 (PXP_VF_BAR0_START_USDM_ZONE_B + PXP_VF_BAR0_SDM_LENGTH_ZONE_B - 1) 607 608 #define PXP_VF_BAR0_START_XSDM_ZONE_B 0x3800 609 #define PXP_VF_BAR0_END_XSDM_ZONE_B \ 610 (PXP_VF_BAR0_START_XSDM_ZONE_B + PXP_VF_BAR0_SDM_LENGTH_ZONE_B - 1) 611 612 #define PXP_VF_BAR0_START_YSDM_ZONE_B 0x3a00 613 #define PXP_VF_BAR0_END_YSDM_ZONE_B \ 614 (PXP_VF_BAR0_START_YSDM_ZONE_B + PXP_VF_BAR0_SDM_LENGTH_ZONE_B - 1) 615 616 #define PXP_VF_BAR0_START_PSDM_ZONE_B 0x3c00 617 #define PXP_VF_BAR0_END_PSDM_ZONE_B \ 618 (PXP_VF_BAR0_START_PSDM_ZONE_B + PXP_VF_BAR0_SDM_LENGTH_ZONE_B - 1) 619 620 #define PXP_VF_BAR0_START_GRC 0x3E00 621 #define PXP_VF_BAR0_GRC_LENGTH 0x200 622 #define PXP_VF_BAR0_END_GRC \ 623 (PXP_VF_BAR0_START_GRC + PXP_VF_BAR0_GRC_LENGTH - 1) 624 625 #define PXP_VF_BAR0_START_SDM_ZONE_A 0x4000 626 #define PXP_VF_BAR0_END_SDM_ZONE_A 0x10000 627 628 #define PXP_VF_BAR0_START_IGU2 0x10000 629 #define PXP_VF_BAR0_IGU2_LENGTH 0xD000 630 #define PXP_VF_BAR0_END_IGU2 \ 631 (PXP_VF_BAR0_START_IGU2 + PXP_VF_BAR0_IGU2_LENGTH - 1) 632 633 #define PXP_VF_BAR0_GRC_WINDOW_LENGTH 32 634 635 #define PXP_ILT_PAGE_SIZE_NUM_BITS_MIN 12 636 #define PXP_ILT_BLOCK_FACTOR_MULTIPLIER 1024 637 638 // ILT Records 639 #define PXP_NUM_ILT_RECORDS_BB 7600 640 #define PXP_NUM_ILT_RECORDS_K2 11000 641 #define MAX_NUM_ILT_RECORDS \ 642 OSAL_MAX_T(PXP_NUM_ILT_RECORDS_BB, PXP_NUM_ILT_RECORDS_K2) 643 644 #define PXP_NUM_ILT_RECORDS_E5 13664 645 646 647 // Host Interface 648 #define PXP_QUEUES_ZONE_MAX_NUM_E4 320 649 #define PXP_QUEUES_ZONE_MAX_NUM_E5 512 650 651 652 /*****************/ 653 /* PRM CONSTANTS */ 654 /*****************/ 655 #define PRM_DMA_PAD_BYTES_NUM 2 656 /*****************/ 657 /* SDMs CONSTANTS */ 658 /*****************/ 659 660 661 #define SDM_OP_GEN_TRIG_NONE 0 662 #define SDM_OP_GEN_TRIG_WAKE_THREAD 1 663 #define SDM_OP_GEN_TRIG_AGG_INT 2 664 #define SDM_OP_GEN_TRIG_LOADER 4 665 #define SDM_OP_GEN_TRIG_INDICATE_ERROR 6 666 #define SDM_OP_GEN_TRIG_INC_ORDER_CNT 9 667 668 /***********************************************************/ 669 /* Completion types */ 670 /***********************************************************/ 671 672 #define SDM_COMP_TYPE_NONE 0 673 #define SDM_COMP_TYPE_WAKE_THREAD 1 674 #define SDM_COMP_TYPE_AGG_INT 2 675 /* Send direct message to local CM and/or remote CMs. Destinations are defined 676 * by vector in CompParams. 677 */ 678 #define SDM_COMP_TYPE_CM 3 679 #define SDM_COMP_TYPE_LOADER 4 680 /* Send direct message to PXP (like "internal write" command) to write to remote 681 * Storm RAM via remote SDM 682 */ 683 #define SDM_COMP_TYPE_PXP 5 684 /* Indicate error per thread */ 685 #define SDM_COMP_TYPE_INDICATE_ERROR 6 686 #define SDM_COMP_TYPE_RELEASE_THREAD 7 687 /* Write to local RAM as a completion */ 688 #define SDM_COMP_TYPE_RAM 8 689 #define SDM_COMP_TYPE_INC_ORDER_CNT 9 /* Applicable only for E4 */ 690 691 692 /******************/ 693 /* PBF CONSTANTS */ 694 /******************/ 695 696 /* Number of PBF command queue lines. Each line is 32B. */ 697 #define PBF_MAX_CMD_LINES_E4 3328 698 #define PBF_MAX_CMD_LINES_E5 5280 699 700 /* Number of BTB blocks. Each block is 256B. */ 701 #define BTB_MAX_BLOCKS 1440 702 703 /*****************/ 704 /* PRS CONSTANTS */ 705 /*****************/ 706 707 #define PRS_GFT_CAM_LINES_NO_MATCH 31 708 709 /* 710 * Interrupt coalescing TimeSet 711 */ 712 struct coalescing_timeset { 713 u8 value; 714 /* Interrupt coalescing TimeSet (timeout_ticks = TimeSet shl (TimerRes+1)) */ 715 #define COALESCING_TIMESET_TIMESET_MASK 0x7F 716 #define COALESCING_TIMESET_TIMESET_SHIFT 0 717 /* Only if this flag is set, timeset will take effect */ 718 #define COALESCING_TIMESET_VALID_MASK 0x1 719 #define COALESCING_TIMESET_VALID_SHIFT 7 720 }; 721 722 struct common_queue_zone { 723 __le16 ring_drv_data_consumer; 724 __le16 reserved; 725 }; 726 727 /* 728 * ETH Rx producers data 729 */ 730 struct eth_rx_prod_data { 731 __le16 bd_prod /* BD producer. */; 732 __le16 cqe_prod /* CQE producer. */; 733 }; 734 735 736 struct tcp_ulp_connect_done_params { 737 __le16 mss; 738 u8 snd_wnd_scale; 739 u8 flags; 740 #define TCP_ULP_CONNECT_DONE_PARAMS_TS_EN_MASK 0x1 741 #define TCP_ULP_CONNECT_DONE_PARAMS_TS_EN_SHIFT 0 742 #define TCP_ULP_CONNECT_DONE_PARAMS_RESERVED_MASK 0x7F 743 #define TCP_ULP_CONNECT_DONE_PARAMS_RESERVED_SHIFT 1 744 }; 745 746 struct iscsi_connect_done_results { 747 __le16 icid /* Context ID of the connection */; 748 __le16 conn_id /* Driver connection ID */; 749 /* decided tcp params after connect done */ 750 struct tcp_ulp_connect_done_params params; 751 }; 752 753 754 struct iscsi_eqe_data { 755 __le16 icid /* Context ID of the connection */; 756 __le16 conn_id /* Driver connection ID */; 757 __le16 reserved; 758 /* error code - relevant only if the opcode indicates its an error */ 759 u8 error_code; 760 u8 error_pdu_opcode_reserved; 761 /* The processed PDUs opcode on which happened the error - updated for specific 762 * error codes, by default=0xFF 763 */ 764 #define ISCSI_EQE_DATA_ERROR_PDU_OPCODE_MASK 0x3F 765 #define ISCSI_EQE_DATA_ERROR_PDU_OPCODE_SHIFT 0 766 /* Indication for driver is the error_pdu_opcode field has valid value */ 767 #define ISCSI_EQE_DATA_ERROR_PDU_OPCODE_VALID_MASK 0x1 768 #define ISCSI_EQE_DATA_ERROR_PDU_OPCODE_VALID_SHIFT 6 769 #define ISCSI_EQE_DATA_RESERVED0_MASK 0x1 770 #define ISCSI_EQE_DATA_RESERVED0_SHIFT 7 771 }; 772 773 774 /* 775 * Multi function mode 776 */ 777 enum mf_mode { 778 ERROR_MODE /* Unsupported mode */, 779 MF_OVLAN /* Multi function based on outer VLAN */, 780 MF_NPAR /* Multi function based on MAC address (NIC partitioning) */, 781 MAX_MF_MODE 782 }; 783 784 /* Per-protocol connection types */ 785 enum protocol_type { 786 PROTOCOLID_ISCSI /* iSCSI */, 787 PROTOCOLID_FCOE /* FCoE */, 788 PROTOCOLID_ROCE /* RoCE */, 789 PROTOCOLID_CORE /* Core (light L2, slow path core) */, 790 PROTOCOLID_ETH /* Ethernet */, 791 PROTOCOLID_IWARP /* iWARP */, 792 PROTOCOLID_TOE /* TOE */, 793 PROTOCOLID_PREROCE /* Pre (tapeout) RoCE */, 794 PROTOCOLID_COMMON /* ProtocolCommon */, 795 PROTOCOLID_TCP /* TCP */, 796 MAX_PROTOCOL_TYPE 797 }; 798 799 800 struct regpair { 801 __le32 lo /* low word for reg-pair */; 802 __le32 hi /* high word for reg-pair */; 803 }; 804 805 806 807 /* 808 * Ustorm Queue Zone 809 */ 810 struct ustorm_eth_queue_zone { 811 /* Rx interrupt coalescing TimeSet */ 812 struct coalescing_timeset int_coalescing_timeset; 813 u8 reserved[3]; 814 }; 815 816 817 struct ustorm_queue_zone { 818 struct ustorm_eth_queue_zone eth; 819 struct common_queue_zone common; 820 }; 821 822 /* status block structure */ 823 struct cau_pi_entry { 824 __le32 prod; 825 /* A per protocol indexPROD value. */ 826 #define CAU_PI_ENTRY_PROD_VAL_MASK 0xFFFF 827 #define CAU_PI_ENTRY_PROD_VAL_SHIFT 0 828 /* This value determines the TimeSet that the PI is associated with */ 829 #define CAU_PI_ENTRY_PI_TIMESET_MASK 0x7F 830 #define CAU_PI_ENTRY_PI_TIMESET_SHIFT 16 831 /* Select the FSM within the SB */ 832 #define CAU_PI_ENTRY_FSM_SEL_MASK 0x1 833 #define CAU_PI_ENTRY_FSM_SEL_SHIFT 23 834 /* Select the FSM within the SB */ 835 #define CAU_PI_ENTRY_RESERVED_MASK 0xFF 836 #define CAU_PI_ENTRY_RESERVED_SHIFT 24 837 }; 838 839 /* status block structure */ 840 struct cau_sb_entry { 841 __le32 data; 842 /* The SB PROD index which is sent to the IGU. */ 843 #define CAU_SB_ENTRY_SB_PROD_MASK 0xFFFFFF 844 #define CAU_SB_ENTRY_SB_PROD_SHIFT 0 845 #define CAU_SB_ENTRY_STATE0_MASK 0xF /* RX state */ 846 #define CAU_SB_ENTRY_STATE0_SHIFT 24 847 #define CAU_SB_ENTRY_STATE1_MASK 0xF /* TX state */ 848 #define CAU_SB_ENTRY_STATE1_SHIFT 28 849 __le32 params; 850 /* Indicates the RX TimeSet that this SB is associated with. */ 851 #define CAU_SB_ENTRY_SB_TIMESET0_MASK 0x7F 852 #define CAU_SB_ENTRY_SB_TIMESET0_SHIFT 0 853 /* Indicates the TX TimeSet that this SB is associated with. */ 854 #define CAU_SB_ENTRY_SB_TIMESET1_MASK 0x7F 855 #define CAU_SB_ENTRY_SB_TIMESET1_SHIFT 7 856 /* This value will determine the RX FSM timer resolution in ticks */ 857 #define CAU_SB_ENTRY_TIMER_RES0_MASK 0x3 858 #define CAU_SB_ENTRY_TIMER_RES0_SHIFT 14 859 /* This value will determine the TX FSM timer resolution in ticks */ 860 #define CAU_SB_ENTRY_TIMER_RES1_MASK 0x3 861 #define CAU_SB_ENTRY_TIMER_RES1_SHIFT 16 862 #define CAU_SB_ENTRY_VF_NUMBER_MASK 0xFF 863 #define CAU_SB_ENTRY_VF_NUMBER_SHIFT 18 864 #define CAU_SB_ENTRY_VF_VALID_MASK 0x1 865 #define CAU_SB_ENTRY_VF_VALID_SHIFT 26 866 #define CAU_SB_ENTRY_PF_NUMBER_MASK 0xF 867 #define CAU_SB_ENTRY_PF_NUMBER_SHIFT 27 868 /* If set then indicates that the TPH STAG is equal to the SB number. Otherwise 869 * the STAG will be equal to all ones. 870 */ 871 #define CAU_SB_ENTRY_TPH_MASK 0x1 872 #define CAU_SB_ENTRY_TPH_SHIFT 31 873 }; 874 875 876 /* 877 * Igu cleanup bit values to distinguish between clean or producer consumer 878 * update. 879 */ 880 enum command_type_bit { 881 IGU_COMMAND_TYPE_NOP = 0, 882 IGU_COMMAND_TYPE_SET = 1, 883 MAX_COMMAND_TYPE_BIT 884 }; 885 886 887 /* core doorbell data */ 888 struct core_db_data { 889 u8 params; 890 /* destination of doorbell (use enum db_dest) */ 891 #define CORE_DB_DATA_DEST_MASK 0x3 892 #define CORE_DB_DATA_DEST_SHIFT 0 893 /* aggregative command to CM (use enum db_agg_cmd_sel) */ 894 #define CORE_DB_DATA_AGG_CMD_MASK 0x3 895 #define CORE_DB_DATA_AGG_CMD_SHIFT 2 896 #define CORE_DB_DATA_BYPASS_EN_MASK 0x1 /* enable QM bypass */ 897 #define CORE_DB_DATA_BYPASS_EN_SHIFT 4 898 #define CORE_DB_DATA_RESERVED_MASK 0x1 899 #define CORE_DB_DATA_RESERVED_SHIFT 5 900 /* aggregative value selection */ 901 #define CORE_DB_DATA_AGG_VAL_SEL_MASK 0x3 902 #define CORE_DB_DATA_AGG_VAL_SEL_SHIFT 6 903 /* bit for every DQ counter flags in CM context that DQ can increment */ 904 u8 agg_flags; 905 __le16 spq_prod; 906 }; 907 908 /* Enum of doorbell aggregative command selection */ 909 enum db_agg_cmd_sel { 910 DB_AGG_CMD_NOP /* No operation */, 911 DB_AGG_CMD_SET /* Set the value */, 912 DB_AGG_CMD_ADD /* Add the value */, 913 DB_AGG_CMD_MAX /* Set max of current and new value */, 914 MAX_DB_AGG_CMD_SEL 915 }; 916 917 /* Enum of doorbell destination */ 918 enum db_dest { 919 DB_DEST_XCM /* TX doorbell to XCM */, 920 DB_DEST_UCM /* RX doorbell to UCM */, 921 DB_DEST_TCM /* RX doorbell to TCM */, 922 DB_NUM_DESTINATIONS, 923 MAX_DB_DEST 924 }; 925 926 927 /* 928 * Enum of doorbell DPM types 929 */ 930 enum db_dpm_type { 931 DPM_LEGACY /* Legacy DPM- to Xstorm RAM */, 932 DPM_RDMA /* RDMA DPM (only RoCE in E4) - to NIG */, 933 /* L2 DPM inline- to PBF, with packet data on doorbell */ 934 DPM_L2_INLINE, 935 DPM_L2_BD /* L2 DPM with BD- to PBF, with TX BD data on doorbell */, 936 MAX_DB_DPM_TYPE 937 }; 938 939 /* 940 * Structure for doorbell data, in L2 DPM mode, for the first doorbell in a DPM 941 * burst 942 */ 943 struct db_l2_dpm_data { 944 __le16 icid /* internal CID */; 945 __le16 bd_prod /* bd producer value to update */; 946 __le32 params; 947 /* Size in QWORD-s of the DPM burst */ 948 #define DB_L2_DPM_DATA_SIZE_MASK 0x3F 949 #define DB_L2_DPM_DATA_SIZE_SHIFT 0 950 /* Type of DPM transaction (DPM_L2_INLINE or DPM_L2_BD) (use enum db_dpm_type) 951 */ 952 #define DB_L2_DPM_DATA_DPM_TYPE_MASK 0x3 953 #define DB_L2_DPM_DATA_DPM_TYPE_SHIFT 6 954 #define DB_L2_DPM_DATA_NUM_BDS_MASK 0xFF /* number of BD-s */ 955 #define DB_L2_DPM_DATA_NUM_BDS_SHIFT 8 956 /* size of the packet to be transmitted in bytes */ 957 #define DB_L2_DPM_DATA_PKT_SIZE_MASK 0x7FF 958 #define DB_L2_DPM_DATA_PKT_SIZE_SHIFT 16 959 #define DB_L2_DPM_DATA_RESERVED0_MASK 0x1 960 #define DB_L2_DPM_DATA_RESERVED0_SHIFT 27 961 /* In DPM_L2_BD mode: the number of SGE-s */ 962 #define DB_L2_DPM_DATA_SGE_NUM_MASK 0x7 963 #define DB_L2_DPM_DATA_SGE_NUM_SHIFT 28 964 /* Flag indicating whether to enable GFS search */ 965 #define DB_L2_DPM_DATA_RESERVED1_MASK 0x1 966 #define DB_L2_DPM_DATA_RESERVED1_SHIFT 31 967 }; 968 969 /* 970 * Structure for SGE in a DPM doorbell of type DPM_L2_BD 971 */ 972 struct db_l2_dpm_sge { 973 struct regpair addr /* Single continuous buffer */; 974 __le16 nbytes /* Number of bytes in this BD. */; 975 __le16 bitfields; 976 /* The TPH STAG index value */ 977 #define DB_L2_DPM_SGE_TPH_ST_INDEX_MASK 0x1FF 978 #define DB_L2_DPM_SGE_TPH_ST_INDEX_SHIFT 0 979 #define DB_L2_DPM_SGE_RESERVED0_MASK 0x3 980 #define DB_L2_DPM_SGE_RESERVED0_SHIFT 9 981 /* Indicate if ST hint is requested or not */ 982 #define DB_L2_DPM_SGE_ST_VALID_MASK 0x1 983 #define DB_L2_DPM_SGE_ST_VALID_SHIFT 11 984 #define DB_L2_DPM_SGE_RESERVED1_MASK 0xF 985 #define DB_L2_DPM_SGE_RESERVED1_SHIFT 12 986 __le32 reserved2; 987 }; 988 989 /* Structure for doorbell address, in legacy mode */ 990 struct db_legacy_addr { 991 __le32 addr; 992 #define DB_LEGACY_ADDR_RESERVED0_MASK 0x3 993 #define DB_LEGACY_ADDR_RESERVED0_SHIFT 0 994 /* doorbell extraction mode specifier- 0 if not used */ 995 #define DB_LEGACY_ADDR_DEMS_MASK 0x7 996 #define DB_LEGACY_ADDR_DEMS_SHIFT 2 997 #define DB_LEGACY_ADDR_ICID_MASK 0x7FFFFFF /* internal CID */ 998 #define DB_LEGACY_ADDR_ICID_SHIFT 5 999 }; 1000 1001 /* 1002 * Structure for doorbell address, in PWM mode 1003 */ 1004 struct db_pwm_addr { 1005 __le32 addr; 1006 #define DB_PWM_ADDR_RESERVED0_MASK 0x7 1007 #define DB_PWM_ADDR_RESERVED0_SHIFT 0 1008 /* Offset in PWM address space */ 1009 #define DB_PWM_ADDR_OFFSET_MASK 0x7F 1010 #define DB_PWM_ADDR_OFFSET_SHIFT 3 1011 #define DB_PWM_ADDR_WID_MASK 0x3 /* Window ID */ 1012 #define DB_PWM_ADDR_WID_SHIFT 10 1013 #define DB_PWM_ADDR_DPI_MASK 0xFFFF /* Doorbell page ID */ 1014 #define DB_PWM_ADDR_DPI_SHIFT 12 1015 #define DB_PWM_ADDR_RESERVED1_MASK 0xF 1016 #define DB_PWM_ADDR_RESERVED1_SHIFT 28 1017 }; 1018 1019 /* 1020 * Parameters to RDMA firmware, passed in EDPM doorbell 1021 */ 1022 struct db_rdma_dpm_params { 1023 __le32 params; 1024 /* Size in QWORD-s of the DPM burst */ 1025 #define DB_RDMA_DPM_PARAMS_SIZE_MASK 0x3F 1026 #define DB_RDMA_DPM_PARAMS_SIZE_SHIFT 0 1027 /* Type of DPM transacation (DPM_RDMA) (use enum db_dpm_type) */ 1028 #define DB_RDMA_DPM_PARAMS_DPM_TYPE_MASK 0x3 1029 #define DB_RDMA_DPM_PARAMS_DPM_TYPE_SHIFT 6 1030 /* opcode for RDMA operation */ 1031 #define DB_RDMA_DPM_PARAMS_OPCODE_MASK 0xFF 1032 #define DB_RDMA_DPM_PARAMS_OPCODE_SHIFT 8 1033 /* the size of the WQE payload in bytes */ 1034 #define DB_RDMA_DPM_PARAMS_WQE_SIZE_MASK 0x7FF 1035 #define DB_RDMA_DPM_PARAMS_WQE_SIZE_SHIFT 16 1036 #define DB_RDMA_DPM_PARAMS_RESERVED0_MASK 0x1 1037 #define DB_RDMA_DPM_PARAMS_RESERVED0_SHIFT 27 1038 /* RoCE completion flag */ 1039 #define DB_RDMA_DPM_PARAMS_COMPLETION_FLG_MASK 0x1 1040 #define DB_RDMA_DPM_PARAMS_COMPLETION_FLG_SHIFT 28 1041 #define DB_RDMA_DPM_PARAMS_S_FLG_MASK 0x1 /* RoCE S flag */ 1042 #define DB_RDMA_DPM_PARAMS_S_FLG_SHIFT 29 1043 #define DB_RDMA_DPM_PARAMS_RESERVED1_MASK 0x1 1044 #define DB_RDMA_DPM_PARAMS_RESERVED1_SHIFT 30 1045 /* Connection type is iWARP */ 1046 #define DB_RDMA_DPM_PARAMS_CONN_TYPE_IS_IWARP_MASK 0x1 1047 #define DB_RDMA_DPM_PARAMS_CONN_TYPE_IS_IWARP_SHIFT 31 1048 }; 1049 1050 /* 1051 * Structure for doorbell data, in RDMA DPM mode, for the first doorbell in a 1052 * DPM burst 1053 */ 1054 struct db_rdma_dpm_data { 1055 __le16 icid /* internal CID */; 1056 __le16 prod_val /* aggregated value to update */; 1057 /* parameters passed to RDMA firmware */ 1058 struct db_rdma_dpm_params params; 1059 }; 1060 1061 /* Igu interrupt command */ 1062 enum igu_int_cmd { 1063 IGU_INT_ENABLE = 0, 1064 IGU_INT_DISABLE = 1, 1065 IGU_INT_NOP = 2, 1066 IGU_INT_NOP2 = 3, 1067 MAX_IGU_INT_CMD 1068 }; 1069 1070 /* IGU producer or consumer update command */ 1071 struct igu_prod_cons_update { 1072 __le32 sb_id_and_flags; 1073 #define IGU_PROD_CONS_UPDATE_SB_INDEX_MASK 0xFFFFFF 1074 #define IGU_PROD_CONS_UPDATE_SB_INDEX_SHIFT 0 1075 #define IGU_PROD_CONS_UPDATE_UPDATE_FLAG_MASK 0x1 1076 #define IGU_PROD_CONS_UPDATE_UPDATE_FLAG_SHIFT 24 1077 /* interrupt enable/disable/nop (use enum igu_int_cmd) */ 1078 #define IGU_PROD_CONS_UPDATE_ENABLE_INT_MASK 0x3 1079 #define IGU_PROD_CONS_UPDATE_ENABLE_INT_SHIFT 25 1080 /* (use enum igu_seg_access) */ 1081 #define IGU_PROD_CONS_UPDATE_SEGMENT_ACCESS_MASK 0x1 1082 #define IGU_PROD_CONS_UPDATE_SEGMENT_ACCESS_SHIFT 27 1083 #define IGU_PROD_CONS_UPDATE_TIMER_MASK_MASK 0x1 1084 #define IGU_PROD_CONS_UPDATE_TIMER_MASK_SHIFT 28 1085 #define IGU_PROD_CONS_UPDATE_RESERVED0_MASK 0x3 1086 #define IGU_PROD_CONS_UPDATE_RESERVED0_SHIFT 29 1087 /* must always be set cleared (use enum command_type_bit) */ 1088 #define IGU_PROD_CONS_UPDATE_COMMAND_TYPE_MASK 0x1 1089 #define IGU_PROD_CONS_UPDATE_COMMAND_TYPE_SHIFT 31 1090 __le32 reserved1; 1091 }; 1092 1093 /* Igu segments access for default status block only */ 1094 enum igu_seg_access { 1095 IGU_SEG_ACCESS_REG = 0, 1096 IGU_SEG_ACCESS_ATTN = 1, 1097 MAX_IGU_SEG_ACCESS 1098 }; 1099 1100 1101 /* 1102 * Enumeration for L3 type field of parsing_and_err_flags_union. L3Type: 1103 * 0 - unknown (not ip) ,1 - Ipv4, 2 - Ipv6 (this field can be filled according 1104 * to the last-ethertype) 1105 */ 1106 enum l3_type { 1107 e_l3_type_unknown, 1108 e_l3_type_ipv4, 1109 e_l3_type_ipv6, 1110 MAX_L3_TYPE 1111 }; 1112 1113 1114 /* 1115 * Enumeration for l4Protocol field of parsing_and_err_flags_union. L4-protocol 1116 * 0 - none, 1 - TCP, 2- UDP. if the packet is IPv4 fragment, and its not the 1117 * first fragment, the protocol-type should be set to none. 1118 */ 1119 enum l4_protocol { 1120 e_l4_protocol_none, 1121 e_l4_protocol_tcp, 1122 e_l4_protocol_udp, 1123 MAX_L4_PROTOCOL 1124 }; 1125 1126 1127 /* 1128 * Parsing and error flags field. 1129 */ 1130 struct parsing_and_err_flags { 1131 __le16 flags; 1132 /* L3Type: 0 - unknown (not ip) ,1 - Ipv4, 2 - Ipv6 (this field can be filled 1133 * according to the last-ethertype) (use enum l3_type) 1134 */ 1135 #define PARSING_AND_ERR_FLAGS_L3TYPE_MASK 0x3 1136 #define PARSING_AND_ERR_FLAGS_L3TYPE_SHIFT 0 1137 /* L4-protocol 0 - none, 1 - TCP, 2- UDP. if the packet is IPv4 fragment, and 1138 * its not the first fragment, the protocol-type should be set to none. 1139 * (use enum l4_protocol) 1140 */ 1141 #define PARSING_AND_ERR_FLAGS_L4PROTOCOL_MASK 0x3 1142 #define PARSING_AND_ERR_FLAGS_L4PROTOCOL_SHIFT 2 1143 /* Set if the packet is IPv4 fragment. */ 1144 #define PARSING_AND_ERR_FLAGS_IPV4FRAG_MASK 0x1 1145 #define PARSING_AND_ERR_FLAGS_IPV4FRAG_SHIFT 4 1146 /* Set if VLAN tag exists. Invalid if tunnel type are IP GRE or IP GENEVE. */ 1147 #define PARSING_AND_ERR_FLAGS_TAG8021QEXIST_MASK 0x1 1148 #define PARSING_AND_ERR_FLAGS_TAG8021QEXIST_SHIFT 5 1149 /* Set if L4 checksum was calculated. */ 1150 #define PARSING_AND_ERR_FLAGS_L4CHKSMWASCALCULATED_MASK 0x1 1151 #define PARSING_AND_ERR_FLAGS_L4CHKSMWASCALCULATED_SHIFT 6 1152 /* Set for PTP packet. */ 1153 #define PARSING_AND_ERR_FLAGS_TIMESYNCPKT_MASK 0x1 1154 #define PARSING_AND_ERR_FLAGS_TIMESYNCPKT_SHIFT 7 1155 /* Set if PTP timestamp recorded. */ 1156 #define PARSING_AND_ERR_FLAGS_TIMESTAMPRECORDED_MASK 0x1 1157 #define PARSING_AND_ERR_FLAGS_TIMESTAMPRECORDED_SHIFT 8 1158 /* Set if either version-mismatch or hdr-len-error or ipv4-cksm is set or ipv6 1159 * ver mismatch 1160 */ 1161 #define PARSING_AND_ERR_FLAGS_IPHDRERROR_MASK 0x1 1162 #define PARSING_AND_ERR_FLAGS_IPHDRERROR_SHIFT 9 1163 /* Set if L4 checksum validation failed. Valid only if L4 checksum was 1164 * calculated. 1165 */ 1166 #define PARSING_AND_ERR_FLAGS_L4CHKSMERROR_MASK 0x1 1167 #define PARSING_AND_ERR_FLAGS_L4CHKSMERROR_SHIFT 10 1168 /* Set if GRE/VXLAN/GENEVE tunnel detected. */ 1169 #define PARSING_AND_ERR_FLAGS_TUNNELEXIST_MASK 0x1 1170 #define PARSING_AND_ERR_FLAGS_TUNNELEXIST_SHIFT 11 1171 /* Set if VLAN tag exists in tunnel header. */ 1172 #define PARSING_AND_ERR_FLAGS_TUNNEL8021QTAGEXIST_MASK 0x1 1173 #define PARSING_AND_ERR_FLAGS_TUNNEL8021QTAGEXIST_SHIFT 12 1174 /* Set if either tunnel-ipv4-version-mismatch or tunnel-ipv4-hdr-len-error or 1175 * tunnel-ipv4-cksm is set or tunneling ipv6 ver mismatch 1176 */ 1177 #define PARSING_AND_ERR_FLAGS_TUNNELIPHDRERROR_MASK 0x1 1178 #define PARSING_AND_ERR_FLAGS_TUNNELIPHDRERROR_SHIFT 13 1179 /* Set if GRE or VXLAN/GENEVE UDP checksum was calculated. */ 1180 #define PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMWASCALCULATED_MASK 0x1 1181 #define PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMWASCALCULATED_SHIFT 14 1182 /* Set if tunnel L4 checksum validation failed. Valid only if tunnel L4 checksum 1183 * was calculated. 1184 */ 1185 #define PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMERROR_MASK 0x1 1186 #define PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMERROR_SHIFT 15 1187 }; 1188 1189 1190 /* 1191 * Parsing error flags bitmap. 1192 */ 1193 struct parsing_err_flags { 1194 __le16 flags; 1195 /* MAC error indication */ 1196 #define PARSING_ERR_FLAGS_MAC_ERROR_MASK 0x1 1197 #define PARSING_ERR_FLAGS_MAC_ERROR_SHIFT 0 1198 /* truncation error indication */ 1199 #define PARSING_ERR_FLAGS_TRUNC_ERROR_MASK 0x1 1200 #define PARSING_ERR_FLAGS_TRUNC_ERROR_SHIFT 1 1201 /* packet too small indication */ 1202 #define PARSING_ERR_FLAGS_PKT_TOO_SMALL_MASK 0x1 1203 #define PARSING_ERR_FLAGS_PKT_TOO_SMALL_SHIFT 2 1204 /* Header Missing Tag */ 1205 #define PARSING_ERR_FLAGS_ANY_HDR_MISSING_TAG_MASK 0x1 1206 #define PARSING_ERR_FLAGS_ANY_HDR_MISSING_TAG_SHIFT 3 1207 /* from frame cracker output */ 1208 #define PARSING_ERR_FLAGS_ANY_HDR_IP_VER_MISMTCH_MASK 0x1 1209 #define PARSING_ERR_FLAGS_ANY_HDR_IP_VER_MISMTCH_SHIFT 4 1210 /* from frame cracker output */ 1211 #define PARSING_ERR_FLAGS_ANY_HDR_IP_V4_HDR_LEN_TOO_SMALL_MASK 0x1 1212 #define PARSING_ERR_FLAGS_ANY_HDR_IP_V4_HDR_LEN_TOO_SMALL_SHIFT 5 1213 /* set this error if: 1. total-len is smaller than hdr-len 2. total-ip-len 1214 * indicates number that is bigger than real packet length 3. tunneling: 1215 * total-ip-length of the outer header points to offset that is smaller than 1216 * the one pointed to by the total-ip-len of the inner hdr. 1217 */ 1218 #define PARSING_ERR_FLAGS_ANY_HDR_IP_BAD_TOTAL_LEN_MASK 0x1 1219 #define PARSING_ERR_FLAGS_ANY_HDR_IP_BAD_TOTAL_LEN_SHIFT 6 1220 /* from frame cracker output */ 1221 #define PARSING_ERR_FLAGS_IP_V4_CHKSM_ERROR_MASK 0x1 1222 #define PARSING_ERR_FLAGS_IP_V4_CHKSM_ERROR_SHIFT 7 1223 /* from frame cracker output. for either TCP or UDP */ 1224 #define PARSING_ERR_FLAGS_ANY_HDR_L4_IP_LEN_MISMTCH_MASK 0x1 1225 #define PARSING_ERR_FLAGS_ANY_HDR_L4_IP_LEN_MISMTCH_SHIFT 8 1226 /* from frame cracker output */ 1227 #define PARSING_ERR_FLAGS_ZERO_UDP_IP_V6_CHKSM_MASK 0x1 1228 #define PARSING_ERR_FLAGS_ZERO_UDP_IP_V6_CHKSM_SHIFT 9 1229 /* cksm calculated and value isn't 0xffff or L4-cksm-wasnt-calculated for any 1230 * reason, like: udp/ipv4 checksum is 0 etc. 1231 */ 1232 #define PARSING_ERR_FLAGS_INNER_L4_CHKSM_ERROR_MASK 0x1 1233 #define PARSING_ERR_FLAGS_INNER_L4_CHKSM_ERROR_SHIFT 10 1234 /* from frame cracker output */ 1235 #define PARSING_ERR_FLAGS_ANY_HDR_ZERO_TTL_OR_HOP_LIM_MASK 0x1 1236 #define PARSING_ERR_FLAGS_ANY_HDR_ZERO_TTL_OR_HOP_LIM_SHIFT 11 1237 /* from frame cracker output */ 1238 #define PARSING_ERR_FLAGS_NON_8021Q_TAG_EXISTS_IN_BOTH_HDRS_MASK 0x1 1239 #define PARSING_ERR_FLAGS_NON_8021Q_TAG_EXISTS_IN_BOTH_HDRS_SHIFT 12 1240 /* set if geneve option size was over 32 byte */ 1241 #define PARSING_ERR_FLAGS_GENEVE_OPTION_OVERSIZED_MASK 0x1 1242 #define PARSING_ERR_FLAGS_GENEVE_OPTION_OVERSIZED_SHIFT 13 1243 /* from frame cracker output */ 1244 #define PARSING_ERR_FLAGS_TUNNEL_IP_V4_CHKSM_ERROR_MASK 0x1 1245 #define PARSING_ERR_FLAGS_TUNNEL_IP_V4_CHKSM_ERROR_SHIFT 14 1246 /* from frame cracker output */ 1247 #define PARSING_ERR_FLAGS_TUNNEL_L4_CHKSM_ERROR_MASK 0x1 1248 #define PARSING_ERR_FLAGS_TUNNEL_L4_CHKSM_ERROR_SHIFT 15 1249 }; 1250 1251 1252 /* 1253 * Pb context 1254 */ 1255 struct pb_context { 1256 __le32 crc[4]; 1257 }; 1258 1259 /* Concrete Function ID. */ 1260 struct pxp_concrete_fid { 1261 __le16 fid; 1262 #define PXP_CONCRETE_FID_PFID_MASK 0xF /* Parent PFID */ 1263 #define PXP_CONCRETE_FID_PFID_SHIFT 0 1264 #define PXP_CONCRETE_FID_PORT_MASK 0x3 /* port number */ 1265 #define PXP_CONCRETE_FID_PORT_SHIFT 4 1266 #define PXP_CONCRETE_FID_PATH_MASK 0x1 /* path number */ 1267 #define PXP_CONCRETE_FID_PATH_SHIFT 6 1268 #define PXP_CONCRETE_FID_VFVALID_MASK 0x1 1269 #define PXP_CONCRETE_FID_VFVALID_SHIFT 7 1270 #define PXP_CONCRETE_FID_VFID_MASK 0xFF 1271 #define PXP_CONCRETE_FID_VFID_SHIFT 8 1272 }; 1273 1274 struct pxp_pretend_concrete_fid { 1275 __le16 fid; 1276 #define PXP_PRETEND_CONCRETE_FID_PFID_MASK 0xF 1277 #define PXP_PRETEND_CONCRETE_FID_PFID_SHIFT 0 1278 #define PXP_PRETEND_CONCRETE_FID_RESERVED_MASK 0x7 1279 #define PXP_PRETEND_CONCRETE_FID_RESERVED_SHIFT 4 1280 #define PXP_PRETEND_CONCRETE_FID_VFVALID_MASK 0x1 1281 #define PXP_PRETEND_CONCRETE_FID_VFVALID_SHIFT 7 1282 #define PXP_PRETEND_CONCRETE_FID_VFID_MASK 0xFF 1283 #define PXP_PRETEND_CONCRETE_FID_VFID_SHIFT 8 1284 }; 1285 1286 union pxp_pretend_fid { 1287 struct pxp_pretend_concrete_fid concrete_fid; 1288 __le16 opaque_fid; 1289 }; 1290 1291 /* Pxp Pretend Command Register. */ 1292 struct pxp_pretend_cmd { 1293 union pxp_pretend_fid fid; 1294 __le16 control; 1295 #define PXP_PRETEND_CMD_PATH_MASK 0x1 1296 #define PXP_PRETEND_CMD_PATH_SHIFT 0 1297 #define PXP_PRETEND_CMD_USE_PORT_MASK 0x1 1298 #define PXP_PRETEND_CMD_USE_PORT_SHIFT 1 1299 #define PXP_PRETEND_CMD_PORT_MASK 0x3 1300 #define PXP_PRETEND_CMD_PORT_SHIFT 2 1301 #define PXP_PRETEND_CMD_RESERVED0_MASK 0xF 1302 #define PXP_PRETEND_CMD_RESERVED0_SHIFT 4 1303 #define PXP_PRETEND_CMD_RESERVED1_MASK 0xF 1304 #define PXP_PRETEND_CMD_RESERVED1_SHIFT 8 1305 #define PXP_PRETEND_CMD_PRETEND_PATH_MASK 0x1 1306 #define PXP_PRETEND_CMD_PRETEND_PATH_SHIFT 12 1307 #define PXP_PRETEND_CMD_PRETEND_PORT_MASK 0x1 1308 #define PXP_PRETEND_CMD_PRETEND_PORT_SHIFT 13 1309 #define PXP_PRETEND_CMD_PRETEND_FUNCTION_MASK 0x1 1310 #define PXP_PRETEND_CMD_PRETEND_FUNCTION_SHIFT 14 1311 #define PXP_PRETEND_CMD_IS_CONCRETE_MASK 0x1 1312 #define PXP_PRETEND_CMD_IS_CONCRETE_SHIFT 15 1313 }; 1314 1315 /* PTT Record in PXP Admin Window. */ 1316 struct pxp_ptt_entry { 1317 __le32 offset; 1318 #define PXP_PTT_ENTRY_OFFSET_MASK 0x7FFFFF 1319 #define PXP_PTT_ENTRY_OFFSET_SHIFT 0 1320 #define PXP_PTT_ENTRY_RESERVED0_MASK 0x1FF 1321 #define PXP_PTT_ENTRY_RESERVED0_SHIFT 23 1322 struct pxp_pretend_cmd pretend; 1323 }; 1324 1325 1326 /* 1327 * VF Zone A Permission Register. 1328 */ 1329 struct pxp_vf_zone_a_permission { 1330 __le32 control; 1331 #define PXP_VF_ZONE_A_PERMISSION_VFID_MASK 0xFF 1332 #define PXP_VF_ZONE_A_PERMISSION_VFID_SHIFT 0 1333 #define PXP_VF_ZONE_A_PERMISSION_VALID_MASK 0x1 1334 #define PXP_VF_ZONE_A_PERMISSION_VALID_SHIFT 8 1335 #define PXP_VF_ZONE_A_PERMISSION_RESERVED0_MASK 0x7F 1336 #define PXP_VF_ZONE_A_PERMISSION_RESERVED0_SHIFT 9 1337 #define PXP_VF_ZONE_A_PERMISSION_RESERVED1_MASK 0xFFFF 1338 #define PXP_VF_ZONE_A_PERMISSION_RESERVED1_SHIFT 16 1339 }; 1340 1341 1342 /* 1343 * Rdif context 1344 */ 1345 struct rdif_task_context { 1346 __le32 initial_ref_tag; 1347 __le16 app_tag_value; 1348 __le16 app_tag_mask; 1349 u8 flags0; 1350 #define RDIF_TASK_CONTEXT_IGNORE_APP_TAG_MASK 0x1 1351 #define RDIF_TASK_CONTEXT_IGNORE_APP_TAG_SHIFT 0 1352 #define RDIF_TASK_CONTEXT_INITIAL_REF_TAG_VALID_MASK 0x1 1353 #define RDIF_TASK_CONTEXT_INITIAL_REF_TAG_VALID_SHIFT 1 1354 /* 0 = IP checksum, 1 = CRC */ 1355 #define RDIF_TASK_CONTEXT_HOST_GUARD_TYPE_MASK 0x1 1356 #define RDIF_TASK_CONTEXT_HOST_GUARD_TYPE_SHIFT 2 1357 #define RDIF_TASK_CONTEXT_SET_ERROR_WITH_EOP_MASK 0x1 1358 #define RDIF_TASK_CONTEXT_SET_ERROR_WITH_EOP_SHIFT 3 1359 /* 1/2/3 - Protection Type */ 1360 #define RDIF_TASK_CONTEXT_PROTECTION_TYPE_MASK 0x3 1361 #define RDIF_TASK_CONTEXT_PROTECTION_TYPE_SHIFT 4 1362 /* 0=0x0000, 1=0xffff */ 1363 #define RDIF_TASK_CONTEXT_CRC_SEED_MASK 0x1 1364 #define RDIF_TASK_CONTEXT_CRC_SEED_SHIFT 6 1365 /* Keep reference tag constant */ 1366 #define RDIF_TASK_CONTEXT_KEEP_REF_TAG_CONST_MASK 0x1 1367 #define RDIF_TASK_CONTEXT_KEEP_REF_TAG_CONST_SHIFT 7 1368 u8 partial_dif_data[7]; 1369 __le16 partial_crc_value; 1370 __le16 partial_checksum_value; 1371 __le32 offset_in_io; 1372 __le16 flags1; 1373 #define RDIF_TASK_CONTEXT_VALIDATE_GUARD_MASK 0x1 1374 #define RDIF_TASK_CONTEXT_VALIDATE_GUARD_SHIFT 0 1375 #define RDIF_TASK_CONTEXT_VALIDATE_APP_TAG_MASK 0x1 1376 #define RDIF_TASK_CONTEXT_VALIDATE_APP_TAG_SHIFT 1 1377 #define RDIF_TASK_CONTEXT_VALIDATE_REF_TAG_MASK 0x1 1378 #define RDIF_TASK_CONTEXT_VALIDATE_REF_TAG_SHIFT 2 1379 #define RDIF_TASK_CONTEXT_FORWARD_GUARD_MASK 0x1 1380 #define RDIF_TASK_CONTEXT_FORWARD_GUARD_SHIFT 3 1381 #define RDIF_TASK_CONTEXT_FORWARD_APP_TAG_MASK 0x1 1382 #define RDIF_TASK_CONTEXT_FORWARD_APP_TAG_SHIFT 4 1383 #define RDIF_TASK_CONTEXT_FORWARD_REF_TAG_MASK 0x1 1384 #define RDIF_TASK_CONTEXT_FORWARD_REF_TAG_SHIFT 5 1385 /* 0=512B, 1=1KB, 2=2KB, 3=4KB, 4=8KB */ 1386 #define RDIF_TASK_CONTEXT_INTERVAL_SIZE_MASK 0x7 1387 #define RDIF_TASK_CONTEXT_INTERVAL_SIZE_SHIFT 6 1388 /* 0=None, 1=DIF, 2=DIX */ 1389 #define RDIF_TASK_CONTEXT_HOST_INTERFACE_MASK 0x3 1390 #define RDIF_TASK_CONTEXT_HOST_INTERFACE_SHIFT 9 1391 /* DIF tag right at the beginning of DIF interval */ 1392 #define RDIF_TASK_CONTEXT_DIF_BEFORE_DATA_MASK 0x1 1393 #define RDIF_TASK_CONTEXT_DIF_BEFORE_DATA_SHIFT 11 1394 #define RDIF_TASK_CONTEXT_RESERVED0_MASK 0x1 1395 #define RDIF_TASK_CONTEXT_RESERVED0_SHIFT 12 1396 /* 0=None, 1=DIF */ 1397 #define RDIF_TASK_CONTEXT_NETWORK_INTERFACE_MASK 0x1 1398 #define RDIF_TASK_CONTEXT_NETWORK_INTERFACE_SHIFT 13 1399 /* Forward application tag with mask */ 1400 #define RDIF_TASK_CONTEXT_FORWARD_APP_TAG_WITH_MASK_MASK 0x1 1401 #define RDIF_TASK_CONTEXT_FORWARD_APP_TAG_WITH_MASK_SHIFT 14 1402 /* Forward reference tag with mask */ 1403 #define RDIF_TASK_CONTEXT_FORWARD_REF_TAG_WITH_MASK_MASK 0x1 1404 #define RDIF_TASK_CONTEXT_FORWARD_REF_TAG_WITH_MASK_SHIFT 15 1405 __le16 state; 1406 #define RDIF_TASK_CONTEXT_RECEIVED_DIF_BYTES_LEFT_MASK 0xF 1407 #define RDIF_TASK_CONTEXT_RECEIVED_DIF_BYTES_LEFT_SHIFT 0 1408 #define RDIF_TASK_CONTEXT_TRANSMITED_DIF_BYTES_LEFT_MASK 0xF 1409 #define RDIF_TASK_CONTEXT_TRANSMITED_DIF_BYTES_LEFT_SHIFT 4 1410 #define RDIF_TASK_CONTEXT_ERROR_IN_IO_MASK 0x1 1411 #define RDIF_TASK_CONTEXT_ERROR_IN_IO_SHIFT 8 1412 #define RDIF_TASK_CONTEXT_CHECKSUM_OVERFLOW_MASK 0x1 1413 #define RDIF_TASK_CONTEXT_CHECKSUM_OVERFLOW_SHIFT 9 1414 /* mask for refernce tag handling */ 1415 #define RDIF_TASK_CONTEXT_REF_TAG_MASK_MASK 0xF 1416 #define RDIF_TASK_CONTEXT_REF_TAG_MASK_SHIFT 10 1417 #define RDIF_TASK_CONTEXT_RESERVED1_MASK 0x3 1418 #define RDIF_TASK_CONTEXT_RESERVED1_SHIFT 14 1419 __le32 reserved2; 1420 }; 1421 1422 /* 1423 * RSS hash type 1424 */ 1425 enum rss_hash_type { 1426 RSS_HASH_TYPE_DEFAULT = 0, 1427 RSS_HASH_TYPE_IPV4 = 1, 1428 RSS_HASH_TYPE_TCP_IPV4 = 2, 1429 RSS_HASH_TYPE_IPV6 = 3, 1430 RSS_HASH_TYPE_TCP_IPV6 = 4, 1431 RSS_HASH_TYPE_UDP_IPV4 = 5, 1432 RSS_HASH_TYPE_UDP_IPV6 = 6, 1433 MAX_RSS_HASH_TYPE 1434 }; 1435 1436 /* 1437 * status block structure 1438 */ 1439 struct status_block_e4 { 1440 __le16 pi_array[PIS_PER_SB_E4]; 1441 __le32 sb_num; 1442 #define STATUS_BLOCK_E4_SB_NUM_MASK 0x1FF 1443 #define STATUS_BLOCK_E4_SB_NUM_SHIFT 0 1444 #define STATUS_BLOCK_E4_ZERO_PAD_MASK 0x7F 1445 #define STATUS_BLOCK_E4_ZERO_PAD_SHIFT 9 1446 #define STATUS_BLOCK_E4_ZERO_PAD2_MASK 0xFFFF 1447 #define STATUS_BLOCK_E4_ZERO_PAD2_SHIFT 16 1448 __le32 prod_index; 1449 #define STATUS_BLOCK_E4_PROD_INDEX_MASK 0xFFFFFF 1450 #define STATUS_BLOCK_E4_PROD_INDEX_SHIFT 0 1451 #define STATUS_BLOCK_E4_ZERO_PAD3_MASK 0xFF 1452 #define STATUS_BLOCK_E4_ZERO_PAD3_SHIFT 24 1453 }; 1454 1455 1456 /* 1457 * status block structure 1458 */ 1459 struct status_block_e5 { 1460 __le16 pi_array[PIS_PER_SB_E5]; 1461 __le32 sb_num; 1462 #define STATUS_BLOCK_E5_SB_NUM_MASK 0x1FF 1463 #define STATUS_BLOCK_E5_SB_NUM_SHIFT 0 1464 #define STATUS_BLOCK_E5_ZERO_PAD_MASK 0x7F 1465 #define STATUS_BLOCK_E5_ZERO_PAD_SHIFT 9 1466 #define STATUS_BLOCK_E5_ZERO_PAD2_MASK 0xFFFF 1467 #define STATUS_BLOCK_E5_ZERO_PAD2_SHIFT 16 1468 __le32 prod_index; 1469 #define STATUS_BLOCK_E5_PROD_INDEX_MASK 0xFFFFFF 1470 #define STATUS_BLOCK_E5_PROD_INDEX_SHIFT 0 1471 #define STATUS_BLOCK_E5_ZERO_PAD3_MASK 0xFF 1472 #define STATUS_BLOCK_E5_ZERO_PAD3_SHIFT 24 1473 }; 1474 1475 1476 /* 1477 * Tdif context 1478 */ 1479 struct tdif_task_context { 1480 __le32 initial_ref_tag; 1481 __le16 app_tag_value; 1482 __le16 app_tag_mask; 1483 __le16 partial_crc_value_b; 1484 __le16 partial_checksum_value_b; 1485 __le16 stateB; 1486 #define TDIF_TASK_CONTEXT_RECEIVED_DIF_BYTES_LEFT_B_MASK 0xF 1487 #define TDIF_TASK_CONTEXT_RECEIVED_DIF_BYTES_LEFT_B_SHIFT 0 1488 #define TDIF_TASK_CONTEXT_TRANSMITED_DIF_BYTES_LEFT_B_MASK 0xF 1489 #define TDIF_TASK_CONTEXT_TRANSMITED_DIF_BYTES_LEFT_B_SHIFT 4 1490 #define TDIF_TASK_CONTEXT_ERROR_IN_IO_B_MASK 0x1 1491 #define TDIF_TASK_CONTEXT_ERROR_IN_IO_B_SHIFT 8 1492 #define TDIF_TASK_CONTEXT_CHECKSUM_VERFLOW_MASK 0x1 1493 #define TDIF_TASK_CONTEXT_CHECKSUM_VERFLOW_SHIFT 9 1494 #define TDIF_TASK_CONTEXT_RESERVED0_MASK 0x3F 1495 #define TDIF_TASK_CONTEXT_RESERVED0_SHIFT 10 1496 u8 reserved1; 1497 u8 flags0; 1498 #define TDIF_TASK_CONTEXT_IGNORE_APP_TAG_MASK 0x1 1499 #define TDIF_TASK_CONTEXT_IGNORE_APP_TAG_SHIFT 0 1500 #define TDIF_TASK_CONTEXT_INITIAL_REF_TAG_VALID_MASK 0x1 1501 #define TDIF_TASK_CONTEXT_INITIAL_REF_TAG_VALID_SHIFT 1 1502 /* 0 = IP checksum, 1 = CRC */ 1503 #define TDIF_TASK_CONTEXT_HOST_GUARD_TYPE_MASK 0x1 1504 #define TDIF_TASK_CONTEXT_HOST_GUARD_TYPE_SHIFT 2 1505 #define TDIF_TASK_CONTEXT_SET_ERROR_WITH_EOP_MASK 0x1 1506 #define TDIF_TASK_CONTEXT_SET_ERROR_WITH_EOP_SHIFT 3 1507 /* 1/2/3 - Protection Type */ 1508 #define TDIF_TASK_CONTEXT_PROTECTION_TYPE_MASK 0x3 1509 #define TDIF_TASK_CONTEXT_PROTECTION_TYPE_SHIFT 4 1510 /* 0=0x0000, 1=0xffff */ 1511 #define TDIF_TASK_CONTEXT_CRC_SEED_MASK 0x1 1512 #define TDIF_TASK_CONTEXT_CRC_SEED_SHIFT 6 1513 #define TDIF_TASK_CONTEXT_RESERVED2_MASK 0x1 1514 #define TDIF_TASK_CONTEXT_RESERVED2_SHIFT 7 1515 __le32 flags1; 1516 #define TDIF_TASK_CONTEXT_VALIDATE_GUARD_MASK 0x1 1517 #define TDIF_TASK_CONTEXT_VALIDATE_GUARD_SHIFT 0 1518 #define TDIF_TASK_CONTEXT_VALIDATE_APP_TAG_MASK 0x1 1519 #define TDIF_TASK_CONTEXT_VALIDATE_APP_TAG_SHIFT 1 1520 #define TDIF_TASK_CONTEXT_VALIDATE_REF_TAG_MASK 0x1 1521 #define TDIF_TASK_CONTEXT_VALIDATE_REF_TAG_SHIFT 2 1522 #define TDIF_TASK_CONTEXT_FORWARD_GUARD_MASK 0x1 1523 #define TDIF_TASK_CONTEXT_FORWARD_GUARD_SHIFT 3 1524 #define TDIF_TASK_CONTEXT_FORWARD_APP_TAG_MASK 0x1 1525 #define TDIF_TASK_CONTEXT_FORWARD_APP_TAG_SHIFT 4 1526 #define TDIF_TASK_CONTEXT_FORWARD_REF_TAG_MASK 0x1 1527 #define TDIF_TASK_CONTEXT_FORWARD_REF_TAG_SHIFT 5 1528 /* 0=512B, 1=1KB, 2=2KB, 3=4KB, 4=8KB */ 1529 #define TDIF_TASK_CONTEXT_INTERVAL_SIZE_MASK 0x7 1530 #define TDIF_TASK_CONTEXT_INTERVAL_SIZE_SHIFT 6 1531 /* 0=None, 1=DIF, 2=DIX */ 1532 #define TDIF_TASK_CONTEXT_HOST_INTERFACE_MASK 0x3 1533 #define TDIF_TASK_CONTEXT_HOST_INTERFACE_SHIFT 9 1534 /* DIF tag right at the beginning of DIF interval */ 1535 #define TDIF_TASK_CONTEXT_DIF_BEFORE_DATA_MASK 0x1 1536 #define TDIF_TASK_CONTEXT_DIF_BEFORE_DATA_SHIFT 11 1537 #define TDIF_TASK_CONTEXT_RESERVED3_MASK 0x1 /* reserved */ 1538 #define TDIF_TASK_CONTEXT_RESERVED3_SHIFT 12 1539 /* 0=None, 1=DIF */ 1540 #define TDIF_TASK_CONTEXT_NETWORK_INTERFACE_MASK 0x1 1541 #define TDIF_TASK_CONTEXT_NETWORK_INTERFACE_SHIFT 13 1542 #define TDIF_TASK_CONTEXT_RECEIVED_DIF_BYTES_LEFT_A_MASK 0xF 1543 #define TDIF_TASK_CONTEXT_RECEIVED_DIF_BYTES_LEFT_A_SHIFT 14 1544 #define TDIF_TASK_CONTEXT_TRANSMITED_DIF_BYTES_LEFT_A_MASK 0xF 1545 #define TDIF_TASK_CONTEXT_TRANSMITED_DIF_BYTES_LEFT_A_SHIFT 18 1546 #define TDIF_TASK_CONTEXT_ERROR_IN_IO_A_MASK 0x1 1547 #define TDIF_TASK_CONTEXT_ERROR_IN_IO_A_SHIFT 22 1548 #define TDIF_TASK_CONTEXT_CHECKSUM_OVERFLOW_A_MASK 0x1 1549 #define TDIF_TASK_CONTEXT_CHECKSUM_OVERFLOW_A_SHIFT 23 1550 /* mask for refernce tag handling */ 1551 #define TDIF_TASK_CONTEXT_REF_TAG_MASK_MASK 0xF 1552 #define TDIF_TASK_CONTEXT_REF_TAG_MASK_SHIFT 24 1553 /* Forward application tag with mask */ 1554 #define TDIF_TASK_CONTEXT_FORWARD_APP_TAG_WITH_MASK_MASK 0x1 1555 #define TDIF_TASK_CONTEXT_FORWARD_APP_TAG_WITH_MASK_SHIFT 28 1556 /* Forward reference tag with mask */ 1557 #define TDIF_TASK_CONTEXT_FORWARD_REF_TAG_WITH_MASK_MASK 0x1 1558 #define TDIF_TASK_CONTEXT_FORWARD_REF_TAG_WITH_MASK_SHIFT 29 1559 /* Keep reference tag constant */ 1560 #define TDIF_TASK_CONTEXT_KEEP_REF_TAG_CONST_MASK 0x1 1561 #define TDIF_TASK_CONTEXT_KEEP_REF_TAG_CONST_SHIFT 30 1562 #define TDIF_TASK_CONTEXT_RESERVED4_MASK 0x1 1563 #define TDIF_TASK_CONTEXT_RESERVED4_SHIFT 31 1564 __le32 offset_in_io_b; 1565 __le16 partial_crc_value_a; 1566 __le16 partial_checksum_value_a; 1567 __le32 offset_in_io_a; 1568 u8 partial_dif_data_a[8]; 1569 u8 partial_dif_data_b[8]; 1570 }; 1571 1572 1573 /* 1574 * Timers context 1575 */ 1576 struct timers_context { 1577 __le32 logical_client_0; 1578 /* Expiration time of logical client 0 */ 1579 #define TIMERS_CONTEXT_EXPIRATIONTIMELC0_MASK 0x7FFFFFF 1580 #define TIMERS_CONTEXT_EXPIRATIONTIMELC0_SHIFT 0 1581 #define TIMERS_CONTEXT_RESERVED0_MASK 0x1 1582 #define TIMERS_CONTEXT_RESERVED0_SHIFT 27 1583 /* Valid bit of logical client 0 */ 1584 #define TIMERS_CONTEXT_VALIDLC0_MASK 0x1 1585 #define TIMERS_CONTEXT_VALIDLC0_SHIFT 28 1586 /* Active bit of logical client 0 */ 1587 #define TIMERS_CONTEXT_ACTIVELC0_MASK 0x1 1588 #define TIMERS_CONTEXT_ACTIVELC0_SHIFT 29 1589 #define TIMERS_CONTEXT_RESERVED1_MASK 0x3 1590 #define TIMERS_CONTEXT_RESERVED1_SHIFT 30 1591 __le32 logical_client_1; 1592 /* Expiration time of logical client 1 */ 1593 #define TIMERS_CONTEXT_EXPIRATIONTIMELC1_MASK 0x7FFFFFF 1594 #define TIMERS_CONTEXT_EXPIRATIONTIMELC1_SHIFT 0 1595 #define TIMERS_CONTEXT_RESERVED2_MASK 0x1 1596 #define TIMERS_CONTEXT_RESERVED2_SHIFT 27 1597 /* Valid bit of logical client 1 */ 1598 #define TIMERS_CONTEXT_VALIDLC1_MASK 0x1 1599 #define TIMERS_CONTEXT_VALIDLC1_SHIFT 28 1600 /* Active bit of logical client 1 */ 1601 #define TIMERS_CONTEXT_ACTIVELC1_MASK 0x1 1602 #define TIMERS_CONTEXT_ACTIVELC1_SHIFT 29 1603 #define TIMERS_CONTEXT_RESERVED3_MASK 0x3 1604 #define TIMERS_CONTEXT_RESERVED3_SHIFT 30 1605 __le32 logical_client_2; 1606 /* Expiration time of logical client 2 */ 1607 #define TIMERS_CONTEXT_EXPIRATIONTIMELC2_MASK 0x7FFFFFF 1608 #define TIMERS_CONTEXT_EXPIRATIONTIMELC2_SHIFT 0 1609 #define TIMERS_CONTEXT_RESERVED4_MASK 0x1 1610 #define TIMERS_CONTEXT_RESERVED4_SHIFT 27 1611 /* Valid bit of logical client 2 */ 1612 #define TIMERS_CONTEXT_VALIDLC2_MASK 0x1 1613 #define TIMERS_CONTEXT_VALIDLC2_SHIFT 28 1614 /* Active bit of logical client 2 */ 1615 #define TIMERS_CONTEXT_ACTIVELC2_MASK 0x1 1616 #define TIMERS_CONTEXT_ACTIVELC2_SHIFT 29 1617 #define TIMERS_CONTEXT_RESERVED5_MASK 0x3 1618 #define TIMERS_CONTEXT_RESERVED5_SHIFT 30 1619 __le32 host_expiration_fields; 1620 /* Expiration time on host (closest one) */ 1621 #define TIMERS_CONTEXT_HOSTEXPRIRATIONVALUE_MASK 0x7FFFFFF 1622 #define TIMERS_CONTEXT_HOSTEXPRIRATIONVALUE_SHIFT 0 1623 #define TIMERS_CONTEXT_RESERVED6_MASK 0x1 1624 #define TIMERS_CONTEXT_RESERVED6_SHIFT 27 1625 /* Valid bit of host expiration */ 1626 #define TIMERS_CONTEXT_HOSTEXPRIRATIONVALID_MASK 0x1 1627 #define TIMERS_CONTEXT_HOSTEXPRIRATIONVALID_SHIFT 28 1628 #define TIMERS_CONTEXT_RESERVED7_MASK 0x7 1629 #define TIMERS_CONTEXT_RESERVED7_SHIFT 29 1630 }; 1631 1632 1633 /* 1634 * Enum for next_protocol field of tunnel_parsing_flags 1635 */ 1636 enum tunnel_next_protocol { 1637 e_unknown = 0, 1638 e_l2 = 1, 1639 e_ipv4 = 2, 1640 e_ipv6 = 3, 1641 MAX_TUNNEL_NEXT_PROTOCOL 1642 }; 1643 1644 #endif /* __COMMON_HSI__ */ 1645