1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2018-2019 NXP 3 */ 4 5 #ifndef _UTIL_CSR_H_ 6 #define _UTIL_CSR_H_ 7 8 #define UTIL_VERSION (UTIL_CSR_BASE_ADDR + 0x000) 9 #define UTIL_TX_CTRL (UTIL_CSR_BASE_ADDR + 0x004) 10 #define UTIL_INQ_PKTPTR (UTIL_CSR_BASE_ADDR + 0x010) 11 12 #define UTIL_HDR_SIZE (UTIL_CSR_BASE_ADDR + 0x014) 13 14 #define UTIL_PE0_QB_DM_ADDR0 (UTIL_CSR_BASE_ADDR + 0x020) 15 #define UTIL_PE0_QB_DM_ADDR1 (UTIL_CSR_BASE_ADDR + 0x024) 16 #define UTIL_PE0_RO_DM_ADDR0 (UTIL_CSR_BASE_ADDR + 0x060) 17 #define UTIL_PE0_RO_DM_ADDR1 (UTIL_CSR_BASE_ADDR + 0x064) 18 19 #define UTIL_MEM_ACCESS_ADDR (UTIL_CSR_BASE_ADDR + 0x100) 20 #define UTIL_MEM_ACCESS_WDATA (UTIL_CSR_BASE_ADDR + 0x104) 21 #define UTIL_MEM_ACCESS_RDATA (UTIL_CSR_BASE_ADDR + 0x108) 22 23 #define UTIL_TM_INQ_ADDR (UTIL_CSR_BASE_ADDR + 0x114) 24 #define UTIL_PE_STATUS (UTIL_CSR_BASE_ADDR + 0x118) 25 26 #define UTIL_PE_SYS_CLK_RATIO (UTIL_CSR_BASE_ADDR + 0x200) 27 #define UTIL_AFULL_THRES (UTIL_CSR_BASE_ADDR + 0x204) 28 #define UTIL_GAP_BETWEEN_READS (UTIL_CSR_BASE_ADDR + 0x208) 29 #define UTIL_MAX_BUF_CNT (UTIL_CSR_BASE_ADDR + 0x20c) 30 #define UTIL_TSQ_FIFO_THRES (UTIL_CSR_BASE_ADDR + 0x210) 31 #define UTIL_TSQ_MAX_CNT (UTIL_CSR_BASE_ADDR + 0x214) 32 #define UTIL_IRAM_DATA_0 (UTIL_CSR_BASE_ADDR + 0x218) 33 #define UTIL_IRAM_DATA_1 (UTIL_CSR_BASE_ADDR + 0x21c) 34 #define UTIL_IRAM_DATA_2 (UTIL_CSR_BASE_ADDR + 0x220) 35 #define UTIL_IRAM_DATA_3 (UTIL_CSR_BASE_ADDR + 0x224) 36 37 #define UTIL_BUS_ACCESS_ADDR (UTIL_CSR_BASE_ADDR + 0x228) 38 #define UTIL_BUS_ACCESS_WDATA (UTIL_CSR_BASE_ADDR + 0x22c) 39 #define UTIL_BUS_ACCESS_RDATA (UTIL_CSR_BASE_ADDR + 0x230) 40 41 #define UTIL_INQ_AFULL_THRES (UTIL_CSR_BASE_ADDR + 0x234) 42 43 struct util_cfg { 44 u32 pe_sys_clk_ratio; 45 }; 46 47 #endif /* _UTIL_CSR_H_ */ 48