xref: /dpdk/drivers/net/pfe/base/cbus/tmu_csr.h (revision f513f620591370c7b10f43fc7baa2e258d2f428d) 
1 /* SPDX-License-Identifier: BSD-3-Clause
2  * Copyright 2018-2019 NXP
3  */
4 
5 #ifndef _TMU_CSR_H_
6 #define _TMU_CSR_H_
7 
8 #define TMU_VERSION	(TMU_CSR_BASE_ADDR + 0x000)
9 #define TMU_INQ_WATERMARK	(TMU_CSR_BASE_ADDR + 0x004)
10 #define TMU_PHY_INQ_PKTPTR	(TMU_CSR_BASE_ADDR + 0x008)
11 #define TMU_PHY_INQ_PKTINFO	(TMU_CSR_BASE_ADDR + 0x00c)
12 #define TMU_PHY_INQ_FIFO_CNT	(TMU_CSR_BASE_ADDR + 0x010)
13 #define TMU_SYS_GENERIC_CONTROL	(TMU_CSR_BASE_ADDR + 0x014)
14 #define TMU_SYS_GENERIC_STATUS	(TMU_CSR_BASE_ADDR + 0x018)
15 #define TMU_SYS_GEN_CON0	(TMU_CSR_BASE_ADDR + 0x01c)
16 #define TMU_SYS_GEN_CON1	(TMU_CSR_BASE_ADDR + 0x020)
17 #define TMU_SYS_GEN_CON2	(TMU_CSR_BASE_ADDR + 0x024)
18 #define TMU_SYS_GEN_CON3	(TMU_CSR_BASE_ADDR + 0x028)
19 #define TMU_SYS_GEN_CON4	(TMU_CSR_BASE_ADDR + 0x02c)
20 #define TMU_TEQ_DISABLE_DROPCHK	(TMU_CSR_BASE_ADDR + 0x030)
21 #define TMU_TEQ_CTRL	(TMU_CSR_BASE_ADDR + 0x034)
22 #define TMU_TEQ_QCFG	(TMU_CSR_BASE_ADDR + 0x038)
23 #define TMU_TEQ_DROP_STAT	(TMU_CSR_BASE_ADDR + 0x03c)
24 #define TMU_TEQ_QAVG	(TMU_CSR_BASE_ADDR + 0x040)
25 #define TMU_TEQ_WREG_PROB	(TMU_CSR_BASE_ADDR + 0x044)
26 #define TMU_TEQ_TRANS_STAT	(TMU_CSR_BASE_ADDR + 0x048)
27 #define TMU_TEQ_HW_PROB_CFG0	(TMU_CSR_BASE_ADDR + 0x04c)
28 #define TMU_TEQ_HW_PROB_CFG1	(TMU_CSR_BASE_ADDR + 0x050)
29 #define TMU_TEQ_HW_PROB_CFG2	(TMU_CSR_BASE_ADDR + 0x054)
30 #define TMU_TEQ_HW_PROB_CFG3	(TMU_CSR_BASE_ADDR + 0x058)
31 #define TMU_TEQ_HW_PROB_CFG4	(TMU_CSR_BASE_ADDR + 0x05c)
32 #define TMU_TEQ_HW_PROB_CFG5	(TMU_CSR_BASE_ADDR + 0x060)
33 #define TMU_TEQ_HW_PROB_CFG6	(TMU_CSR_BASE_ADDR + 0x064)
34 #define TMU_TEQ_HW_PROB_CFG7	(TMU_CSR_BASE_ADDR + 0x068)
35 #define TMU_TEQ_HW_PROB_CFG8	(TMU_CSR_BASE_ADDR + 0x06c)
36 #define TMU_TEQ_HW_PROB_CFG9	(TMU_CSR_BASE_ADDR + 0x070)
37 #define TMU_TEQ_HW_PROB_CFG10	(TMU_CSR_BASE_ADDR + 0x074)
38 #define TMU_TEQ_HW_PROB_CFG11	(TMU_CSR_BASE_ADDR + 0x078)
39 #define TMU_TEQ_HW_PROB_CFG12	(TMU_CSR_BASE_ADDR + 0x07c)
40 #define TMU_TEQ_HW_PROB_CFG13	(TMU_CSR_BASE_ADDR + 0x080)
41 #define TMU_TEQ_HW_PROB_CFG14	(TMU_CSR_BASE_ADDR + 0x084)
42 #define TMU_TEQ_HW_PROB_CFG15	(TMU_CSR_BASE_ADDR + 0x088)
43 #define TMU_TEQ_HW_PROB_CFG16	(TMU_CSR_BASE_ADDR + 0x08c)
44 #define TMU_TEQ_HW_PROB_CFG17	(TMU_CSR_BASE_ADDR + 0x090)
45 #define TMU_TEQ_HW_PROB_CFG18	(TMU_CSR_BASE_ADDR + 0x094)
46 #define TMU_TEQ_HW_PROB_CFG19	(TMU_CSR_BASE_ADDR + 0x098)
47 #define TMU_TEQ_HW_PROB_CFG20	(TMU_CSR_BASE_ADDR + 0x09c)
48 #define TMU_TEQ_HW_PROB_CFG21	(TMU_CSR_BASE_ADDR + 0x0a0)
49 #define TMU_TEQ_HW_PROB_CFG22	(TMU_CSR_BASE_ADDR + 0x0a4)
50 #define TMU_TEQ_HW_PROB_CFG23	(TMU_CSR_BASE_ADDR + 0x0a8)
51 #define TMU_TEQ_HW_PROB_CFG24	(TMU_CSR_BASE_ADDR + 0x0ac)
52 #define TMU_TEQ_HW_PROB_CFG25	(TMU_CSR_BASE_ADDR + 0x0b0)
53 #define TMU_TDQ_IIFG_CFG	(TMU_CSR_BASE_ADDR + 0x0b4)
54 /* [9:0] Scheduler Enable for each of the scheduler in the TDQ.
55  * This is a global Enable for all schedulers in PHY0
56  */
57 #define TMU_TDQ0_SCH_CTRL	(TMU_CSR_BASE_ADDR + 0x0b8)
58 
59 #define TMU_LLM_CTRL	(TMU_CSR_BASE_ADDR + 0x0bc)
60 #define TMU_LLM_BASE_ADDR	(TMU_CSR_BASE_ADDR + 0x0c0)
61 #define TMU_LLM_QUE_LEN	(TMU_CSR_BASE_ADDR + 0x0c4)
62 #define TMU_LLM_QUE_HEADPTR	(TMU_CSR_BASE_ADDR + 0x0c8)
63 #define TMU_LLM_QUE_TAILPTR	(TMU_CSR_BASE_ADDR + 0x0cc)
64 #define TMU_LLM_QUE_DROPCNT	(TMU_CSR_BASE_ADDR + 0x0d0)
65 #define TMU_INT_EN	(TMU_CSR_BASE_ADDR + 0x0d4)
66 #define TMU_INT_SRC	(TMU_CSR_BASE_ADDR + 0x0d8)
67 #define TMU_INQ_STAT	(TMU_CSR_BASE_ADDR + 0x0dc)
68 #define TMU_CTRL	(TMU_CSR_BASE_ADDR + 0x0e0)
69 
70 /* [31] Mem Access Command. 0 = Internal Memory Read, 1 = Internal memory
71  * Write [27:24] Byte Enables of the Internal memory access [23:0] Address of
72  * the internal memory. This address is used to access both the PM and DM of
73  * all the PE's
74  */
75 #define TMU_MEM_ACCESS_ADDR	(TMU_CSR_BASE_ADDR + 0x0e4)
76 
77 /* Internal Memory Access Write Data */
78 #define TMU_MEM_ACCESS_WDATA	(TMU_CSR_BASE_ADDR + 0x0e8)
79 /* Internal Memory Access Read Data. The commands are blocked
80  * at the mem_access only
81  */
82 #define TMU_MEM_ACCESS_RDATA	(TMU_CSR_BASE_ADDR + 0x0ec)
83 
84 /* [31:0] PHY0 in queue address (must be initialized with one of the
85  * xxx_INQ_PKTPTR cbus addresses)
86  */
87 #define TMU_PHY0_INQ_ADDR	(TMU_CSR_BASE_ADDR + 0x0f0)
88 /* [31:0] PHY1 in queue address (must be initialized with one of the
89  * xxx_INQ_PKTPTR cbus addresses)
90  */
91 #define TMU_PHY1_INQ_ADDR	(TMU_CSR_BASE_ADDR + 0x0f4)
92 /* [31:0] PHY2 in queue address (must be initialized with one of the
93  * xxx_INQ_PKTPTR cbus addresses)
94  */
95 #define TMU_PHY2_INQ_ADDR	(TMU_CSR_BASE_ADDR + 0x0f8)
96 /* [31:0] PHY3 in queue address (must be initialized with one of the
97  * xxx_INQ_PKTPTR cbus addresses)
98  */
99 #define TMU_PHY3_INQ_ADDR	(TMU_CSR_BASE_ADDR + 0x0fc)
100 #define TMU_BMU_INQ_ADDR	(TMU_CSR_BASE_ADDR + 0x100)
101 #define TMU_TX_CTRL	(TMU_CSR_BASE_ADDR + 0x104)
102 
103 #define TMU_BUS_ACCESS_WDATA	(TMU_CSR_BASE_ADDR + 0x108)
104 #define TMU_BUS_ACCESS	(TMU_CSR_BASE_ADDR + 0x10c)
105 #define TMU_BUS_ACCESS_RDATA	(TMU_CSR_BASE_ADDR + 0x110)
106 
107 #define TMU_PE_SYS_CLK_RATIO	(TMU_CSR_BASE_ADDR + 0x114)
108 #define TMU_PE_STATUS	(TMU_CSR_BASE_ADDR + 0x118)
109 #define TMU_TEQ_MAX_THRESHOLD	(TMU_CSR_BASE_ADDR + 0x11c)
110 /* [31:0] PHY4 in queue address (must be initialized with one of the
111  * xxx_INQ_PKTPTR cbus addresses)
112  */
113 #define TMU_PHY4_INQ_ADDR	(TMU_CSR_BASE_ADDR + 0x134)
114 /* [9:0] Scheduler Enable for each of the scheduler in the TDQ.
115  * This is a global Enable for all schedulers in PHY1
116  */
117 #define TMU_TDQ1_SCH_CTRL	(TMU_CSR_BASE_ADDR + 0x138)
118 /* [9:0] Scheduler Enable for each of the scheduler in the TDQ.
119  * This is a global Enable for all schedulers in PHY2
120  */
121 #define TMU_TDQ2_SCH_CTRL	(TMU_CSR_BASE_ADDR + 0x13c)
122 /* [9:0] Scheduler Enable for each of the scheduler in the TDQ.
123  * This is a global Enable for all schedulers in PHY3
124  */
125 #define TMU_TDQ3_SCH_CTRL	(TMU_CSR_BASE_ADDR + 0x140)
126 #define TMU_BMU_BUF_SIZE	(TMU_CSR_BASE_ADDR + 0x144)
127 /* [31:0] PHY5 in queue address (must be initialized with one of the
128  * xxx_INQ_PKTPTR cbus addresses)
129  */
130 #define TMU_PHY5_INQ_ADDR	(TMU_CSR_BASE_ADDR + 0x148)
131 
132 #define SW_RESET		BIT(0)	/* Global software reset */
133 #define INQ_RESET		BIT(2)
134 #define TEQ_RESET		BIT(3)
135 #define TDQ_RESET		BIT(4)
136 #define PE_RESET		BIT(5)
137 #define MEM_INIT		BIT(6)
138 #define MEM_INIT_DONE		BIT(7)
139 #define LLM_INIT		BIT(8)
140 #define LLM_INIT_DONE		BIT(9)
141 #define ECC_MEM_INIT_DONE	BIT(10)
142 
143 struct tmu_cfg {
144 	u32 pe_sys_clk_ratio;
145 	unsigned long llm_base_addr;
146 	u32 llm_queue_len;
147 };
148 
149 /* Not HW related for pfe_ctrl / pfe common defines */
150 #define DEFAULT_MAX_QDEPTH	80
151 #define DEFAULT_Q0_QDEPTH	511 /*We keep one large queue for host tx qos */
152 #define DEFAULT_TMU3_QDEPTH	127
153 
154 #endif /* _TMU_CSR_H_ */
155