xref: /dpdk/drivers/net/pfe/base/cbus/hif.h (revision f513f620591370c7b10f43fc7baa2e258d2f428d)
1 /* SPDX-License-Identifier: BSD-3-Clause
2  * Copyright 2018-2019 NXP
3  */
4 
5 #ifndef _HIF_H_
6 #define _HIF_H_
7 
8 /* @file hif.h.
9  * hif - PFE hif block control and status register.
10  * Mapped on CBUS and accessible from all PE's and ARM.
11  */
12 #define HIF_VERSION	(HIF_BASE_ADDR + 0x00)
13 #define HIF_TX_CTRL	(HIF_BASE_ADDR + 0x04)
14 #define HIF_TX_CURR_BD_ADDR	(HIF_BASE_ADDR + 0x08)
15 #define HIF_TX_ALLOC	(HIF_BASE_ADDR + 0x0c)
16 #define HIF_TX_BDP_ADDR	(HIF_BASE_ADDR + 0x10)
17 #define HIF_TX_STATUS	(HIF_BASE_ADDR + 0x14)
18 #define HIF_RX_CTRL	(HIF_BASE_ADDR + 0x20)
19 #define HIF_RX_BDP_ADDR	(HIF_BASE_ADDR + 0x24)
20 #define HIF_RX_STATUS	(HIF_BASE_ADDR + 0x30)
21 #define HIF_INT_SRC	(HIF_BASE_ADDR + 0x34)
22 #define HIF_INT_ENABLE	(HIF_BASE_ADDR + 0x38)
23 #define HIF_POLL_CTRL	(HIF_BASE_ADDR + 0x3c)
24 #define HIF_RX_CURR_BD_ADDR	(HIF_BASE_ADDR + 0x40)
25 #define HIF_RX_ALLOC	(HIF_BASE_ADDR + 0x44)
26 #define HIF_TX_DMA_STATUS	(HIF_BASE_ADDR + 0x48)
27 #define HIF_RX_DMA_STATUS	(HIF_BASE_ADDR + 0x4c)
28 #define HIF_INT_COAL	(HIF_BASE_ADDR + 0x50)
29 
30 /* HIF_INT_SRC/ HIF_INT_ENABLE control bits */
31 #define HIF_INT		BIT(0)
32 #define HIF_RXBD_INT	BIT(1)
33 #define HIF_RXPKT_INT	BIT(2)
34 #define HIF_TXBD_INT	BIT(3)
35 #define HIF_TXPKT_INT	BIT(4)
36 
37 /* HIF_TX_CTRL bits */
38 #define HIF_CTRL_DMA_EN			BIT(0)
39 #define HIF_CTRL_BDP_POLL_CTRL_EN	BIT(1)
40 #define HIF_CTRL_BDP_CH_START_WSTB	BIT(2)
41 
42 /* HIF_RX_STATUS bits */
43 #define BDP_CSR_RX_DMA_ACTV     BIT(16)
44 
45 /* HIF_INT_ENABLE bits */
46 #define HIF_INT_EN		BIT(0)
47 #define HIF_RXBD_INT_EN		BIT(1)
48 #define HIF_RXPKT_INT_EN	BIT(2)
49 #define HIF_TXBD_INT_EN		BIT(3)
50 #define HIF_TXPKT_INT_EN	BIT(4)
51 
52 /* HIF_POLL_CTRL bits*/
53 #define HIF_RX_POLL_CTRL_CYCLE	0x0400
54 #define HIF_TX_POLL_CTRL_CYCLE	0x0400
55 
56 /* HIF_INT_COAL bits*/
57 #define HIF_INT_COAL_ENABLE	BIT(31)
58 
59 /* Buffer descriptor control bits */
60 #define BD_CTRL_BUFLEN_MASK	0x3fff
61 #define BD_BUF_LEN(x)	((x) & BD_CTRL_BUFLEN_MASK)
62 #define BD_CTRL_CBD_INT_EN	BIT(16)
63 #define BD_CTRL_PKT_INT_EN	BIT(17)
64 #define BD_CTRL_LIFM		BIT(18)
65 #define BD_CTRL_LAST_BD		BIT(19)
66 #define BD_CTRL_DIR		BIT(20)
67 #define BD_CTRL_LMEM_CPY	BIT(21) /* Valid only for HIF_NOCPY */
68 #define BD_CTRL_PKT_XFER	BIT(24)
69 #define BD_CTRL_DESC_EN		BIT(31)
70 #define BD_CTRL_PARSE_DISABLE	BIT(25)
71 #define BD_CTRL_BRFETCH_DISABLE	BIT(26)
72 #define BD_CTRL_RTFETCH_DISABLE	BIT(27)
73 
74 /* Buffer descriptor status bits*/
75 #define BD_STATUS_CONN_ID(x)	((x) & 0xffff)
76 #define BD_STATUS_DIR_PROC_ID	BIT(16)
77 #define BD_STATUS_CONN_ID_EN	BIT(17)
78 #define BD_STATUS_PE2PROC_ID(x)	(((x) & 7) << 18)
79 #define BD_STATUS_LE_DATA	BIT(21)
80 #define BD_STATUS_CHKSUM_EN	BIT(22)
81 
82 /* HIF Buffer descriptor status bits */
83 #define DIR_PROC_ID	BIT(16)
84 #define PROC_ID(id)	((id) << 18)
85 
86 #endif /* _HIF_H_ */
87