1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2018-2019 NXP 3 */ 4 5 #ifndef _CLASS_CSR_H_ 6 #define _CLASS_CSR_H_ 7 8 #include <compat.h> 9 10 /* @file class_csr.h. 11 * class_csr - block containing all the classifier control and status register. 12 * Mapped on CBUS and accessible from all PE's and ARM. 13 */ 14 #define CLASS_VERSION (CLASS_CSR_BASE_ADDR + 0x000) 15 #define CLASS_TX_CTRL (CLASS_CSR_BASE_ADDR + 0x004) 16 #define CLASS_INQ_PKTPTR (CLASS_CSR_BASE_ADDR + 0x010) 17 18 /* (ddr_hdr_size[24:16], lmem_hdr_size[5:0]) */ 19 #define CLASS_HDR_SIZE (CLASS_CSR_BASE_ADDR + 0x014) 20 21 /* LMEM header size for the Classifier block.\ Data in the LMEM 22 * is written from this offset. 23 */ 24 #define CLASS_HDR_SIZE_LMEM(off) ((off) & 0x3f) 25 26 /* DDR header size for the Classifier block.\ Data in the DDR 27 * is written from this offset. 28 */ 29 #define CLASS_HDR_SIZE_DDR(off) (((off) & 0x1ff) << 16) 30 31 #define CLASS_PE0_QB_DM_ADDR0 (CLASS_CSR_BASE_ADDR + 0x020) 32 33 /* DMEM address of first [15:0] and second [31:16] buffers on QB side. */ 34 #define CLASS_PE0_QB_DM_ADDR1 (CLASS_CSR_BASE_ADDR + 0x024) 35 36 /* DMEM address of third [15:0] and fourth [31:16] buffers on QB side. */ 37 #define CLASS_PE0_RO_DM_ADDR0 (CLASS_CSR_BASE_ADDR + 0x060) 38 39 /* DMEM address of first [15:0] and second [31:16] buffers on RO side. */ 40 #define CLASS_PE0_RO_DM_ADDR1 (CLASS_CSR_BASE_ADDR + 0x064) 41 42 /* DMEM address of third [15:0] and fourth [31:16] buffers on RO side. */ 43 44 /* @name Class PE memory access. Allows external PE's and HOST to 45 * read/write PMEM/DMEM memory ranges for each classifier PE. 46 */ 47 /* {sr_pe_mem_cmd[31], csr_pe_mem_wren[27:24], csr_pe_mem_addr[23:0]}, 48 * See \ref XXX_MEM_ACCESS_ADDR for details. 49 */ 50 #define CLASS_MEM_ACCESS_ADDR (CLASS_CSR_BASE_ADDR + 0x100) 51 52 /* Internal Memory Access Write Data [31:0] */ 53 #define CLASS_MEM_ACCESS_WDATA (CLASS_CSR_BASE_ADDR + 0x104) 54 55 /* Internal Memory Access Read Data [31:0] */ 56 #define CLASS_MEM_ACCESS_RDATA (CLASS_CSR_BASE_ADDR + 0x108) 57 #define CLASS_TM_INQ_ADDR (CLASS_CSR_BASE_ADDR + 0x114) 58 #define CLASS_PE_STATUS (CLASS_CSR_BASE_ADDR + 0x118) 59 60 #define CLASS_PHY1_RX_PKTS (CLASS_CSR_BASE_ADDR + 0x11c) 61 #define CLASS_PHY1_TX_PKTS (CLASS_CSR_BASE_ADDR + 0x120) 62 #define CLASS_PHY1_LP_FAIL_PKTS (CLASS_CSR_BASE_ADDR + 0x124) 63 #define CLASS_PHY1_INTF_FAIL_PKTS (CLASS_CSR_BASE_ADDR + 0x128) 64 #define CLASS_PHY1_INTF_MATCH_PKTS (CLASS_CSR_BASE_ADDR + 0x12c) 65 #define CLASS_PHY1_L3_FAIL_PKTS (CLASS_CSR_BASE_ADDR + 0x130) 66 #define CLASS_PHY1_V4_PKTS (CLASS_CSR_BASE_ADDR + 0x134) 67 #define CLASS_PHY1_V6_PKTS (CLASS_CSR_BASE_ADDR + 0x138) 68 #define CLASS_PHY1_CHKSUM_ERR_PKTS (CLASS_CSR_BASE_ADDR + 0x13c) 69 #define CLASS_PHY1_TTL_ERR_PKTS (CLASS_CSR_BASE_ADDR + 0x140) 70 #define CLASS_PHY2_RX_PKTS (CLASS_CSR_BASE_ADDR + 0x144) 71 #define CLASS_PHY2_TX_PKTS (CLASS_CSR_BASE_ADDR + 0x148) 72 #define CLASS_PHY2_LP_FAIL_PKTS (CLASS_CSR_BASE_ADDR + 0x14c) 73 #define CLASS_PHY2_INTF_FAIL_PKTS (CLASS_CSR_BASE_ADDR + 0x150) 74 #define CLASS_PHY2_INTF_MATCH_PKTS (CLASS_CSR_BASE_ADDR + 0x154) 75 #define CLASS_PHY2_L3_FAIL_PKTS (CLASS_CSR_BASE_ADDR + 0x158) 76 #define CLASS_PHY2_V4_PKTS (CLASS_CSR_BASE_ADDR + 0x15c) 77 #define CLASS_PHY2_V6_PKTS (CLASS_CSR_BASE_ADDR + 0x160) 78 #define CLASS_PHY2_CHKSUM_ERR_PKTS (CLASS_CSR_BASE_ADDR + 0x164) 79 #define CLASS_PHY2_TTL_ERR_PKTS (CLASS_CSR_BASE_ADDR + 0x168) 80 #define CLASS_PHY3_RX_PKTS (CLASS_CSR_BASE_ADDR + 0x16c) 81 #define CLASS_PHY3_TX_PKTS (CLASS_CSR_BASE_ADDR + 0x170) 82 #define CLASS_PHY3_LP_FAIL_PKTS (CLASS_CSR_BASE_ADDR + 0x174) 83 #define CLASS_PHY3_INTF_FAIL_PKTS (CLASS_CSR_BASE_ADDR + 0x178) 84 #define CLASS_PHY3_INTF_MATCH_PKTS (CLASS_CSR_BASE_ADDR + 0x17c) 85 #define CLASS_PHY3_L3_FAIL_PKTS (CLASS_CSR_BASE_ADDR + 0x180) 86 #define CLASS_PHY3_V4_PKTS (CLASS_CSR_BASE_ADDR + 0x184) 87 #define CLASS_PHY3_V6_PKTS (CLASS_CSR_BASE_ADDR + 0x188) 88 #define CLASS_PHY3_CHKSUM_ERR_PKTS (CLASS_CSR_BASE_ADDR + 0x18c) 89 #define CLASS_PHY3_TTL_ERR_PKTS (CLASS_CSR_BASE_ADDR + 0x190) 90 #define CLASS_PHY1_ICMP_PKTS (CLASS_CSR_BASE_ADDR + 0x194) 91 #define CLASS_PHY1_IGMP_PKTS (CLASS_CSR_BASE_ADDR + 0x198) 92 #define CLASS_PHY1_TCP_PKTS (CLASS_CSR_BASE_ADDR + 0x19c) 93 #define CLASS_PHY1_UDP_PKTS (CLASS_CSR_BASE_ADDR + 0x1a0) 94 #define CLASS_PHY2_ICMP_PKTS (CLASS_CSR_BASE_ADDR + 0x1a4) 95 #define CLASS_PHY2_IGMP_PKTS (CLASS_CSR_BASE_ADDR + 0x1a8) 96 #define CLASS_PHY2_TCP_PKTS (CLASS_CSR_BASE_ADDR + 0x1ac) 97 #define CLASS_PHY2_UDP_PKTS (CLASS_CSR_BASE_ADDR + 0x1b0) 98 #define CLASS_PHY3_ICMP_PKTS (CLASS_CSR_BASE_ADDR + 0x1b4) 99 #define CLASS_PHY3_IGMP_PKTS (CLASS_CSR_BASE_ADDR + 0x1b8) 100 #define CLASS_PHY3_TCP_PKTS (CLASS_CSR_BASE_ADDR + 0x1bc) 101 #define CLASS_PHY3_UDP_PKTS (CLASS_CSR_BASE_ADDR + 0x1c0) 102 #define CLASS_PHY4_ICMP_PKTS (CLASS_CSR_BASE_ADDR + 0x1c4) 103 #define CLASS_PHY4_IGMP_PKTS (CLASS_CSR_BASE_ADDR + 0x1c8) 104 #define CLASS_PHY4_TCP_PKTS (CLASS_CSR_BASE_ADDR + 0x1cc) 105 #define CLASS_PHY4_UDP_PKTS (CLASS_CSR_BASE_ADDR + 0x1d0) 106 #define CLASS_PHY4_RX_PKTS (CLASS_CSR_BASE_ADDR + 0x1d4) 107 #define CLASS_PHY4_TX_PKTS (CLASS_CSR_BASE_ADDR + 0x1d8) 108 #define CLASS_PHY4_LP_FAIL_PKTS (CLASS_CSR_BASE_ADDR + 0x1dc) 109 #define CLASS_PHY4_INTF_FAIL_PKTS (CLASS_CSR_BASE_ADDR + 0x1e0) 110 #define CLASS_PHY4_INTF_MATCH_PKTS (CLASS_CSR_BASE_ADDR + 0x1e4) 111 #define CLASS_PHY4_L3_FAIL_PKTS (CLASS_CSR_BASE_ADDR + 0x1e8) 112 #define CLASS_PHY4_V4_PKTS (CLASS_CSR_BASE_ADDR + 0x1ec) 113 #define CLASS_PHY4_V6_PKTS (CLASS_CSR_BASE_ADDR + 0x1f0) 114 #define CLASS_PHY4_CHKSUM_ERR_PKTS (CLASS_CSR_BASE_ADDR + 0x1f4) 115 #define CLASS_PHY4_TTL_ERR_PKTS (CLASS_CSR_BASE_ADDR + 0x1f8) 116 117 #define CLASS_PE_SYS_CLK_RATIO (CLASS_CSR_BASE_ADDR + 0x200) 118 #define CLASS_AFULL_THRES (CLASS_CSR_BASE_ADDR + 0x204) 119 #define CLASS_GAP_BETWEEN_READS (CLASS_CSR_BASE_ADDR + 0x208) 120 #define CLASS_MAX_BUF_CNT (CLASS_CSR_BASE_ADDR + 0x20c) 121 #define CLASS_TSQ_FIFO_THRES (CLASS_CSR_BASE_ADDR + 0x210) 122 #define CLASS_TSQ_MAX_CNT (CLASS_CSR_BASE_ADDR + 0x214) 123 #define CLASS_IRAM_DATA_0 (CLASS_CSR_BASE_ADDR + 0x218) 124 #define CLASS_IRAM_DATA_1 (CLASS_CSR_BASE_ADDR + 0x21c) 125 #define CLASS_IRAM_DATA_2 (CLASS_CSR_BASE_ADDR + 0x220) 126 #define CLASS_IRAM_DATA_3 (CLASS_CSR_BASE_ADDR + 0x224) 127 128 #define CLASS_BUS_ACCESS_ADDR (CLASS_CSR_BASE_ADDR + 0x228) 129 130 #define CLASS_BUS_ACCESS_WDATA (CLASS_CSR_BASE_ADDR + 0x22c) 131 #define CLASS_BUS_ACCESS_RDATA (CLASS_CSR_BASE_ADDR + 0x230) 132 133 /* (route_entry_size[9:0], route_hash_size[23:16] 134 * (this is actually ln2(size))) 135 */ 136 #define CLASS_ROUTE_HASH_ENTRY_SIZE (CLASS_CSR_BASE_ADDR + 0x234) 137 138 #define CLASS_ROUTE_ENTRY_SIZE(size) ((size) & 0x1ff) 139 #define CLASS_ROUTE_HASH_SIZE(hash_bits) (((hash_bits) & 0xff) << 16) 140 141 #define CLASS_ROUTE_TABLE_BASE (CLASS_CSR_BASE_ADDR + 0x238) 142 143 #define CLASS_ROUTE_MULTI (CLASS_CSR_BASE_ADDR + 0x23c) 144 #define CLASS_SMEM_OFFSET (CLASS_CSR_BASE_ADDR + 0x240) 145 #define CLASS_LMEM_BUF_SIZE (CLASS_CSR_BASE_ADDR + 0x244) 146 #define CLASS_VLAN_ID (CLASS_CSR_BASE_ADDR + 0x248) 147 #define CLASS_BMU1_BUF_FREE (CLASS_CSR_BASE_ADDR + 0x24c) 148 #define CLASS_USE_TMU_INQ (CLASS_CSR_BASE_ADDR + 0x250) 149 #define CLASS_VLAN_ID1 (CLASS_CSR_BASE_ADDR + 0x254) 150 151 #define CLASS_BUS_ACCESS_BASE (CLASS_CSR_BASE_ADDR + 0x258) 152 #define CLASS_BUS_ACCESS_BASE_MASK (0xFF000000) 153 /* bit 31:24 of PE peripheral address are stored in CLASS_BUS_ACCESS_BASE */ 154 155 #define CLASS_HIF_PARSE (CLASS_CSR_BASE_ADDR + 0x25c) 156 157 #define CLASS_HOST_PE0_GP (CLASS_CSR_BASE_ADDR + 0x260) 158 #define CLASS_PE0_GP (CLASS_CSR_BASE_ADDR + 0x264) 159 #define CLASS_HOST_PE1_GP (CLASS_CSR_BASE_ADDR + 0x268) 160 #define CLASS_PE1_GP (CLASS_CSR_BASE_ADDR + 0x26c) 161 #define CLASS_HOST_PE2_GP (CLASS_CSR_BASE_ADDR + 0x270) 162 #define CLASS_PE2_GP (CLASS_CSR_BASE_ADDR + 0x274) 163 #define CLASS_HOST_PE3_GP (CLASS_CSR_BASE_ADDR + 0x278) 164 #define CLASS_PE3_GP (CLASS_CSR_BASE_ADDR + 0x27c) 165 #define CLASS_HOST_PE4_GP (CLASS_CSR_BASE_ADDR + 0x280) 166 #define CLASS_PE4_GP (CLASS_CSR_BASE_ADDR + 0x284) 167 #define CLASS_HOST_PE5_GP (CLASS_CSR_BASE_ADDR + 0x288) 168 #define CLASS_PE5_GP (CLASS_CSR_BASE_ADDR + 0x28c) 169 170 #define CLASS_PE_INT_SRC (CLASS_CSR_BASE_ADDR + 0x290) 171 #define CLASS_PE_INT_ENABLE (CLASS_CSR_BASE_ADDR + 0x294) 172 173 #define CLASS_TPID0_TPID1 (CLASS_CSR_BASE_ADDR + 0x298) 174 #define CLASS_TPID2 (CLASS_CSR_BASE_ADDR + 0x29c) 175 176 #define CLASS_L4_CHKSUM_ADDR (CLASS_CSR_BASE_ADDR + 0x2a0) 177 178 #define CLASS_PE0_DEBUG (CLASS_CSR_BASE_ADDR + 0x2a4) 179 #define CLASS_PE1_DEBUG (CLASS_CSR_BASE_ADDR + 0x2a8) 180 #define CLASS_PE2_DEBUG (CLASS_CSR_BASE_ADDR + 0x2ac) 181 #define CLASS_PE3_DEBUG (CLASS_CSR_BASE_ADDR + 0x2b0) 182 #define CLASS_PE4_DEBUG (CLASS_CSR_BASE_ADDR + 0x2b4) 183 #define CLASS_PE5_DEBUG (CLASS_CSR_BASE_ADDR + 0x2b8) 184 185 #define CLASS_STATE (CLASS_CSR_BASE_ADDR + 0x2bc) 186 187 /* CLASS defines */ 188 #define CLASS_PBUF_SIZE 0x100 /* Fixed by hardware */ 189 #define CLASS_PBUF_HEADER_OFFSET 0x80 /* Can be configured */ 190 191 /* Can be configured */ 192 #define CLASS_PBUF0_BASE_ADDR 0x000 193 /* Can be configured */ 194 #define CLASS_PBUF1_BASE_ADDR (CLASS_PBUF0_BASE_ADDR + CLASS_PBUF_SIZE) 195 /* Can be configured */ 196 #define CLASS_PBUF2_BASE_ADDR (CLASS_PBUF1_BASE_ADDR + CLASS_PBUF_SIZE) 197 /* Can be configured */ 198 #define CLASS_PBUF3_BASE_ADDR (CLASS_PBUF2_BASE_ADDR + CLASS_PBUF_SIZE) 199 200 #define CLASS_PBUF0_HEADER_BASE_ADDR (CLASS_PBUF0_BASE_ADDR + \ 201 CLASS_PBUF_HEADER_OFFSET) 202 #define CLASS_PBUF1_HEADER_BASE_ADDR (CLASS_PBUF1_BASE_ADDR + \ 203 CLASS_PBUF_HEADER_OFFSET) 204 #define CLASS_PBUF2_HEADER_BASE_ADDR (CLASS_PBUF2_BASE_ADDR + \ 205 CLASS_PBUF_HEADER_OFFSET) 206 #define CLASS_PBUF3_HEADER_BASE_ADDR (CLASS_PBUF3_BASE_ADDR + \ 207 CLASS_PBUF_HEADER_OFFSET) 208 209 #define CLASS_PE0_RO_DM_ADDR0_VAL ((CLASS_PBUF1_BASE_ADDR << 16) | \ 210 CLASS_PBUF0_BASE_ADDR) 211 #define CLASS_PE0_RO_DM_ADDR1_VAL ((CLASS_PBUF3_BASE_ADDR << 16) | \ 212 CLASS_PBUF2_BASE_ADDR) 213 214 #define CLASS_PE0_QB_DM_ADDR0_VAL ((CLASS_PBUF1_HEADER_BASE_ADDR << 16) |\ 215 CLASS_PBUF0_HEADER_BASE_ADDR) 216 #define CLASS_PE0_QB_DM_ADDR1_VAL ((CLASS_PBUF3_HEADER_BASE_ADDR << 16) |\ 217 CLASS_PBUF2_HEADER_BASE_ADDR) 218 219 #define CLASS_ROUTE_SIZE 128 220 #define CLASS_MAX_ROUTE_SIZE 256 221 #define CLASS_ROUTE_HASH_BITS 20 222 #define CLASS_ROUTE_HASH_MASK (BIT(CLASS_ROUTE_HASH_BITS) - 1) 223 224 /* Can be configured */ 225 #define CLASS_ROUTE0_BASE_ADDR 0x400 226 /* Can be configured */ 227 #define CLASS_ROUTE1_BASE_ADDR (CLASS_ROUTE0_BASE_ADDR + CLASS_ROUTE_SIZE) 228 /* Can be configured */ 229 #define CLASS_ROUTE2_BASE_ADDR (CLASS_ROUTE1_BASE_ADDR + CLASS_ROUTE_SIZE) 230 /* Can be configured */ 231 #define CLASS_ROUTE3_BASE_ADDR (CLASS_ROUTE2_BASE_ADDR + CLASS_ROUTE_SIZE) 232 233 #define CLASS_SA_SIZE 128 234 #define CLASS_IPSEC_SA0_BASE_ADDR 0x600 235 /* not used */ 236 #define CLASS_IPSEC_SA1_BASE_ADDR (CLASS_IPSEC_SA0_BASE_ADDR + CLASS_SA_SIZE) 237 /* not used */ 238 #define CLASS_IPSEC_SA2_BASE_ADDR (CLASS_IPSEC_SA1_BASE_ADDR + CLASS_SA_SIZE) 239 /* not used */ 240 #define CLASS_IPSEC_SA3_BASE_ADDR (CLASS_IPSEC_SA2_BASE_ADDR + CLASS_SA_SIZE) 241 242 /* generic purpose free dmem buffer, last portion of 2K dmem pbuf */ 243 #define CLASS_GP_DMEM_BUF_SIZE (2048 - (CLASS_PBUF_SIZE * 4) - \ 244 (CLASS_ROUTE_SIZE * 4) - (CLASS_SA_SIZE)) 245 #define CLASS_GP_DMEM_BUF ((void *)(CLASS_IPSEC_SA0_BASE_ADDR + \ 246 CLASS_SA_SIZE)) 247 248 #define TWO_LEVEL_ROUTE BIT(0) 249 #define PHYNO_IN_HASH BIT(1) 250 #define HW_ROUTE_FETCH BIT(3) 251 #define HW_BRIDGE_FETCH BIT(5) 252 #define IP_ALIGNED BIT(6) 253 #define ARC_HIT_CHECK_EN BIT(7) 254 #define CLASS_TOE BIT(11) 255 #define HASH_NORMAL (0 << 12) 256 #define HASH_CRC_PORT BIT(12) 257 #define HASH_CRC_IP (2 << 12) 258 #define HASH_CRC_PORT_IP (3 << 12) 259 #define QB2BUS_LE BIT(15) 260 261 #define TCP_CHKSUM_DROP BIT(0) 262 #define UDP_CHKSUM_DROP BIT(1) 263 #define IPV4_CHKSUM_DROP BIT(9) 264 265 /*CLASS_HIF_PARSE bits*/ 266 #define HIF_PKT_CLASS_EN BIT(0) 267 #define HIF_PKT_OFFSET(ofst) (((ofst) & 0xF) << 1) 268 269 struct class_cfg { 270 u32 toe_mode; 271 unsigned long route_table_baseaddr; 272 u32 route_table_hash_bits; 273 u32 pe_sys_clk_ratio; 274 u32 resume; 275 }; 276 277 #endif /* _CLASS_CSR_H_ */ 278