1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2018-2019 NXP 3 */ 4 5 #ifndef _CBUS_H_ 6 #define _CBUS_H_ 7 8 #include <compat.h> 9 10 #define EMAC1_BASE_ADDR (CBUS_BASE_ADDR + 0x200000) 11 #define EGPI1_BASE_ADDR (CBUS_BASE_ADDR + 0x210000) 12 #define EMAC2_BASE_ADDR (CBUS_BASE_ADDR + 0x220000) 13 #define EGPI2_BASE_ADDR (CBUS_BASE_ADDR + 0x230000) 14 #define BMU1_BASE_ADDR (CBUS_BASE_ADDR + 0x240000) 15 #define BMU2_BASE_ADDR (CBUS_BASE_ADDR + 0x250000) 16 #define ARB_BASE_ADDR (CBUS_BASE_ADDR + 0x260000) 17 #define DDR_CONFIG_BASE_ADDR (CBUS_BASE_ADDR + 0x270000) 18 #define HIF_BASE_ADDR (CBUS_BASE_ADDR + 0x280000) 19 #define HGPI_BASE_ADDR (CBUS_BASE_ADDR + 0x290000) 20 #define LMEM_BASE_ADDR (CBUS_BASE_ADDR + 0x300000) 21 #define LMEM_SIZE 0x10000 22 #define LMEM_END (LMEM_BASE_ADDR + LMEM_SIZE) 23 #define TMU_CSR_BASE_ADDR (CBUS_BASE_ADDR + 0x310000) 24 #define CLASS_CSR_BASE_ADDR (CBUS_BASE_ADDR + 0x320000) 25 #define HIF_NOCPY_BASE_ADDR (CBUS_BASE_ADDR + 0x350000) 26 #define UTIL_CSR_BASE_ADDR (CBUS_BASE_ADDR + 0x360000) 27 #define CBUS_GPT_BASE_ADDR (CBUS_BASE_ADDR + 0x370000) 28 29 /* 30 * defgroup XXX_MEM_ACCESS_ADDR PE memory access through CSR 31 * XXX_MEM_ACCESS_ADDR register bit definitions. 32 */ 33 #define PE_MEM_ACCESS_WRITE BIT(31) /* Internal Memory Write. */ 34 #define PE_MEM_ACCESS_IMEM BIT(15) 35 #define PE_MEM_ACCESS_DMEM BIT(16) 36 37 /* Byte Enables of the Internal memory access. These are interpred in BE */ 38 #define PE_MEM_ACCESS_BYTE_ENABLE(offset, size) \ 39 __extension__ ({ typeof(size) size_ = (size); \ 40 (((BIT(size_) - 1) << (4 - (offset) - (size_))) & 0xf) << 24; }) 41 42 #include "cbus/emac_mtip.h" 43 #include "cbus/gpi.h" 44 #include "cbus/bmu.h" 45 #include "cbus/hif.h" 46 #include "cbus/tmu_csr.h" 47 #include "cbus/class_csr.h" 48 #include "cbus/hif_nocpy.h" 49 #include "cbus/util_csr.h" 50 51 /* PFE cores states */ 52 #define CORE_DISABLE 0x00000000 53 #define CORE_ENABLE 0x00000001 54 #define CORE_SW_RESET 0x00000002 55 56 /* LMEM defines */ 57 #define LMEM_HDR_SIZE 0x0010 58 #define LMEM_BUF_SIZE_LN2 0x7 59 #define LMEM_BUF_SIZE BIT(LMEM_BUF_SIZE_LN2) 60 61 /* DDR defines */ 62 #define DDR_HDR_SIZE 0x0100 63 #define DDR_BUF_SIZE_LN2 0xb 64 #define DDR_BUF_SIZE BIT(DDR_BUF_SIZE_LN2) 65 66 #endif /* _CBUS_H_ */ 67