1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2017 Cavium, Inc 3 */ 4 5 #ifndef __OCTEONTX_ETHDEV_H__ 6 #define __OCTEONTX_ETHDEV_H__ 7 8 #include <stdbool.h> 9 10 #include <rte_common.h> 11 #include <rte_ethdev_driver.h> 12 #include <rte_eventdev.h> 13 #include <rte_mempool.h> 14 #include <rte_memory.h> 15 16 #include <octeontx_fpavf.h> 17 18 #include "base/octeontx_bgx.h" 19 #include "base/octeontx_pki_var.h" 20 #include "base/octeontx_pkivf.h" 21 #include "base/octeontx_pkovf.h" 22 #include "base/octeontx_io.h" 23 24 #define OCTEONTX_VDEV_DEFAULT_MAX_NR_PORT 12 25 #define OCTEONTX_VDEV_NR_PORT_ARG ("nr_port") 26 #define OCTEONTX_MAX_NAME_LEN 32 27 28 #define OCTEONTX_MAX_BGX_PORTS 4 29 #define OCTEONTX_MAX_LMAC_PER_BGX 4 30 31 static inline struct octeontx_nic * 32 octeontx_pmd_priv(struct rte_eth_dev *dev) 33 { 34 return dev->data->dev_private; 35 } 36 37 extern uint16_t 38 rte_octeontx_pchan_map[OCTEONTX_MAX_BGX_PORTS][OCTEONTX_MAX_LMAC_PER_BGX]; 39 40 /* Octeontx ethdev nic */ 41 struct octeontx_nic { 42 struct rte_eth_dev *dev; 43 int node; 44 int port_id; 45 int port_ena; 46 int base_ichan; 47 int num_ichans; 48 int base_ochan; 49 int num_ochans; 50 uint8_t evdev; 51 uint8_t bpen; 52 uint8_t fcs_strip; 53 uint8_t bcast_mode; 54 uint8_t mcast_mode; 55 uint16_t num_tx_queues; 56 uint64_t hwcap; 57 uint8_t link_up; 58 uint8_t duplex; 59 uint8_t speed; 60 uint16_t mtu; 61 uint8_t mac_addr[ETHER_ADDR_LEN]; 62 /* Rx port parameters */ 63 struct { 64 bool classifier_enable; 65 bool hash_enable; 66 bool initialized; 67 } pki; 68 69 uint16_t ev_queues; 70 uint16_t ev_ports; 71 } __rte_cache_aligned; 72 73 struct octeontx_txq { 74 uint16_t queue_id; 75 octeontx_dq_t dq; 76 struct rte_eth_dev *eth_dev; 77 } __rte_cache_aligned; 78 79 struct octeontx_rxq { 80 uint16_t queue_id; 81 uint16_t port_id; 82 uint8_t evdev; 83 struct rte_eth_dev *eth_dev; 84 uint16_t ev_queues; 85 uint16_t ev_ports; 86 } __rte_cache_aligned; 87 88 #endif /* __OCTEONTX_ETHDEV_H__ */ 89