1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2017 Cavium, Inc 3 */ 4 5 #ifndef __OCTEONTX_ETHDEV_H__ 6 #define __OCTEONTX_ETHDEV_H__ 7 8 #include <stdbool.h> 9 10 #include <rte_common.h> 11 #include <rte_ethdev_driver.h> 12 #include <rte_eventdev.h> 13 #include <rte_mempool.h> 14 #include <rte_memory.h> 15 16 #include <octeontx_fpavf.h> 17 18 #include "base/octeontx_bgx.h" 19 #include "base/octeontx_pki_var.h" 20 #include "base/octeontx_pkivf.h" 21 #include "base/octeontx_pkovf.h" 22 #include "base/octeontx_io.h" 23 24 #define OCTEONTX_PMD net_octeontx 25 #define OCTEONTX_VDEV_DEFAULT_MAX_NR_PORT 12 26 #define OCTEONTX_VDEV_NR_PORT_ARG ("nr_port") 27 #define OCTEONTX_MAX_NAME_LEN 32 28 29 #define OCTEONTX_MAX_BGX_PORTS 4 30 #define OCTEONTX_MAX_LMAC_PER_BGX 4 31 32 #define OCCTX_RX_NB_SEG_MAX 6 33 34 /* VLAN tag inserted by OCCTX_TX_VTAG_ACTION. 35 * In Tx space is always reserved for this in FRS. 36 */ 37 #define OCCTX_MAX_VTAG_INS 2 38 #define OCCTX_MAX_VTAG_ACT_SIZE (4 * OCCTX_MAX_VTAG_INS) 39 40 /* HW config of frame size doesn't include FCS */ 41 #define OCCTX_MAX_HW_FRS 9212 42 #define OCCTX_MIN_HW_FRS 60 43 44 /* ETH_HLEN+ETH_FCS+2*VLAN_HLEN */ 45 #define OCCTX_L2_OVERHEAD (RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN + \ 46 OCCTX_MAX_VTAG_ACT_SIZE) 47 48 /* Since HW FRS includes NPC VTAG insertion space, user has reduced FRS */ 49 #define OCCTX_MAX_FRS \ 50 (OCCTX_MAX_HW_FRS + RTE_ETHER_CRC_LEN - OCCTX_MAX_VTAG_ACT_SIZE) 51 52 #define OCCTX_MIN_FRS (OCCTX_MIN_HW_FRS + RTE_ETHER_CRC_LEN) 53 54 #define OCCTX_MAX_MTU (OCCTX_MAX_FRS - OCCTX_L2_OVERHEAD) 55 56 #define OCTEONTX_RX_OFFLOADS (DEV_RX_OFFLOAD_CHECKSUM | \ 57 DEV_RX_OFFLOAD_SCATTER | \ 58 DEV_RX_OFFLOAD_JUMBO_FRAME | \ 59 DEV_RX_OFFLOAD_VLAN_FILTER) 60 61 #define OCTEONTX_TX_OFFLOADS (DEV_TX_OFFLOAD_MT_LOCKFREE | \ 62 DEV_TX_OFFLOAD_MBUF_FAST_FREE | \ 63 DEV_TX_OFFLOAD_MULTI_SEGS) 64 65 static inline struct octeontx_nic * 66 octeontx_pmd_priv(struct rte_eth_dev *dev) 67 { 68 return dev->data->dev_private; 69 } 70 71 extern uint16_t 72 rte_octeontx_pchan_map[OCTEONTX_MAX_BGX_PORTS][OCTEONTX_MAX_LMAC_PER_BGX]; 73 74 struct vlan_entry { 75 TAILQ_ENTRY(vlan_entry) next; 76 uint16_t vlan_id; 77 }; 78 79 TAILQ_HEAD(octeontx_vlan_filter_tbl, vlan_entry); 80 81 struct octeontx_vlan_info { 82 struct octeontx_vlan_filter_tbl fltr_tbl; 83 uint8_t filter_on; 84 }; 85 86 /* Octeontx ethdev nic */ 87 struct octeontx_nic { 88 struct rte_eth_dev *dev; 89 int node; 90 int port_id; 91 int port_ena; 92 int base_ichan; 93 int num_ichans; 94 int base_ochan; 95 int num_ochans; 96 uint8_t evdev; 97 uint8_t bpen; 98 uint8_t fcs_strip; 99 uint8_t bcast_mode; 100 uint8_t mcast_mode; 101 uint16_t num_tx_queues; 102 uint64_t hwcap; 103 uint8_t pko_vfid; 104 uint8_t link_up; 105 uint8_t duplex; 106 uint8_t speed; 107 uint16_t bgx_mtu; 108 uint16_t mtu; 109 uint8_t mac_addr[RTE_ETHER_ADDR_LEN]; 110 /* Rx port parameters */ 111 struct { 112 bool classifier_enable; 113 bool hash_enable; 114 bool initialized; 115 } pki; 116 117 uint16_t ev_queues; 118 uint16_t ev_ports; 119 uint64_t rx_offloads; 120 uint16_t rx_offload_flags; 121 uint64_t tx_offloads; 122 uint16_t tx_offload_flags; 123 struct octeontx_vlan_info vlan_info; 124 } __rte_cache_aligned; 125 126 struct octeontx_txq { 127 uint16_t queue_id; 128 octeontx_dq_t dq; 129 struct rte_eth_dev *eth_dev; 130 } __rte_cache_aligned; 131 132 struct octeontx_rxq { 133 uint16_t queue_id; 134 uint16_t port_id; 135 uint8_t evdev; 136 struct rte_eth_dev *eth_dev; 137 uint16_t ev_queues; 138 uint16_t ev_ports; 139 struct rte_mempool *pool; 140 } __rte_cache_aligned; 141 142 void 143 octeontx_set_tx_function(struct rte_eth_dev *dev); 144 145 /* VLAN */ 146 int octeontx_dev_vlan_offload_init(struct rte_eth_dev *dev); 147 int octeontx_dev_vlan_offload_fini(struct rte_eth_dev *eth_dev); 148 int octeontx_dev_vlan_offload_set(struct rte_eth_dev *dev, int mask); 149 int octeontx_dev_vlan_filter_set(struct rte_eth_dev *dev, 150 uint16_t vlan_id, int on); 151 152 #endif /* __OCTEONTX_ETHDEV_H__ */ 153