1 /* 2 * BSD LICENSE 3 * 4 * Copyright (C) Cavium Inc. 2017. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 10 * * Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * * Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in 14 * the documentation and/or other materials provided with the 15 * distribution. 16 * * Neither the name of Cavium networks nor the names of its 17 * contributors may be used to endorse or promote products derived 18 * from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 23 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 24 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 25 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 26 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 #include <string.h> 33 34 #include <rte_eal.h> 35 #include <rte_pci.h> 36 37 #include "octeontx_pkivf.h" 38 39 int 40 octeontx_pki_port_open(int port) 41 { 42 struct octeontx_mbox_hdr hdr; 43 int res; 44 45 hdr.coproc = OCTEONTX_PKI_COPROC; 46 hdr.msg = MBOX_PKI_PORT_OPEN; 47 hdr.vfid = port; 48 49 res = octeontx_ssovf_mbox_send(&hdr, NULL, 0, NULL, 0); 50 if (res < 0) 51 return -EACCES; 52 return res; 53 } 54 55 int 56 octeontx_pki_port_hash_config(int port, pki_hash_cfg_t *hash_cfg) 57 { 58 struct octeontx_mbox_hdr hdr; 59 int res; 60 61 mbox_pki_hash_cfg_t h_cfg = *(mbox_pki_hash_cfg_t *)hash_cfg; 62 int len = sizeof(mbox_pki_hash_cfg_t); 63 64 hdr.coproc = OCTEONTX_PKI_COPROC; 65 hdr.msg = MBOX_PKI_PORT_HASH_CONFIG; 66 hdr.vfid = port; 67 68 res = octeontx_ssovf_mbox_send(&hdr, &h_cfg, len, NULL, 0); 69 if (res < 0) 70 return -EACCES; 71 72 return res; 73 } 74 75 int 76 octeontx_pki_port_pktbuf_config(int port, pki_pktbuf_cfg_t *buf_cfg) 77 { 78 struct octeontx_mbox_hdr hdr; 79 int res; 80 81 mbox_pki_pktbuf_cfg_t b_cfg = *(mbox_pki_pktbuf_cfg_t *)buf_cfg; 82 int len = sizeof(mbox_pki_pktbuf_cfg_t); 83 84 hdr.coproc = OCTEONTX_PKI_COPROC; 85 hdr.msg = MBOX_PKI_PORT_PKTBUF_CONFIG; 86 hdr.vfid = port; 87 88 res = octeontx_ssovf_mbox_send(&hdr, &b_cfg, len, NULL, 0); 89 if (res < 0) 90 return -EACCES; 91 return res; 92 } 93 94 int 95 octeontx_pki_port_create_qos(int port, pki_qos_cfg_t *qos_cfg) 96 { 97 struct octeontx_mbox_hdr hdr; 98 int res; 99 100 mbox_pki_qos_cfg_t q_cfg = *(mbox_pki_qos_cfg_t *)qos_cfg; 101 int len = sizeof(mbox_pki_qos_cfg_t); 102 103 hdr.coproc = OCTEONTX_PKI_COPROC; 104 hdr.msg = MBOX_PKI_PORT_CREATE_QOS; 105 hdr.vfid = port; 106 107 res = octeontx_ssovf_mbox_send(&hdr, &q_cfg, len, NULL, 0); 108 if (res < 0) 109 return -EACCES; 110 111 return res; 112 } 113 114 int 115 octeontx_pki_port_close(int port) 116 { 117 struct octeontx_mbox_hdr hdr; 118 int res; 119 120 mbox_pki_port_t ptype; 121 int len = sizeof(mbox_pki_port_t); 122 memset(&ptype, 0, len); 123 ptype.port_type = OCTTX_PORT_TYPE_NET; 124 125 hdr.coproc = OCTEONTX_PKI_COPROC; 126 hdr.msg = MBOX_PKI_PORT_CLOSE; 127 hdr.vfid = port; 128 129 res = octeontx_ssovf_mbox_send(&hdr, &ptype, len, NULL, 0); 130 if (res < 0) 131 return -EACCES; 132 133 return res; 134 } 135 136 int 137 octeontx_pki_port_start(int port) 138 { 139 struct octeontx_mbox_hdr hdr; 140 int res; 141 142 mbox_pki_port_t ptype; 143 int len = sizeof(mbox_pki_port_t); 144 memset(&ptype, 0, len); 145 ptype.port_type = OCTTX_PORT_TYPE_NET; 146 147 hdr.coproc = OCTEONTX_PKI_COPROC; 148 hdr.msg = MBOX_PKI_PORT_START; 149 hdr.vfid = port; 150 151 res = octeontx_ssovf_mbox_send(&hdr, &ptype, len, NULL, 0); 152 if (res < 0) 153 return -EACCES; 154 155 return res; 156 } 157 158 int 159 octeontx_pki_port_stop(int port) 160 { 161 struct octeontx_mbox_hdr hdr; 162 int res; 163 164 mbox_pki_port_t ptype; 165 int len = sizeof(mbox_pki_port_t); 166 memset(&ptype, 0, len); 167 ptype.port_type = OCTTX_PORT_TYPE_NET; 168 169 hdr.coproc = OCTEONTX_PKI_COPROC; 170 hdr.msg = MBOX_PKI_PORT_STOP; 171 hdr.vfid = port; 172 173 res = octeontx_ssovf_mbox_send(&hdr, &ptype, len, NULL, 0); 174 if (res < 0) 175 return -EACCES; 176 177 return res; 178 } 179 180 int 181 octeontx_pki_port_errchk_config(int port, pki_errchk_cfg_t *cfg) 182 { 183 struct octeontx_mbox_hdr hdr; 184 int res; 185 186 mbox_pki_errcheck_cfg_t e_cfg; 187 e_cfg = *((mbox_pki_errcheck_cfg_t *)(cfg)); 188 int len = sizeof(mbox_pki_errcheck_cfg_t); 189 190 hdr.coproc = OCTEONTX_PKI_COPROC; 191 hdr.msg = MBOX_PKI_PORT_ERRCHK_CONFIG; 192 hdr.vfid = port; 193 194 res = octeontx_ssovf_mbox_send(&hdr, &e_cfg, len, NULL, 0); 195 if (res < 0) 196 return -EACCES; 197 198 return res; 199 } 200 201 #define PCI_VENDOR_ID_CAVIUM 0x177D 202 #define PCI_DEVICE_ID_OCTEONTX_PKI_VF 0xA0DD 203 204 /* PKIVF pcie device */ 205 static int 206 pkivf_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev) 207 { 208 RTE_SET_USED(pci_drv); 209 RTE_SET_USED(pci_dev); 210 211 /* For secondary processes, the primary has done all the work */ 212 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 213 return 0; 214 215 return 0; 216 } 217 218 static const struct rte_pci_id pci_pkivf_map[] = { 219 { 220 RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, 221 PCI_DEVICE_ID_OCTEONTX_PKI_VF) 222 }, 223 { 224 .vendor_id = 0, 225 }, 226 }; 227 228 static struct rte_pci_driver pci_pkivf = { 229 .id_table = pci_pkivf_map, 230 .drv_flags = RTE_PCI_DRV_NEED_MAPPING, 231 .probe = pkivf_probe, 232 }; 233 234 RTE_PMD_REGISTER_PCI(octeontx_pkivf, pci_pkivf); 235