1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2017 Cavium, Inc 3 */ 4 5 #include <string.h> 6 7 #include <rte_eal.h> 8 #include <rte_bus_pci.h> 9 10 #include "../octeontx_logs.h" 11 #include "octeontx_io.h" 12 #include "octeontx_pkivf.h" 13 14 15 struct octeontx_pkivf { 16 uint8_t *bar0; 17 uint8_t status; 18 uint16_t domain; 19 uint16_t vfid; 20 }; 21 22 struct octeontx_pki_vf_ctl_s { 23 struct octeontx_pkivf pki[PKI_VF_MAX]; 24 }; 25 26 static struct octeontx_pki_vf_ctl_s pki_vf_ctl; 27 28 int 29 octeontx_pki_port_open(int port) 30 { 31 uint16_t global_domain = octeontx_get_global_domain(); 32 struct octeontx_mbox_hdr hdr; 33 mbox_pki_port_t port_type = { 34 .port_type = OCTTX_PORT_TYPE_NET, 35 }; 36 int i, res; 37 38 /* Check if atleast one PKI vf is in application domain. */ 39 for (i = 0; i < PKI_VF_MAX; i++) { 40 if (pki_vf_ctl.pki[i].domain != global_domain) 41 continue; 42 break; 43 } 44 45 if (i == PKI_VF_MAX) 46 return -ENODEV; 47 48 hdr.coproc = OCTEONTX_PKI_COPROC; 49 hdr.msg = MBOX_PKI_PORT_OPEN; 50 hdr.vfid = port; 51 52 res = octeontx_mbox_send(&hdr, &port_type, sizeof(mbox_pki_port_t), 53 NULL, 0); 54 if (res < 0) 55 return -EACCES; 56 return res; 57 } 58 59 int 60 octeontx_pki_port_hash_config(int port, pki_hash_cfg_t *hash_cfg) 61 { 62 struct octeontx_mbox_hdr hdr; 63 int res; 64 65 mbox_pki_hash_cfg_t h_cfg = *(mbox_pki_hash_cfg_t *)hash_cfg; 66 int len = sizeof(mbox_pki_hash_cfg_t); 67 68 hdr.coproc = OCTEONTX_PKI_COPROC; 69 hdr.msg = MBOX_PKI_PORT_HASH_CONFIG; 70 hdr.vfid = port; 71 72 res = octeontx_mbox_send(&hdr, &h_cfg, len, NULL, 0); 73 if (res < 0) 74 return -EACCES; 75 76 return res; 77 } 78 79 int 80 octeontx_pki_port_pktbuf_config(int port, pki_pktbuf_cfg_t *buf_cfg) 81 { 82 struct octeontx_mbox_hdr hdr; 83 int res; 84 85 mbox_pki_pktbuf_cfg_t b_cfg = *(mbox_pki_pktbuf_cfg_t *)buf_cfg; 86 int len = sizeof(mbox_pki_pktbuf_cfg_t); 87 88 hdr.coproc = OCTEONTX_PKI_COPROC; 89 hdr.msg = MBOX_PKI_PORT_PKTBUF_CONFIG; 90 hdr.vfid = port; 91 92 res = octeontx_mbox_send(&hdr, &b_cfg, len, NULL, 0); 93 if (res < 0) 94 return -EACCES; 95 return res; 96 } 97 98 int 99 octeontx_pki_port_create_qos(int port, pki_qos_cfg_t *qos_cfg) 100 { 101 struct octeontx_mbox_hdr hdr; 102 int res; 103 104 mbox_pki_qos_cfg_t q_cfg = *(mbox_pki_qos_cfg_t *)qos_cfg; 105 int len = sizeof(mbox_pki_qos_cfg_t); 106 107 hdr.coproc = OCTEONTX_PKI_COPROC; 108 hdr.msg = MBOX_PKI_PORT_CREATE_QOS; 109 hdr.vfid = port; 110 111 res = octeontx_mbox_send(&hdr, &q_cfg, len, NULL, 0); 112 if (res < 0) 113 return -EACCES; 114 115 return res; 116 } 117 118 119 int 120 octeontx_pki_port_errchk_config(int port, pki_errchk_cfg_t *cfg) 121 { 122 struct octeontx_mbox_hdr hdr; 123 int res; 124 125 mbox_pki_errcheck_cfg_t e_cfg; 126 e_cfg = *((mbox_pki_errcheck_cfg_t *)(cfg)); 127 int len = sizeof(mbox_pki_errcheck_cfg_t); 128 129 hdr.coproc = OCTEONTX_PKI_COPROC; 130 hdr.msg = MBOX_PKI_PORT_ERRCHK_CONFIG; 131 hdr.vfid = port; 132 133 res = octeontx_mbox_send(&hdr, &e_cfg, len, NULL, 0); 134 if (res < 0) 135 return -EACCES; 136 137 return res; 138 } 139 140 #define PCI_VENDOR_ID_CAVIUM 0x177D 141 #define PCI_DEVICE_ID_OCTEONTX_PKI_VF 0xA0DD 142 143 /* PKIVF pcie device */ 144 static int 145 pkivf_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev) 146 { 147 struct octeontx_pkivf *res; 148 static uint8_t vf_cnt; 149 uint16_t domain; 150 uint16_t vfid; 151 uint8_t *bar0; 152 uint64_t val; 153 154 RTE_SET_USED(pci_drv); 155 /* For secondary processes, the primary has done all the work */ 156 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 157 return 0; 158 159 if (pci_dev->mem_resource[0].addr == NULL) { 160 octeontx_log_err("PKI Empty bar[0] %p", 161 pci_dev->mem_resource[0].addr); 162 return -ENODEV; 163 } 164 165 bar0 = pci_dev->mem_resource[0].addr; 166 val = octeontx_read64(bar0); 167 domain = val & 0xffff; 168 vfid = (val >> 16) & 0xffff; 169 170 if (unlikely(vfid >= PKI_VF_MAX)) { 171 octeontx_log_err("pki: Invalid vfid %d", vfid); 172 return -EINVAL; 173 } 174 175 res = &pki_vf_ctl.pki[vf_cnt++]; 176 res->vfid = vfid; 177 res->domain = domain; 178 res->bar0 = bar0; 179 180 octeontx_log_dbg("PKI Domain=%d vfid=%d", res->domain, res->vfid); 181 return 0; 182 } 183 184 static const struct rte_pci_id pci_pkivf_map[] = { 185 { 186 RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, 187 PCI_DEVICE_ID_OCTEONTX_PKI_VF) 188 }, 189 { 190 .vendor_id = 0, 191 }, 192 }; 193 194 static struct rte_pci_driver pci_pkivf = { 195 .id_table = pci_pkivf_map, 196 .drv_flags = RTE_PCI_DRV_NEED_MAPPING, 197 .probe = pkivf_probe, 198 }; 199 200 RTE_PMD_REGISTER_PCI(octeontx_pkivf, pci_pkivf); 201