1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2017 Cavium, Inc 3 */ 4 5 #include <string.h> 6 7 #include <rte_eal.h> 8 #include <rte_bus_pci.h> 9 10 #include "octeontx_pkivf.h" 11 12 int 13 octeontx_pki_port_open(int port) 14 { 15 struct octeontx_mbox_hdr hdr; 16 int res; 17 18 hdr.coproc = OCTEONTX_PKI_COPROC; 19 hdr.msg = MBOX_PKI_PORT_OPEN; 20 hdr.vfid = port; 21 22 res = octeontx_mbox_send(&hdr, NULL, 0, NULL, 0); 23 if (res < 0) 24 return -EACCES; 25 return res; 26 } 27 28 int 29 octeontx_pki_port_hash_config(int port, pki_hash_cfg_t *hash_cfg) 30 { 31 struct octeontx_mbox_hdr hdr; 32 int res; 33 34 mbox_pki_hash_cfg_t h_cfg = *(mbox_pki_hash_cfg_t *)hash_cfg; 35 int len = sizeof(mbox_pki_hash_cfg_t); 36 37 hdr.coproc = OCTEONTX_PKI_COPROC; 38 hdr.msg = MBOX_PKI_PORT_HASH_CONFIG; 39 hdr.vfid = port; 40 41 res = octeontx_mbox_send(&hdr, &h_cfg, len, NULL, 0); 42 if (res < 0) 43 return -EACCES; 44 45 return res; 46 } 47 48 int 49 octeontx_pki_port_pktbuf_config(int port, pki_pktbuf_cfg_t *buf_cfg) 50 { 51 struct octeontx_mbox_hdr hdr; 52 int res; 53 54 mbox_pki_pktbuf_cfg_t b_cfg = *(mbox_pki_pktbuf_cfg_t *)buf_cfg; 55 int len = sizeof(mbox_pki_pktbuf_cfg_t); 56 57 hdr.coproc = OCTEONTX_PKI_COPROC; 58 hdr.msg = MBOX_PKI_PORT_PKTBUF_CONFIG; 59 hdr.vfid = port; 60 61 res = octeontx_mbox_send(&hdr, &b_cfg, len, NULL, 0); 62 if (res < 0) 63 return -EACCES; 64 return res; 65 } 66 67 int 68 octeontx_pki_port_create_qos(int port, pki_qos_cfg_t *qos_cfg) 69 { 70 struct octeontx_mbox_hdr hdr; 71 int res; 72 73 mbox_pki_qos_cfg_t q_cfg = *(mbox_pki_qos_cfg_t *)qos_cfg; 74 int len = sizeof(mbox_pki_qos_cfg_t); 75 76 hdr.coproc = OCTEONTX_PKI_COPROC; 77 hdr.msg = MBOX_PKI_PORT_CREATE_QOS; 78 hdr.vfid = port; 79 80 res = octeontx_mbox_send(&hdr, &q_cfg, len, NULL, 0); 81 if (res < 0) 82 return -EACCES; 83 84 return res; 85 } 86 87 88 int 89 octeontx_pki_port_errchk_config(int port, pki_errchk_cfg_t *cfg) 90 { 91 struct octeontx_mbox_hdr hdr; 92 int res; 93 94 mbox_pki_errcheck_cfg_t e_cfg; 95 e_cfg = *((mbox_pki_errcheck_cfg_t *)(cfg)); 96 int len = sizeof(mbox_pki_errcheck_cfg_t); 97 98 hdr.coproc = OCTEONTX_PKI_COPROC; 99 hdr.msg = MBOX_PKI_PORT_ERRCHK_CONFIG; 100 hdr.vfid = port; 101 102 res = octeontx_mbox_send(&hdr, &e_cfg, len, NULL, 0); 103 if (res < 0) 104 return -EACCES; 105 106 return res; 107 } 108 109 #define PCI_VENDOR_ID_CAVIUM 0x177D 110 #define PCI_DEVICE_ID_OCTEONTX_PKI_VF 0xA0DD 111 112 /* PKIVF pcie device */ 113 static int 114 pkivf_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev) 115 { 116 RTE_SET_USED(pci_drv); 117 RTE_SET_USED(pci_dev); 118 119 /* For secondary processes, the primary has done all the work */ 120 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 121 return 0; 122 123 return 0; 124 } 125 126 static const struct rte_pci_id pci_pkivf_map[] = { 127 { 128 RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, 129 PCI_DEVICE_ID_OCTEONTX_PKI_VF) 130 }, 131 { 132 .vendor_id = 0, 133 }, 134 }; 135 136 static struct rte_pci_driver pci_pkivf = { 137 .id_table = pci_pkivf_map, 138 .drv_flags = RTE_PCI_DRV_NEED_MAPPING, 139 .probe = pkivf_probe, 140 }; 141 142 RTE_PMD_REGISTER_PCI(octeontx_pkivf, pci_pkivf); 143