xref: /dpdk/drivers/net/octeon_ep/otx_ep_mbox.h (revision e77506397fc8005c5129e22e9e2d15d5876790fd)
1 /* SPDX-License-Identifier: BSD-3-Clause
2  * Copyright(C) 2021 Marvell.
3  */
4 
5 #ifndef _OTX_EP_MBOX_H_
6 #define _OTX_EP_MBOX_H_
7 
8 /*
9  * When a new command is implemented, VF Mbox version should be bumped.
10  */
11 enum octep_pfvf_mbox_version {
12 	OTX_EP_MBOX_VERSION_V0,
13 	OTX_EP_MBOX_VERSION_V1,
14 	OTX_EP_MBOX_VERSION_V2,
15 	OTX_EP_MBOX_VERSION_V3,
16 };
17 
18 #define OTX_EP_MBOX_VERSION_CURRENT OTX_EP_MBOX_VERSION_V3
19 
20 enum otx_ep_mbox_opcode {
21 	OTX_EP_MBOX_CMD_VERSION,
22 	OTX_EP_MBOX_CMD_SET_MTU,
23 	OTX_EP_MBOX_CMD_SET_MAC_ADDR,
24 	OTX_EP_MBOX_CMD_GET_MAC_ADDR,
25 	OTX_EP_MBOX_CMD_GET_LINK_INFO,
26 	OTX_EP_MBOX_CMD_GET_STATS,
27 	OTX_EP_MBOX_CMD_SET_RX_STATE,
28 	OTX_EP_MBOX_CMD_SET_LINK_STATUS,
29 	OTX_EP_MBOX_CMD_GET_LINK_STATUS,
30 	OTX_EP_MBOX_CMD_GET_MTU,
31 	OTX_EP_MBOX_CMD_DEV_REMOVE,
32 	OTX_EP_MBOX_CMD_GET_FW_INFO,
33 	OTX_EP_MBOX_CMD_SET_OFFLOADS,
34 	OTX_EP_MBOX_NOTIF_LINK_STATUS,
35 	OTX_EP_MBOX_NOTIF_PF_FLR,
36 	OTX_EP_MBOX_CMD_MAX,
37 };
38 
39 enum otx_ep_mbox_word_type {
40 	OTX_EP_MBOX_TYPE_CMD,
41 	OTX_EP_MBOX_TYPE_RSP_ACK,
42 	OTX_EP_MBOX_TYPE_RSP_NACK,
43 };
44 
45 enum otx_ep_mbox_cmd_status {
46 	OTX_EP_MBOX_CMD_STATUS_NOT_SETUP = 1,
47 	OTX_EP_MBOX_CMD_STATUS_TIMEDOUT = 2,
48 	OTX_EP_MBOX_CMD_STATUS_NACK = 3,
49 	OTX_EP_MBOX_CMD_STATUS_BUSY = 4
50 };
51 
52 enum otx_ep_mbox_state {
53 	OTX_EP_MBOX_STATE_IDLE = 0,
54 	OTX_EP_MBOX_STATE_BUSY = 1,
55 };
56 
57 enum otx_ep_link_status {
58 	OTX_EP_LINK_STATUS_DOWN,
59 	OTX_EP_LINK_STATUS_UP,
60 };
61 
62 enum otx_ep_link_duplex {
63 	OTX_EP_LINK_HALF_DUPLEX,
64 	OTX_EP_LINK_FULL_DUPLEX,
65 };
66 
67 enum otx_ep_link_autoneg {
68 	OTX_EP_LINK_FIXED,
69 	OTX_EP_LINK_AUTONEG,
70 };
71 
72 #define OTX_EP_MBOX_TIMEOUT_MS     1200
73 #define OTX_EP_MBOX_MAX_RETRIES    2
74 #define OTX_EP_MBOX_MAX_DATA_SIZE  6
75 #define OTX_EP_MBOX_MAX_DATA_BUF_SIZE 256
76 #define OTX_EP_MBOX_MORE_FRAG_FLAG 1
77 #define OTX_EP_MBOX_WRITE_WAIT_TIME msecs_to_jiffies(1)
78 
79 union __rte_packed_begin otx_ep_mbox_word {
80 	uint64_t u64;
81 	struct {
82 		uint64_t opcode:8;
83 		uint64_t type:2;
84 		uint64_t rsvd:6;
85 		uint64_t data:48;
86 	} s;
87 	struct {
88 		uint64_t opcode:8;
89 		uint64_t type:2;
90 		uint64_t frag:1;
91 		uint64_t rsvd:5;
92 		uint8_t data[6];
93 	} s_data;
94 	struct {
95 		uint64_t opcode:8;
96 		uint64_t type:2;
97 		uint64_t rsvd:6;
98 		uint64_t version:48;
99 	} s_version;
100 	struct {
101 		uint64_t opcode:8;
102 		uint64_t type:2;
103 		uint64_t rsvd:6;
104 		uint8_t mac_addr[6];
105 	} s_set_mac;
106 	struct {
107 		uint64_t opcode:8;
108 		uint64_t type:2;
109 		uint64_t rsvd:6;
110 		uint64_t mtu:48;
111 	} s_set_mtu;
112 	struct {
113 		uint64_t opcode:8;
114 		uint64_t type:2;
115 		uint64_t rsvd:6;
116 		uint64_t mtu:48;
117 	} s_get_mtu;
118 	struct {
119 		uint64_t opcode:8;
120 		uint64_t type:2;
121 		uint64_t state:1;
122 		uint64_t rsvd:53;
123 	} s_link_state;
124 	struct {
125 		uint64_t opcode:8;
126 		uint64_t type:2;
127 		uint64_t status:1;
128 		uint64_t rsvd:53;
129 	} s_link_status;
130 } __rte_packed_end;
131 
132 /* Hardware interface link state information. */
133 struct otx_ep_iface_link_info {
134 	/* Bitmap of Supported link speeds/modes. */
135 	uint64_t supported_modes;
136 
137 	/* Bitmap of Advertised link speeds/modes. */
138 	uint64_t advertised_modes;
139 
140 	/* Negotiated link speed in Mbps. */
141 	uint32_t speed;
142 
143 	/* MTU */
144 	uint16_t mtu;
145 
146 	/* Autonegotiation state. */
147 #define OCTEP_VF_LINK_MODE_AUTONEG_SUPPORTED   BIT(0)
148 #define OCTEP_VF_LINK_MODE_AUTONEG_ADVERTISED  BIT(1)
149 	uint8_t autoneg;
150 
151 	/* Pause frames setting. */
152 #define OCTEP_VF_LINK_MODE_PAUSE_SUPPORTED   BIT(0)
153 #define OCTEP_VF_LINK_MODE_PAUSE_ADVERTISED  BIT(1)
154 	uint8_t pause;
155 
156 	/* Admin state of the link (ifconfig <iface> up/down */
157 	uint8_t  admin_up;
158 
159 	/* Operational state of the link: physical link is up down */
160 	uint8_t  oper_up;
161 };
162 
163 int otx_ep_mbox_set_mtu(struct rte_eth_dev *eth_dev, uint16_t mtu);
164 int otx_ep_mbox_set_mac_addr(struct rte_eth_dev *eth_dev,
165 			     struct rte_ether_addr *mac_addr);
166 int otx_ep_mbox_get_mac_addr(struct rte_eth_dev *eth_dev,
167 			     struct rte_ether_addr *mac_addr);
168 int otx_ep_mbox_get_link_status(struct rte_eth_dev *eth_dev,
169 				uint8_t *oper_up);
170 int otx_ep_mbox_get_link_info(struct rte_eth_dev *eth_dev, struct rte_eth_link *link);
171 void otx_ep_mbox_enable_interrupt(struct otx_ep_device *otx_ep);
172 void otx_ep_mbox_disable_interrupt(struct otx_ep_device *otx_ep);
173 int otx_ep_mbox_get_max_pkt_len(struct rte_eth_dev *eth_dev);
174 int otx_ep_mbox_send_dev_exit(struct rte_eth_dev *eth_dev);
175 int otx_ep_mbox_init(struct rte_eth_dev *eth_dev);
176 void otx_ep_mbox_uninit(struct rte_eth_dev *eth_dev);
177 #endif
178