xref: /dpdk/drivers/net/octeon_ep/otx2_ep_vf.h (revision d360d7bfa13792a590cda949a15b268bf727fd30) 
1 /* SPDX-License-Identifier: BSD-3-Clause
2  * Copyright(C) 2021 Marvell.
3  */
4 #ifndef _OTX2_EP_VF_H_
5 #define _OTX2_EP_VF_H_
6 
7 #include <rte_io.h>
8 
9 #define SDP_VF_R_IN_CTL_IDLE            (0x1ull << 28)
10 #define SDP_VF_R_IN_CTL_RDSIZE          (0x3ull << 25) /* Setting to max(4) */
11 #define SDP_VF_R_IN_CTL_IS_64B          (0x1ull << 24)
12 #define SDP_VF_R_IN_CTL_ESR             (0x1ull << 1)
13 
14 #define SDP_VF_BUSY_LOOP_COUNT      (10000)
15 
16 /* SDP VF OQ Masks */
17 #define SDP_VF_R_OUT_CTL_IDLE         (0x1ull << 40)
18 #define SDP_VF_R_OUT_CTL_ES_I         (0x1ull << 34)
19 #define SDP_VF_R_OUT_CTL_NSR_I        (0x1ull << 33)
20 #define SDP_VF_R_OUT_CTL_ROR_I        (0x1ull << 32)
21 #define SDP_VF_R_OUT_CTL_ES_D         (0x1ull << 30)
22 #define SDP_VF_R_OUT_CTL_NSR_D        (0x1ull << 29)
23 #define SDP_VF_R_OUT_CTL_ROR_D        (0x1ull << 28)
24 #define SDP_VF_R_OUT_CTL_ES_P         (0x1ull << 26)
25 #define SDP_VF_R_OUT_CTL_NSR_P        (0x1ull << 25)
26 #define SDP_VF_R_OUT_CTL_ROR_P        (0x1ull << 24)
27 #define SDP_VF_R_OUT_CTL_IMODE        (0x1ull << 23)
28 #define SDP_VF_R_OUT_CNTS_OUT_INT     (0x1ull << 62)
29 #define SDP_VF_R_OUT_CNTS_IN_INT      (0x1ull << 61)
30 #define SDP_VF_R_IN_CNTS_OUT_INT      (0x1ull << 62)
31 
32 /* SDP VF Register definitions */
33 #define SDP_VF_RING_OFFSET                (0x1ull << 17)
34 
35 /* SDP VF IQ Registers */
36 #define SDP_VF_R_IN_CONTROL_START         (0x10000)
37 #define SDP_VF_R_IN_ENABLE_START          (0x10010)
38 #define SDP_VF_R_IN_INSTR_BADDR_START     (0x10020)
39 #define SDP_VF_R_IN_INSTR_RSIZE_START     (0x10030)
40 #define SDP_VF_R_IN_INSTR_DBELL_START     (0x10040)
41 #define SDP_VF_R_IN_CNTS_START            (0x10050)
42 #define SDP_VF_R_IN_INT_LEVELS_START      (0x10060)
43 #define SDP_VF_R_IN_PKT_CNT_START         (0x10080)
44 #define SDP_VF_R_IN_BYTE_CNT_START        (0x10090)
45 #define SDP_VF_R_IN_CNTS_ISM_START        (0x10520)
46 
47 #define SDP_VF_R_IN_CONTROL(ring)  \
48 	(SDP_VF_R_IN_CONTROL_START + ((ring) * SDP_VF_RING_OFFSET))
49 
50 #define SDP_VF_R_IN_ENABLE(ring)   \
51 	(SDP_VF_R_IN_ENABLE_START + ((ring) * SDP_VF_RING_OFFSET))
52 
53 #define SDP_VF_R_IN_INSTR_BADDR(ring)   \
54 	(SDP_VF_R_IN_INSTR_BADDR_START + ((ring) * SDP_VF_RING_OFFSET))
55 
56 #define SDP_VF_R_IN_INSTR_RSIZE(ring)   \
57 	(SDP_VF_R_IN_INSTR_RSIZE_START + ((ring) * SDP_VF_RING_OFFSET))
58 
59 #define SDP_VF_R_IN_INSTR_DBELL(ring)   \
60 	(SDP_VF_R_IN_INSTR_DBELL_START + ((ring) * SDP_VF_RING_OFFSET))
61 
62 #define SDP_VF_R_IN_CNTS(ring)          \
63 	(SDP_VF_R_IN_CNTS_START + ((ring) * SDP_VF_RING_OFFSET))
64 
65 #define SDP_VF_R_IN_INT_LEVELS(ring)    \
66 	(SDP_VF_R_IN_INT_LEVELS_START + ((ring) * SDP_VF_RING_OFFSET))
67 
68 #define SDP_VF_R_IN_PKT_CNT(ring)       \
69 	(SDP_VF_R_IN_PKT_CNT_START + ((ring) * SDP_VF_RING_OFFSET))
70 
71 #define SDP_VF_R_IN_BYTE_CNT(ring)          \
72 	(SDP_VF_R_IN_BYTE_CNT_START + ((ring) * SDP_VF_RING_OFFSET))
73 
74 #define SDP_VF_R_IN_CNTS_ISM(ring)          \
75 	(SDP_VF_R_IN_CNTS_ISM_START + (SDP_VF_RING_OFFSET * (ring)))
76 
77 /* SDP VF OQ Registers */
78 #define SDP_VF_R_OUT_CNTS_START              (0x10100)
79 #define SDP_VF_R_OUT_INT_LEVELS_START        (0x10110)
80 #define SDP_VF_R_OUT_SLIST_BADDR_START       (0x10120)
81 #define SDP_VF_R_OUT_SLIST_RSIZE_START       (0x10130)
82 #define SDP_VF_R_OUT_SLIST_DBELL_START       (0x10140)
83 #define SDP_VF_R_OUT_CONTROL_START           (0x10150)
84 #define SDP_VF_R_OUT_ENABLE_START            (0x10160)
85 #define SDP_VF_R_OUT_PKT_CNT_START           (0x10180)
86 #define SDP_VF_R_OUT_BYTE_CNT_START          (0x10190)
87 #define SDP_VF_R_OUT_CNTS_ISM_START          (0x10510)
88 
89 #define SDP_VF_R_OUT_CONTROL(ring)    \
90 	(SDP_VF_R_OUT_CONTROL_START + ((ring) * SDP_VF_RING_OFFSET))
91 
92 #define SDP_VF_R_OUT_ENABLE(ring)     \
93 	(SDP_VF_R_OUT_ENABLE_START + ((ring) * SDP_VF_RING_OFFSET))
94 
95 #define SDP_VF_R_OUT_SLIST_BADDR(ring)  \
96 	(SDP_VF_R_OUT_SLIST_BADDR_START + ((ring) * SDP_VF_RING_OFFSET))
97 
98 #define SDP_VF_R_OUT_SLIST_RSIZE(ring)  \
99 	(SDP_VF_R_OUT_SLIST_RSIZE_START + ((ring) * SDP_VF_RING_OFFSET))
100 
101 #define SDP_VF_R_OUT_SLIST_DBELL(ring)  \
102 	(SDP_VF_R_OUT_SLIST_DBELL_START + ((ring) * SDP_VF_RING_OFFSET))
103 
104 #define SDP_VF_R_OUT_CNTS(ring)   \
105 	(SDP_VF_R_OUT_CNTS_START + ((ring) * SDP_VF_RING_OFFSET))
106 
107 #define SDP_VF_R_OUT_INT_LEVELS(ring)   \
108 	(SDP_VF_R_OUT_INT_LEVELS_START + ((ring) * SDP_VF_RING_OFFSET))
109 
110 #define SDP_VF_R_OUT_PKT_CNT(ring)   \
111 	(SDP_VF_R_OUT_PKT_CNT_START + ((ring) * SDP_VF_RING_OFFSET))
112 
113 #define SDP_VF_R_OUT_BYTE_CNT(ring)   \
114 	(SDP_VF_R_OUT_BYTE_CNT_START + ((ring) * SDP_VF_RING_OFFSET))
115 
116 #define SDP_VF_R_OUT_CNTS_ISM(ring)   \
117 	(SDP_VF_R_OUT_CNTS_ISM_START + (SDP_VF_RING_OFFSET * (ring)))
118 
119 /* SDP VF IQ Masks */
120 #define SDP_VF_R_IN_CTL_RPVF_MASK       (0xF)
121 #define	SDP_VF_R_IN_CTL_RPVF_POS        (48)
122 
123 /* IO Access */
124 #define otx2_read64(addr) rte_read64_relaxed((void *)(addr))
125 #define otx2_write64(val, addr) rte_write64_relaxed((val), (void *)(addr))
126 
127 #define PCI_DEVID_CN9K_EP_NET_VF		0xB203 /* OCTEON 9 EP mode */
128 #define PCI_DEVID_CN98XX_EP_NET_VF		0xB103
129 #define PCI_DEVID_CNF95N_EP_NET_VF		0xB403
130 #define PCI_DEVID_CNF95O_EP_NET_VF		0xB603
131 
132 int
133 otx2_ep_vf_setup_device(struct otx_ep_device *sdpvf);
134 
135 struct otx2_ep_instr_64B {
136 	/* Pointer where the input data is available. */
137 	uint64_t dptr;
138 
139 	/* OTX_EP Instruction Header. */
140 	union otx_ep_instr_ih ih;
141 
142 	/** Pointer where the response for a RAW mode packet
143 	 * will be written by OCTEON TX.
144 	 */
145 	uint64_t rptr;
146 
147 	/* Input Request Header. */
148 	union otx_ep_instr_irh irh;
149 
150 	/* Additional headers available in a 64-byte instruction. */
151 	uint64_t exhdr[4];
152 };
153 
154 #define OTX2_EP_IQ_ISM_OFFSET(queue)   (RTE_CACHE_LINE_SIZE * (queue) + 4)
155 #define OTX2_EP_OQ_ISM_OFFSET(queue)   (RTE_CACHE_LINE_SIZE * (queue))
156 #define OTX2_EP_ISM_EN                 (0x1)
157 #define OTX2_EP_ISM_MSIX_DIS           (0x2)
158 #define OTX2_EP_MAX_RX_PKT_LEN         (16384)
159 
160 union out_int_lvl_t {
161 	uint64_t d64;
162 	struct {
163 		uint64_t cnt:32;
164 		uint64_t timet:22;
165 		uint64_t max_len:7;
166 		uint64_t max_len_en:1;
167 		uint64_t time_cnt_en:1;
168 		uint64_t bmode:1;
169 	} s;
170 };
171 
172 union out_cnts_t {
173 	uint64_t d64;
174 	struct {
175 		uint64_t cnt:32;
176 		uint64_t timer:22;
177 		uint64_t rsvd:5;
178 		uint64_t resend:1;
179 		uint64_t mbox_int:1;
180 		uint64_t in_int:1;
181 		uint64_t out_int:1;
182 		uint64_t send_ism:1;
183 	} s;
184 };
185 
186 #define OTX2_EP_64B_INSTR_SIZE	(sizeof(otx2_ep_instr_64B))
187 
188 #define NIX_MAX_HW_FRS			9212
189 #define NIX_MAX_VTAG_INS		2
190 #define NIX_MAX_VTAG_ACT_SIZE		(4 * NIX_MAX_VTAG_INS)
191 #define NIX_MAX_FRS	\
192 	(NIX_MAX_HW_FRS + RTE_ETHER_CRC_LEN - NIX_MAX_VTAG_ACT_SIZE)
193 
194 #define CN93XX_INTR_R_OUT_INT        (1ULL << 62)
195 #define CN93XX_INTR_R_IN_INT         (1ULL << 61)
196 #endif /*_OTX2_EP_VF_H_ */
197