1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(C) 2022 Marvell. 3 */ 4 #ifndef _CNXK_EP_VF_H_ 5 #define _CNXK_EP_VF_H_ 6 7 #include <rte_io.h> 8 9 #include "otx_ep_common.h" 10 11 #define CNXK_CONFIG_XPANSION_BAR 0x38 12 #define CNXK_CONFIG_PCIE_CAP 0x70 13 #define CNXK_CONFIG_PCIE_DEVCAP 0x74 14 #define CNXK_CONFIG_PCIE_DEVCTL 0x78 15 #define CNXK_CONFIG_PCIE_LINKCAP 0x7C 16 #define CNXK_CONFIG_PCIE_LINKCTL 0x80 17 #define CNXK_CONFIG_PCIE_SLOTCAP 0x84 18 #define CNXK_CONFIG_PCIE_SLOTCTL 0x88 19 #define CNXK_CONFIG_PCIE_FLTMSK 0x720 20 21 #define CNXK_EP_RING_OFFSET (0x1ULL << 17) 22 23 #define CNXK_EP_R_IN_CONTROL_START 0x10000 24 #define CNXK_EP_R_IN_ENABLE_START 0x10010 25 #define CNXK_EP_R_IN_INSTR_BADDR_START 0x10020 26 #define CNXK_EP_R_IN_INSTR_RSIZE_START 0x10030 27 #define CNXK_EP_R_IN_INSTR_DBELL_START 0x10040 28 #define CNXK_EP_R_IN_CNTS_START 0x10050 29 #define CNXK_EP_R_IN_INT_LEVELS_START 0x10060 30 #define CNXK_EP_R_IN_PKT_CNT_START 0x10080 31 #define CNXK_EP_R_IN_BYTE_CNT_START 0x10090 32 #define CNXK_EP_R_IN_CNTS_ISM_START 0x10520 33 34 #define CNXK_EP_R_IN_CONTROL(ring) \ 35 (CNXK_EP_R_IN_CONTROL_START + ((ring) * CNXK_EP_RING_OFFSET)) 36 37 #define CNXK_EP_R_IN_ENABLE(ring) \ 38 (CNXK_EP_R_IN_ENABLE_START + ((ring) * CNXK_EP_RING_OFFSET)) 39 40 #define CNXK_EP_R_IN_INSTR_BADDR(ring) \ 41 (CNXK_EP_R_IN_INSTR_BADDR_START + ((ring) * CNXK_EP_RING_OFFSET)) 42 43 #define CNXK_EP_R_IN_INSTR_RSIZE(ring) \ 44 (CNXK_EP_R_IN_INSTR_RSIZE_START + ((ring) * CNXK_EP_RING_OFFSET)) 45 46 #define CNXK_EP_R_IN_INSTR_DBELL(ring) \ 47 (CNXK_EP_R_IN_INSTR_DBELL_START + ((ring) * CNXK_EP_RING_OFFSET)) 48 49 #define CNXK_EP_R_IN_CNTS(ring) \ 50 (CNXK_EP_R_IN_CNTS_START + ((ring) * CNXK_EP_RING_OFFSET)) 51 52 #define CNXK_EP_R_IN_INT_LEVELS(ring) \ 53 (CNXK_EP_R_IN_INT_LEVELS_START + ((ring) * CNXK_EP_RING_OFFSET)) 54 55 #define CNXK_EP_R_IN_PKT_CNT(ring) \ 56 (CNXK_EP_R_IN_PKT_CNT_START + ((ring) * CNXK_EP_RING_OFFSET)) 57 58 #define CNXK_EP_R_IN_BYTE_CNT(ring) \ 59 (CNXK_EP_R_IN_BYTE_CNT_START + ((ring) * CNXK_EP_RING_OFFSET)) 60 61 #define CNXK_EP_R_IN_CNTS_ISM(ring) \ 62 (CNXK_EP_R_IN_CNTS_ISM_START + ((ring) * CNXK_EP_RING_OFFSET)) 63 64 /** Rings per Virtual Function **/ 65 #define CNXK_EP_R_IN_CTL_RPVF_MASK (0xF) 66 #define CNXK_EP_R_IN_CTL_RPVF_POS (48) 67 68 /* Number of instructions to be read in one MAC read request. 69 * setting to Max value(4) 70 */ 71 #define CNXK_EP_R_IN_CTL_IDLE (0x1ULL << 28) 72 #define CNXK_EP_R_IN_CTL_RDSIZE (0x3ULL << 25) 73 #define CNXK_EP_R_IN_CTL_IS_64B (0x1ULL << 24) 74 #define CNXK_EP_R_IN_CTL_D_NSR (0x1ULL << 8) 75 #define CNXK_EP_R_IN_CTL_D_ROR (0x1ULL << 5) 76 #define CNXK_EP_R_IN_CTL_NSR (0x1ULL << 3) 77 #define CNXK_EP_R_IN_CTL_ROR (0x1ULL << 0) 78 #define CNXK_EP_R_IN_CTL_ESR (0x1ull << 1) 79 80 #define CNXK_EP_R_IN_CTL_MASK \ 81 (CNXK_EP_R_IN_CTL_RDSIZE \ 82 | CNXK_EP_R_IN_CTL_IS_64B) 83 84 #define CNXK_EP_R_OUT_CNTS_START 0x10100 85 #define CNXK_EP_R_OUT_INT_LEVELS_START 0x10110 86 #define CNXK_EP_R_OUT_SLIST_BADDR_START 0x10120 87 #define CNXK_EP_R_OUT_SLIST_RSIZE_START 0x10130 88 #define CNXK_EP_R_OUT_SLIST_DBELL_START 0x10140 89 #define CNXK_EP_R_OUT_CONTROL_START 0x10150 90 /* WMARK need to be set; New in CN10K */ 91 #define CNXK_EP_R_OUT_WMARK_START 0x10160 92 #define CNXK_EP_R_OUT_ENABLE_START 0x10170 93 #define CNXK_EP_R_OUT_PKT_CNT_START 0x10180 94 #define CNXK_EP_R_OUT_BYTE_CNT_START 0x10190 95 #define CNXK_EP_R_OUT_CNTS_ISM_START 0x10510 96 97 #define CNXK_EP_R_MBOX_PF_VF_DATA_START 0x10210 98 #define CNXK_EP_R_MBOX_VF_PF_DATA_START 0x10230 99 #define CNXK_EP_R_MBOX_PF_VF_INT_START 0x10220 100 101 #define CNXK_EP_R_OUT_CNTS(ring) \ 102 (CNXK_EP_R_OUT_CNTS_START + ((ring) * CNXK_EP_RING_OFFSET)) 103 104 #define CNXK_EP_R_OUT_INT_LEVELS(ring) \ 105 (CNXK_EP_R_OUT_INT_LEVELS_START + ((ring) * CNXK_EP_RING_OFFSET)) 106 107 #define CNXK_EP_R_OUT_SLIST_BADDR(ring) \ 108 (CNXK_EP_R_OUT_SLIST_BADDR_START + ((ring) * CNXK_EP_RING_OFFSET)) 109 110 #define CNXK_EP_R_OUT_SLIST_RSIZE(ring) \ 111 (CNXK_EP_R_OUT_SLIST_RSIZE_START + ((ring) * CNXK_EP_RING_OFFSET)) 112 113 #define CNXK_EP_R_OUT_SLIST_DBELL(ring) \ 114 (CNXK_EP_R_OUT_SLIST_DBELL_START + ((ring) * CNXK_EP_RING_OFFSET)) 115 116 #define CNXK_EP_R_OUT_CONTROL(ring) \ 117 (CNXK_EP_R_OUT_CONTROL_START + ((ring) * CNXK_EP_RING_OFFSET)) 118 119 #define CNXK_EP_R_OUT_ENABLE(ring) \ 120 (CNXK_EP_R_OUT_ENABLE_START + ((ring) * CNXK_EP_RING_OFFSET)) 121 122 #define CNXK_EP_R_OUT_WMARK(ring) \ 123 (CNXK_EP_R_OUT_WMARK_START + ((ring) * CNXK_EP_RING_OFFSET)) 124 125 #define CNXK_EP_R_OUT_PKT_CNT(ring) \ 126 (CNXK_EP_R_OUT_PKT_CNT_START + ((ring) * CNXK_EP_RING_OFFSET)) 127 128 #define CNXK_EP_R_OUT_BYTE_CNT(ring) \ 129 (CNXK_EP_R_OUT_BYTE_CNT_START + ((ring) * CNXK_EP_RING_OFFSET)) 130 131 #define CNXK_EP_R_OUT_CNTS_ISM(ring) \ 132 (CNXK_EP_R_OUT_CNTS_ISM_START + ((ring) * CNXK_EP_RING_OFFSET)) 133 134 #define CNXK_EP_R_MBOX_VF_PF_DATA(ring) \ 135 (CNXK_EP_R_MBOX_VF_PF_DATA_START + ((ring) * CNXK_EP_RING_OFFSET)) 136 137 #define CNXK_EP_R_MBOX_PF_VF_DATA(ring) \ 138 (CNXK_EP_R_MBOX_PF_VF_DATA_START + ((ring) * CNXK_EP_RING_OFFSET)) 139 140 #define CNXK_EP_R_MBOX_PF_VF_INT(ring) \ 141 (CNXK_EP_R_MBOX_PF_VF_INT_START + ((ring) * CNXK_EP_RING_OFFSET)) 142 143 /*------------------ R_OUT Masks ----------------*/ 144 #define CNXK_EP_R_OUT_INT_LEVELS_BMODE (1ULL << 63) 145 #define CNXK_EP_R_OUT_INT_LEVELS_TIMET (32) 146 147 #define CNXK_EP_R_OUT_CTL_IDLE (1ULL << 40) 148 #define CNXK_EP_R_OUT_CTL_ES_I (1ull << 34) 149 #define CNXK_EP_R_OUT_CTL_NSR_I (1ULL << 33) 150 #define CNXK_EP_R_OUT_CTL_ROR_I (1ULL << 32) 151 #define CNXK_EP_R_OUT_CTL_ES_D (1ull << 30) 152 #define CNXK_EP_R_OUT_CTL_NSR_D (1ULL << 29) 153 #define CNXK_EP_R_OUT_CTL_ROR_D (1ULL << 28) 154 #define CNXK_EP_R_OUT_CTL_ES_P (1ull << 26) 155 #define CNXK_EP_R_OUT_CTL_NSR_P (1ULL << 25) 156 #define CNXK_EP_R_OUT_CTL_ROR_P (1ULL << 24) 157 #define CNXK_EP_R_OUT_CTL_IMODE (1ULL << 23) 158 159 #define PCI_DEVID_CN10KA_EP_NET_VF 0xB903 160 #define PCI_DEVID_CNF10KA_EP_NET_VF 0xBA03 161 #define PCI_DEVID_CNF10KB_EP_NET_VF 0xBC03 162 #define PCI_DEVID_CN10KB_EP_NET_VF 0xBD03 163 164 int 165 cnxk_ep_vf_setup_device(struct otx_ep_device *sdpvf); 166 167 struct cnxk_ep_instr_64B { 168 /* Pointer where the input data is available. */ 169 uint64_t dptr; 170 171 /* OTX_EP Instruction Header. */ 172 union otx_ep_instr_ih ih; 173 174 /** Pointer where the response for a RAW mode packet 175 * will be written by OCTEON TX. 176 */ 177 uint64_t rptr; 178 179 /* Input Request Header. */ 180 union otx_ep_instr_irh irh; 181 182 /* Additional headers available in a 64-byte instruction. */ 183 uint64_t exhdr[4]; 184 }; 185 186 struct cnxk_ep_instr_32B { 187 /* Pointer where the input data is available. */ 188 uint64_t dptr; 189 190 /* OTX_EP Instruction Header. */ 191 union otx_ep_instr_ih ih; 192 193 /* Misc data bytes that can be passed as front data */ 194 uint64_t rsvd[2]; 195 }; 196 197 #define CNXK_EP_IQ_ISM_OFFSET(queue) (RTE_CACHE_LINE_SIZE * (queue) + 4) 198 #define CNXK_EP_OQ_ISM_OFFSET(queue) (RTE_CACHE_LINE_SIZE * (queue)) 199 #define CNXK_EP_ISM_EN (0x1) 200 #define CNXK_EP_ISM_MSIX_DIS (0x2) 201 #define CNXK_EP_MBOX_INTR (0x1) 202 #define CNXK_EP_MBOX_ENAB (0x2) 203 204 #endif /*_CNXK_EP_VF_H_ */ 205