1 /* 2 * SPDX-License-Identifier: BSD-3-Clause 3 * Copyright(c) 2024 Napatech A/S 4 */ 5 6 #ifndef _NTHW_FPGA_REG_DEFS_TSM_ 7 #define _NTHW_FPGA_REG_DEFS_TSM_ 8 9 /* TSM */ 10 #define TSM_CON0_CONFIG (0xf893d371UL) 11 #define TSM_CON0_CONFIG_BLIND (0x59ccfcbUL) 12 #define TSM_CON0_CONFIG_DC_SRC (0x1879812bUL) 13 #define TSM_CON0_CONFIG_PORT (0x3ff0bb08UL) 14 #define TSM_CON0_CONFIG_PPSIN_2_5V (0xb8e78227UL) 15 #define TSM_CON0_CONFIG_SAMPLE_EDGE (0x4a4022ebUL) 16 #define TSM_CON0_INTERFACE (0x76e93b59UL) 17 #define TSM_CON0_INTERFACE_EX_TERM (0xd079b416UL) 18 #define TSM_CON0_INTERFACE_IN_REF_PWM (0x16f73c33UL) 19 #define TSM_CON0_INTERFACE_PWM_ENA (0x3629e73fUL) 20 #define TSM_CON0_INTERFACE_RESERVED (0xf9c5066UL) 21 #define TSM_CON0_INTERFACE_VTERM_PWM (0x6d2b1e23UL) 22 #define TSM_CON0_SAMPLE_HI (0x6e536b8UL) 23 #define TSM_CON0_SAMPLE_HI_SEC (0x5fc26159UL) 24 #define TSM_CON0_SAMPLE_LO (0x8bea5689UL) 25 #define TSM_CON0_SAMPLE_LO_NS (0x13d0010dUL) 26 #define TSM_CON1_CONFIG (0x3439d3efUL) 27 #define TSM_CON1_CONFIG_BLIND (0x98932ebdUL) 28 #define TSM_CON1_CONFIG_DC_SRC (0xa1825ac3UL) 29 #define TSM_CON1_CONFIG_PORT (0xe266628dUL) 30 #define TSM_CON1_CONFIG_PPSIN_2_5V (0x6f05027fUL) 31 #define TSM_CON1_CONFIG_SAMPLE_EDGE (0x2f2719adUL) 32 #define TSM_CON1_SAMPLE_HI (0xc76be978UL) 33 #define TSM_CON1_SAMPLE_HI_SEC (0xe639bab1UL) 34 #define TSM_CON1_SAMPLE_LO (0x4a648949UL) 35 #define TSM_CON1_SAMPLE_LO_NS (0x8edfe07bUL) 36 #define TSM_CON2_CONFIG (0xbab6d40cUL) 37 #define TSM_CON2_CONFIG_BLIND (0xe4f20b66UL) 38 #define TSM_CON2_CONFIG_DC_SRC (0xb0ff30baUL) 39 #define TSM_CON2_CONFIG_PORT (0x5fac0e43UL) 40 #define TSM_CON2_CONFIG_PPSIN_2_5V (0xcc5384d6UL) 41 #define TSM_CON2_CONFIG_SAMPLE_EDGE (0x808e5467UL) 42 #define TSM_CON2_SAMPLE_HI (0x5e898f79UL) 43 #define TSM_CON2_SAMPLE_HI_SEC (0xf744d0c8UL) 44 #define TSM_CON2_SAMPLE_LO (0xd386ef48UL) 45 #define TSM_CON2_SAMPLE_LO_NS (0xf2bec5a0UL) 46 #define TSM_CON3_CONFIG (0x761cd492UL) 47 #define TSM_CON3_CONFIG_BLIND (0x79fdea10UL) 48 #define TSM_CON3_CONFIG_PORT (0x823ad7c6UL) 49 #define TSM_CON3_CONFIG_SAMPLE_EDGE (0xe5e96f21UL) 50 #define TSM_CON3_SAMPLE_HI (0x9f0750b9UL) 51 #define TSM_CON3_SAMPLE_HI_SEC (0x4ebf0b20UL) 52 #define TSM_CON3_SAMPLE_LO (0x12083088UL) 53 #define TSM_CON3_SAMPLE_LO_NS (0x6fb124d6UL) 54 #define TSM_CON4_CONFIG (0x7cd9dd8bUL) 55 #define TSM_CON4_CONFIG_BLIND (0x1c3040d0UL) 56 #define TSM_CON4_CONFIG_PORT (0xff49d19eUL) 57 #define TSM_CON4_CONFIG_SAMPLE_EDGE (0x4adc9b2UL) 58 #define TSM_CON4_SAMPLE_HI (0xb63c453aUL) 59 #define TSM_CON4_SAMPLE_HI_SEC (0xd5be043aUL) 60 #define TSM_CON4_SAMPLE_LO (0x3b33250bUL) 61 #define TSM_CON4_SAMPLE_LO_NS (0xa7c8e16UL) 62 #define TSM_CON5_CONFIG (0xb073dd15UL) 63 #define TSM_CON5_CONFIG_BLIND (0x813fa1a6UL) 64 #define TSM_CON5_CONFIG_PORT (0x22df081bUL) 65 #define TSM_CON5_CONFIG_SAMPLE_EDGE (0x61caf2f4UL) 66 #define TSM_CON5_SAMPLE_HI (0x77b29afaUL) 67 #define TSM_CON5_SAMPLE_HI_SEC (0x6c45dfd2UL) 68 #define TSM_CON5_SAMPLE_LO (0xfabdfacbUL) 69 #define TSM_CON5_SAMPLE_LO_TIME (0x945d87e8UL) 70 #define TSM_CON6_CONFIG (0x3efcdaf6UL) 71 #define TSM_CON6_CONFIG_BLIND (0xfd5e847dUL) 72 #define TSM_CON6_CONFIG_PORT (0x9f1564d5UL) 73 #define TSM_CON6_CONFIG_SAMPLE_EDGE (0xce63bf3eUL) 74 #define TSM_CON6_SAMPLE_HI (0xee50fcfbUL) 75 #define TSM_CON6_SAMPLE_HI_SEC (0x7d38b5abUL) 76 #define TSM_CON6_SAMPLE_LO (0x635f9ccaUL) 77 #define TSM_CON6_SAMPLE_LO_NS (0xeb124abbUL) 78 #define TSM_CON7_HOST_SAMPLE_HI (0xdcd90e52UL) 79 #define TSM_CON7_HOST_SAMPLE_HI_SEC (0xd98d3618UL) 80 #define TSM_CON7_HOST_SAMPLE_LO (0x51d66e63UL) 81 #define TSM_CON7_HOST_SAMPLE_LO_NS (0x8f5594ddUL) 82 #define TSM_CONFIG (0xef5dec83UL) 83 #define TSM_CONFIG_NTTS_SRC (0x1b60227bUL) 84 #define TSM_CONFIG_NTTS_SYNC (0x43e0a69dUL) 85 #define TSM_CONFIG_TIMESET_EDGE (0x8c381127UL) 86 #define TSM_CONFIG_TIMESET_SRC (0xe7590a31UL) 87 #define TSM_CONFIG_TIMESET_UP (0x561980c1UL) 88 #define TSM_CONFIG_TS_FORMAT (0xe6efc2faUL) 89 #define TSM_INT_CONFIG (0x9a0d52dUL) 90 #define TSM_INT_CONFIG_AUTO_DISABLE (0x9581470UL) 91 #define TSM_INT_CONFIG_MASK (0xf00cd3d7UL) 92 #define TSM_INT_STAT (0xa4611a70UL) 93 #define TSM_INT_STAT_CAUSE (0x315168cfUL) 94 #define TSM_INT_STAT_ENABLE (0x980a12d1UL) 95 #define TSM_LED (0x6ae05f87UL) 96 #define TSM_LED_LED0_BG_COLOR (0x897cf9eeUL) 97 #define TSM_LED_LED0_COLOR (0x6d7ada39UL) 98 #define TSM_LED_LED0_MODE (0x6087b644UL) 99 #define TSM_LED_LED0_SRC (0x4fe29639UL) 100 #define TSM_LED_LED1_BG_COLOR (0x66be92d0UL) 101 #define TSM_LED_LED1_COLOR (0xcb0dd18dUL) 102 #define TSM_LED_LED1_MODE (0xabdb65e1UL) 103 #define TSM_LED_LED1_SRC (0x7282bf89UL) 104 #define TSM_LED_LED2_BG_COLOR (0x8d8929d3UL) 105 #define TSM_LED_LED2_COLOR (0xfae5cb10UL) 106 #define TSM_LED_LED2_MODE (0x2d4f174fUL) 107 #define TSM_LED_LED2_SRC (0x3522c559UL) 108 #define TSM_NTTS_CONFIG (0x8bc38bdeUL) 109 #define TSM_NTTS_CONFIG_AUTO_HARDSET (0xd75be25dUL) 110 #define TSM_NTTS_CONFIG_EXT_CLK_ADJ (0x700425b6UL) 111 #define TSM_NTTS_CONFIG_HIGH_SAMPLE (0x37135b7eUL) 112 #define TSM_NTTS_CONFIG_TS_SRC_FORMAT (0x6e6e707UL) 113 #define TSM_NTTS_EXT_STAT (0x2b0315b7UL) 114 #define TSM_NTTS_EXT_STAT_MASTER_ID (0xf263315eUL) 115 #define TSM_NTTS_EXT_STAT_MASTER_REV (0xd543795eUL) 116 #define TSM_NTTS_EXT_STAT_MASTER_STAT (0x92d96f5eUL) 117 #define TSM_NTTS_LIMIT_HI (0x1ddaa85fUL) 118 #define TSM_NTTS_LIMIT_HI_SEC (0x315c6ef2UL) 119 #define TSM_NTTS_LIMIT_LO (0x90d5c86eUL) 120 #define TSM_NTTS_LIMIT_LO_NS (0xe6d94d9aUL) 121 #define TSM_NTTS_OFFSET (0x6436e72UL) 122 #define TSM_NTTS_OFFSET_NS (0x12d43a06UL) 123 #define TSM_NTTS_SAMPLE_HI (0xcdc8aa3eUL) 124 #define TSM_NTTS_SAMPLE_HI_SEC (0x4f6588fdUL) 125 #define TSM_NTTS_SAMPLE_LO (0x40c7ca0fUL) 126 #define TSM_NTTS_SAMPLE_LO_NS (0x6e43ff97UL) 127 #define TSM_NTTS_STAT (0x6502b820UL) 128 #define TSM_NTTS_STAT_NTTS_VALID (0x3e184471UL) 129 #define TSM_NTTS_STAT_SIGNAL_LOST (0x178bedfdUL) 130 #define TSM_NTTS_STAT_SYNC_LOST (0xe4cd53dfUL) 131 #define TSM_NTTS_TS_T0_HI (0x1300d1b6UL) 132 #define TSM_NTTS_TS_T0_HI_TIME (0xa016ae4fUL) 133 #define TSM_NTTS_TS_T0_LO (0x9e0fb187UL) 134 #define TSM_NTTS_TS_T0_LO_TIME (0x82006941UL) 135 #define TSM_NTTS_TS_T0_OFFSET (0xbf70ce4fUL) 136 #define TSM_NTTS_TS_T0_OFFSET_COUNT (0x35dd4398UL) 137 #define TSM_PB_CTRL (0x7a8b60faUL) 138 #define TSM_PB_CTRL_INSTMEM_WR (0xf96e2cbcUL) 139 #define TSM_PB_CTRL_RESET (0xa38ade8bUL) 140 #define TSM_PB_CTRL_RST (0x3aaa82f4UL) 141 #define TSM_PB_INSTMEM (0xb54aeecUL) 142 #define TSM_PB_INSTMEM_MEM_ADDR (0x9ac79b6eUL) 143 #define TSM_PB_INSTMEM_MEM_DATA (0x65aefa38UL) 144 #define TSM_PI_CTRL_I (0x8d71a4e2UL) 145 #define TSM_PI_CTRL_I_VAL (0x98baedc9UL) 146 #define TSM_PI_CTRL_KI (0xa1bd86cbUL) 147 #define TSM_PI_CTRL_KI_GAIN (0x53faa916UL) 148 #define TSM_PI_CTRL_KP (0xc5d62e0bUL) 149 #define TSM_PI_CTRL_KP_GAIN (0x7723fa45UL) 150 #define TSM_PI_CTRL_SHL (0xaa518701UL) 151 #define TSM_PI_CTRL_SHL_VAL (0x56f56a6fUL) 152 #define TSM_STAT (0xa55bf677UL) 153 #define TSM_STAT_HARD_SYNC (0x7fff20fdUL) 154 #define TSM_STAT_LINK_CON0 (0x216086f0UL) 155 #define TSM_STAT_LINK_CON1 (0x5667b666UL) 156 #define TSM_STAT_LINK_CON2 (0xcf6ee7dcUL) 157 #define TSM_STAT_LINK_CON3 (0xb869d74aUL) 158 #define TSM_STAT_LINK_CON4 (0x260d42e9UL) 159 #define TSM_STAT_LINK_CON5 (0x510a727fUL) 160 #define TSM_STAT_NTTS_INSYNC (0xb593a245UL) 161 #define TSM_STAT_PTP_MI_PRESENT (0x43131eb0UL) 162 #define TSM_TIMER_CTRL (0x648da051UL) 163 #define TSM_TIMER_CTRL_TIMER_EN_T0 (0x17cee154UL) 164 #define TSM_TIMER_CTRL_TIMER_EN_T1 (0x60c9d1c2UL) 165 #define TSM_TIMER_T0 (0x417217a5UL) 166 #define TSM_TIMER_T0_MAX_COUNT (0xaa601706UL) 167 #define TSM_TIMER_T1 (0x36752733UL) 168 #define TSM_TIMER_T1_MAX_COUNT (0x6beec8c6UL) 169 #define TSM_TIME_HARDSET_HI (0xf28bdb46UL) 170 #define TSM_TIME_HARDSET_HI_TIME (0x2d9a28baUL) 171 #define TSM_TIME_HARDSET_LO (0x7f84bb77UL) 172 #define TSM_TIME_HARDSET_LO_TIME (0xf8cefb4UL) 173 #define TSM_TIME_HI (0x175acea1UL) 174 #define TSM_TIME_HI_SEC (0xc0e9c9a1UL) 175 #define TSM_TIME_LO (0x9a55ae90UL) 176 #define TSM_TIME_LO_NS (0x879c5c4bUL) 177 #define TSM_TIME_RATE_ADJ (0xb1cc4bb1UL) 178 #define TSM_TIME_RATE_ADJ_FRACTION (0xb7ab96UL) 179 #define TSM_TS_HI (0xccfe9e5eUL) 180 #define TSM_TS_HI_TIME (0xc23fed30UL) 181 #define TSM_TS_LO (0x41f1fe6fUL) 182 #define TSM_TS_LO_TIME (0xe0292a3eUL) 183 #define TSM_TS_OFFSET (0x4b2e6e13UL) 184 #define TSM_TS_OFFSET_NS (0x68c286b9UL) 185 #define TSM_TS_STAT (0x64d41b8cUL) 186 #define TSM_TS_STAT_OVERRUN (0xad9db92aUL) 187 #define TSM_TS_STAT_SAMPLES (0xb6350e0bUL) 188 #define TSM_TS_STAT_HI_OFFSET (0x1aa2ddf2UL) 189 #define TSM_TS_STAT_HI_OFFSET_NS (0xeb040e0fUL) 190 #define TSM_TS_STAT_LO_OFFSET (0x81218579UL) 191 #define TSM_TS_STAT_LO_OFFSET_NS (0xb7ff33UL) 192 #define TSM_TS_STAT_TAR_HI (0x65af24b6UL) 193 #define TSM_TS_STAT_TAR_HI_SEC (0x7e92f619UL) 194 #define TSM_TS_STAT_TAR_LO (0xe8a04487UL) 195 #define TSM_TS_STAT_TAR_LO_NS (0xf7b3f439UL) 196 #define TSM_TS_STAT_X (0x419f0ddUL) 197 #define TSM_TS_STAT_X_NS (0xa48c3f27UL) 198 #define TSM_TS_STAT_X2_HI (0xd6b1c517UL) 199 #define TSM_TS_STAT_X2_HI_NS (0x4288c50fUL) 200 #define TSM_TS_STAT_X2_LO (0x5bbea526UL) 201 #define TSM_TS_STAT_X2_LO_NS (0x92633c13UL) 202 #define TSM_UTC_OFFSET (0xf622a13aUL) 203 #define TSM_UTC_OFFSET_SEC (0xd9c80209UL) 204 205 #endif /* _NTHW_FPGA_REG_DEFS_TSM_ */ 206