1 /* 2 * SPDX-License-Identifier: BSD-3-Clause 3 * Copyright(c) 2024 Napatech A/S 4 */ 5 6 #ifndef _NTHW_FPGA_REG_DEFS_STA_ 7 #define _NTHW_FPGA_REG_DEFS_STA_ 8 9 /* STA */ 10 #define STA_BYTE (0xa08364d4UL) 11 #define STA_BYTE_CNT (0x3119e6bcUL) 12 #define STA_CFG (0xcecaf9f4UL) 13 #define STA_CFG_CNT_CLEAR (0xc325e12eUL) 14 #define STA_CFG_CNT_FRZ (0x8c27a596UL) 15 #define STA_CFG_DMA_ENA (0x940dbacUL) 16 #define STA_CFG_TX_DISABLE (0x30f43250UL) 17 #define STA_CV_ERR (0x7db7db5dUL) 18 #define STA_CV_ERR_CNT (0x2c02fbbeUL) 19 #define STA_FCS_ERR (0xa0de1647UL) 20 #define STA_FCS_ERR_CNT (0xc68c37d1UL) 21 #define STA_HOST_ADR_LSB (0xde569336UL) 22 #define STA_HOST_ADR_LSB_LSB (0xb6f2f94bUL) 23 #define STA_HOST_ADR_MSB (0xdf94f901UL) 24 #define STA_HOST_ADR_MSB_MSB (0x114798c8UL) 25 #define STA_LOAD_BIN (0x2e842591UL) 26 #define STA_LOAD_BIN_BIN (0x1a2b942eUL) 27 #define STA_LOAD_BPS_RX_0 (0xbf8f4595UL) 28 #define STA_LOAD_BPS_RX_0_BPS (0x41647781UL) 29 #define STA_LOAD_BPS_RX_1 (0xc8887503UL) 30 #define STA_LOAD_BPS_RX_1_BPS (0x7c045e31UL) 31 #define STA_LOAD_BPS_TX_0 (0x9ae41a49UL) 32 #define STA_LOAD_BPS_TX_0_BPS (0x870b7e06UL) 33 #define STA_LOAD_BPS_TX_1 (0xede32adfUL) 34 #define STA_LOAD_BPS_TX_1_BPS (0xba6b57b6UL) 35 #define STA_LOAD_PPS_RX_0 (0x811173c3UL) 36 #define STA_LOAD_PPS_RX_0_PPS (0xbee573fcUL) 37 #define STA_LOAD_PPS_RX_1 (0xf6164355UL) 38 #define STA_LOAD_PPS_RX_1_PPS (0x83855a4cUL) 39 #define STA_LOAD_PPS_TX_0 (0xa47a2c1fUL) 40 #define STA_LOAD_PPS_TX_0_PPS (0x788a7a7bUL) 41 #define STA_LOAD_PPS_TX_1 (0xd37d1c89UL) 42 #define STA_LOAD_PPS_TX_1_PPS (0x45ea53cbUL) 43 #define STA_PCKT (0xecc8f30aUL) 44 #define STA_PCKT_CNT (0x63291d16UL) 45 #define STA_STATUS (0x91c5c51cUL) 46 #define STA_STATUS_STAT_TOGGLE_MISSED (0xf7242b11UL) 47 48 #endif /* _NTHW_FPGA_REG_DEFS_STA_ */ 49