1 /* 2 * SPDX-License-Identifier: BSD-3-Clause 3 * Copyright(c) 2024 Napatech A/S 4 */ 5 6 /* 7 * nthw_fpga_reg_defs_rac.h 8 * 9 * Auto-generated file - do *NOT* edit 10 * 11 */ 12 13 #ifndef _NTHW_FPGA_REG_DEFS_RAC_ 14 #define _NTHW_FPGA_REG_DEFS_RAC_ 15 16 /* RAC */ 17 #define NTHW_MOD_RAC (0xae830b42UL) 18 #define RAC_DBG_CTRL (0x587273e2UL) 19 #define RAC_DBG_CTRL_C (0x4fe263UL) 20 #define RAC_DBG_DATA (0xf7a3f1fbUL) 21 #define RAC_DBG_DATA_D (0x69d9305UL) 22 #define RAC_DUMMY0 (0xd8e9ed5bUL) 23 #define RAC_DUMMY1 (0xafeeddcdUL) 24 #define RAC_DUMMY2 (0x36e78c77UL) 25 #define RAC_NDM_REGISTER (0x36b9e7d0UL) 26 #define RAC_NDM_REGISTER_NDM (0xf791ef23UL) 27 #define RAC_NMB_DATA (0xc0e60c69UL) 28 #define RAC_NMB_DATA_NMB_DATA (0x21f71466UL) 29 #define RAC_NMB_RD_ADR (0x274e1df2UL) 30 #define RAC_NMB_RD_ADR_ADR (0xf2e063d0UL) 31 #define RAC_NMB_RD_ADR_RES (0x829c7f2eUL) 32 #define RAC_NMB_STATUS (0x2070b64UL) 33 #define RAC_NMB_STATUS_BUS_TIMEOUT (0x7b220848UL) 34 #define RAC_NMB_STATUS_NMB_READY (0xe67a182bUL) 35 #define RAC_NMB_WR_ADR (0x9823ee63UL) 36 #define RAC_NMB_WR_ADR_ADR (0xcb13936fUL) 37 #define RAC_NMB_WR_ADR_RES (0xbb6f8f91UL) 38 #define RAC_RAB_BUF_FREE (0x60f7f2d8UL) 39 #define RAC_RAB_BUF_FREE_IB_FREE (0x4ddd870fUL) 40 #define RAC_RAB_BUF_FREE_IB_OVF (0x92388832UL) 41 #define RAC_RAB_BUF_FREE_OB_FREE (0x2e0db235UL) 42 #define RAC_RAB_BUF_FREE_OB_OVF (0x44616b2fUL) 43 #define RAC_RAB_BUF_FREE_TIMEOUT (0x1d0ae34eUL) 44 #define RAC_RAB_BUF_USED (0x549e5008UL) 45 #define RAC_RAB_BUF_USED_FLUSH (0xeb99f9baUL) 46 #define RAC_RAB_BUF_USED_IB_USED (0xd4c7d150UL) 47 #define RAC_RAB_BUF_USED_OB_USED (0xb717e46aUL) 48 #define RAC_RAB_DMA_IB_HI (0x3adf4e92UL) 49 #define RAC_RAB_DMA_IB_HI_PHYADDR (0x482070e9UL) 50 #define RAC_RAB_DMA_IB_LO (0xb7d02ea3UL) 51 #define RAC_RAB_DMA_IB_LO_PHYADDR (0x32d1a919UL) 52 #define RAC_RAB_DMA_IB_RD (0xf443c8f4UL) 53 #define RAC_RAB_DMA_IB_RD_PTR (0xa19bede2UL) 54 #define RAC_RAB_DMA_IB_WR (0x7de089e0UL) 55 #define RAC_RAB_DMA_IB_WR_PTR (0x1ef61e73UL) 56 #define RAC_RAB_DMA_OB_HI (0xb59fbb32UL) 57 #define RAC_RAB_DMA_OB_HI_PHYADDR (0xe8c5af34UL) 58 #define RAC_RAB_DMA_OB_LO (0x3890db03UL) 59 #define RAC_RAB_DMA_OB_LO_PHYADDR (0x923476c4UL) 60 #define RAC_RAB_DMA_OB_WR (0xf2a07c40UL) 61 #define RAC_RAB_DMA_OB_WR_PTR (0x6dec67f9UL) 62 #define RAC_RAB_IB_DATA (0xea524b52UL) 63 #define RAC_RAB_IB_DATA_D (0x52ecd3c6UL) 64 #define RAC_RAB_INIT (0x47d5556eUL) 65 #define RAC_RAB_INIT_RAB (0xda582a35UL) 66 #define RAC_RAB_OB_DATA (0x89827e68UL) 67 #define RAC_RAB_OB_DATA_D (0x21f6aa4cUL) 68 69 #endif /* _NTHW_FPGA_REG_DEFS_RAC_ */ 70