1 /* 2 * SPDX-License-Identifier: BSD-3-Clause 3 * Copyright(c) 2024 Napatech A/S 4 */ 5 6 /* 7 * nthw_fpga_reg_defs_km.h 8 * 9 * Auto-generated file - do *NOT* edit 10 * 11 */ 12 13 #ifndef _NTHW_FPGA_REG_DEFS_KM_ 14 #define _NTHW_FPGA_REG_DEFS_KM_ 15 16 /* KM */ 17 #define NTHW_MOD_KM (0xcfbd9dbeUL) 18 #define KM_CAM_CTRL (0x601dcc08UL) 19 #define KM_CAM_CTRL_ADR (0xee5e10b0UL) 20 #define KM_CAM_CTRL_CNT (0xfe568961UL) 21 #define KM_CAM_DATA (0xcfcc4e11UL) 22 #define KM_CAM_DATA_FT0 (0x138589ccUL) 23 #define KM_CAM_DATA_FT1 (0x6482b95aUL) 24 #define KM_CAM_DATA_FT2 (0xfd8be8e0UL) 25 #define KM_CAM_DATA_FT3 (0x8a8cd876UL) 26 #define KM_CAM_DATA_FT4 (0x14e84dd5UL) 27 #define KM_CAM_DATA_FT5 (0x63ef7d43UL) 28 #define KM_CAM_DATA_W0 (0xff7d6c5fUL) 29 #define KM_CAM_DATA_W1 (0x887a5cc9UL) 30 #define KM_CAM_DATA_W2 (0x11730d73UL) 31 #define KM_CAM_DATA_W3 (0x66743de5UL) 32 #define KM_CAM_DATA_W4 (0xf810a846UL) 33 #define KM_CAM_DATA_W5 (0x8f1798d0UL) 34 #define KM_RCP_CTRL (0xf8dbfdd1UL) 35 #define KM_RCP_CTRL_ADR (0xf3df02baUL) 36 #define KM_RCP_CTRL_CNT (0xe3d79b6bUL) 37 #define KM_RCP_DATA (0x570a7fc8UL) 38 #define KM_RCP_DATA_BANK_A (0x7fd7bd1UL) 39 #define KM_RCP_DATA_BANK_B (0x9ef42a6bUL) 40 #define KM_RCP_DATA_DUAL (0x428e6b23UL) 41 #define KM_RCP_DATA_DW0_B_DYN (0x342bde5aUL) 42 #define KM_RCP_DATA_DW0_B_OFS (0x962253fcUL) 43 #define KM_RCP_DATA_DW10_DYN (0x54eccf30UL) 44 #define KM_RCP_DATA_DW10_OFS (0xf6e54296UL) 45 #define KM_RCP_DATA_DW10_SEL_A (0x6237e887UL) 46 #define KM_RCP_DATA_DW10_SEL_B (0xfb3eb93dUL) 47 #define KM_RCP_DATA_DW2_B_DYN (0xa3b4cf73UL) 48 #define KM_RCP_DATA_DW2_B_OFS (0x1bd42d5UL) 49 #define KM_RCP_DATA_DW8_B_DYN (0x7c4903dUL) 50 #define KM_RCP_DATA_DW8_B_OFS (0xa5cd1d9bUL) 51 #define KM_RCP_DATA_DW8_DYN (0x3f6b49f0UL) 52 #define KM_RCP_DATA_DW8_OFS (0x9d62c456UL) 53 #define KM_RCP_DATA_DW8_SEL_A (0xad16725bUL) 54 #define KM_RCP_DATA_DW8_SEL_B (0x341f23e1UL) 55 #define KM_RCP_DATA_EL_A (0x4335d7dbUL) 56 #define KM_RCP_DATA_EL_B (0xda3c8661UL) 57 #define KM_RCP_DATA_FLOW_SET (0x6b56d647UL) 58 #define KM_RCP_DATA_FTM_A (0xdb75ed61UL) 59 #define KM_RCP_DATA_FTM_B (0x427cbcdbUL) 60 #define KM_RCP_DATA_INFO_A (0x2dd79cf0UL) 61 #define KM_RCP_DATA_INFO_B (0xb4decd4aUL) 62 #define KM_RCP_DATA_KEYWAY_A (0xd0e5dc89UL) 63 #define KM_RCP_DATA_KEYWAY_B (0x49ec8d33UL) 64 #define KM_RCP_DATA_KL_A (0xa3eaa0e8UL) 65 #define KM_RCP_DATA_KL_B (0x3ae3f152UL) 66 #define KM_RCP_DATA_MASK_A (0x54d84646UL) 67 #define KM_RCP_DATA_MASK_B (0xcdd117fcUL) 68 #define KM_RCP_DATA_PAIRED (0x7847653UL) 69 #define KM_RCP_DATA_QW0_B_DYN (0xd27cd964UL) 70 #define KM_RCP_DATA_QW0_B_OFS (0x707554c2UL) 71 #define KM_RCP_DATA_QW0_DYN (0x3afdb158UL) 72 #define KM_RCP_DATA_QW0_OFS (0x98f43cfeUL) 73 #define KM_RCP_DATA_QW0_SEL_A (0x78ae3b02UL) 74 #define KM_RCP_DATA_QW0_SEL_B (0xe1a76ab8UL) 75 #define KM_RCP_DATA_QW4_B_DYN (0x2633fd77UL) 76 #define KM_RCP_DATA_QW4_B_OFS (0x843a70d1UL) 77 #define KM_RCP_DATA_QW4_DYN (0xcf7d1798UL) 78 #define KM_RCP_DATA_QW4_OFS (0x6d749a3eUL) 79 #define KM_RCP_DATA_QW4_SEL_A (0x8ce11f11UL) 80 #define KM_RCP_DATA_QW4_SEL_B (0x15e84eabUL) 81 #define KM_RCP_DATA_SW4_B_DYN (0x8c5d5f1UL) 82 #define KM_RCP_DATA_SW4_B_OFS (0xaacc5857UL) 83 #define KM_RCP_DATA_SW5_B_DYN (0xaeb2de45UL) 84 #define KM_RCP_DATA_SW5_B_OFS (0xcbb53e3UL) 85 #define KM_RCP_DATA_SW8_B_DYN (0xcf65bf85UL) 86 #define KM_RCP_DATA_SW8_B_OFS (0x6d6c3223UL) 87 #define KM_RCP_DATA_SW8_DYN (0x9d12ebb0UL) 88 #define KM_RCP_DATA_SW8_OFS (0x3f1b6616UL) 89 #define KM_RCP_DATA_SW8_SEL_A (0x65b75de3UL) 90 #define KM_RCP_DATA_SW8_SEL_B (0xfcbe0c59UL) 91 #define KM_RCP_DATA_SW9_B_DYN (0x6912b431UL) 92 #define KM_RCP_DATA_SW9_B_OFS (0xcb1b3997UL) 93 #define KM_RCP_DATA_SW9_DYN (0xa072c200UL) 94 #define KM_RCP_DATA_SW9_OFS (0x27b4fa6UL) 95 #define KM_RCP_DATA_SW9_SEL_A (0xc3c05657UL) 96 #define KM_RCP_DATA_SW9_SEL_B (0x5ac907edUL) 97 #define KM_RCP_DATA_SWX_CCH (0x5821d596UL) 98 #define KM_RCP_DATA_SWX_OVS_SB (0x808773bdUL) 99 #define KM_RCP_DATA_SWX_SEL_A (0xee011106UL) 100 #define KM_RCP_DATA_SWX_SEL_B (0x770840bcUL) 101 #define KM_RCP_DATA_SYNERGY_MODE (0x35a76c4aUL) 102 #define KM_STATUS (0x2f1f9d13UL) 103 #define KM_STATUS_TCQ_RDY (0x653553c4UL) 104 #define KM_TCAM_CTRL (0x18fbc021UL) 105 #define KM_TCAM_CTRL_ADR (0x6c84a404UL) 106 #define KM_TCAM_CTRL_CNT (0x7c8c3dd5UL) 107 #define KM_TCAM_DATA (0xb72a4238UL) 108 #define KM_TCAM_DATA_T (0xa995a553UL) 109 #define KM_TCI_CTRL (0x1a6da705UL) 110 #define KM_TCI_CTRL_ADR (0xc7590d78UL) 111 #define KM_TCI_CTRL_CNT (0xd75194a9UL) 112 #define KM_TCI_DATA (0xb5bc251cUL) 113 #define KM_TCI_DATA_COLOR (0x324017ecUL) 114 #define KM_TCI_DATA_FT (0x38afba77UL) 115 #define KM_TCQ_CTRL (0xf5e827f3UL) 116 #define KM_TCQ_CTRL_ADR (0xf320cc64UL) 117 #define KM_TCQ_CTRL_CNT (0xe32855b5UL) 118 #define KM_TCQ_DATA (0x5a39a5eaUL) 119 #define KM_TCQ_DATA_BANK_MASK (0x97cf4b5aUL) 120 #define KM_TCQ_DATA_QUAL (0x4422cc93UL) 121 122 #endif /* _NTHW_FPGA_REG_DEFS_KM_ */ 123 124 /* 125 * Auto-generated file - do *NOT* edit 126 */ 127