1 /* 2 * SPDX-License-Identifier: BSD-3-Clause 3 * Copyright(c) 2023 Napatech A/S 4 */ 5 6 #include <errno.h> 7 #include "ntlog.h" 8 9 #include "nthw_drv.h" 10 #include "nthw_register.h" 11 12 static void set_shadow_tx_qp_data(nthw_dbs_t *p, uint32_t index, uint32_t virtual_port); 13 static void flush_tx_qp_data(nthw_dbs_t *p, uint32_t index); 14 static void set_shadow_tx_dr_data(nthw_dbs_t *p, 15 uint32_t index, 16 uint64_t guest_physical_address, 17 uint32_t host_id, 18 uint32_t queue_size, 19 uint32_t port, 20 uint32_t header, 21 uint32_t packed); 22 static void flush_tx_dr_data(nthw_dbs_t *p, uint32_t index); 23 static void set_shadow_rx_dr_data(nthw_dbs_t *p, 24 uint32_t index, 25 uint64_t guest_physical_address, 26 uint32_t host_id, 27 uint32_t queue_size, 28 uint32_t header, 29 uint32_t packed); 30 static void flush_rx_dr_data(nthw_dbs_t *p, uint32_t index); 31 static void set_shadow_tx_uw_data(nthw_dbs_t *p, 32 uint32_t index, 33 uint64_t guest_physical_address, 34 uint32_t host_id, 35 uint32_t queue_size, 36 uint32_t packed, 37 uint32_t int_enable, 38 uint32_t vec, 39 uint32_t istk, 40 uint32_t in_order); 41 static void flush_tx_uw_data(nthw_dbs_t *p, uint32_t index); 42 static void set_shadow_rx_uw_data(nthw_dbs_t *p, 43 uint32_t index, 44 uint64_t guest_physical_address, 45 uint32_t host_id, 46 uint32_t queue_size, 47 uint32_t packed, 48 uint32_t int_enable, 49 uint32_t vec, 50 uint32_t istk); 51 static void flush_rx_uw_data(nthw_dbs_t *p, uint32_t index); 52 static void set_shadow_rx_am_data(nthw_dbs_t *p, 53 uint32_t index, 54 uint64_t guest_physical_address, 55 uint32_t enable, 56 uint32_t host_id, 57 uint32_t packed, 58 uint32_t int_enable); 59 static void flush_rx_am_data(nthw_dbs_t *p, uint32_t index); 60 static void set_shadow_tx_am_data(nthw_dbs_t *p, 61 uint32_t index, 62 uint64_t guest_physical_address, 63 uint32_t enable, 64 uint32_t host_id, 65 uint32_t packed, 66 uint32_t int_enable); 67 static void flush_tx_am_data(nthw_dbs_t *p, uint32_t index); 68 69 nthw_dbs_t *nthw_dbs_new(void) 70 { 71 nthw_dbs_t *p = malloc(sizeof(nthw_dbs_t)); 72 73 if (p) 74 memset(p, 0, sizeof(nthw_dbs_t)); 75 76 return p; 77 } 78 79 int dbs_init(nthw_dbs_t *p, nthw_fpga_t *p_fpga, int n_instance) 80 { 81 nthw_module_t *mod = nthw_fpga_query_module(p_fpga, MOD_DBS, n_instance); 82 83 if (p == NULL) 84 return mod == NULL ? -1 : 0; 85 86 if (mod == NULL) { 87 NT_LOG(ERR, NTHW, "%s: DBS %d: no such instance", 88 p_fpga->p_fpga_info->mp_adapter_id_str, n_instance); 89 return -1; 90 } 91 92 p->mp_fpga = p_fpga; 93 p->mn_instance = n_instance; 94 p->mp_mod_dbs = mod; 95 96 p->mn_param_dbs_present = nthw_fpga_get_product_param(p_fpga, NT_DBS_PRESENT, 0); 97 98 if (p->mn_param_dbs_present == 0) { 99 NT_LOG(WRN, NTHW, 100 "%s: DBS %d: logical error: module found but not flagged at present", 101 p->mp_fpga->p_fpga_info->mp_adapter_id_str, p->mn_instance); 102 } 103 104 p->mp_reg_rx_control = nthw_module_get_register(p->mp_mod_dbs, DBS_RX_CONTROL); 105 p->mp_fld_rx_control_last_queue = 106 nthw_register_get_field(p->mp_reg_rx_control, DBS_RX_CONTROL_LQ); 107 p->mp_fld_rx_control_avail_monitor_enable = 108 nthw_register_get_field(p->mp_reg_rx_control, DBS_RX_CONTROL_AME); 109 p->mp_fld_rx_control_avail_monitor_scan_speed = 110 nthw_register_get_field(p->mp_reg_rx_control, DBS_RX_CONTROL_AMS); 111 p->mp_fld_rx_control_used_write_enable = 112 nthw_register_get_field(p->mp_reg_rx_control, DBS_RX_CONTROL_UWE); 113 p->mp_fld_rx_control_used_writer_update_speed = 114 nthw_register_get_field(p->mp_reg_rx_control, DBS_RX_CONTROL_UWS); 115 p->mp_fld_rx_control_rx_queues_enable = 116 nthw_register_get_field(p->mp_reg_rx_control, DBS_RX_CONTROL_QE); 117 118 p->mp_reg_tx_control = nthw_module_get_register(p->mp_mod_dbs, DBS_TX_CONTROL); 119 p->mp_fld_tx_control_last_queue = 120 nthw_register_get_field(p->mp_reg_tx_control, DBS_TX_CONTROL_LQ); 121 p->mp_fld_tx_control_avail_monitor_enable = 122 nthw_register_get_field(p->mp_reg_tx_control, DBS_TX_CONTROL_AME); 123 p->mp_fld_tx_control_avail_monitor_scan_speed = 124 nthw_register_get_field(p->mp_reg_tx_control, DBS_TX_CONTROL_AMS); 125 p->mp_fld_tx_control_used_write_enable = 126 nthw_register_get_field(p->mp_reg_tx_control, DBS_TX_CONTROL_UWE); 127 p->mp_fld_tx_control_used_writer_update_speed = 128 nthw_register_get_field(p->mp_reg_tx_control, DBS_TX_CONTROL_UWS); 129 p->mp_fld_tx_control_tx_queues_enable = 130 nthw_register_get_field(p->mp_reg_tx_control, DBS_TX_CONTROL_QE); 131 132 p->mp_reg_rx_init = nthw_module_get_register(p->mp_mod_dbs, DBS_RX_INIT); 133 p->mp_fld_rx_init_init = nthw_register_get_field(p->mp_reg_rx_init, DBS_RX_INIT_INIT); 134 p->mp_fld_rx_init_queue = nthw_register_get_field(p->mp_reg_rx_init, DBS_RX_INIT_QUEUE); 135 p->mp_fld_rx_init_busy = nthw_register_get_field(p->mp_reg_rx_init, DBS_RX_INIT_BUSY); 136 137 p->mp_reg_rx_init_val = nthw_module_query_register(p->mp_mod_dbs, DBS_RX_INIT_VAL); 138 139 if (p->mp_reg_rx_init_val) { 140 p->mp_fld_rx_init_val_idx = 141 nthw_register_query_field(p->mp_reg_rx_init_val, DBS_RX_INIT_VAL_IDX); 142 p->mp_fld_rx_init_val_ptr = 143 nthw_register_query_field(p->mp_reg_rx_init_val, DBS_RX_INIT_VAL_PTR); 144 } 145 146 p->mp_reg_rx_ptr = nthw_module_query_register(p->mp_mod_dbs, DBS_RX_PTR); 147 148 if (p->mp_reg_rx_ptr) { 149 p->mp_fld_rx_ptr_ptr = nthw_register_query_field(p->mp_reg_rx_ptr, DBS_RX_PTR_PTR); 150 p->mp_fld_rx_ptr_queue = 151 nthw_register_query_field(p->mp_reg_rx_ptr, DBS_RX_PTR_QUEUE); 152 p->mp_fld_rx_ptr_valid = 153 nthw_register_query_field(p->mp_reg_rx_ptr, DBS_RX_PTR_VALID); 154 } 155 156 p->mp_reg_tx_init = nthw_module_get_register(p->mp_mod_dbs, DBS_TX_INIT); 157 p->mp_fld_tx_init_init = nthw_register_get_field(p->mp_reg_tx_init, DBS_TX_INIT_INIT); 158 p->mp_fld_tx_init_queue = nthw_register_get_field(p->mp_reg_tx_init, DBS_TX_INIT_QUEUE); 159 p->mp_fld_tx_init_busy = nthw_register_get_field(p->mp_reg_tx_init, DBS_TX_INIT_BUSY); 160 161 p->mp_reg_tx_init_val = nthw_module_query_register(p->mp_mod_dbs, DBS_TX_INIT_VAL); 162 163 if (p->mp_reg_tx_init_val) { 164 p->mp_fld_tx_init_val_idx = 165 nthw_register_query_field(p->mp_reg_tx_init_val, DBS_TX_INIT_VAL_IDX); 166 p->mp_fld_tx_init_val_ptr = 167 nthw_register_query_field(p->mp_reg_tx_init_val, DBS_TX_INIT_VAL_PTR); 168 } 169 170 p->mp_reg_tx_ptr = nthw_module_query_register(p->mp_mod_dbs, DBS_TX_PTR); 171 172 if (p->mp_reg_tx_ptr) { 173 p->mp_fld_tx_ptr_ptr = nthw_register_query_field(p->mp_reg_tx_ptr, DBS_TX_PTR_PTR); 174 p->mp_fld_tx_ptr_queue = 175 nthw_register_query_field(p->mp_reg_tx_ptr, DBS_TX_PTR_QUEUE); 176 p->mp_fld_tx_ptr_valid = 177 nthw_register_query_field(p->mp_reg_tx_ptr, DBS_TX_PTR_VALID); 178 } 179 180 p->mp_reg_rx_idle = nthw_module_query_register(p->mp_mod_dbs, DBS_RX_IDLE); 181 182 if (p->mp_reg_rx_idle) { 183 p->mp_fld_rx_idle_idle = 184 nthw_register_query_field(p->mp_reg_rx_idle, DBS_RX_IDLE_IDLE); 185 p->mp_fld_rx_idle_queue = 186 nthw_register_query_field(p->mp_reg_rx_idle, DBS_RX_IDLE_QUEUE); 187 p->mp_fld_rx_idle_busy = 188 nthw_register_query_field(p->mp_reg_rx_idle, DBS_RX_IDLE_BUSY); 189 } 190 191 p->mp_reg_tx_idle = nthw_module_query_register(p->mp_mod_dbs, DBS_TX_IDLE); 192 193 if (p->mp_reg_tx_idle) { 194 p->mp_fld_tx_idle_idle = 195 nthw_register_query_field(p->mp_reg_tx_idle, DBS_TX_IDLE_IDLE); 196 p->mp_fld_tx_idle_queue = 197 nthw_register_query_field(p->mp_reg_tx_idle, DBS_TX_IDLE_QUEUE); 198 p->mp_fld_tx_idle_busy = 199 nthw_register_query_field(p->mp_reg_tx_idle, DBS_TX_IDLE_BUSY); 200 } 201 202 p->mp_reg_rx_avail_monitor_control = 203 nthw_module_get_register(p->mp_mod_dbs, DBS_RX_AM_CTRL); 204 p->mp_fld_rx_avail_monitor_control_adr = 205 nthw_register_get_field(p->mp_reg_rx_avail_monitor_control, DBS_RX_AM_CTRL_ADR); 206 p->mp_fld_rx_avail_monitor_control_cnt = 207 nthw_register_get_field(p->mp_reg_rx_avail_monitor_control, DBS_RX_AM_CTRL_CNT); 208 209 p->mp_reg_rx_avail_monitor_data = nthw_module_get_register(p->mp_mod_dbs, DBS_RX_AM_DATA); 210 p->mp_fld_rx_avail_monitor_data_guest_physical_address = 211 nthw_register_get_field(p->mp_reg_rx_avail_monitor_data, DBS_RX_AM_DATA_GPA); 212 p->mp_fld_rx_avail_monitor_data_enable = 213 nthw_register_get_field(p->mp_reg_rx_avail_monitor_data, DBS_RX_AM_DATA_ENABLE); 214 p->mp_fld_rx_avail_monitor_data_host_id = 215 nthw_register_get_field(p->mp_reg_rx_avail_monitor_data, DBS_RX_AM_DATA_HID); 216 p->mp_fld_rx_avail_monitor_data_packed = 217 nthw_register_query_field(p->mp_reg_rx_avail_monitor_data, DBS_RX_AM_DATA_PCKED); 218 p->mp_fld_rx_avail_monitor_data_int = 219 nthw_register_query_field(p->mp_reg_rx_avail_monitor_data, DBS_RX_AM_DATA_INT); 220 221 p->mp_reg_tx_avail_monitor_control = 222 nthw_module_get_register(p->mp_mod_dbs, DBS_TX_AM_CTRL); 223 p->mp_fld_tx_avail_monitor_control_adr = 224 nthw_register_get_field(p->mp_reg_tx_avail_monitor_control, DBS_TX_AM_CTRL_ADR); 225 p->mp_fld_tx_avail_monitor_control_cnt = 226 nthw_register_get_field(p->mp_reg_tx_avail_monitor_control, DBS_TX_AM_CTRL_CNT); 227 228 p->mp_reg_tx_avail_monitor_data = nthw_module_get_register(p->mp_mod_dbs, DBS_TX_AM_DATA); 229 p->mp_fld_tx_avail_monitor_data_guest_physical_address = 230 nthw_register_get_field(p->mp_reg_tx_avail_monitor_data, DBS_TX_AM_DATA_GPA); 231 p->mp_fld_tx_avail_monitor_data_enable = 232 nthw_register_get_field(p->mp_reg_tx_avail_monitor_data, DBS_TX_AM_DATA_ENABLE); 233 p->mp_fld_tx_avail_monitor_data_host_id = 234 nthw_register_get_field(p->mp_reg_tx_avail_monitor_data, DBS_TX_AM_DATA_HID); 235 p->mp_fld_tx_avail_monitor_data_packed = 236 nthw_register_query_field(p->mp_reg_tx_avail_monitor_data, DBS_TX_AM_DATA_PCKED); 237 p->mp_fld_tx_avail_monitor_data_int = 238 nthw_register_query_field(p->mp_reg_tx_avail_monitor_data, DBS_TX_AM_DATA_INT); 239 240 p->mp_reg_rx_used_writer_control = nthw_module_get_register(p->mp_mod_dbs, DBS_RX_UW_CTRL); 241 p->mp_fld_rx_used_writer_control_adr = 242 nthw_register_get_field(p->mp_reg_rx_used_writer_control, DBS_RX_UW_CTRL_ADR); 243 p->mp_fld_rx_used_writer_control_cnt = 244 nthw_register_get_field(p->mp_reg_rx_used_writer_control, DBS_RX_UW_CTRL_CNT); 245 246 p->mp_reg_rx_used_writer_data = nthw_module_get_register(p->mp_mod_dbs, DBS_RX_UW_DATA); 247 p->mp_fld_rx_used_writer_data_guest_physical_address = 248 nthw_register_get_field(p->mp_reg_rx_used_writer_data, DBS_RX_UW_DATA_GPA); 249 p->mp_fld_rx_used_writer_data_host_id = 250 nthw_register_get_field(p->mp_reg_rx_used_writer_data, DBS_RX_UW_DATA_HID); 251 p->mp_fld_rx_used_writer_data_queue_size = 252 nthw_register_get_field(p->mp_reg_rx_used_writer_data, DBS_RX_UW_DATA_QS); 253 p->mp_fld_rx_used_writer_data_packed = 254 nthw_register_query_field(p->mp_reg_rx_used_writer_data, DBS_RX_UW_DATA_PCKED); 255 p->mp_fld_rx_used_writer_data_int = 256 nthw_register_query_field(p->mp_reg_rx_used_writer_data, DBS_RX_UW_DATA_INT); 257 p->mp_fld_rx_used_writer_data_vec = 258 nthw_register_query_field(p->mp_reg_rx_used_writer_data, DBS_RX_UW_DATA_VEC); 259 p->mp_fld_rx_used_writer_data_istk = 260 nthw_register_query_field(p->mp_reg_rx_used_writer_data, DBS_RX_UW_DATA_ISTK); 261 262 p->mp_reg_tx_used_writer_control = nthw_module_get_register(p->mp_mod_dbs, DBS_TX_UW_CTRL); 263 p->mp_fld_tx_used_writer_control_adr = 264 nthw_register_get_field(p->mp_reg_tx_used_writer_control, DBS_TX_UW_CTRL_ADR); 265 p->mp_fld_tx_used_writer_control_cnt = 266 nthw_register_get_field(p->mp_reg_tx_used_writer_control, DBS_TX_UW_CTRL_CNT); 267 268 p->mp_reg_tx_used_writer_data = nthw_module_get_register(p->mp_mod_dbs, DBS_TX_UW_DATA); 269 p->mp_fld_tx_used_writer_data_guest_physical_address = 270 nthw_register_get_field(p->mp_reg_tx_used_writer_data, DBS_TX_UW_DATA_GPA); 271 p->mp_fld_tx_used_writer_data_host_id = 272 nthw_register_get_field(p->mp_reg_tx_used_writer_data, DBS_TX_UW_DATA_HID); 273 p->mp_fld_tx_used_writer_data_queue_size = 274 nthw_register_get_field(p->mp_reg_tx_used_writer_data, DBS_TX_UW_DATA_QS); 275 p->mp_fld_tx_used_writer_data_packed = 276 nthw_register_query_field(p->mp_reg_tx_used_writer_data, DBS_TX_UW_DATA_PCKED); 277 p->mp_fld_tx_used_writer_data_int = 278 nthw_register_query_field(p->mp_reg_tx_used_writer_data, DBS_TX_UW_DATA_INT); 279 p->mp_fld_tx_used_writer_data_vec = 280 nthw_register_query_field(p->mp_reg_tx_used_writer_data, DBS_TX_UW_DATA_VEC); 281 p->mp_fld_tx_used_writer_data_istk = 282 nthw_register_query_field(p->mp_reg_tx_used_writer_data, DBS_TX_UW_DATA_ISTK); 283 p->mp_fld_tx_used_writer_data_in_order = 284 nthw_register_query_field(p->mp_reg_tx_used_writer_data, DBS_TX_UW_DATA_INO); 285 286 p->mp_reg_rx_descriptor_reader_control = 287 nthw_module_get_register(p->mp_mod_dbs, DBS_RX_DR_CTRL); 288 p->mp_fld_rx_descriptor_reader_control_adr = 289 nthw_register_get_field(p->mp_reg_rx_descriptor_reader_control, 290 DBS_RX_DR_CTRL_ADR); 291 p->mp_fld_rx_descriptor_reader_control_cnt = 292 nthw_register_get_field(p->mp_reg_rx_descriptor_reader_control, 293 DBS_RX_DR_CTRL_CNT); 294 295 p->mp_reg_rx_descriptor_reader_data = 296 nthw_module_get_register(p->mp_mod_dbs, DBS_RX_DR_DATA); 297 p->mp_fld_rx_descriptor_reader_data_guest_physical_address = 298 nthw_register_get_field(p->mp_reg_rx_descriptor_reader_data, DBS_RX_DR_DATA_GPA); 299 p->mp_fld_rx_descriptor_reader_data_host_id = 300 nthw_register_get_field(p->mp_reg_rx_descriptor_reader_data, DBS_RX_DR_DATA_HID); 301 p->mp_fld_rx_descriptor_reader_data_queue_size = 302 nthw_register_get_field(p->mp_reg_rx_descriptor_reader_data, DBS_RX_DR_DATA_QS); 303 p->mp_fld_rx_descriptor_reader_data_header = 304 nthw_register_get_field(p->mp_reg_rx_descriptor_reader_data, DBS_RX_DR_DATA_HDR); 305 p->mp_fld_rx_descriptor_reader_data_packed = 306 nthw_register_query_field(p->mp_reg_rx_descriptor_reader_data, 307 DBS_RX_DR_DATA_PCKED); 308 309 p->mp_reg_tx_descriptor_reader_control = 310 nthw_module_get_register(p->mp_mod_dbs, DBS_TX_DR_CTRL); 311 p->mp_fld_tx_descriptor_reader_control_adr = 312 nthw_register_get_field(p->mp_reg_tx_descriptor_reader_control, 313 DBS_TX_DR_CTRL_ADR); 314 p->mp_fld_tx_descriptor_reader_control_cnt = 315 nthw_register_get_field(p->mp_reg_tx_descriptor_reader_control, 316 DBS_TX_DR_CTRL_CNT); 317 318 p->mp_reg_tx_descriptor_reader_data = 319 nthw_module_get_register(p->mp_mod_dbs, DBS_TX_DR_DATA); 320 p->mp_fld_tx_descriptor_reader_data_guest_physical_address = 321 nthw_register_get_field(p->mp_reg_tx_descriptor_reader_data, DBS_TX_DR_DATA_GPA); 322 p->mp_fld_tx_descriptor_reader_data_host_id = 323 nthw_register_get_field(p->mp_reg_tx_descriptor_reader_data, DBS_TX_DR_DATA_HID); 324 p->mp_fld_tx_descriptor_reader_data_queue_size = 325 nthw_register_get_field(p->mp_reg_tx_descriptor_reader_data, DBS_TX_DR_DATA_QS); 326 p->mp_fld_tx_descriptor_reader_data_header = 327 nthw_register_get_field(p->mp_reg_tx_descriptor_reader_data, DBS_TX_DR_DATA_HDR); 328 p->mp_fld_tx_descriptor_reader_data_port = 329 nthw_register_get_field(p->mp_reg_tx_descriptor_reader_data, DBS_TX_DR_DATA_PORT); 330 p->mp_fld_tx_descriptor_reader_data_packed = 331 nthw_register_query_field(p->mp_reg_tx_descriptor_reader_data, 332 DBS_TX_DR_DATA_PCKED); 333 334 p->mp_reg_tx_queue_property_control = 335 nthw_module_get_register(p->mp_mod_dbs, DBS_TX_QP_CTRL); 336 p->mp_fld_tx_queue_property_control_adr = 337 nthw_register_get_field(p->mp_reg_tx_queue_property_control, DBS_TX_QP_CTRL_ADR); 338 p->mp_fld_tx_queue_property_control_cnt = 339 nthw_register_get_field(p->mp_reg_tx_queue_property_control, DBS_TX_QP_CTRL_CNT); 340 341 p->mp_reg_tx_queue_property_data = nthw_module_get_register(p->mp_mod_dbs, DBS_TX_QP_DATA); 342 p->mp_fld_tx_queue_property_data_v_port = 343 nthw_register_get_field(p->mp_reg_tx_queue_property_data, DBS_TX_QP_DATA_VPORT); 344 345 return 0; 346 } 347 348 static int dbs_reset_rx_control(nthw_dbs_t *p) 349 { 350 nthw_field_set_val32(p->mp_fld_rx_control_last_queue, 0); 351 nthw_field_set_val32(p->mp_fld_rx_control_avail_monitor_enable, 0); 352 nthw_field_set_val32(p->mp_fld_rx_control_avail_monitor_scan_speed, 8); 353 nthw_field_set_val32(p->mp_fld_rx_control_used_write_enable, 0); 354 nthw_field_set_val32(p->mp_fld_rx_control_used_writer_update_speed, 5); 355 nthw_field_set_val32(p->mp_fld_rx_control_rx_queues_enable, 0); 356 nthw_register_flush(p->mp_reg_rx_control, 1); 357 return 0; 358 } 359 360 static int dbs_reset_tx_control(nthw_dbs_t *p) 361 { 362 nthw_field_set_val32(p->mp_fld_tx_control_last_queue, 0); 363 nthw_field_set_val32(p->mp_fld_tx_control_avail_monitor_enable, 0); 364 nthw_field_set_val32(p->mp_fld_tx_control_avail_monitor_scan_speed, 5); 365 nthw_field_set_val32(p->mp_fld_tx_control_used_write_enable, 0); 366 nthw_field_set_val32(p->mp_fld_tx_control_used_writer_update_speed, 8); 367 nthw_field_set_val32(p->mp_fld_tx_control_tx_queues_enable, 0); 368 nthw_register_flush(p->mp_reg_tx_control, 1); 369 return 0; 370 } 371 372 void dbs_reset(nthw_dbs_t *p) 373 { 374 int i; 375 dbs_reset_rx_control(p); 376 dbs_reset_tx_control(p); 377 378 /* Reset RX memory banks and shado */ 379 for (i = 0; i < NT_DBS_RX_QUEUES_MAX; ++i) { 380 set_shadow_rx_am_data(p, i, 0, 0, 0, 0, 0); 381 flush_rx_am_data(p, i); 382 383 set_shadow_rx_uw_data(p, i, 0, 0, 0, 0, 0, 0, 0); 384 flush_rx_uw_data(p, i); 385 386 set_shadow_rx_dr_data(p, i, 0, 0, 0, 0, 0); 387 flush_rx_dr_data(p, i); 388 } 389 390 /* Reset TX memory banks and shado */ 391 for (i = 0; i < NT_DBS_TX_QUEUES_MAX; ++i) { 392 set_shadow_tx_am_data(p, i, 0, 0, 0, 0, 0); 393 flush_tx_am_data(p, i); 394 395 set_shadow_tx_uw_data(p, i, 0, 0, 0, 0, 0, 0, 0, 0); 396 flush_tx_uw_data(p, i); 397 398 set_shadow_tx_dr_data(p, i, 0, 0, 0, 0, 0, 0); 399 flush_tx_dr_data(p, i); 400 401 set_shadow_tx_qp_data(p, i, 0); 402 flush_tx_qp_data(p, i); 403 } 404 } 405 406 int set_rx_control(nthw_dbs_t *p, 407 uint32_t last_queue, 408 uint32_t avail_monitor_enable, 409 uint32_t avail_monitor_speed, 410 uint32_t used_write_enable, 411 uint32_t used_write_speed, 412 uint32_t rx_queue_enable) 413 { 414 nthw_field_set_val32(p->mp_fld_rx_control_last_queue, last_queue); 415 nthw_field_set_val32(p->mp_fld_rx_control_avail_monitor_enable, avail_monitor_enable); 416 nthw_field_set_val32(p->mp_fld_rx_control_avail_monitor_scan_speed, avail_monitor_speed); 417 nthw_field_set_val32(p->mp_fld_rx_control_used_write_enable, used_write_enable); 418 nthw_field_set_val32(p->mp_fld_rx_control_used_writer_update_speed, used_write_speed); 419 nthw_field_set_val32(p->mp_fld_rx_control_rx_queues_enable, rx_queue_enable); 420 nthw_register_flush(p->mp_reg_rx_control, 1); 421 return 0; 422 } 423 424 int set_tx_control(nthw_dbs_t *p, 425 uint32_t last_queue, 426 uint32_t avail_monitor_enable, 427 uint32_t avail_monitor_speed, 428 uint32_t used_write_enable, 429 uint32_t used_write_speed, 430 uint32_t tx_queue_enable) 431 { 432 nthw_field_set_val32(p->mp_fld_tx_control_last_queue, last_queue); 433 nthw_field_set_val32(p->mp_fld_tx_control_avail_monitor_enable, avail_monitor_enable); 434 nthw_field_set_val32(p->mp_fld_tx_control_avail_monitor_scan_speed, avail_monitor_speed); 435 nthw_field_set_val32(p->mp_fld_tx_control_used_write_enable, used_write_enable); 436 nthw_field_set_val32(p->mp_fld_tx_control_used_writer_update_speed, used_write_speed); 437 nthw_field_set_val32(p->mp_fld_tx_control_tx_queues_enable, tx_queue_enable); 438 nthw_register_flush(p->mp_reg_tx_control, 1); 439 return 0; 440 } 441 442 int set_rx_init(nthw_dbs_t *p, uint32_t start_idx, uint32_t start_ptr, uint32_t init, 443 uint32_t queue) 444 { 445 if (p->mp_reg_rx_init_val) { 446 nthw_field_set_val32(p->mp_fld_rx_init_val_idx, start_idx); 447 nthw_field_set_val32(p->mp_fld_rx_init_val_ptr, start_ptr); 448 nthw_register_flush(p->mp_reg_rx_init_val, 1); 449 } 450 451 nthw_field_set_val32(p->mp_fld_rx_init_init, init); 452 nthw_field_set_val32(p->mp_fld_rx_init_queue, queue); 453 nthw_register_flush(p->mp_reg_rx_init, 1); 454 return 0; 455 } 456 457 int get_rx_init(nthw_dbs_t *p, uint32_t *init, uint32_t *queue, uint32_t *busy) 458 { 459 *init = nthw_field_get_val32(p->mp_fld_rx_init_init); 460 *queue = nthw_field_get_val32(p->mp_fld_rx_init_queue); 461 *busy = nthw_field_get_val32(p->mp_fld_rx_init_busy); 462 return 0; 463 } 464 465 int set_tx_init(nthw_dbs_t *p, uint32_t start_idx, uint32_t start_ptr, uint32_t init, 466 uint32_t queue) 467 { 468 if (p->mp_reg_tx_init_val) { 469 nthw_field_set_val32(p->mp_fld_tx_init_val_idx, start_idx); 470 nthw_field_set_val32(p->mp_fld_tx_init_val_ptr, start_ptr); 471 nthw_register_flush(p->mp_reg_tx_init_val, 1); 472 } 473 474 nthw_field_set_val32(p->mp_fld_tx_init_init, init); 475 nthw_field_set_val32(p->mp_fld_tx_init_queue, queue); 476 nthw_register_flush(p->mp_reg_tx_init, 1); 477 return 0; 478 } 479 480 int get_tx_init(nthw_dbs_t *p, uint32_t *init, uint32_t *queue, uint32_t *busy) 481 { 482 *init = nthw_field_get_val32(p->mp_fld_tx_init_init); 483 *queue = nthw_field_get_val32(p->mp_fld_tx_init_queue); 484 *busy = nthw_field_get_val32(p->mp_fld_tx_init_busy); 485 return 0; 486 } 487 488 int set_rx_idle(nthw_dbs_t *p, uint32_t idle, uint32_t queue) 489 { 490 if (!p->mp_reg_rx_idle) 491 return -ENOTSUP; 492 493 nthw_field_set_val32(p->mp_fld_rx_idle_idle, idle); 494 nthw_field_set_val32(p->mp_fld_rx_idle_queue, queue); 495 nthw_register_flush(p->mp_reg_rx_idle, 1); 496 return 0; 497 } 498 499 int get_rx_idle(nthw_dbs_t *p, uint32_t *idle, uint32_t *queue, uint32_t *busy) 500 { 501 if (!p->mp_reg_rx_idle) 502 return -ENOTSUP; 503 504 *idle = nthw_field_get_updated(p->mp_fld_rx_idle_idle); 505 *queue = 0; 506 *busy = nthw_field_get_updated(p->mp_fld_rx_idle_busy); 507 return 0; 508 } 509 510 int set_tx_idle(nthw_dbs_t *p, uint32_t idle, uint32_t queue) 511 { 512 if (!p->mp_reg_tx_idle) 513 return -ENOTSUP; 514 515 nthw_field_set_val32(p->mp_fld_tx_idle_idle, idle); 516 nthw_field_set_val32(p->mp_fld_tx_idle_queue, queue); 517 nthw_register_flush(p->mp_reg_tx_idle, 1); 518 return 0; 519 } 520 521 int get_tx_idle(nthw_dbs_t *p, uint32_t *idle, uint32_t *queue, uint32_t *busy) 522 { 523 if (!p->mp_reg_tx_idle) 524 return -ENOTSUP; 525 526 *idle = nthw_field_get_updated(p->mp_fld_tx_idle_idle); 527 *queue = 0; 528 *busy = nthw_field_get_updated(p->mp_fld_tx_idle_busy); 529 return 0; 530 } 531 532 533 static void set_rx_am_data_index(nthw_dbs_t *p, uint32_t index) 534 { 535 nthw_field_set_val32(p->mp_fld_rx_avail_monitor_control_adr, index); 536 nthw_field_set_val32(p->mp_fld_rx_avail_monitor_control_cnt, 1); 537 nthw_register_flush(p->mp_reg_rx_avail_monitor_control, 1); 538 } 539 540 static void set_shadow_rx_am_data_guest_physical_address(nthw_dbs_t *p, uint32_t index, 541 uint64_t guest_physical_address) 542 { 543 p->m_rx_am_shadow[index].guest_physical_address = guest_physical_address; 544 } 545 546 static void nthw_dbs_set_shadow_rx_am_data_enable(nthw_dbs_t *p, uint32_t index, uint32_t enable) 547 { 548 p->m_rx_am_shadow[index].enable = enable; 549 } 550 551 static void set_shadow_rx_am_data_host_id(nthw_dbs_t *p, uint32_t index, uint32_t host_id) 552 { 553 p->m_rx_am_shadow[index].host_id = host_id; 554 } 555 556 static void set_shadow_rx_am_data_packed(nthw_dbs_t *p, uint32_t index, uint32_t packed) 557 { 558 p->m_rx_am_shadow[index].packed = packed; 559 } 560 561 static void set_shadow_rx_am_data_int_enable(nthw_dbs_t *p, uint32_t index, uint32_t int_enable) 562 { 563 p->m_rx_am_shadow[index].int_enable = int_enable; 564 } 565 566 static void set_shadow_rx_am_data(nthw_dbs_t *p, 567 uint32_t index, 568 uint64_t guest_physical_address, 569 uint32_t enable, 570 uint32_t host_id, 571 uint32_t packed, 572 uint32_t int_enable) 573 { 574 set_shadow_rx_am_data_guest_physical_address(p, index, guest_physical_address); 575 nthw_dbs_set_shadow_rx_am_data_enable(p, index, enable); 576 set_shadow_rx_am_data_host_id(p, index, host_id); 577 set_shadow_rx_am_data_packed(p, index, packed); 578 set_shadow_rx_am_data_int_enable(p, index, int_enable); 579 } 580 581 static void flush_rx_am_data(nthw_dbs_t *p, uint32_t index) 582 { 583 nthw_field_set_val(p->mp_fld_rx_avail_monitor_data_guest_physical_address, 584 (uint32_t *)&p->m_rx_am_shadow[index].guest_physical_address, 2); 585 nthw_field_set_val32(p->mp_fld_rx_avail_monitor_data_enable, 586 p->m_rx_am_shadow[index].enable); 587 nthw_field_set_val32(p->mp_fld_rx_avail_monitor_data_host_id, 588 p->m_rx_am_shadow[index].host_id); 589 590 if (p->mp_fld_rx_avail_monitor_data_packed) { 591 nthw_field_set_val32(p->mp_fld_rx_avail_monitor_data_packed, 592 p->m_rx_am_shadow[index].packed); 593 } 594 595 if (p->mp_fld_rx_avail_monitor_data_int) { 596 nthw_field_set_val32(p->mp_fld_rx_avail_monitor_data_int, 597 p->m_rx_am_shadow[index].int_enable); 598 } 599 600 set_rx_am_data_index(p, index); 601 nthw_register_flush(p->mp_reg_rx_avail_monitor_data, 1); 602 } 603 604 int set_rx_am_data(nthw_dbs_t *p, 605 uint32_t index, 606 uint64_t guest_physical_address, 607 uint32_t enable, 608 uint32_t host_id, 609 uint32_t packed, 610 uint32_t int_enable) 611 { 612 if (!p->mp_reg_rx_avail_monitor_data) 613 return -ENOTSUP; 614 615 set_shadow_rx_am_data(p, index, guest_physical_address, enable, host_id, packed, 616 int_enable); 617 flush_rx_am_data(p, index); 618 return 0; 619 } 620 621 static void set_tx_am_data_index(nthw_dbs_t *p, uint32_t index) 622 { 623 nthw_field_set_val32(p->mp_fld_tx_avail_monitor_control_adr, index); 624 nthw_field_set_val32(p->mp_fld_tx_avail_monitor_control_cnt, 1); 625 nthw_register_flush(p->mp_reg_tx_avail_monitor_control, 1); 626 } 627 628 static void set_shadow_tx_am_data(nthw_dbs_t *p, 629 uint32_t index, 630 uint64_t guest_physical_address, 631 uint32_t enable, 632 uint32_t host_id, 633 uint32_t packed, 634 uint32_t int_enable) 635 { 636 p->m_tx_am_shadow[index].guest_physical_address = guest_physical_address; 637 p->m_tx_am_shadow[index].enable = enable; 638 p->m_tx_am_shadow[index].host_id = host_id; 639 p->m_tx_am_shadow[index].packed = packed; 640 p->m_tx_am_shadow[index].int_enable = int_enable; 641 } 642 643 static void flush_tx_am_data(nthw_dbs_t *p, uint32_t index) 644 { 645 nthw_field_set_val(p->mp_fld_tx_avail_monitor_data_guest_physical_address, 646 (uint32_t *)&p->m_tx_am_shadow[index].guest_physical_address, 2); 647 nthw_field_set_val32(p->mp_fld_tx_avail_monitor_data_enable, 648 p->m_tx_am_shadow[index].enable); 649 nthw_field_set_val32(p->mp_fld_tx_avail_monitor_data_host_id, 650 p->m_tx_am_shadow[index].host_id); 651 652 if (p->mp_fld_tx_avail_monitor_data_packed) { 653 nthw_field_set_val32(p->mp_fld_tx_avail_monitor_data_packed, 654 p->m_tx_am_shadow[index].packed); 655 } 656 657 if (p->mp_fld_tx_avail_monitor_data_int) { 658 nthw_field_set_val32(p->mp_fld_tx_avail_monitor_data_int, 659 p->m_tx_am_shadow[index].int_enable); 660 } 661 662 set_tx_am_data_index(p, index); 663 nthw_register_flush(p->mp_reg_tx_avail_monitor_data, 1); 664 } 665 666 int set_tx_am_data(nthw_dbs_t *p, 667 uint32_t index, 668 uint64_t guest_physical_address, 669 uint32_t enable, 670 uint32_t host_id, 671 uint32_t packed, 672 uint32_t int_enable) 673 { 674 if (!p->mp_reg_tx_avail_monitor_data) 675 return -ENOTSUP; 676 677 set_shadow_tx_am_data(p, index, guest_physical_address, enable, host_id, packed, 678 int_enable); 679 flush_tx_am_data(p, index); 680 return 0; 681 } 682 683 static void set_rx_uw_data_index(nthw_dbs_t *p, uint32_t index) 684 { 685 nthw_field_set_val32(p->mp_fld_rx_used_writer_control_adr, index); 686 nthw_field_set_val32(p->mp_fld_rx_used_writer_control_cnt, 1); 687 nthw_register_flush(p->mp_reg_rx_used_writer_control, 1); 688 } 689 690 static void set_shadow_rx_uw_data_guest_physical_address(nthw_dbs_t *p, uint32_t index, 691 uint64_t guest_physical_address) 692 { 693 p->m_rx_uw_shadow[index].guest_physical_address = guest_physical_address; 694 } 695 696 static void set_shadow_rx_uw_data_host_id(nthw_dbs_t *p, uint32_t index, uint32_t host_id) 697 { 698 p->m_rx_uw_shadow[index].host_id = host_id; 699 } 700 701 static void set_shadow_rx_uw_data_queue_size(nthw_dbs_t *p, uint32_t index, uint32_t queue_size) 702 { 703 p->m_rx_uw_shadow[index].queue_size = queue_size; 704 } 705 706 static void set_shadow_rx_uw_data_packed(nthw_dbs_t *p, uint32_t index, uint32_t packed) 707 { 708 p->m_rx_uw_shadow[index].packed = packed; 709 } 710 711 static void set_shadow_rx_uw_data_int_enable(nthw_dbs_t *p, uint32_t index, uint32_t int_enable) 712 { 713 p->m_rx_uw_shadow[index].int_enable = int_enable; 714 } 715 716 static void set_shadow_rx_uw_data_vec(nthw_dbs_t *p, uint32_t index, uint32_t vec) 717 { 718 p->m_rx_uw_shadow[index].vec = vec; 719 } 720 721 static void set_shadow_rx_uw_data_istk(nthw_dbs_t *p, uint32_t index, uint32_t istk) 722 { 723 p->m_rx_uw_shadow[index].istk = istk; 724 } 725 726 static void set_shadow_rx_uw_data(nthw_dbs_t *p, 727 uint32_t index, 728 uint64_t guest_physical_address, 729 uint32_t host_id, 730 uint32_t queue_size, 731 uint32_t packed, 732 uint32_t int_enable, 733 uint32_t vec, 734 uint32_t istk) 735 { 736 set_shadow_rx_uw_data_guest_physical_address(p, index, guest_physical_address); 737 set_shadow_rx_uw_data_host_id(p, index, host_id); 738 set_shadow_rx_uw_data_queue_size(p, index, queue_size); 739 set_shadow_rx_uw_data_packed(p, index, packed); 740 set_shadow_rx_uw_data_int_enable(p, index, int_enable); 741 set_shadow_rx_uw_data_vec(p, index, vec); 742 set_shadow_rx_uw_data_istk(p, index, istk); 743 } 744 745 static void flush_rx_uw_data(nthw_dbs_t *p, uint32_t index) 746 { 747 nthw_field_set_val(p->mp_fld_rx_used_writer_data_guest_physical_address, 748 (uint32_t *)&p->m_rx_uw_shadow[index].guest_physical_address, 2); 749 nthw_field_set_val32(p->mp_fld_rx_used_writer_data_host_id, 750 p->m_rx_uw_shadow[index].host_id); 751 752 if (nthw_module_is_version_newer(p->mp_mod_dbs, 0, 8)) { 753 nthw_field_set_val32(p->mp_fld_rx_used_writer_data_queue_size, 754 (1U << p->m_rx_uw_shadow[index].queue_size) - 1U); 755 756 } else { 757 nthw_field_set_val32(p->mp_fld_rx_used_writer_data_queue_size, 758 p->m_rx_uw_shadow[index].queue_size); 759 } 760 761 if (p->mp_fld_rx_used_writer_data_packed) { 762 nthw_field_set_val32(p->mp_fld_rx_used_writer_data_packed, 763 p->m_rx_uw_shadow[index].packed); 764 } 765 766 if (p->mp_fld_rx_used_writer_data_int) { 767 nthw_field_set_val32(p->mp_fld_rx_used_writer_data_int, 768 p->m_rx_uw_shadow[index].int_enable); 769 nthw_field_set_val32(p->mp_fld_rx_used_writer_data_vec, 770 p->m_rx_uw_shadow[index].vec); 771 nthw_field_set_val32(p->mp_fld_rx_used_writer_data_istk, 772 p->m_rx_uw_shadow[index].istk); 773 } 774 775 set_rx_uw_data_index(p, index); 776 nthw_register_flush(p->mp_reg_rx_used_writer_data, 1); 777 } 778 779 int set_rx_uw_data(nthw_dbs_t *p, 780 uint32_t index, 781 uint64_t guest_physical_address, 782 uint32_t host_id, 783 uint32_t queue_size, 784 uint32_t packed, 785 uint32_t int_enable, 786 uint32_t vec, 787 uint32_t istk) 788 { 789 if (!p->mp_reg_rx_used_writer_data) 790 return -ENOTSUP; 791 792 set_shadow_rx_uw_data(p, index, guest_physical_address, host_id, queue_size, packed, 793 int_enable, vec, istk); 794 flush_rx_uw_data(p, index); 795 return 0; 796 } 797 798 static void set_tx_uw_data_index(nthw_dbs_t *p, uint32_t index) 799 { 800 nthw_field_set_val32(p->mp_fld_tx_used_writer_control_adr, index); 801 nthw_field_set_val32(p->mp_fld_tx_used_writer_control_cnt, 1); 802 nthw_register_flush(p->mp_reg_tx_used_writer_control, 1); 803 } 804 805 static void set_shadow_tx_uw_data_guest_physical_address(nthw_dbs_t *p, uint32_t index, 806 uint64_t guest_physical_address) 807 { 808 p->m_tx_uw_shadow[index].guest_physical_address = guest_physical_address; 809 } 810 811 static void set_shadow_tx_uw_data_host_id(nthw_dbs_t *p, uint32_t index, uint32_t host_id) 812 { 813 p->m_tx_uw_shadow[index].host_id = host_id; 814 } 815 816 static void set_shadow_tx_uw_data_queue_size(nthw_dbs_t *p, uint32_t index, uint32_t queue_size) 817 { 818 p->m_tx_uw_shadow[index].queue_size = queue_size; 819 } 820 821 static void set_shadow_tx_uw_data_packed(nthw_dbs_t *p, uint32_t index, uint32_t packed) 822 { 823 p->m_tx_uw_shadow[index].packed = packed; 824 } 825 826 static void set_shadow_tx_uw_data_int_enable(nthw_dbs_t *p, uint32_t index, uint32_t int_enable) 827 { 828 p->m_tx_uw_shadow[index].int_enable = int_enable; 829 } 830 831 static void set_shadow_tx_uw_data_vec(nthw_dbs_t *p, uint32_t index, uint32_t vec) 832 { 833 p->m_tx_uw_shadow[index].vec = vec; 834 } 835 836 static void set_shadow_tx_uw_data_istk(nthw_dbs_t *p, uint32_t index, uint32_t istk) 837 { 838 p->m_tx_uw_shadow[index].istk = istk; 839 } 840 841 static void set_shadow_tx_uw_data_in_order(nthw_dbs_t *p, uint32_t index, uint32_t in_order) 842 { 843 p->m_tx_uw_shadow[index].in_order = in_order; 844 } 845 846 static void set_shadow_tx_uw_data(nthw_dbs_t *p, 847 uint32_t index, 848 uint64_t guest_physical_address, 849 uint32_t host_id, 850 uint32_t queue_size, 851 uint32_t packed, 852 uint32_t int_enable, 853 uint32_t vec, 854 uint32_t istk, 855 uint32_t in_order) 856 { 857 set_shadow_tx_uw_data_guest_physical_address(p, index, guest_physical_address); 858 set_shadow_tx_uw_data_host_id(p, index, host_id); 859 set_shadow_tx_uw_data_queue_size(p, index, queue_size); 860 set_shadow_tx_uw_data_packed(p, index, packed); 861 set_shadow_tx_uw_data_int_enable(p, index, int_enable); 862 set_shadow_tx_uw_data_vec(p, index, vec); 863 set_shadow_tx_uw_data_istk(p, index, istk); 864 set_shadow_tx_uw_data_in_order(p, index, in_order); 865 } 866 867 static void flush_tx_uw_data(nthw_dbs_t *p, uint32_t index) 868 { 869 nthw_field_set_val(p->mp_fld_tx_used_writer_data_guest_physical_address, 870 (uint32_t *)&p->m_tx_uw_shadow[index].guest_physical_address, 2); 871 nthw_field_set_val32(p->mp_fld_tx_used_writer_data_host_id, 872 p->m_tx_uw_shadow[index].host_id); 873 874 if (nthw_module_is_version_newer(p->mp_mod_dbs, 0, 8)) { 875 nthw_field_set_val32(p->mp_fld_tx_used_writer_data_queue_size, 876 (1U << p->m_tx_uw_shadow[index].queue_size) - 1U); 877 878 } else { 879 nthw_field_set_val32(p->mp_fld_tx_used_writer_data_queue_size, 880 p->m_tx_uw_shadow[index].queue_size); 881 } 882 883 if (p->mp_fld_tx_used_writer_data_packed) { 884 nthw_field_set_val32(p->mp_fld_tx_used_writer_data_packed, 885 p->m_tx_uw_shadow[index].packed); 886 } 887 888 if (p->mp_fld_tx_used_writer_data_int) { 889 nthw_field_set_val32(p->mp_fld_tx_used_writer_data_int, 890 p->m_tx_uw_shadow[index].int_enable); 891 nthw_field_set_val32(p->mp_fld_tx_used_writer_data_vec, 892 p->m_tx_uw_shadow[index].vec); 893 nthw_field_set_val32(p->mp_fld_tx_used_writer_data_istk, 894 p->m_tx_uw_shadow[index].istk); 895 } 896 897 if (p->mp_fld_tx_used_writer_data_in_order) { 898 nthw_field_set_val32(p->mp_fld_tx_used_writer_data_in_order, 899 p->m_tx_uw_shadow[index].in_order); 900 } 901 902 set_tx_uw_data_index(p, index); 903 nthw_register_flush(p->mp_reg_tx_used_writer_data, 1); 904 } 905 906 int set_tx_uw_data(nthw_dbs_t *p, 907 uint32_t index, 908 uint64_t guest_physical_address, 909 uint32_t host_id, 910 uint32_t queue_size, 911 uint32_t packed, 912 uint32_t int_enable, 913 uint32_t vec, 914 uint32_t istk, 915 uint32_t in_order) 916 { 917 if (!p->mp_reg_tx_used_writer_data) 918 return -ENOTSUP; 919 920 set_shadow_tx_uw_data(p, index, guest_physical_address, host_id, queue_size, packed, 921 int_enable, vec, istk, in_order); 922 flush_tx_uw_data(p, index); 923 return 0; 924 } 925 926 static void set_rx_dr_data_index(nthw_dbs_t *p, uint32_t index) 927 { 928 nthw_field_set_val32(p->mp_fld_rx_descriptor_reader_control_adr, index); 929 nthw_field_set_val32(p->mp_fld_rx_descriptor_reader_control_cnt, 1); 930 nthw_register_flush(p->mp_reg_rx_descriptor_reader_control, 1); 931 } 932 933 static void set_shadow_rx_dr_data_guest_physical_address(nthw_dbs_t *p, uint32_t index, 934 uint64_t guest_physical_address) 935 { 936 p->m_rx_dr_shadow[index].guest_physical_address = guest_physical_address; 937 } 938 939 static void set_shadow_rx_dr_data_host_id(nthw_dbs_t *p, uint32_t index, uint32_t host_id) 940 { 941 p->m_rx_dr_shadow[index].host_id = host_id; 942 } 943 944 static void set_shadow_rx_dr_data_queue_size(nthw_dbs_t *p, uint32_t index, uint32_t queue_size) 945 { 946 p->m_rx_dr_shadow[index].queue_size = queue_size; 947 } 948 949 static void set_shadow_rx_dr_data_header(nthw_dbs_t *p, uint32_t index, uint32_t header) 950 { 951 p->m_rx_dr_shadow[index].header = header; 952 } 953 954 static void set_shadow_rx_dr_data_packed(nthw_dbs_t *p, uint32_t index, uint32_t packed) 955 { 956 p->m_rx_dr_shadow[index].packed = packed; 957 } 958 959 static void set_shadow_rx_dr_data(nthw_dbs_t *p, 960 uint32_t index, 961 uint64_t guest_physical_address, 962 uint32_t host_id, 963 uint32_t queue_size, 964 uint32_t header, 965 uint32_t packed) 966 { 967 set_shadow_rx_dr_data_guest_physical_address(p, index, guest_physical_address); 968 set_shadow_rx_dr_data_host_id(p, index, host_id); 969 set_shadow_rx_dr_data_queue_size(p, index, queue_size); 970 set_shadow_rx_dr_data_header(p, index, header); 971 set_shadow_rx_dr_data_packed(p, index, packed); 972 } 973 974 static void flush_rx_dr_data(nthw_dbs_t *p, uint32_t index) 975 { 976 nthw_field_set_val(p->mp_fld_rx_descriptor_reader_data_guest_physical_address, 977 (uint32_t *)&p->m_rx_dr_shadow[index].guest_physical_address, 2); 978 nthw_field_set_val32(p->mp_fld_rx_descriptor_reader_data_host_id, 979 p->m_rx_dr_shadow[index].host_id); 980 981 if (nthw_module_is_version_newer(p->mp_mod_dbs, 0, 8)) { 982 nthw_field_set_val32(p->mp_fld_rx_descriptor_reader_data_queue_size, 983 (1U << p->m_rx_dr_shadow[index].queue_size) - 1U); 984 985 } else { 986 nthw_field_set_val32(p->mp_fld_rx_descriptor_reader_data_queue_size, 987 p->m_rx_dr_shadow[index].queue_size); 988 } 989 990 nthw_field_set_val32(p->mp_fld_rx_descriptor_reader_data_header, 991 p->m_rx_dr_shadow[index].header); 992 993 if (p->mp_fld_rx_descriptor_reader_data_packed) { 994 nthw_field_set_val32(p->mp_fld_rx_descriptor_reader_data_packed, 995 p->m_rx_dr_shadow[index].packed); 996 } 997 998 set_rx_dr_data_index(p, index); 999 nthw_register_flush(p->mp_reg_rx_descriptor_reader_data, 1); 1000 } 1001 1002 int set_rx_dr_data(nthw_dbs_t *p, 1003 uint32_t index, 1004 uint64_t guest_physical_address, 1005 uint32_t host_id, 1006 uint32_t queue_size, 1007 uint32_t header, 1008 uint32_t packed) 1009 { 1010 if (!p->mp_reg_rx_descriptor_reader_data) 1011 return -ENOTSUP; 1012 1013 set_shadow_rx_dr_data(p, index, guest_physical_address, host_id, queue_size, header, 1014 packed); 1015 flush_rx_dr_data(p, index); 1016 return 0; 1017 } 1018 1019 static void set_tx_dr_data_index(nthw_dbs_t *p, uint32_t index) 1020 { 1021 nthw_field_set_val32(p->mp_fld_tx_descriptor_reader_control_adr, index); 1022 nthw_field_set_val32(p->mp_fld_tx_descriptor_reader_control_cnt, 1); 1023 nthw_register_flush(p->mp_reg_tx_descriptor_reader_control, 1); 1024 } 1025 1026 static void set_shadow_tx_dr_data_guest_physical_address(nthw_dbs_t *p, uint32_t index, 1027 uint64_t guest_physical_address) 1028 { 1029 p->m_tx_dr_shadow[index].guest_physical_address = guest_physical_address; 1030 } 1031 1032 static void set_shadow_tx_dr_data_host_id(nthw_dbs_t *p, uint32_t index, uint32_t host_id) 1033 { 1034 p->m_tx_dr_shadow[index].host_id = host_id; 1035 } 1036 1037 static void set_shadow_tx_dr_data_queue_size(nthw_dbs_t *p, uint32_t index, uint32_t queue_size) 1038 { 1039 p->m_tx_dr_shadow[index].queue_size = queue_size; 1040 } 1041 1042 static void set_shadow_tx_dr_data_header(nthw_dbs_t *p, uint32_t index, uint32_t header) 1043 { 1044 p->m_tx_dr_shadow[index].header = header; 1045 } 1046 1047 static void set_shadow_tx_dr_data_port(nthw_dbs_t *p, uint32_t index, uint32_t port) 1048 { 1049 p->m_tx_dr_shadow[index].port = port; 1050 } 1051 1052 static void set_shadow_tx_dr_data_packed(nthw_dbs_t *p, uint32_t index, uint32_t packed) 1053 { 1054 p->m_tx_dr_shadow[index].packed = packed; 1055 } 1056 1057 static void set_shadow_tx_dr_data(nthw_dbs_t *p, 1058 uint32_t index, 1059 uint64_t guest_physical_address, 1060 uint32_t host_id, 1061 uint32_t queue_size, 1062 uint32_t port, 1063 uint32_t header, 1064 uint32_t packed) 1065 { 1066 set_shadow_tx_dr_data_guest_physical_address(p, index, guest_physical_address); 1067 set_shadow_tx_dr_data_host_id(p, index, host_id); 1068 set_shadow_tx_dr_data_queue_size(p, index, queue_size); 1069 set_shadow_tx_dr_data_header(p, index, header); 1070 set_shadow_tx_dr_data_port(p, index, port); 1071 set_shadow_tx_dr_data_packed(p, index, packed); 1072 } 1073 1074 static void flush_tx_dr_data(nthw_dbs_t *p, uint32_t index) 1075 { 1076 nthw_field_set_val(p->mp_fld_tx_descriptor_reader_data_guest_physical_address, 1077 (uint32_t *)&p->m_tx_dr_shadow[index].guest_physical_address, 2); 1078 nthw_field_set_val32(p->mp_fld_tx_descriptor_reader_data_host_id, 1079 p->m_tx_dr_shadow[index].host_id); 1080 1081 if (nthw_module_is_version_newer(p->mp_mod_dbs, 0, 8)) { 1082 nthw_field_set_val32(p->mp_fld_tx_descriptor_reader_data_queue_size, 1083 (1U << p->m_tx_dr_shadow[index].queue_size) - 1U); 1084 1085 } else { 1086 nthw_field_set_val32(p->mp_fld_tx_descriptor_reader_data_queue_size, 1087 p->m_tx_dr_shadow[index].queue_size); 1088 } 1089 1090 nthw_field_set_val32(p->mp_fld_tx_descriptor_reader_data_header, 1091 p->m_tx_dr_shadow[index].header); 1092 nthw_field_set_val32(p->mp_fld_tx_descriptor_reader_data_port, 1093 p->m_tx_dr_shadow[index].port); 1094 1095 if (p->mp_fld_tx_descriptor_reader_data_packed) { 1096 nthw_field_set_val32(p->mp_fld_tx_descriptor_reader_data_packed, 1097 p->m_tx_dr_shadow[index].packed); 1098 } 1099 1100 set_tx_dr_data_index(p, index); 1101 nthw_register_flush(p->mp_reg_tx_descriptor_reader_data, 1); 1102 } 1103 1104 int set_tx_dr_data(nthw_dbs_t *p, 1105 uint32_t index, 1106 uint64_t guest_physical_address, 1107 uint32_t host_id, 1108 uint32_t queue_size, 1109 uint32_t port, 1110 uint32_t header, 1111 uint32_t packed) 1112 { 1113 if (!p->mp_reg_tx_descriptor_reader_data) 1114 return -ENOTSUP; 1115 1116 set_shadow_tx_dr_data(p, index, guest_physical_address, host_id, queue_size, port, header, 1117 packed); 1118 flush_tx_dr_data(p, index); 1119 return 0; 1120 } 1121 1122 static void set_tx_qp_data_index(nthw_dbs_t *p, uint32_t index) 1123 { 1124 nthw_field_set_val32(p->mp_fld_tx_queue_property_control_adr, index); 1125 nthw_field_set_val32(p->mp_fld_tx_queue_property_control_cnt, 1); 1126 nthw_register_flush(p->mp_reg_tx_queue_property_control, 1); 1127 } 1128 1129 static void set_shadow_tx_qp_data_virtual_port(nthw_dbs_t *p, uint32_t index, 1130 uint32_t virtual_port) 1131 { 1132 p->m_tx_qp_shadow[index].virtual_port = virtual_port; 1133 } 1134 1135 static void set_shadow_tx_qp_data(nthw_dbs_t *p, uint32_t index, uint32_t virtual_port) 1136 { 1137 set_shadow_tx_qp_data_virtual_port(p, index, virtual_port); 1138 } 1139 1140 static void flush_tx_qp_data(nthw_dbs_t *p, uint32_t index) 1141 { 1142 nthw_field_set_val32(p->mp_fld_tx_queue_property_data_v_port, 1143 p->m_tx_qp_shadow[index].virtual_port); 1144 1145 set_tx_qp_data_index(p, index); 1146 nthw_register_flush(p->mp_reg_tx_queue_property_data, 1); 1147 } 1148 1149 int nthw_dbs_set_tx_qp_data(nthw_dbs_t *p, uint32_t index, uint32_t virtual_port) 1150 { 1151 if (!p->mp_reg_tx_queue_property_data) 1152 return -ENOTSUP; 1153 1154 set_shadow_tx_qp_data(p, index, virtual_port); 1155 flush_tx_qp_data(p, index); 1156 return 0; 1157 } 1158