11d3f62a0SOleksandr Kolomeiets /* 21d3f62a0SOleksandr Kolomeiets * SPDX-License-Identifier: BSD-3-Clause 31d3f62a0SOleksandr Kolomeiets * Copyright(c) 2023 Napatech A/S 41d3f62a0SOleksandr Kolomeiets */ 51d3f62a0SOleksandr Kolomeiets 61d3f62a0SOleksandr Kolomeiets #ifndef _STREAM_BINARY_FLOW_API_H_ 71d3f62a0SOleksandr Kolomeiets #define _STREAM_BINARY_FLOW_API_H_ 81d3f62a0SOleksandr Kolomeiets 9ed01e436SSerhii Iliushyk #include "rte_flow.h" 10ed01e436SSerhii Iliushyk #include "rte_flow_driver.h" 11*e02fdb65SSerhii Iliushyk 12*e02fdb65SSerhii Iliushyk /* Max RSS hash key length in bytes */ 13*e02fdb65SSerhii Iliushyk #define MAX_RSS_KEY_LEN 40 14*e02fdb65SSerhii Iliushyk 151d3f62a0SOleksandr Kolomeiets /* 161d3f62a0SOleksandr Kolomeiets * Flow frontend for binary programming interface 171d3f62a0SOleksandr Kolomeiets */ 181d3f62a0SOleksandr Kolomeiets 191d3f62a0SOleksandr Kolomeiets #define FLOW_MAX_QUEUES 128 201d3f62a0SOleksandr Kolomeiets 21b01eb812SDanylo Vodopianov /* 22b01eb812SDanylo Vodopianov * Flow eth dev profile determines how the FPGA module resources are 23b01eb812SDanylo Vodopianov * managed and what features are available 24b01eb812SDanylo Vodopianov */ 25b01eb812SDanylo Vodopianov enum flow_eth_dev_profile { 26b01eb812SDanylo Vodopianov FLOW_ETH_DEV_PROFILE_INLINE = 0, 27b01eb812SDanylo Vodopianov }; 28b01eb812SDanylo Vodopianov 291d3f62a0SOleksandr Kolomeiets struct flow_queue_id_s { 301d3f62a0SOleksandr Kolomeiets int id; 311d3f62a0SOleksandr Kolomeiets int hw_id; 321d3f62a0SOleksandr Kolomeiets }; 331d3f62a0SOleksandr Kolomeiets 341d3f62a0SOleksandr Kolomeiets struct flow_eth_dev; /* port device */ 35b01eb812SDanylo Vodopianov struct flow_handle; 361d3f62a0SOleksandr Kolomeiets 371d3f62a0SOleksandr Kolomeiets #endif /* _STREAM_BINARY_FLOW_API_H_ */ 38