1 /* 2 * SPDX-License-Identifier: BSD-3-Clause 3 * Copyright(c) 2023 Napatech A/S 4 */ 5 6 #ifndef _NTNIC_DBS_H_ 7 #define _NTNIC_DBS_H_ 8 9 #include "nthw_fpga_model.h" 10 11 #define NT_DBS_RX_QUEUES_MAX (128) 12 #define NT_DBS_TX_QUEUES_MAX (128) 13 14 /* 15 * Struct for implementation of memory bank shadows 16 */ 17 18 /* DBS_RX_AM_DATA */ 19 struct nthw_dbs_rx_am_data_s { 20 uint64_t guest_physical_address; 21 uint32_t enable; 22 uint32_t host_id; 23 uint32_t packed; 24 uint32_t int_enable; 25 }; 26 27 /* DBS_TX_AM_DATA */ 28 struct nthw_dbs_tx_am_data_s { 29 uint64_t guest_physical_address; 30 uint32_t enable; 31 uint32_t host_id; 32 uint32_t packed; 33 uint32_t int_enable; 34 }; 35 36 /* DBS_RX_UW_DATA */ 37 struct nthw_dbs_rx_uw_data_s { 38 uint64_t guest_physical_address; 39 uint32_t host_id; 40 uint32_t queue_size; 41 uint32_t packed; 42 uint32_t int_enable; 43 uint32_t vec; 44 uint32_t istk; 45 }; 46 47 /* DBS_TX_UW_DATA */ 48 struct nthw_dbs_tx_uw_data_s { 49 uint64_t guest_physical_address; 50 uint32_t host_id; 51 uint32_t queue_size; 52 uint32_t packed; 53 uint32_t int_enable; 54 uint32_t vec; 55 uint32_t istk; 56 uint32_t in_order; 57 }; 58 59 /* DBS_RX_DR_DATA */ 60 struct nthw_dbs_rx_dr_data_s { 61 uint64_t guest_physical_address; 62 uint32_t host_id; 63 uint32_t queue_size; 64 uint32_t header; 65 uint32_t packed; 66 }; 67 68 /* DBS_TX_DR_DATA */ 69 struct nthw_dbs_tx_dr_data_s { 70 uint64_t guest_physical_address; 71 uint32_t host_id; 72 uint32_t queue_size; 73 uint32_t header; 74 uint32_t port; 75 uint32_t packed; 76 }; 77 78 /* DBS_TX_QP_DATA */ 79 struct nthw_dbs_tx_qp_data_s { 80 uint32_t virtual_port; 81 }; 82 83 struct nthw_dbs_s { 84 nthw_fpga_t *mp_fpga; 85 nthw_module_t *mp_mod_dbs; 86 int mn_instance; 87 88 int mn_param_dbs_present; 89 90 nthw_register_t *mp_reg_rx_control; 91 nthw_field_t *mp_fld_rx_control_last_queue; 92 nthw_field_t *mp_fld_rx_control_avail_monitor_enable; 93 nthw_field_t *mp_fld_rx_control_avail_monitor_scan_speed; 94 nthw_field_t *mp_fld_rx_control_used_write_enable; 95 nthw_field_t *mp_fld_rx_control_used_writer_update_speed; 96 nthw_field_t *mp_fld_rx_control_rx_queues_enable; 97 98 nthw_register_t *mp_reg_tx_control; 99 nthw_field_t *mp_fld_tx_control_last_queue; 100 nthw_field_t *mp_fld_tx_control_avail_monitor_enable; 101 nthw_field_t *mp_fld_tx_control_avail_monitor_scan_speed; 102 nthw_field_t *mp_fld_tx_control_used_write_enable; 103 nthw_field_t *mp_fld_tx_control_used_writer_update_speed; 104 nthw_field_t *mp_fld_tx_control_tx_queues_enable; 105 106 nthw_register_t *mp_reg_rx_init; 107 nthw_field_t *mp_fld_rx_init_init; 108 nthw_field_t *mp_fld_rx_init_queue; 109 nthw_field_t *mp_fld_rx_init_busy; 110 111 nthw_register_t *mp_reg_rx_init_val; 112 nthw_field_t *mp_fld_rx_init_val_idx; 113 nthw_field_t *mp_fld_rx_init_val_ptr; 114 115 nthw_register_t *mp_reg_rx_ptr; 116 nthw_field_t *mp_fld_rx_ptr_ptr; 117 nthw_field_t *mp_fld_rx_ptr_queue; 118 nthw_field_t *mp_fld_rx_ptr_valid; 119 120 nthw_register_t *mp_reg_tx_init; 121 nthw_field_t *mp_fld_tx_init_init; 122 nthw_field_t *mp_fld_tx_init_queue; 123 nthw_field_t *mp_fld_tx_init_busy; 124 125 nthw_register_t *mp_reg_tx_init_val; 126 nthw_field_t *mp_fld_tx_init_val_idx; 127 nthw_field_t *mp_fld_tx_init_val_ptr; 128 129 nthw_register_t *mp_reg_tx_ptr; 130 nthw_field_t *mp_fld_tx_ptr_ptr; 131 nthw_field_t *mp_fld_tx_ptr_queue; 132 nthw_field_t *mp_fld_tx_ptr_valid; 133 134 nthw_register_t *mp_reg_rx_idle; 135 nthw_field_t *mp_fld_rx_idle_idle; 136 nthw_field_t *mp_fld_rx_idle_queue; 137 nthw_field_t *mp_fld_rx_idle_busy; 138 139 nthw_register_t *mp_reg_tx_idle; 140 nthw_field_t *mp_fld_tx_idle_idle; 141 nthw_field_t *mp_fld_tx_idle_queue; 142 nthw_field_t *mp_fld_tx_idle_busy; 143 144 nthw_register_t *mp_reg_rx_avail_monitor_control; 145 nthw_field_t *mp_fld_rx_avail_monitor_control_adr; 146 nthw_field_t *mp_fld_rx_avail_monitor_control_cnt; 147 148 nthw_register_t *mp_reg_rx_avail_monitor_data; 149 nthw_field_t *mp_fld_rx_avail_monitor_data_guest_physical_address; 150 nthw_field_t *mp_fld_rx_avail_monitor_data_enable; 151 nthw_field_t *mp_fld_rx_avail_monitor_data_host_id; 152 nthw_field_t *mp_fld_rx_avail_monitor_data_packed; 153 nthw_field_t *mp_fld_rx_avail_monitor_data_int; 154 155 nthw_register_t *mp_reg_tx_avail_monitor_control; 156 nthw_field_t *mp_fld_tx_avail_monitor_control_adr; 157 nthw_field_t *mp_fld_tx_avail_monitor_control_cnt; 158 159 nthw_register_t *mp_reg_tx_avail_monitor_data; 160 nthw_field_t *mp_fld_tx_avail_monitor_data_guest_physical_address; 161 nthw_field_t *mp_fld_tx_avail_monitor_data_enable; 162 nthw_field_t *mp_fld_tx_avail_monitor_data_host_id; 163 nthw_field_t *mp_fld_tx_avail_monitor_data_packed; 164 nthw_field_t *mp_fld_tx_avail_monitor_data_int; 165 166 nthw_register_t *mp_reg_rx_used_writer_control; 167 nthw_field_t *mp_fld_rx_used_writer_control_adr; 168 nthw_field_t *mp_fld_rx_used_writer_control_cnt; 169 170 nthw_register_t *mp_reg_rx_used_writer_data; 171 nthw_field_t *mp_fld_rx_used_writer_data_guest_physical_address; 172 nthw_field_t *mp_fld_rx_used_writer_data_host_id; 173 nthw_field_t *mp_fld_rx_used_writer_data_queue_size; 174 nthw_field_t *mp_fld_rx_used_writer_data_packed; 175 nthw_field_t *mp_fld_rx_used_writer_data_int; 176 nthw_field_t *mp_fld_rx_used_writer_data_vec; 177 nthw_field_t *mp_fld_rx_used_writer_data_istk; 178 179 nthw_register_t *mp_reg_tx_used_writer_control; 180 nthw_field_t *mp_fld_tx_used_writer_control_adr; 181 nthw_field_t *mp_fld_tx_used_writer_control_cnt; 182 183 nthw_register_t *mp_reg_tx_used_writer_data; 184 nthw_field_t *mp_fld_tx_used_writer_data_guest_physical_address; 185 nthw_field_t *mp_fld_tx_used_writer_data_host_id; 186 nthw_field_t *mp_fld_tx_used_writer_data_queue_size; 187 nthw_field_t *mp_fld_tx_used_writer_data_packed; 188 nthw_field_t *mp_fld_tx_used_writer_data_int; 189 nthw_field_t *mp_fld_tx_used_writer_data_vec; 190 nthw_field_t *mp_fld_tx_used_writer_data_istk; 191 nthw_field_t *mp_fld_tx_used_writer_data_in_order; 192 193 nthw_register_t *mp_reg_rx_descriptor_reader_control; 194 nthw_field_t *mp_fld_rx_descriptor_reader_control_adr; 195 nthw_field_t *mp_fld_rx_descriptor_reader_control_cnt; 196 197 nthw_register_t *mp_reg_rx_descriptor_reader_data; 198 nthw_field_t *mp_fld_rx_descriptor_reader_data_guest_physical_address; 199 nthw_field_t *mp_fld_rx_descriptor_reader_data_host_id; 200 nthw_field_t *mp_fld_rx_descriptor_reader_data_queue_size; 201 nthw_field_t *mp_fld_rx_descriptor_reader_data_header; 202 nthw_field_t *mp_fld_rx_descriptor_reader_data_packed; 203 204 nthw_register_t *mp_reg_tx_descriptor_reader_control; 205 nthw_field_t *mp_fld_tx_descriptor_reader_control_adr; 206 nthw_field_t *mp_fld_tx_descriptor_reader_control_cnt; 207 208 nthw_register_t *mp_reg_tx_descriptor_reader_data; 209 nthw_field_t *mp_fld_tx_descriptor_reader_data_guest_physical_address; 210 nthw_field_t *mp_fld_tx_descriptor_reader_data_host_id; 211 nthw_field_t *mp_fld_tx_descriptor_reader_data_queue_size; 212 nthw_field_t *mp_fld_tx_descriptor_reader_data_port; 213 nthw_field_t *mp_fld_tx_descriptor_reader_data_header; 214 nthw_field_t *mp_fld_tx_descriptor_reader_data_packed; 215 216 nthw_register_t *mp_reg_tx_queue_property_control; 217 nthw_field_t *mp_fld_tx_queue_property_control_adr; 218 nthw_field_t *mp_fld_tx_queue_property_control_cnt; 219 220 nthw_register_t *mp_reg_tx_queue_property_data; 221 nthw_field_t *mp_fld_tx_queue_property_data_v_port; 222 223 struct nthw_dbs_rx_am_data_s m_rx_am_shadow[NT_DBS_RX_QUEUES_MAX]; 224 struct nthw_dbs_rx_uw_data_s m_rx_uw_shadow[NT_DBS_RX_QUEUES_MAX]; 225 struct nthw_dbs_rx_dr_data_s m_rx_dr_shadow[NT_DBS_RX_QUEUES_MAX]; 226 227 struct nthw_dbs_tx_am_data_s m_tx_am_shadow[NT_DBS_TX_QUEUES_MAX]; 228 struct nthw_dbs_tx_uw_data_s m_tx_uw_shadow[NT_DBS_TX_QUEUES_MAX]; 229 struct nthw_dbs_tx_dr_data_s m_tx_dr_shadow[NT_DBS_TX_QUEUES_MAX]; 230 struct nthw_dbs_tx_qp_data_s m_tx_qp_shadow[NT_DBS_TX_QUEUES_MAX]; 231 }; 232 233 typedef struct nthw_dbs_s nthw_dbs_t; 234 235 nthw_dbs_t *nthw_dbs_new(void); 236 int dbs_init(nthw_dbs_t *p, nthw_fpga_t *p_fpga, int n_instance); 237 void dbs_reset(nthw_dbs_t *p); 238 239 int set_rx_control(nthw_dbs_t *p, 240 uint32_t last_queue, 241 uint32_t avail_monitor_enable, 242 uint32_t avail_monitor_speed, 243 uint32_t used_write_enable, 244 uint32_t used_write_speed, 245 uint32_t rx_queue_enable); 246 int set_tx_control(nthw_dbs_t *p, 247 uint32_t last_queue, 248 uint32_t avail_monitor_enable, 249 uint32_t avail_monitor_speed, 250 uint32_t used_write_enable, 251 uint32_t used_write_speed, 252 uint32_t tx_queue_enable); 253 int set_rx_init(nthw_dbs_t *p, uint32_t start_idx, uint32_t start_ptr, uint32_t init, 254 uint32_t queue); 255 int get_rx_init(nthw_dbs_t *p, uint32_t *init, uint32_t *queue, uint32_t *busy); 256 int set_tx_init(nthw_dbs_t *p, uint32_t start_idx, uint32_t start_ptr, uint32_t init, 257 uint32_t queue); 258 int get_tx_init(nthw_dbs_t *p, uint32_t *init, uint32_t *queue, uint32_t *busy); 259 int set_rx_idle(nthw_dbs_t *p, uint32_t idle, uint32_t queue); 260 int get_rx_idle(nthw_dbs_t *p, uint32_t *idle, uint32_t *queue, uint32_t *busy); 261 int set_tx_idle(nthw_dbs_t *p, uint32_t idle, uint32_t queue); 262 int get_tx_idle(nthw_dbs_t *p, uint32_t *idle, uint32_t *queue, uint32_t *busy); 263 int set_rx_am_data(nthw_dbs_t *p, 264 uint32_t index, 265 uint64_t guest_physical_address, 266 uint32_t enable, 267 uint32_t host_id, 268 uint32_t packed, 269 uint32_t int_enable); 270 int set_tx_am_data(nthw_dbs_t *p, 271 uint32_t index, 272 uint64_t guest_physical_address, 273 uint32_t enable, 274 uint32_t host_id, 275 uint32_t packed, 276 uint32_t int_enable); 277 int set_rx_uw_data(nthw_dbs_t *p, 278 uint32_t index, 279 uint64_t guest_physical_address, 280 uint32_t host_id, 281 uint32_t queue_size, 282 uint32_t packed, 283 uint32_t int_enable, 284 uint32_t vec, 285 uint32_t istk); 286 int set_tx_uw_data(nthw_dbs_t *p, 287 uint32_t index, 288 uint64_t guest_physical_address, 289 uint32_t host_id, 290 uint32_t queue_size, 291 uint32_t packed, 292 uint32_t int_enable, 293 uint32_t vec, 294 uint32_t istk, 295 uint32_t in_order); 296 int set_rx_dr_data(nthw_dbs_t *p, 297 uint32_t index, 298 uint64_t guest_physical_address, 299 uint32_t host_id, 300 uint32_t queue_size, 301 uint32_t header, 302 uint32_t packed); 303 int set_tx_dr_data(nthw_dbs_t *p, 304 uint32_t index, 305 uint64_t guest_physical_address, 306 uint32_t host_id, 307 uint32_t queue_size, 308 uint32_t port, 309 uint32_t header, 310 uint32_t packed); 311 int nthw_dbs_set_tx_qp_data(nthw_dbs_t *p, uint32_t index, uint32_t virtual_port); 312 313 #endif /* _NTNIC_DBS_H_ */ 314