1 /* 2 * SPDX-License-Identifier: BSD-3-Clause 3 * Copyright(c) 2023 Napatech A/S 4 */ 5 6 #ifndef _HW_MOD_KM_V7_H_ 7 #define _HW_MOD_KM_V7_H_ 8 9 #include <stdint.h> 10 11 struct km_v7_rcp_s { 12 uint32_t qw0_dyn; 13 int32_t qw0_ofs; 14 uint32_t qw0_sel_a; 15 uint32_t qw0_sel_b; 16 uint32_t qw4_dyn; 17 int32_t qw4_ofs; 18 uint32_t qw4_sel_a; 19 uint32_t qw4_sel_b; 20 uint32_t dw8_dyn; 21 int32_t dw8_ofs; 22 uint32_t dw8_sel_a; 23 uint32_t dw8_sel_b; 24 uint32_t dw10_dyn; 25 int32_t dw10_ofs; 26 uint32_t dw10_sel_a; 27 uint32_t dw10_sel_b; 28 uint32_t swx_cch; 29 uint32_t swx_sel_a; 30 uint32_t swx_sel_b; 31 uint32_t mask_d_a[12]; 32 uint32_t mask_b[6]; 33 uint32_t dual; 34 uint32_t paired; 35 uint32_t el_a; 36 uint32_t el_b; 37 uint32_t info_a; 38 uint32_t info_b; 39 uint32_t ftm_a; 40 uint32_t ftm_b; 41 uint32_t bank_a; 42 uint32_t bank_b; 43 uint32_t kl_a; 44 uint32_t kl_b; 45 uint32_t keyway_a; 46 uint32_t keyway_b; 47 uint32_t synergy_mode; 48 uint32_t dw0_b_dyn; 49 int32_t dw0_b_ofs; 50 uint32_t dw2_b_dyn; 51 int32_t dw2_b_ofs; 52 uint32_t sw4_b_dyn; 53 int32_t sw4_b_ofs; 54 uint32_t sw5_b_dyn; 55 int32_t sw5_b_ofs; 56 }; 57 58 struct km_v7_cam_s { 59 uint32_t w0; 60 uint32_t w1; 61 uint32_t w2; 62 uint32_t w3; 63 uint32_t w4; 64 uint32_t w5; 65 uint32_t ft0; 66 uint32_t ft1; 67 uint32_t ft2; 68 uint32_t ft3; 69 uint32_t ft4; 70 uint32_t ft5; 71 }; 72 73 struct km_v7_tcam_s { 74 uint32_t t[3]; 75 uint32_t dirty; 76 }; 77 78 struct km_v7_tci_s { 79 uint32_t color; 80 uint32_t ft; 81 }; 82 83 struct km_v7_tcq_s { 84 uint32_t bank_mask; 85 uint32_t qual; 86 }; 87 88 struct hw_mod_km_v7_s { 89 struct km_v7_rcp_s *rcp; 90 struct km_v7_cam_s *cam; 91 struct km_v7_tcam_s *tcam; 92 struct km_v7_tci_s *tci; 93 struct km_v7_tcq_s *tcq; 94 }; 95 96 #endif /* _HW_MOD_KM_V7_H_ */ 97