1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2018-2021 Beijing WangXun Technology Co., Ltd. 3 * Copyright(c) 2010-2017 Intel Corporation 4 */ 5 6 #ifndef _NGBE_MNG_H_ 7 #define _NGBE_MNG_H_ 8 9 #include "ngbe_type.h" 10 11 #define NGBE_PMMBX_QSIZE 64 /* Num of dwords in range */ 12 #define NGBE_PMMBX_BSIZE (NGBE_PMMBX_QSIZE * 4) 13 #define NGBE_PMMBX_DATA_SIZE (NGBE_PMMBX_BSIZE - FW_NVM_DATA_OFFSET * 4) 14 #define NGBE_HI_COMMAND_TIMEOUT 5000 /* Process HI command limit */ 15 16 /* CEM Support */ 17 #define FW_CEM_MAX_RETRIES 3 18 #define FW_CEM_RESP_STATUS_SUCCESS 0x1 19 #define FW_READ_SHADOW_RAM_CMD 0x31 20 #define FW_READ_SHADOW_RAM_LEN 0x6 21 #define FW_WRITE_SHADOW_RAM_CMD 0x33 22 #define FW_WRITE_SHADOW_RAM_LEN 0xA /* 8 plus 1 WORD to write */ 23 #define FW_PCIE_READ_CMD 0xEC 24 #define FW_PCIE_WRITE_CMD 0xED 25 #define FW_PCIE_BUSMASTER_OFFSET 2 26 #define FW_DEFAULT_CHECKSUM 0xFF /* checksum always 0xFF */ 27 #define FW_NVM_DATA_OFFSET 3 28 #define FW_EEPROM_CHECK_STATUS 0xE9 29 #define FW_PHY_LED_CONF 0xF1 30 #define FW_READ_SHADOW_RAM_GPIO 0xB4 31 #define FW_LLDP_GET_CMD 0xF5 32 #define FW_LLDP_SET_CMD_OFF 0xF3 33 #define FW_LLDP_SET_CMD_ON 0xF2 34 #define FW_CEM_CMD_RESERVED 0X0 35 36 #define FW_CHECKSUM_CAP_ST_PASS 0x80658383 37 #define FW_CHECKSUM_CAP_ST_FAIL 0x70657376 38 39 /* Host Interface Command Structures */ 40 struct ngbe_hic_hdr { 41 u8 cmd; 42 u8 buf_len; 43 union { 44 u8 cmd_resv; 45 u8 ret_status; 46 } cmd_or_resp; 47 u8 checksum; 48 }; 49 50 struct ngbe_hic_hdr2_req { 51 u8 cmd; 52 u8 buf_lenh; 53 u8 buf_lenl; 54 u8 checksum; 55 }; 56 57 struct ngbe_hic_hdr2_rsp { 58 u8 cmd; 59 u8 buf_lenl; 60 u8 ret_status; /* 7-5: high bits of buf_len, 4-0: status */ 61 u8 checksum; 62 }; 63 64 union ngbe_hic_hdr2 { 65 struct ngbe_hic_hdr2_req req; 66 struct ngbe_hic_hdr2_rsp rsp; 67 }; 68 69 /* These need to be dword aligned */ 70 struct ngbe_hic_read_shadow_ram { 71 union ngbe_hic_hdr2 hdr; 72 u32 address; 73 u16 length; 74 u16 pad2; 75 u16 data; 76 u16 pad3; 77 }; 78 79 struct ngbe_hic_write_shadow_ram { 80 union ngbe_hic_hdr2 hdr; 81 u32 address; 82 u16 length; 83 u16 pad2; 84 u16 data; 85 u16 pad3; 86 }; 87 88 struct ngbe_hic_read_pcie { 89 struct ngbe_hic_hdr hdr; 90 u8 lan_id; 91 u8 rsvd; 92 u16 addr; 93 u32 data; 94 }; 95 96 struct ngbe_hic_write_pcie { 97 struct ngbe_hic_hdr hdr; 98 u8 lan_id; 99 u8 rsvd; 100 u16 addr; 101 u32 data; 102 }; 103 104 struct ngbe_hic_write_lldp { 105 struct ngbe_hic_hdr hdr; 106 u8 func; 107 u8 pad2; 108 u16 pad3; 109 }; 110 111 s32 ngbe_hic_sr_read(struct ngbe_hw *hw, u32 addr, u8 *buf, int len); 112 s32 ngbe_hic_sr_write(struct ngbe_hw *hw, u32 addr, u8 *buf, int len); 113 s32 ngbe_hic_pcie_read(struct ngbe_hw *hw, u16 addr, u32 *buf, int len); 114 s32 ngbe_hic_pcie_write(struct ngbe_hw *hw, u16 addr, u32 *buf, int len); 115 116 s32 ngbe_hic_check_cap(struct ngbe_hw *hw); 117 s32 ngbe_phy_led_oem_chk(struct ngbe_hw *hw, u32 *data); 118 s32 ngbe_hic_get_lldp(struct ngbe_hw *hw); 119 s32 ngbe_hic_set_lldp(struct ngbe_hw *hw, bool on); 120 121 #endif /* _NGBE_MNG_H_ */ 122