1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2018-2021 Beijing WangXun Technology Co., Ltd. 3 * Copyright(c) 2010-2017 Intel Corporation 4 */ 5 6 #include "ngbe_type.h" 7 #include "ngbe_mbx.h" 8 #include "ngbe_phy.h" 9 #include "ngbe_eeprom.h" 10 #include "ngbe_mng.h" 11 #include "ngbe_hw.h" 12 #include "ngbe_vf.h" 13 14 static s32 ngbe_is_lldp(struct ngbe_hw *hw) 15 { 16 u32 tmp = 0, lldp_flash_data = 0, i; 17 s32 err = 0; 18 19 if ((hw->eeprom_id & NGBE_FW_MASK) >= NGBE_FW_GET_LLDP) { 20 err = ngbe_hic_get_lldp(hw); 21 if (err == 0) 22 return 0; 23 } 24 25 for (i = 0; i < 1024; i++) { 26 err = ngbe_flash_read_dword(hw, NGBE_LLDP_REG + i * 4, &tmp); 27 if (err) 28 return err; 29 30 if (tmp == BIT_MASK32) 31 break; 32 lldp_flash_data = tmp; 33 } 34 35 if (lldp_flash_data & MS(hw->bus.lan_id, 1)) 36 hw->lldp_enabled = true; 37 else 38 hw->lldp_enabled = false; 39 40 return 0; 41 } 42 43 static void ngbe_disable_lldp(struct ngbe_hw *hw) 44 { 45 s32 err = 0; 46 47 if ((hw->eeprom_id & NGBE_FW_MASK) < NGBE_FW_SUPPORT_LLDP) 48 return; 49 50 err = ngbe_is_lldp(hw); 51 if (err) { 52 PMD_INIT_LOG(INFO, "Can not get LLDP status."); 53 } else if (hw->lldp_enabled) { 54 err = ngbe_hic_set_lldp(hw, false); 55 if (!err) 56 PMD_INIT_LOG(INFO, 57 "LLDP detected on port %d, turn it off by default.", 58 hw->port_id); 59 else 60 PMD_INIT_LOG(INFO, "Can not set LLDP status."); 61 } 62 } 63 64 /** 65 * ngbe_start_hw - Prepare hardware for Tx/Rx 66 * @hw: pointer to hardware structure 67 * 68 * Starts the hardware. 69 **/ 70 s32 ngbe_start_hw(struct ngbe_hw *hw) 71 { 72 s32 err; 73 74 /* Clear the VLAN filter table */ 75 hw->mac.clear_vfta(hw); 76 77 /* Clear statistics registers */ 78 hw->mac.clear_hw_cntrs(hw); 79 80 /* Setup flow control */ 81 err = hw->mac.setup_fc(hw); 82 if (err != 0 && err != NGBE_NOT_IMPLEMENTED) { 83 DEBUGOUT("Flow control setup failed, returning %d", err); 84 return err; 85 } 86 87 /* Clear adapter stopped flag */ 88 hw->adapter_stopped = false; 89 90 return 0; 91 } 92 93 /** 94 * ngbe_init_hw - Generic hardware initialization 95 * @hw: pointer to hardware structure 96 * 97 * Initialize the hardware by resetting the hardware, filling the bus info 98 * structure and media type, clears all on chip counters, initializes receive 99 * address registers, multicast table, VLAN filter table, calls routine to set 100 * up link and flow control settings, and leaves transmit and receive units 101 * disabled and uninitialized 102 **/ 103 s32 ngbe_init_hw(struct ngbe_hw *hw) 104 { 105 s32 status; 106 107 ngbe_read_efuse(hw); 108 ngbe_save_eeprom_version(hw); 109 ngbe_disable_lldp(hw); 110 111 /* Reset the hardware */ 112 status = hw->mac.reset_hw(hw); 113 if (status == 0) { 114 /* Start the HW */ 115 status = hw->mac.start_hw(hw); 116 } 117 118 if (status != 0) 119 DEBUGOUT("Failed to initialize HW, STATUS = %d", status); 120 121 return status; 122 } 123 124 static void 125 ngbe_reset_misc_em(struct ngbe_hw *hw) 126 { 127 int i; 128 129 wr32(hw, NGBE_ISBADDRL, hw->isb_dma & 0xFFFFFFFF); 130 wr32(hw, NGBE_ISBADDRH, hw->isb_dma >> 32); 131 132 /* receive packets that size > 2048 */ 133 wr32m(hw, NGBE_MACRXCFG, 134 NGBE_MACRXCFG_JUMBO, NGBE_MACRXCFG_JUMBO); 135 136 wr32m(hw, NGBE_FRMSZ, NGBE_FRMSZ_MAX_MASK, 137 NGBE_FRMSZ_MAX(NGBE_FRAME_SIZE_DFT)); 138 139 /* clear counters on read */ 140 wr32m(hw, NGBE_MACCNTCTL, 141 NGBE_MACCNTCTL_RC, NGBE_MACCNTCTL_RC); 142 143 wr32m(hw, NGBE_RXFCCFG, 144 NGBE_RXFCCFG_FC, NGBE_RXFCCFG_FC); 145 wr32m(hw, NGBE_TXFCCFG, 146 NGBE_TXFCCFG_FC, NGBE_TXFCCFG_FC); 147 148 wr32m(hw, NGBE_MACRXFLT, 149 NGBE_MACRXFLT_PROMISC, NGBE_MACRXFLT_PROMISC); 150 151 wr32m(hw, NGBE_RSTSTAT, 152 NGBE_RSTSTAT_TMRINIT_MASK, NGBE_RSTSTAT_TMRINIT(30)); 153 154 /* errata 4: initialize mng flex tbl and wakeup flex tbl*/ 155 wr32(hw, NGBE_MNGFLEXSEL, 0); 156 for (i = 0; i < 16; i++) { 157 wr32(hw, NGBE_MNGFLEXDWL(i), 0); 158 wr32(hw, NGBE_MNGFLEXDWH(i), 0); 159 wr32(hw, NGBE_MNGFLEXMSK(i), 0); 160 } 161 wr32(hw, NGBE_LANFLEXSEL, 0); 162 for (i = 0; i < 16; i++) { 163 wr32(hw, NGBE_LANFLEXDWL(i), 0); 164 wr32(hw, NGBE_LANFLEXDWH(i), 0); 165 wr32(hw, NGBE_LANFLEXMSK(i), 0); 166 } 167 168 /* set pause frame dst mac addr */ 169 wr32(hw, NGBE_RXPBPFCDMACL, 0xC2000001); 170 wr32(hw, NGBE_RXPBPFCDMACH, 0x0180); 171 172 wr32(hw, NGBE_MDIOMODE, 0xF); 173 174 wr32m(hw, NGBE_GPIE, NGBE_GPIE_MSIX, NGBE_GPIE_MSIX); 175 176 if (hw->gpio_ctl) { 177 /* gpio0 is used to power on/off control*/ 178 wr32(hw, NGBE_GPIODIR, NGBE_GPIODIR_DDR(1)); 179 wr32(hw, NGBE_GPIODATA, NGBE_GPIOBIT_0); 180 } 181 182 hw->mac.init_thermal_sensor_thresh(hw); 183 184 /* enable mac transmitter */ 185 wr32m(hw, NGBE_MACTXCFG, NGBE_MACTXCFG_TE, NGBE_MACTXCFG_TE); 186 187 /* sellect GMII */ 188 wr32m(hw, NGBE_MACTXCFG, 189 NGBE_MACTXCFG_SPEED_MASK, NGBE_MACTXCFG_SPEED_1G); 190 191 for (i = 0; i < 4; i++) 192 wr32m(hw, NGBE_IVAR(i), 0x80808080, 0); 193 } 194 195 /** 196 * ngbe_reset_hw_em - Perform hardware reset 197 * @hw: pointer to hardware structure 198 * 199 * Resets the hardware by resetting the transmit and receive units, masks 200 * and clears all interrupts, perform a PHY reset, and perform a link (MAC) 201 * reset. 202 **/ 203 s32 ngbe_reset_hw_em(struct ngbe_hw *hw) 204 { 205 s32 status; 206 207 /* Call adapter stop to disable tx/rx and clear interrupts */ 208 status = hw->mac.stop_hw(hw); 209 if (status != 0) 210 return status; 211 212 /* Identify PHY and related function pointers */ 213 status = ngbe_init_phy(hw); 214 if (status) 215 return status; 216 217 /* Reset PHY */ 218 if (!hw->phy.reset_disable) 219 hw->phy.reset_hw(hw); 220 221 wr32(hw, NGBE_RST, NGBE_RST_LAN(hw->bus.lan_id)); 222 ngbe_flush(hw); 223 msec_delay(50); 224 225 ngbe_reset_misc_em(hw); 226 hw->mac.clear_hw_cntrs(hw); 227 228 if (!(((hw->sub_device_id & NGBE_OEM_MASK) == NGBE_RGMII_FPGA) || 229 hw->ncsi_enabled || hw->wol_enabled)) 230 hw->phy.set_phy_power(hw, false); 231 232 msec_delay(50); 233 234 /* Store the permanent mac address */ 235 hw->mac.get_mac_addr(hw, hw->mac.perm_addr); 236 237 /* 238 * Store MAC address from RAR0, clear receive address registers, and 239 * clear the multicast table. 240 */ 241 hw->mac.num_rar_entries = NGBE_EM_RAR_ENTRIES; 242 hw->mac.init_rx_addrs(hw); 243 244 return status; 245 } 246 247 /** 248 * ngbe_clear_hw_cntrs - Generic clear hardware counters 249 * @hw: pointer to hardware structure 250 * 251 * Clears all hardware statistics counters by reading them from the hardware 252 * Statistics counters are clear on read. 253 **/ 254 s32 ngbe_clear_hw_cntrs(struct ngbe_hw *hw) 255 { 256 u16 i = 0; 257 258 /* QP Stats */ 259 /* don't write clear queue stats */ 260 for (i = 0; i < NGBE_MAX_QP; i++) { 261 hw->qp_last[i].rx_qp_packets = 0; 262 hw->qp_last[i].tx_qp_packets = 0; 263 hw->qp_last[i].rx_qp_bytes = 0; 264 hw->qp_last[i].tx_qp_bytes = 0; 265 hw->qp_last[i].rx_qp_mc_packets = 0; 266 hw->qp_last[i].tx_qp_mc_packets = 0; 267 hw->qp_last[i].rx_qp_bc_packets = 0; 268 hw->qp_last[i].tx_qp_bc_packets = 0; 269 } 270 271 /* PB Stats */ 272 rd32(hw, NGBE_PBRXLNKXON); 273 rd32(hw, NGBE_PBRXLNKXOFF); 274 rd32(hw, NGBE_PBTXLNKXON); 275 rd32(hw, NGBE_PBTXLNKXOFF); 276 277 /* DMA Stats */ 278 rd32(hw, NGBE_DMARXPKT); 279 rd32(hw, NGBE_DMATXPKT); 280 281 rd64(hw, NGBE_DMARXOCTL); 282 rd64(hw, NGBE_DMATXOCTL); 283 284 /* MAC Stats */ 285 rd64(hw, NGBE_MACRXERRCRCL); 286 rd64(hw, NGBE_MACRXMPKTL); 287 rd64(hw, NGBE_MACTXMPKTL); 288 289 rd64(hw, NGBE_MACRXPKTL); 290 rd64(hw, NGBE_MACTXPKTL); 291 rd64(hw, NGBE_MACRXGBOCTL); 292 293 rd64(hw, NGBE_MACRXOCTL); 294 rd32(hw, NGBE_MACTXOCTL); 295 296 rd64(hw, NGBE_MACRX1TO64L); 297 rd64(hw, NGBE_MACRX65TO127L); 298 rd64(hw, NGBE_MACRX128TO255L); 299 rd64(hw, NGBE_MACRX256TO511L); 300 rd64(hw, NGBE_MACRX512TO1023L); 301 rd64(hw, NGBE_MACRX1024TOMAXL); 302 rd64(hw, NGBE_MACTX1TO64L); 303 rd64(hw, NGBE_MACTX65TO127L); 304 rd64(hw, NGBE_MACTX128TO255L); 305 rd64(hw, NGBE_MACTX256TO511L); 306 rd64(hw, NGBE_MACTX512TO1023L); 307 rd64(hw, NGBE_MACTX1024TOMAXL); 308 309 rd64(hw, NGBE_MACRXERRLENL); 310 rd32(hw, NGBE_MACRXOVERSIZE); 311 rd32(hw, NGBE_MACRXJABBER); 312 313 /* MACsec Stats */ 314 rd32(hw, NGBE_LSECTX_UTPKT); 315 rd32(hw, NGBE_LSECTX_ENCPKT); 316 rd32(hw, NGBE_LSECTX_PROTPKT); 317 rd32(hw, NGBE_LSECTX_ENCOCT); 318 rd32(hw, NGBE_LSECTX_PROTOCT); 319 rd32(hw, NGBE_LSECRX_UTPKT); 320 rd32(hw, NGBE_LSECRX_BTPKT); 321 rd32(hw, NGBE_LSECRX_NOSCIPKT); 322 rd32(hw, NGBE_LSECRX_UNSCIPKT); 323 rd32(hw, NGBE_LSECRX_DECOCT); 324 rd32(hw, NGBE_LSECRX_VLDOCT); 325 rd32(hw, NGBE_LSECRX_UNCHKPKT); 326 rd32(hw, NGBE_LSECRX_DLYPKT); 327 rd32(hw, NGBE_LSECRX_LATEPKT); 328 for (i = 0; i < 2; i++) { 329 rd32(hw, NGBE_LSECRX_OKPKT(i)); 330 rd32(hw, NGBE_LSECRX_INVPKT(i)); 331 rd32(hw, NGBE_LSECRX_BADPKT(i)); 332 } 333 for (i = 0; i < 4; i++) { 334 rd32(hw, NGBE_LSECRX_INVSAPKT(i)); 335 rd32(hw, NGBE_LSECRX_BADSAPKT(i)); 336 } 337 338 return 0; 339 } 340 341 /** 342 * ngbe_get_mac_addr - Generic get MAC address 343 * @hw: pointer to hardware structure 344 * @mac_addr: Adapter MAC address 345 * 346 * Reads the adapter's MAC address from first Receive Address Register (RAR0) 347 * A reset of the adapter must be performed prior to calling this function 348 * in order for the MAC address to have been loaded from the EEPROM into RAR0 349 **/ 350 s32 ngbe_get_mac_addr(struct ngbe_hw *hw, u8 *mac_addr) 351 { 352 u32 rar_high; 353 u32 rar_low; 354 u16 i; 355 356 wr32(hw, NGBE_ETHADDRIDX, 0); 357 rar_high = rd32(hw, NGBE_ETHADDRH); 358 rar_low = rd32(hw, NGBE_ETHADDRL); 359 360 for (i = 0; i < 2; i++) 361 mac_addr[i] = (u8)(rar_high >> (1 - i) * 8); 362 363 for (i = 0; i < 4; i++) 364 mac_addr[i + 2] = (u8)(rar_low >> (3 - i) * 8); 365 366 return 0; 367 } 368 369 /** 370 * ngbe_set_lan_id_multi_port - Set LAN id for PCIe multiple port devices 371 * @hw: pointer to the HW structure 372 * 373 * Determines the LAN function id by reading memory-mapped registers and swaps 374 * the port value if requested, and set MAC instance for devices. 375 **/ 376 void ngbe_set_lan_id_multi_port(struct ngbe_hw *hw) 377 { 378 struct ngbe_bus_info *bus = &hw->bus; 379 u32 reg = 0; 380 381 reg = rd32(hw, NGBE_PORTSTAT); 382 bus->lan_id = NGBE_PORTSTAT_ID(reg); 383 bus->func = bus->lan_id; 384 } 385 386 /** 387 * ngbe_stop_hw - Generic stop Tx/Rx units 388 * @hw: pointer to hardware structure 389 * 390 * Sets the adapter_stopped flag within ngbe_hw struct. Clears interrupts, 391 * disables transmit and receive units. The adapter_stopped flag is used by 392 * the shared code and drivers to determine if the adapter is in a stopped 393 * state and should not touch the hardware. 394 **/ 395 s32 ngbe_stop_hw(struct ngbe_hw *hw) 396 { 397 u16 i; 398 s32 status = 0; 399 400 /* 401 * Set the adapter_stopped flag so other driver functions stop touching 402 * the hardware 403 */ 404 hw->adapter_stopped = true; 405 406 /* Disable the receive unit */ 407 ngbe_disable_rx(hw); 408 409 /* Clear interrupt mask to stop interrupts from being generated */ 410 wr32(hw, NGBE_IENMISC, 0); 411 wr32(hw, NGBE_IMS(0), NGBE_IMS_MASK); 412 413 /* Clear any pending interrupts, flush previous writes */ 414 wr32(hw, NGBE_ICRMISC, NGBE_ICRMISC_MASK); 415 wr32(hw, NGBE_ICR(0), NGBE_ICR_MASK); 416 417 wr32(hw, NGBE_BMECTL, 0x3); 418 419 /* Disable the receive unit by stopping each queue */ 420 for (i = 0; i < hw->mac.max_rx_queues; i++) 421 wr32(hw, NGBE_RXCFG(i), 0); 422 423 /* flush all queues disables */ 424 ngbe_flush(hw); 425 msec_delay(2); 426 427 /* 428 * Prevent the PCI-E bus from hanging by disabling PCI-E master 429 * access and verify no pending requests 430 */ 431 status = ngbe_set_pcie_master(hw, false); 432 if (status) 433 return status; 434 435 /* Disable the transmit unit. Each queue must be disabled. */ 436 for (i = 0; i < hw->mac.max_tx_queues; i++) 437 wr32(hw, NGBE_TXCFG(i), 0); 438 439 /* flush all queues disables */ 440 ngbe_flush(hw); 441 msec_delay(2); 442 443 return 0; 444 } 445 446 /** 447 * ngbe_led_on - Turns on the software controllable LEDs. 448 * @hw: pointer to hardware structure 449 * @index: led number to turn on 450 **/ 451 s32 ngbe_led_on(struct ngbe_hw *hw, u32 index) 452 { 453 u32 led_reg = rd32(hw, NGBE_LEDCTL); 454 455 if (index > 3) 456 return NGBE_ERR_PARAM; 457 458 /* To turn on the LED, set mode to ON. */ 459 led_reg |= NGBE_LEDCTL_100M; 460 wr32(hw, NGBE_LEDCTL, led_reg); 461 ngbe_flush(hw); 462 463 return 0; 464 } 465 466 /** 467 * ngbe_led_off - Turns off the software controllable LEDs. 468 * @hw: pointer to hardware structure 469 * @index: led number to turn off 470 **/ 471 s32 ngbe_led_off(struct ngbe_hw *hw, u32 index) 472 { 473 u32 led_reg = rd32(hw, NGBE_LEDCTL); 474 475 if (index > 3) 476 return NGBE_ERR_PARAM; 477 478 /* To turn off the LED, set mode to OFF. */ 479 led_reg &= ~NGBE_LEDCTL_100M; 480 wr32(hw, NGBE_LEDCTL, led_reg); 481 ngbe_flush(hw); 482 483 return 0; 484 } 485 486 /** 487 * ngbe_validate_mac_addr - Validate MAC address 488 * @mac_addr: pointer to MAC address. 489 * 490 * Tests a MAC address to ensure it is a valid Individual Address. 491 **/ 492 s32 ngbe_validate_mac_addr(u8 *mac_addr) 493 { 494 s32 status = 0; 495 496 /* Make sure it is not a multicast address */ 497 if (NGBE_IS_MULTICAST((struct rte_ether_addr *)mac_addr)) { 498 status = NGBE_ERR_INVALID_MAC_ADDR; 499 /* Not a broadcast address */ 500 } else if (NGBE_IS_BROADCAST((struct rte_ether_addr *)mac_addr)) { 501 status = NGBE_ERR_INVALID_MAC_ADDR; 502 /* Reject the zero address */ 503 } else if (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 && 504 mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0) { 505 status = NGBE_ERR_INVALID_MAC_ADDR; 506 } 507 return status; 508 } 509 510 /** 511 * ngbe_set_rar - Set Rx address register 512 * @hw: pointer to hardware structure 513 * @index: Receive address register to write 514 * @addr: Address to put into receive address register 515 * @vmdq: VMDq "set" or "pool" index 516 * @enable_addr: set flag that address is active 517 * 518 * Puts an ethernet address into a receive address register. 519 **/ 520 s32 ngbe_set_rar(struct ngbe_hw *hw, u32 index, u8 *addr, u32 vmdq, 521 u32 enable_addr) 522 { 523 u32 rar_low, rar_high; 524 u32 rar_entries = hw->mac.num_rar_entries; 525 526 /* Make sure we are using a valid rar index range */ 527 if (index >= rar_entries) { 528 DEBUGOUT("RAR index %d is out of range.", index); 529 return NGBE_ERR_INVALID_ARGUMENT; 530 } 531 532 /* setup VMDq pool selection before this RAR gets enabled */ 533 hw->mac.set_vmdq(hw, index, vmdq); 534 535 /* 536 * HW expects these in little endian so we reverse the byte 537 * order from network order (big endian) to little endian 538 */ 539 rar_low = NGBE_ETHADDRL_AD0(addr[5]) | 540 NGBE_ETHADDRL_AD1(addr[4]) | 541 NGBE_ETHADDRL_AD2(addr[3]) | 542 NGBE_ETHADDRL_AD3(addr[2]); 543 /* 544 * Some parts put the VMDq setting in the extra RAH bits, 545 * so save everything except the lower 16 bits that hold part 546 * of the address and the address valid bit. 547 */ 548 rar_high = rd32(hw, NGBE_ETHADDRH); 549 rar_high &= ~NGBE_ETHADDRH_AD_MASK; 550 rar_high |= (NGBE_ETHADDRH_AD4(addr[1]) | 551 NGBE_ETHADDRH_AD5(addr[0])); 552 553 rar_high &= ~NGBE_ETHADDRH_VLD; 554 if (enable_addr != 0) 555 rar_high |= NGBE_ETHADDRH_VLD; 556 557 wr32(hw, NGBE_ETHADDRIDX, index); 558 wr32(hw, NGBE_ETHADDRL, rar_low); 559 wr32(hw, NGBE_ETHADDRH, rar_high); 560 561 return 0; 562 } 563 564 /** 565 * ngbe_clear_rar - Remove Rx address register 566 * @hw: pointer to hardware structure 567 * @index: Receive address register to write 568 * 569 * Clears an ethernet address from a receive address register. 570 **/ 571 s32 ngbe_clear_rar(struct ngbe_hw *hw, u32 index) 572 { 573 u32 rar_high; 574 u32 rar_entries = hw->mac.num_rar_entries; 575 576 /* Make sure we are using a valid rar index range */ 577 if (index >= rar_entries) { 578 DEBUGOUT("RAR index %d is out of range.", index); 579 return NGBE_ERR_INVALID_ARGUMENT; 580 } 581 582 /* 583 * Some parts put the VMDq setting in the extra RAH bits, 584 * so save everything except the lower 16 bits that hold part 585 * of the address and the address valid bit. 586 */ 587 wr32(hw, NGBE_ETHADDRIDX, index); 588 rar_high = rd32(hw, NGBE_ETHADDRH); 589 rar_high &= ~(NGBE_ETHADDRH_AD_MASK | NGBE_ETHADDRH_VLD); 590 591 wr32(hw, NGBE_ETHADDRL, 0); 592 wr32(hw, NGBE_ETHADDRH, rar_high); 593 594 /* clear VMDq pool/queue selection for this RAR */ 595 hw->mac.clear_vmdq(hw, index, BIT_MASK32); 596 597 return 0; 598 } 599 600 /** 601 * ngbe_init_rx_addrs - Initializes receive address filters. 602 * @hw: pointer to hardware structure 603 * 604 * Places the MAC address in receive address register 0 and clears the rest 605 * of the receive address registers. Clears the multicast table. Assumes 606 * the receiver is in reset when the routine is called. 607 **/ 608 s32 ngbe_init_rx_addrs(struct ngbe_hw *hw) 609 { 610 u32 i; 611 u32 psrctl; 612 u32 rar_entries = hw->mac.num_rar_entries; 613 614 /* 615 * If the current mac address is valid, assume it is a software override 616 * to the permanent address. 617 * Otherwise, use the permanent address from the eeprom. 618 */ 619 if (ngbe_validate_mac_addr(hw->mac.addr) == 620 NGBE_ERR_INVALID_MAC_ADDR) { 621 /* Get the MAC address from the RAR0 for later reference */ 622 hw->mac.get_mac_addr(hw, hw->mac.addr); 623 624 DEBUGOUT(" Keeping Current RAR0 Addr = " 625 RTE_ETHER_ADDR_PRT_FMT, 626 hw->mac.addr[0], hw->mac.addr[1], 627 hw->mac.addr[2], hw->mac.addr[3], 628 hw->mac.addr[4], hw->mac.addr[5]); 629 } else { 630 /* Setup the receive address. */ 631 DEBUGOUT("Overriding MAC Address in RAR[0]"); 632 DEBUGOUT(" New MAC Addr = " 633 RTE_ETHER_ADDR_PRT_FMT, 634 hw->mac.addr[0], hw->mac.addr[1], 635 hw->mac.addr[2], hw->mac.addr[3], 636 hw->mac.addr[4], hw->mac.addr[5]); 637 638 hw->mac.set_rar(hw, 0, hw->mac.addr, 0, true); 639 } 640 641 /* clear VMDq pool/queue selection for RAR 0 */ 642 hw->mac.clear_vmdq(hw, 0, BIT_MASK32); 643 644 /* Zero out the other receive addresses. */ 645 DEBUGOUT("Clearing RAR[1-%d]", rar_entries - 1); 646 for (i = 1; i < rar_entries; i++) { 647 wr32(hw, NGBE_ETHADDRIDX, i); 648 wr32(hw, NGBE_ETHADDRL, 0); 649 wr32(hw, NGBE_ETHADDRH, 0); 650 } 651 652 /* Clear the MTA */ 653 hw->addr_ctrl.mta_in_use = 0; 654 psrctl = rd32(hw, NGBE_PSRCTL); 655 psrctl &= ~(NGBE_PSRCTL_ADHF12_MASK | NGBE_PSRCTL_MCHFENA); 656 psrctl |= NGBE_PSRCTL_ADHF12(hw->mac.mc_filter_type); 657 wr32(hw, NGBE_PSRCTL, psrctl); 658 659 DEBUGOUT(" Clearing MTA"); 660 for (i = 0; i < hw->mac.mcft_size; i++) 661 wr32(hw, NGBE_MCADDRTBL(i), 0); 662 663 ngbe_init_uta_tables(hw); 664 665 return 0; 666 } 667 668 /** 669 * ngbe_mta_vector - Determines bit-vector in multicast table to set 670 * @hw: pointer to hardware structure 671 * @mc_addr: the multicast address 672 * 673 * Extracts the 12 bits, from a multicast address, to determine which 674 * bit-vector to set in the multicast table. The hardware uses 12 bits, from 675 * incoming rx multicast addresses, to determine the bit-vector to check in 676 * the MTA. Which of the 4 combination, of 12-bits, the hardware uses is set 677 * by the MO field of the PSRCTRL. The MO field is set during initialization 678 * to mc_filter_type. 679 **/ 680 static s32 ngbe_mta_vector(struct ngbe_hw *hw, u8 *mc_addr) 681 { 682 u32 vector = 0; 683 684 switch (hw->mac.mc_filter_type) { 685 case 0: /* use bits [47:36] of the address */ 686 vector = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4)); 687 break; 688 case 1: /* use bits [46:35] of the address */ 689 vector = ((mc_addr[4] >> 3) | (((u16)mc_addr[5]) << 5)); 690 break; 691 case 2: /* use bits [45:34] of the address */ 692 vector = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6)); 693 break; 694 case 3: /* use bits [43:32] of the address */ 695 vector = ((mc_addr[4]) | (((u16)mc_addr[5]) << 8)); 696 break; 697 default: /* Invalid mc_filter_type */ 698 DEBUGOUT("MC filter type param set incorrectly"); 699 ASSERT(0); 700 break; 701 } 702 703 /* vector can only be 12-bits or boundary will be exceeded */ 704 vector &= 0xFFF; 705 return vector; 706 } 707 708 /** 709 * ngbe_set_mta - Set bit-vector in multicast table 710 * @hw: pointer to hardware structure 711 * @mc_addr: Multicast address 712 * 713 * Sets the bit-vector in the multicast table. 714 **/ 715 void ngbe_set_mta(struct ngbe_hw *hw, u8 *mc_addr) 716 { 717 u32 vector; 718 u32 vector_bit; 719 u32 vector_reg; 720 721 hw->addr_ctrl.mta_in_use++; 722 723 vector = ngbe_mta_vector(hw, mc_addr); 724 DEBUGOUT(" bit-vector = 0x%03X", vector); 725 726 /* 727 * The MTA is a register array of 128 32-bit registers. It is treated 728 * like an array of 4096 bits. We want to set bit 729 * BitArray[vector_value]. So we figure out what register the bit is 730 * in, read it, OR in the new bit, then write back the new value. The 731 * register is determined by the upper 7 bits of the vector value and 732 * the bit within that register are determined by the lower 5 bits of 733 * the value. 734 */ 735 vector_reg = (vector >> 5) & 0x7F; 736 vector_bit = vector & 0x1F; 737 hw->mac.mta_shadow[vector_reg] |= (1 << vector_bit); 738 } 739 740 /** 741 * ngbe_update_mc_addr_list - Updates MAC list of multicast addresses 742 * @hw: pointer to hardware structure 743 * @mc_addr_list: the list of new multicast addresses 744 * @mc_addr_count: number of addresses 745 * @next: iterator function to walk the multicast address list 746 * @clear: flag, when set clears the table beforehand 747 * 748 * When the clear flag is set, the given list replaces any existing list. 749 * Hashes the given addresses into the multicast table. 750 **/ 751 s32 ngbe_update_mc_addr_list(struct ngbe_hw *hw, u8 *mc_addr_list, 752 u32 mc_addr_count, ngbe_mc_addr_itr next, 753 bool clear) 754 { 755 u32 i; 756 u32 vmdq; 757 758 /* 759 * Set the new number of MC addresses that we are being requested to 760 * use. 761 */ 762 hw->addr_ctrl.num_mc_addrs = mc_addr_count; 763 hw->addr_ctrl.mta_in_use = 0; 764 765 /* Clear mta_shadow */ 766 if (clear) { 767 DEBUGOUT(" Clearing MTA"); 768 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow)); 769 } 770 771 /* Update mta_shadow */ 772 for (i = 0; i < mc_addr_count; i++) { 773 DEBUGOUT(" Adding the multicast addresses:"); 774 ngbe_set_mta(hw, next(hw, &mc_addr_list, &vmdq)); 775 } 776 777 /* Enable mta */ 778 for (i = 0; i < hw->mac.mcft_size; i++) 779 wr32a(hw, NGBE_MCADDRTBL(0), i, 780 hw->mac.mta_shadow[i]); 781 782 if (hw->addr_ctrl.mta_in_use > 0) { 783 u32 psrctl = rd32(hw, NGBE_PSRCTL); 784 psrctl &= ~(NGBE_PSRCTL_ADHF12_MASK | NGBE_PSRCTL_MCHFENA); 785 psrctl |= NGBE_PSRCTL_MCHFENA | 786 NGBE_PSRCTL_ADHF12(hw->mac.mc_filter_type); 787 wr32(hw, NGBE_PSRCTL, psrctl); 788 } 789 790 DEBUGOUT("ngbe update mc addr list complete"); 791 return 0; 792 } 793 794 /** 795 * ngbe_setup_fc_em - Set up flow control 796 * @hw: pointer to hardware structure 797 * 798 * Called at init time to set up flow control. 799 **/ 800 s32 ngbe_setup_fc_em(struct ngbe_hw *hw) 801 { 802 s32 err = 0; 803 u16 reg_cu = 0; 804 805 /* Validate the requested mode */ 806 if (hw->fc.strict_ieee && hw->fc.requested_mode == ngbe_fc_rx_pause) { 807 DEBUGOUT("ngbe_fc_rx_pause not valid in strict IEEE mode"); 808 err = NGBE_ERR_INVALID_LINK_SETTINGS; 809 goto out; 810 } 811 812 /* 813 * 1gig parts do not have a word in the EEPROM to determine the 814 * default flow control setting, so we explicitly set it to full. 815 */ 816 if (hw->fc.requested_mode == ngbe_fc_default) 817 hw->fc.requested_mode = ngbe_fc_full; 818 819 /* 820 * The possible values of fc.requested_mode are: 821 * 0: Flow control is completely disabled 822 * 1: Rx flow control is enabled (we can receive pause frames, 823 * but not send pause frames). 824 * 2: Tx flow control is enabled (we can send pause frames but 825 * we do not support receiving pause frames). 826 * 3: Both Rx and Tx flow control (symmetric) are enabled. 827 * other: Invalid. 828 */ 829 switch (hw->fc.requested_mode) { 830 case ngbe_fc_none: 831 /* Flow control completely disabled by software override. */ 832 break; 833 case ngbe_fc_tx_pause: 834 /* 835 * Tx Flow control is enabled, and Rx Flow control is 836 * disabled by software override. 837 */ 838 if (hw->phy.type == ngbe_phy_mvl_sfi || 839 hw->phy.type == ngbe_phy_yt8521s_sfi) 840 reg_cu |= MVL_FANA_ASM_PAUSE; 841 else 842 reg_cu |= 0x800; /*need to merge rtl and mvl on page 0*/ 843 break; 844 case ngbe_fc_rx_pause: 845 /* 846 * Rx Flow control is enabled and Tx Flow control is 847 * disabled by software override. Since there really 848 * isn't a way to advertise that we are capable of RX 849 * Pause ONLY, we will advertise that we support both 850 * symmetric and asymmetric Rx PAUSE, as such we fall 851 * through to the fc_full statement. Later, we will 852 * disable the adapter's ability to send PAUSE frames. 853 */ 854 case ngbe_fc_full: 855 /* Flow control (both Rx and Tx) is enabled by SW override. */ 856 if (hw->phy.type == ngbe_phy_mvl_sfi || 857 hw->phy.type == ngbe_phy_yt8521s_sfi) 858 reg_cu |= MVL_FANA_SYM_PAUSE; 859 else 860 reg_cu |= 0xC00; /*need to merge rtl and mvl on page 0*/ 861 break; 862 default: 863 DEBUGOUT("Flow control param set incorrectly"); 864 err = NGBE_ERR_CONFIG; 865 goto out; 866 } 867 868 err = hw->phy.set_pause_adv(hw, reg_cu); 869 870 out: 871 return err; 872 } 873 874 /** 875 * ngbe_fc_enable - Enable flow control 876 * @hw: pointer to hardware structure 877 * 878 * Enable flow control according to the current settings. 879 **/ 880 s32 ngbe_fc_enable(struct ngbe_hw *hw) 881 { 882 s32 err = 0; 883 u32 mflcn_reg, fccfg_reg; 884 u32 pause_time; 885 u32 fcrtl, fcrth; 886 887 /* Validate the water mark configuration */ 888 if (!hw->fc.pause_time) { 889 err = NGBE_ERR_INVALID_LINK_SETTINGS; 890 goto out; 891 } 892 893 /* Low water mark of zero causes XOFF floods */ 894 if ((hw->fc.current_mode & ngbe_fc_tx_pause) && hw->fc.high_water) { 895 if (!hw->fc.low_water || 896 hw->fc.low_water >= hw->fc.high_water) { 897 DEBUGOUT("Invalid water mark configuration"); 898 err = NGBE_ERR_INVALID_LINK_SETTINGS; 899 goto out; 900 } 901 } 902 903 /* Negotiate the fc mode to use */ 904 hw->mac.fc_autoneg(hw); 905 906 /* Disable any previous flow control settings */ 907 mflcn_reg = rd32(hw, NGBE_RXFCCFG); 908 mflcn_reg &= ~NGBE_RXFCCFG_FC; 909 910 fccfg_reg = rd32(hw, NGBE_TXFCCFG); 911 fccfg_reg &= ~NGBE_TXFCCFG_FC; 912 /* 913 * The possible values of fc.current_mode are: 914 * 0: Flow control is completely disabled 915 * 1: Rx flow control is enabled (we can receive pause frames, 916 * but not send pause frames). 917 * 2: Tx flow control is enabled (we can send pause frames but 918 * we do not support receiving pause frames). 919 * 3: Both Rx and Tx flow control (symmetric) are enabled. 920 * other: Invalid. 921 */ 922 switch (hw->fc.current_mode) { 923 case ngbe_fc_none: 924 /* 925 * Flow control is disabled by software override or autoneg. 926 * The code below will actually disable it in the HW. 927 */ 928 break; 929 case ngbe_fc_rx_pause: 930 /* 931 * Rx Flow control is enabled and Tx Flow control is 932 * disabled by software override. Since there really 933 * isn't a way to advertise that we are capable of RX 934 * Pause ONLY, we will advertise that we support both 935 * symmetric and asymmetric Rx PAUSE. Later, we will 936 * disable the adapter's ability to send PAUSE frames. 937 */ 938 mflcn_reg |= NGBE_RXFCCFG_FC; 939 break; 940 case ngbe_fc_tx_pause: 941 /* 942 * Tx Flow control is enabled, and Rx Flow control is 943 * disabled by software override. 944 */ 945 fccfg_reg |= NGBE_TXFCCFG_FC; 946 break; 947 case ngbe_fc_full: 948 /* Flow control (both Rx and Tx) is enabled by SW override. */ 949 mflcn_reg |= NGBE_RXFCCFG_FC; 950 fccfg_reg |= NGBE_TXFCCFG_FC; 951 break; 952 default: 953 DEBUGOUT("Flow control param set incorrectly"); 954 err = NGBE_ERR_CONFIG; 955 goto out; 956 } 957 958 /* Set 802.3x based flow control settings. */ 959 wr32(hw, NGBE_RXFCCFG, mflcn_reg); 960 wr32(hw, NGBE_TXFCCFG, fccfg_reg); 961 962 /* Set up and enable Rx high/low water mark thresholds, enable XON. */ 963 if ((hw->fc.current_mode & ngbe_fc_tx_pause) && 964 hw->fc.high_water) { 965 fcrtl = NGBE_FCWTRLO_TH(hw->fc.low_water) | 966 NGBE_FCWTRLO_XON; 967 fcrth = NGBE_FCWTRHI_TH(hw->fc.high_water) | 968 NGBE_FCWTRHI_XOFF; 969 } else { 970 /* 971 * In order to prevent Tx hangs when the internal Tx 972 * switch is enabled we must set the high water mark 973 * to the Rx packet buffer size - 24KB. This allows 974 * the Tx switch to function even under heavy Rx 975 * workloads. 976 */ 977 fcrtl = 0; 978 fcrth = rd32(hw, NGBE_PBRXSIZE) - 24576; 979 } 980 wr32(hw, NGBE_FCWTRLO, fcrtl); 981 wr32(hw, NGBE_FCWTRHI, fcrth); 982 983 /* Configure pause time */ 984 pause_time = NGBE_RXFCFSH_TIME(hw->fc.pause_time); 985 wr32(hw, NGBE_FCXOFFTM, pause_time * 0x00010000); 986 987 /* Configure flow control refresh threshold value */ 988 wr32(hw, NGBE_RXFCRFSH, hw->fc.pause_time / 2); 989 990 out: 991 return err; 992 } 993 994 /** 995 * ngbe_negotiate_fc - Negotiate flow control 996 * @hw: pointer to hardware structure 997 * @adv_reg: flow control advertised settings 998 * @lp_reg: link partner's flow control settings 999 * @adv_sym: symmetric pause bit in advertisement 1000 * @adv_asm: asymmetric pause bit in advertisement 1001 * @lp_sym: symmetric pause bit in link partner advertisement 1002 * @lp_asm: asymmetric pause bit in link partner advertisement 1003 * 1004 * Find the intersection between advertised settings and link partner's 1005 * advertised settings 1006 **/ 1007 s32 ngbe_negotiate_fc(struct ngbe_hw *hw, u32 adv_reg, u32 lp_reg, 1008 u32 adv_sym, u32 adv_asm, u32 lp_sym, u32 lp_asm) 1009 { 1010 if ((!(adv_reg)) || (!(lp_reg))) { 1011 DEBUGOUT("Local or link partner's advertised flow control settings are NULL. Local: %x, link partner: %x", 1012 adv_reg, lp_reg); 1013 return NGBE_ERR_FC_NOT_NEGOTIATED; 1014 } 1015 1016 if ((adv_reg & adv_sym) && (lp_reg & lp_sym)) { 1017 /* 1018 * Now we need to check if the user selected Rx ONLY 1019 * of pause frames. In this case, we had to advertise 1020 * FULL flow control because we could not advertise RX 1021 * ONLY. Hence, we must now check to see if we need to 1022 * turn OFF the TRANSMISSION of PAUSE frames. 1023 */ 1024 if (hw->fc.requested_mode == ngbe_fc_full) { 1025 hw->fc.current_mode = ngbe_fc_full; 1026 DEBUGOUT("Flow Control = FULL."); 1027 } else { 1028 hw->fc.current_mode = ngbe_fc_rx_pause; 1029 DEBUGOUT("Flow Control=RX PAUSE frames only"); 1030 } 1031 } else if (!(adv_reg & adv_sym) && (adv_reg & adv_asm) && 1032 (lp_reg & lp_sym) && (lp_reg & lp_asm)) { 1033 hw->fc.current_mode = ngbe_fc_tx_pause; 1034 DEBUGOUT("Flow Control = TX PAUSE frames only."); 1035 } else if ((adv_reg & adv_sym) && (adv_reg & adv_asm) && 1036 !(lp_reg & lp_sym) && (lp_reg & lp_asm)) { 1037 hw->fc.current_mode = ngbe_fc_rx_pause; 1038 DEBUGOUT("Flow Control = RX PAUSE frames only."); 1039 } else { 1040 hw->fc.current_mode = ngbe_fc_none; 1041 DEBUGOUT("Flow Control = NONE."); 1042 } 1043 return 0; 1044 } 1045 1046 /** 1047 * ngbe_fc_autoneg_em - Enable flow control IEEE clause 37 1048 * @hw: pointer to hardware structure 1049 * 1050 * Enable flow control according to IEEE clause 37. 1051 **/ 1052 STATIC s32 ngbe_fc_autoneg_em(struct ngbe_hw *hw) 1053 { 1054 u8 technology_ability_reg = 0; 1055 u8 lp_technology_ability_reg = 0; 1056 1057 hw->phy.get_adv_pause(hw, &technology_ability_reg); 1058 hw->phy.get_lp_adv_pause(hw, &lp_technology_ability_reg); 1059 1060 return ngbe_negotiate_fc(hw, (u32)technology_ability_reg, 1061 (u32)lp_technology_ability_reg, 1062 NGBE_TAF_SYM_PAUSE, NGBE_TAF_ASM_PAUSE, 1063 NGBE_TAF_SYM_PAUSE, NGBE_TAF_ASM_PAUSE); 1064 } 1065 1066 /** 1067 * ngbe_fc_autoneg - Configure flow control 1068 * @hw: pointer to hardware structure 1069 * 1070 * Compares our advertised flow control capabilities to those advertised by 1071 * our link partner, and determines the proper flow control mode to use. 1072 **/ 1073 void ngbe_fc_autoneg(struct ngbe_hw *hw) 1074 { 1075 s32 err = NGBE_ERR_FC_NOT_NEGOTIATED; 1076 u32 speed; 1077 bool link_up; 1078 1079 /* 1080 * AN should have completed when the cable was plugged in. 1081 * Look for reasons to bail out. Bail out if: 1082 * - FC autoneg is disabled, or if 1083 * - link is not up. 1084 */ 1085 if (hw->fc.disable_fc_autoneg) { 1086 DEBUGOUT("Flow control autoneg is disabled"); 1087 goto out; 1088 } 1089 1090 hw->mac.check_link(hw, &speed, &link_up, false); 1091 if (!link_up) { 1092 DEBUGOUT("The link is down"); 1093 goto out; 1094 } 1095 1096 err = ngbe_fc_autoneg_em(hw); 1097 1098 out: 1099 if (err == 0) { 1100 hw->fc.fc_was_autonegged = true; 1101 } else { 1102 hw->fc.fc_was_autonegged = false; 1103 hw->fc.current_mode = hw->fc.requested_mode; 1104 } 1105 } 1106 1107 /** 1108 * ngbe_set_pcie_master - Disable or Enable PCI-express master access 1109 * @hw: pointer to hardware structure 1110 * 1111 * Disables PCI-Express master access and verifies there are no pending 1112 * requests. NGBE_ERR_MASTER_REQUESTS_PENDING is returned if master disable 1113 * bit hasn't caused the master requests to be disabled, else 0 1114 * is returned signifying master requests disabled. 1115 **/ 1116 s32 ngbe_set_pcie_master(struct ngbe_hw *hw, bool enable) 1117 { 1118 struct rte_pci_device *pci_dev = (struct rte_pci_device *)hw->back; 1119 s32 status = 0; 1120 u32 i; 1121 1122 if (rte_pci_set_bus_master(pci_dev, enable) < 0) { 1123 DEBUGOUT("Cannot configure PCI bus master"); 1124 return -1; 1125 } 1126 1127 if (enable) 1128 goto out; 1129 1130 /* Exit if master requests are blocked */ 1131 if (!(rd32(hw, NGBE_BMEPEND)) || 1132 NGBE_REMOVED(hw->hw_addr)) 1133 goto out; 1134 1135 /* Poll for master request bit to clear */ 1136 for (i = 0; i < NGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) { 1137 usec_delay(100); 1138 if (!(rd32(hw, NGBE_BMEPEND))) 1139 goto out; 1140 } 1141 1142 DEBUGOUT("PCIe transaction pending bit also did not clear."); 1143 status = NGBE_ERR_MASTER_REQUESTS_PENDING; 1144 1145 out: 1146 return status; 1147 } 1148 1149 /** 1150 * ngbe_acquire_swfw_sync - Acquire SWFW semaphore 1151 * @hw: pointer to hardware structure 1152 * @mask: Mask to specify which semaphore to acquire 1153 * 1154 * Acquires the SWFW semaphore through the MNGSEM register for the specified 1155 * function (CSR, PHY0, PHY1, EEPROM, Flash) 1156 **/ 1157 s32 ngbe_acquire_swfw_sync(struct ngbe_hw *hw, u32 mask) 1158 { 1159 u32 mngsem = 0; 1160 u32 fwsm = 0; 1161 u32 swmask = NGBE_MNGSEM_SW(mask); 1162 u32 fwmask = NGBE_MNGSEM_FW(mask); 1163 u32 timeout = 200; 1164 u32 i; 1165 1166 for (i = 0; i < timeout; i++) { 1167 /* 1168 * SW NVM semaphore bit is used for access to all 1169 * SW_FW_SYNC bits (not just NVM) 1170 */ 1171 if (ngbe_get_eeprom_semaphore(hw)) 1172 return NGBE_ERR_SWFW_SYNC; 1173 1174 mngsem = rd32(hw, NGBE_MNGSEM); 1175 if (mngsem & (fwmask | swmask)) { 1176 /* Resource is currently in use by FW or SW */ 1177 ngbe_release_eeprom_semaphore(hw); 1178 msec_delay(5); 1179 } else { 1180 mngsem |= swmask; 1181 wr32(hw, NGBE_MNGSEM, mngsem); 1182 ngbe_release_eeprom_semaphore(hw); 1183 return 0; 1184 } 1185 } 1186 1187 fwsm = rd32(hw, NGBE_MNGFWSYNC); 1188 DEBUGOUT("SWFW semaphore not granted: MNG_SWFW_SYNC = 0x%x, MNG_FW_SM = 0x%x", 1189 mngsem, fwsm); 1190 1191 msec_delay(5); 1192 return NGBE_ERR_SWFW_SYNC; 1193 } 1194 1195 /** 1196 * ngbe_release_swfw_sync - Release SWFW semaphore 1197 * @hw: pointer to hardware structure 1198 * @mask: Mask to specify which semaphore to release 1199 * 1200 * Releases the SWFW semaphore through the MNGSEM register for the specified 1201 * function (CSR, PHY0, PHY1, EEPROM, Flash) 1202 **/ 1203 void ngbe_release_swfw_sync(struct ngbe_hw *hw, u32 mask) 1204 { 1205 u32 mngsem; 1206 u32 swmask = mask; 1207 1208 ngbe_get_eeprom_semaphore(hw); 1209 1210 mngsem = rd32(hw, NGBE_MNGSEM); 1211 mngsem &= ~swmask; 1212 wr32(hw, NGBE_MNGSEM, mngsem); 1213 1214 ngbe_release_eeprom_semaphore(hw); 1215 } 1216 1217 /** 1218 * ngbe_disable_sec_rx_path - Stops the receive data path 1219 * @hw: pointer to hardware structure 1220 * 1221 * Stops the receive data path and waits for the HW to internally empty 1222 * the Rx security block 1223 **/ 1224 s32 ngbe_disable_sec_rx_path(struct ngbe_hw *hw) 1225 { 1226 #define NGBE_MAX_SECRX_POLL 4000 1227 1228 int i; 1229 u32 secrxreg; 1230 1231 secrxreg = rd32(hw, NGBE_SECRXCTL); 1232 secrxreg |= NGBE_SECRXCTL_XDSA; 1233 wr32(hw, NGBE_SECRXCTL, secrxreg); 1234 for (i = 0; i < NGBE_MAX_SECRX_POLL; i++) { 1235 secrxreg = rd32(hw, NGBE_SECRXSTAT); 1236 if (!(secrxreg & NGBE_SECRXSTAT_RDY)) 1237 /* Use interrupt-safe sleep just in case */ 1238 usec_delay(10); 1239 else 1240 break; 1241 } 1242 1243 /* For informational purposes only */ 1244 if (i >= NGBE_MAX_SECRX_POLL) 1245 DEBUGOUT("Rx unit being enabled before security path fully disabled. Continuing with init."); 1246 1247 return 0; 1248 } 1249 1250 /** 1251 * ngbe_enable_sec_rx_path - Enables the receive data path 1252 * @hw: pointer to hardware structure 1253 * 1254 * Enables the receive data path. 1255 **/ 1256 s32 ngbe_enable_sec_rx_path(struct ngbe_hw *hw) 1257 { 1258 u32 secrxreg; 1259 1260 secrxreg = rd32(hw, NGBE_SECRXCTL); 1261 secrxreg &= ~NGBE_SECRXCTL_XDSA; 1262 wr32(hw, NGBE_SECRXCTL, secrxreg); 1263 ngbe_flush(hw); 1264 1265 return 0; 1266 } 1267 1268 /** 1269 * ngbe_clear_vmdq - Disassociate a VMDq pool index from a rx address 1270 * @hw: pointer to hardware struct 1271 * @rar: receive address register index to disassociate 1272 * @vmdq: VMDq pool index to remove from the rar 1273 **/ 1274 s32 ngbe_clear_vmdq(struct ngbe_hw *hw, u32 rar, u32 vmdq) 1275 { 1276 u32 mpsar; 1277 u32 rar_entries = hw->mac.num_rar_entries; 1278 1279 /* Make sure we are using a valid rar index range */ 1280 if (rar >= rar_entries) { 1281 DEBUGOUT("RAR index %d is out of range.", rar); 1282 return NGBE_ERR_INVALID_ARGUMENT; 1283 } 1284 1285 wr32(hw, NGBE_ETHADDRIDX, rar); 1286 mpsar = rd32(hw, NGBE_ETHADDRASS); 1287 1288 if (NGBE_REMOVED(hw->hw_addr)) 1289 goto done; 1290 1291 if (!mpsar) 1292 goto done; 1293 1294 mpsar &= ~(1 << vmdq); 1295 wr32(hw, NGBE_ETHADDRASS, mpsar); 1296 1297 /* was that the last pool using this rar? */ 1298 if (mpsar == 0 && rar != 0) 1299 hw->mac.clear_rar(hw, rar); 1300 done: 1301 return 0; 1302 } 1303 1304 /** 1305 * ngbe_set_vmdq - Associate a VMDq pool index with a rx address 1306 * @hw: pointer to hardware struct 1307 * @rar: receive address register index to associate with a VMDq index 1308 * @vmdq: VMDq pool index 1309 **/ 1310 s32 ngbe_set_vmdq(struct ngbe_hw *hw, u32 rar, u32 vmdq) 1311 { 1312 u32 mpsar; 1313 u32 rar_entries = hw->mac.num_rar_entries; 1314 1315 /* Make sure we are using a valid rar index range */ 1316 if (rar >= rar_entries) { 1317 DEBUGOUT("RAR index %d is out of range.", rar); 1318 return NGBE_ERR_INVALID_ARGUMENT; 1319 } 1320 1321 wr32(hw, NGBE_ETHADDRIDX, rar); 1322 1323 mpsar = rd32(hw, NGBE_ETHADDRASS); 1324 mpsar |= 1 << vmdq; 1325 wr32(hw, NGBE_ETHADDRASS, mpsar); 1326 1327 return 0; 1328 } 1329 1330 /** 1331 * ngbe_init_uta_tables - Initialize the Unicast Table Array 1332 * @hw: pointer to hardware structure 1333 **/ 1334 s32 ngbe_init_uta_tables(struct ngbe_hw *hw) 1335 { 1336 int i; 1337 1338 DEBUGOUT(" Clearing UTA"); 1339 1340 for (i = 0; i < 128; i++) 1341 wr32(hw, NGBE_UCADDRTBL(i), 0); 1342 1343 return 0; 1344 } 1345 1346 /** 1347 * ngbe_find_vlvf_slot - find the vlanid or the first empty slot 1348 * @hw: pointer to hardware structure 1349 * @vlan: VLAN id to write to VLAN filter 1350 * @vlvf_bypass: true to find vlanid only, false returns first empty slot if 1351 * vlanid not found 1352 * 1353 * 1354 * return the VLVF index where this VLAN id should be placed 1355 * 1356 **/ 1357 s32 ngbe_find_vlvf_slot(struct ngbe_hw *hw, u32 vlan, bool vlvf_bypass) 1358 { 1359 s32 regindex, first_empty_slot; 1360 u32 bits; 1361 1362 /* short cut the special case */ 1363 if (vlan == 0) 1364 return 0; 1365 1366 /* if vlvf_bypass is set we don't want to use an empty slot, we 1367 * will simply bypass the VLVF if there are no entries present in the 1368 * VLVF that contain our VLAN 1369 */ 1370 first_empty_slot = vlvf_bypass ? NGBE_ERR_NO_SPACE : 0; 1371 1372 /* add VLAN enable bit for comparison */ 1373 vlan |= NGBE_PSRVLAN_EA; 1374 1375 /* Search for the vlan id in the VLVF entries. Save off the first empty 1376 * slot found along the way. 1377 * 1378 * pre-decrement loop covering (NGBE_NUM_POOL - 1) .. 1 1379 */ 1380 for (regindex = NGBE_NUM_POOL; --regindex;) { 1381 wr32(hw, NGBE_PSRVLANIDX, regindex); 1382 bits = rd32(hw, NGBE_PSRVLAN); 1383 if (bits == vlan) 1384 return regindex; 1385 if (!first_empty_slot && !bits) 1386 first_empty_slot = regindex; 1387 } 1388 1389 /* If we are here then we didn't find the VLAN. Return first empty 1390 * slot we found during our search, else error. 1391 */ 1392 if (!first_empty_slot) 1393 DEBUGOUT("No space in VLVF."); 1394 1395 return first_empty_slot ? first_empty_slot : NGBE_ERR_NO_SPACE; 1396 } 1397 1398 /** 1399 * ngbe_set_vfta - Set VLAN filter table 1400 * @hw: pointer to hardware structure 1401 * @vlan: VLAN id to write to VLAN filter 1402 * @vind: VMDq output index that maps queue to VLAN id in VLVFB 1403 * @vlan_on: boolean flag to turn on/off VLAN 1404 * @vlvf_bypass: boolean flag indicating updating default pool is okay 1405 * 1406 * Turn on/off specified VLAN in the VLAN filter table. 1407 **/ 1408 s32 ngbe_set_vfta(struct ngbe_hw *hw, u32 vlan, u32 vind, 1409 bool vlan_on, bool vlvf_bypass) 1410 { 1411 u32 regidx, vfta_delta, vfta; 1412 s32 err; 1413 1414 if (vlan > 4095 || vind > 63) 1415 return NGBE_ERR_PARAM; 1416 1417 /* 1418 * this is a 2 part operation - first the VFTA, then the 1419 * VLVF and VLVFB if VT Mode is set 1420 * We don't write the VFTA until we know the VLVF part succeeded. 1421 */ 1422 1423 /* Part 1 1424 * The VFTA is a bitstring made up of 128 32-bit registers 1425 * that enable the particular VLAN id, much like the MTA: 1426 * bits[11-5]: which register 1427 * bits[4-0]: which bit in the register 1428 */ 1429 regidx = vlan / 32; 1430 vfta_delta = 1 << (vlan % 32); 1431 vfta = rd32(hw, NGBE_VLANTBL(regidx)); 1432 1433 /* 1434 * vfta_delta represents the difference between the current value 1435 * of vfta and the value we want in the register. Since the diff 1436 * is an XOR mask we can just update the vfta using an XOR 1437 */ 1438 vfta_delta &= vlan_on ? ~vfta : vfta; 1439 vfta ^= vfta_delta; 1440 1441 /* Part 2 1442 * Call ngbe_set_vlvf to set VLVFB and VLVF 1443 */ 1444 err = ngbe_set_vlvf(hw, vlan, vind, vlan_on, &vfta_delta, 1445 vfta, vlvf_bypass); 1446 if (err != 0) { 1447 if (vlvf_bypass) 1448 goto vfta_update; 1449 return err; 1450 } 1451 1452 vfta_update: 1453 /* Update VFTA now that we are ready for traffic */ 1454 if (vfta_delta) 1455 wr32(hw, NGBE_VLANTBL(regidx), vfta); 1456 1457 return 0; 1458 } 1459 1460 /** 1461 * ngbe_set_vlvf - Set VLAN Pool Filter 1462 * @hw: pointer to hardware structure 1463 * @vlan: VLAN id to write to VLAN filter 1464 * @vind: VMDq output index that maps queue to VLAN id in PSRVLANPLM 1465 * @vlan_on: boolean flag to turn on/off VLAN in PSRVLAN 1466 * @vfta_delta: pointer to the difference between the current value 1467 * of PSRVLANPLM and the desired value 1468 * @vfta: the desired value of the VFTA 1469 * @vlvf_bypass: boolean flag indicating updating default pool is okay 1470 * 1471 * Turn on/off specified bit in VLVF table. 1472 **/ 1473 s32 ngbe_set_vlvf(struct ngbe_hw *hw, u32 vlan, u32 vind, 1474 bool vlan_on, u32 *vfta_delta, u32 vfta, 1475 bool vlvf_bypass) 1476 { 1477 u32 bits; 1478 u32 portctl; 1479 s32 vlvf_index; 1480 1481 if (vlan > 4095 || vind > 63) 1482 return NGBE_ERR_PARAM; 1483 1484 /* If VT Mode is set 1485 * Either vlan_on 1486 * make sure the vlan is in PSRVLAN 1487 * set the vind bit in the matching PSRVLANPLM 1488 * Or !vlan_on 1489 * clear the pool bit and possibly the vind 1490 */ 1491 portctl = rd32(hw, NGBE_PORTCTL); 1492 if (!(portctl & NGBE_PORTCTL_NUMVT_MASK)) 1493 return 0; 1494 1495 vlvf_index = ngbe_find_vlvf_slot(hw, vlan, vlvf_bypass); 1496 if (vlvf_index < 0) 1497 return vlvf_index; 1498 1499 wr32(hw, NGBE_PSRVLANIDX, vlvf_index); 1500 bits = rd32(hw, NGBE_PSRVLANPLM(vind / 32)); 1501 1502 /* set the pool bit */ 1503 bits |= 1 << (vind % 32); 1504 if (vlan_on) 1505 goto vlvf_update; 1506 1507 /* clear the pool bit */ 1508 bits ^= 1 << (vind % 32); 1509 1510 if (!bits && 1511 !rd32(hw, NGBE_PSRVLANPLM(vind / 32))) { 1512 /* Clear PSRVLANPLM first, then disable PSRVLAN. Otherwise 1513 * we run the risk of stray packets leaking into 1514 * the PF via the default pool 1515 */ 1516 if (*vfta_delta) 1517 wr32(hw, NGBE_PSRVLANPLM(vlan / 32), vfta); 1518 1519 /* disable VLVF and clear remaining bit from pool */ 1520 wr32(hw, NGBE_PSRVLAN, 0); 1521 wr32(hw, NGBE_PSRVLANPLM(vind / 32), 0); 1522 1523 return 0; 1524 } 1525 1526 /* If there are still bits set in the PSRVLANPLM registers 1527 * for the VLAN ID indicated we need to see if the 1528 * caller is requesting that we clear the PSRVLANPLM entry bit. 1529 * If the caller has requested that we clear the PSRVLANPLM 1530 * entry bit but there are still pools/VFs using this VLAN 1531 * ID entry then ignore the request. We're not worried 1532 * about the case where we're turning the PSRVLANPLM VLAN ID 1533 * entry bit on, only when requested to turn it off as 1534 * there may be multiple pools and/or VFs using the 1535 * VLAN ID entry. In that case we cannot clear the 1536 * PSRVLANPLM bit until all pools/VFs using that VLAN ID have also 1537 * been cleared. This will be indicated by "bits" being 1538 * zero. 1539 */ 1540 *vfta_delta = 0; 1541 1542 vlvf_update: 1543 /* record pool change and enable VLAN ID if not already enabled */ 1544 wr32(hw, NGBE_PSRVLANPLM(vind / 32), bits); 1545 wr32(hw, NGBE_PSRVLAN, NGBE_PSRVLAN_EA | vlan); 1546 1547 return 0; 1548 } 1549 1550 /** 1551 * ngbe_clear_vfta - Clear VLAN filter table 1552 * @hw: pointer to hardware structure 1553 * 1554 * Clears the VLAN filer table, and the VMDq index associated with the filter 1555 **/ 1556 s32 ngbe_clear_vfta(struct ngbe_hw *hw) 1557 { 1558 u32 offset; 1559 1560 for (offset = 0; offset < hw->mac.vft_size; offset++) 1561 wr32(hw, NGBE_VLANTBL(offset), 0); 1562 1563 for (offset = 0; offset < NGBE_NUM_POOL; offset++) { 1564 wr32(hw, NGBE_PSRVLANIDX, offset); 1565 wr32(hw, NGBE_PSRVLAN, 0); 1566 wr32(hw, NGBE_PSRVLANPLM(0), 0); 1567 } 1568 1569 return 0; 1570 } 1571 1572 /** 1573 * ngbe_check_mac_link_em - Determine link and speed status 1574 * @hw: pointer to hardware structure 1575 * @speed: pointer to link speed 1576 * @link_up: true when link is up 1577 * @link_up_wait_to_complete: bool used to wait for link up or not 1578 * 1579 * Reads the links register to determine if link is up and the current speed 1580 **/ 1581 s32 ngbe_check_mac_link_em(struct ngbe_hw *hw, u32 *speed, 1582 bool *link_up, bool link_up_wait_to_complete) 1583 { 1584 u32 i; 1585 s32 status = 0; 1586 1587 if (hw->lsc) { 1588 u32 reg; 1589 1590 reg = rd32(hw, NGBE_GPIOINTSTAT); 1591 wr32(hw, NGBE_GPIOEOI, reg); 1592 } 1593 1594 if (link_up_wait_to_complete) { 1595 for (i = 0; i < hw->mac.max_link_up_time; i++) { 1596 status = hw->phy.check_link(hw, speed, link_up); 1597 if (*link_up) 1598 break; 1599 msec_delay(100); 1600 } 1601 } else { 1602 status = hw->phy.check_link(hw, speed, link_up); 1603 } 1604 1605 return status; 1606 } 1607 1608 s32 ngbe_get_link_capabilities_em(struct ngbe_hw *hw, 1609 u32 *speed, 1610 bool *autoneg) 1611 { 1612 s32 status = 0; 1613 u16 value = 0; 1614 1615 hw->mac.autoneg = *autoneg; 1616 1617 if (hw->phy.type == ngbe_phy_rtl) { 1618 *speed = NGBE_LINK_SPEED_1GB_FULL | 1619 NGBE_LINK_SPEED_100M_FULL | 1620 NGBE_LINK_SPEED_10M_FULL; 1621 } 1622 1623 if (hw->phy.type == ngbe_phy_yt8521s_sfi) { 1624 ngbe_read_phy_reg_ext_yt(hw, YT_CHIP, 0, &value); 1625 if ((value & YT_CHIP_MODE_MASK) == YT_CHIP_MODE_SEL(1)) 1626 *speed = NGBE_LINK_SPEED_1GB_FULL; 1627 } 1628 1629 return status; 1630 } 1631 1632 s32 ngbe_setup_mac_link_em(struct ngbe_hw *hw, 1633 u32 speed, 1634 bool autoneg_wait_to_complete) 1635 { 1636 s32 status; 1637 1638 /* Setup the PHY according to input speed */ 1639 status = hw->phy.setup_link(hw, speed, autoneg_wait_to_complete); 1640 1641 return status; 1642 } 1643 1644 /** 1645 * ngbe_set_mac_anti_spoofing - Enable/Disable MAC anti-spoofing 1646 * @hw: pointer to hardware structure 1647 * @enable: enable or disable switch for MAC anti-spoofing 1648 * @vf: Virtual Function pool - VF Pool to set for MAC anti-spoofing 1649 * 1650 **/ 1651 void ngbe_set_mac_anti_spoofing(struct ngbe_hw *hw, bool enable, int vf) 1652 { 1653 u32 pfvfspoof; 1654 1655 pfvfspoof = rd32(hw, NGBE_POOLTXASMAC); 1656 if (enable) 1657 pfvfspoof |= (1 << vf); 1658 else 1659 pfvfspoof &= ~(1 << vf); 1660 wr32(hw, NGBE_POOLTXASMAC, pfvfspoof); 1661 } 1662 1663 /** 1664 * ngbe_set_pba - Initialize Rx packet buffer 1665 * @hw: pointer to hardware structure 1666 * @headroom: reserve n KB of headroom 1667 **/ 1668 void ngbe_set_pba(struct ngbe_hw *hw) 1669 { 1670 u32 rxpktsize = hw->mac.rx_pb_size; 1671 u32 txpktsize, txpbthresh; 1672 1673 /* Reserve 256 KB of headroom */ 1674 rxpktsize -= 256; 1675 1676 rxpktsize <<= 10; 1677 wr32(hw, NGBE_PBRXSIZE, rxpktsize); 1678 1679 /* Only support an equally distributed Tx packet buffer strategy. */ 1680 txpktsize = NGBE_PBTXSIZE_MAX; 1681 txpbthresh = (txpktsize / 1024) - NGBE_TXPKT_SIZE_MAX; 1682 1683 wr32(hw, NGBE_PBTXSIZE, txpktsize); 1684 wr32(hw, NGBE_PBTXDMATH, txpbthresh); 1685 } 1686 1687 /** 1688 * ngbe_set_vlan_anti_spoofing - Enable/Disable VLAN anti-spoofing 1689 * @hw: pointer to hardware structure 1690 * @enable: enable or disable switch for VLAN anti-spoofing 1691 * @vf: Virtual Function pool - VF Pool to set for VLAN anti-spoofing 1692 * 1693 **/ 1694 void ngbe_set_vlan_anti_spoofing(struct ngbe_hw *hw, bool enable, int vf) 1695 { 1696 u32 pfvfspoof; 1697 1698 pfvfspoof = rd32(hw, NGBE_POOLTXASVLAN); 1699 if (enable) 1700 pfvfspoof |= (1 << vf); 1701 else 1702 pfvfspoof &= ~(1 << vf); 1703 wr32(hw, NGBE_POOLTXASVLAN, pfvfspoof); 1704 } 1705 1706 /** 1707 * ngbe_init_thermal_sensor_thresh - Inits thermal sensor thresholds 1708 * @hw: pointer to hardware structure 1709 * 1710 * Inits the thermal sensor thresholds according to the NVM map 1711 * and save off the threshold and location values into mac.thermal_sensor_data 1712 **/ 1713 s32 ngbe_init_thermal_sensor_thresh(struct ngbe_hw *hw) 1714 { 1715 struct ngbe_thermal_sensor_data *data = &hw->mac.thermal_sensor_data; 1716 1717 memset(data, 0, sizeof(struct ngbe_thermal_sensor_data)); 1718 1719 if (hw->bus.lan_id != 0) 1720 return NGBE_NOT_IMPLEMENTED; 1721 1722 wr32(hw, NGBE_TSINTR, 1723 NGBE_TSINTR_AEN | NGBE_TSINTR_DEN); 1724 wr32(hw, NGBE_TSEN, NGBE_TSEN_ENA); 1725 1726 1727 data->sensor[0].alarm_thresh = 115; 1728 wr32(hw, NGBE_TSATHRE, 0x344); 1729 data->sensor[0].dalarm_thresh = 110; 1730 wr32(hw, NGBE_TSDTHRE, 0x330); 1731 1732 return 0; 1733 } 1734 1735 s32 ngbe_mac_check_overtemp(struct ngbe_hw *hw) 1736 { 1737 s32 status = 0; 1738 u32 ts_state; 1739 1740 /* Check that the LASI temp alarm status was triggered */ 1741 ts_state = rd32(hw, NGBE_TSALM); 1742 1743 if (ts_state & NGBE_TSALM_HI) 1744 status = NGBE_ERR_UNDERTEMP; 1745 else if (ts_state & NGBE_TSALM_LO) 1746 status = NGBE_ERR_OVERTEMP; 1747 1748 return status; 1749 } 1750 1751 void ngbe_disable_rx(struct ngbe_hw *hw) 1752 { 1753 u32 pfdtxgswc; 1754 1755 pfdtxgswc = rd32(hw, NGBE_PSRCTL); 1756 if (pfdtxgswc & NGBE_PSRCTL_LBENA) { 1757 pfdtxgswc &= ~NGBE_PSRCTL_LBENA; 1758 wr32(hw, NGBE_PSRCTL, pfdtxgswc); 1759 hw->mac.set_lben = true; 1760 } else { 1761 hw->mac.set_lben = false; 1762 } 1763 1764 wr32m(hw, NGBE_PBRXCTL, NGBE_PBRXCTL_ENA, 0); 1765 if (!(hw->ncsi_enabled || hw->wol_enabled)) 1766 wr32m(hw, NGBE_MACRXCFG, NGBE_MACRXCFG_ENA, 0); 1767 } 1768 1769 void ngbe_enable_rx(struct ngbe_hw *hw) 1770 { 1771 u32 pfdtxgswc; 1772 1773 wr32m(hw, NGBE_MACRXCFG, NGBE_MACRXCFG_ENA, NGBE_MACRXCFG_ENA); 1774 wr32m(hw, NGBE_PBRXCTL, NGBE_PBRXCTL_ENA, NGBE_PBRXCTL_ENA); 1775 1776 if (hw->mac.set_lben) { 1777 pfdtxgswc = rd32(hw, NGBE_PSRCTL); 1778 pfdtxgswc |= NGBE_PSRCTL_LBENA; 1779 wr32(hw, NGBE_PSRCTL, pfdtxgswc); 1780 hw->mac.set_lben = false; 1781 } 1782 } 1783 1784 /** 1785 * ngbe_set_mac_type - Sets MAC type 1786 * @hw: pointer to the HW structure 1787 * 1788 * This function sets the mac type of the adapter based on the 1789 * vendor ID and device ID stored in the hw structure. 1790 **/ 1791 s32 ngbe_set_mac_type(struct ngbe_hw *hw) 1792 { 1793 s32 err = 0; 1794 1795 if (hw->vendor_id != PCI_VENDOR_ID_WANGXUN) { 1796 DEBUGOUT("Unsupported vendor id: %x", hw->vendor_id); 1797 return NGBE_ERR_DEVICE_NOT_SUPPORTED; 1798 } 1799 1800 switch (hw->sub_device_id) { 1801 case NGBE_SUB_DEV_ID_EM_RTL_SGMII: 1802 case NGBE_SUB_DEV_ID_EM_MVL_RGMII: 1803 hw->phy.media_type = ngbe_media_type_copper; 1804 hw->mac.type = ngbe_mac_em; 1805 hw->mac.link_type = ngbe_link_copper; 1806 break; 1807 case NGBE_SUB_DEV_ID_EM_RTL_YT8521S_SFP: 1808 hw->phy.media_type = ngbe_media_type_copper; 1809 hw->mac.type = ngbe_mac_em; 1810 hw->mac.link_type = ngbe_link_fiber; 1811 break; 1812 case NGBE_SUB_DEV_ID_EM_MVL_SFP: 1813 case NGBE_SUB_DEV_ID_EM_YT8521S_SFP: 1814 hw->phy.media_type = ngbe_media_type_fiber; 1815 hw->mac.type = ngbe_mac_em; 1816 hw->mac.link_type = ngbe_link_fiber; 1817 break; 1818 case NGBE_SUB_DEV_ID_EM_MVL_MIX: 1819 hw->phy.media_type = ngbe_media_type_unknown; 1820 hw->mac.type = ngbe_mac_em; 1821 hw->mac.link_type = ngbe_link_type_unknown; 1822 break; 1823 case NGBE_SUB_DEV_ID_EM_VF: 1824 hw->phy.media_type = ngbe_media_type_virtual; 1825 hw->mac.type = ngbe_mac_em_vf; 1826 break; 1827 default: 1828 err = NGBE_ERR_DEVICE_NOT_SUPPORTED; 1829 hw->phy.media_type = ngbe_media_type_unknown; 1830 hw->mac.type = ngbe_mac_unknown; 1831 DEBUGOUT("Unsupported device id: %x", hw->device_id); 1832 break; 1833 } 1834 1835 DEBUGOUT("found mac: %d media: %d, returns: %d", 1836 hw->mac.type, hw->phy.media_type, err); 1837 return err; 1838 } 1839 1840 /** 1841 * ngbe_enable_rx_dma - Enable the Rx DMA unit 1842 * @hw: pointer to hardware structure 1843 * @regval: register value to write to RXCTRL 1844 * 1845 * Enables the Rx DMA unit 1846 **/ 1847 s32 ngbe_enable_rx_dma(struct ngbe_hw *hw, u32 regval) 1848 { 1849 /* 1850 * Workaround silicon errata when enabling the Rx datapath. 1851 * If traffic is incoming before we enable the Rx unit, it could hang 1852 * the Rx DMA unit. Therefore, make sure the security engine is 1853 * completely disabled prior to enabling the Rx unit. 1854 */ 1855 hw->mac.disable_sec_rx_path(hw); 1856 1857 if (regval & NGBE_PBRXCTL_ENA) 1858 ngbe_enable_rx(hw); 1859 else 1860 ngbe_disable_rx(hw); 1861 1862 hw->mac.enable_sec_rx_path(hw); 1863 1864 return 0; 1865 } 1866 1867 /* cmd_addr is used for some special command: 1868 * 1. to be sector address, when implemented erase sector command 1869 * 2. to be flash address when implemented read, write flash address 1870 * 1871 * Return 0 on success, return NGBE_ERR_TIMEOUT on failure. 1872 */ 1873 s32 ngbe_fmgr_cmd_op(struct ngbe_hw *hw, u32 cmd, u32 cmd_addr) 1874 { 1875 u32 cmd_val, i; 1876 1877 cmd_val = NGBE_SPICMD_CMD(cmd) | NGBE_SPICMD_CLK(3) | cmd_addr; 1878 wr32(hw, NGBE_SPICMD, cmd_val); 1879 1880 for (i = 0; i < NGBE_SPI_TIMEOUT; i++) { 1881 if (rd32(hw, NGBE_SPISTAT) & NGBE_SPISTAT_OPDONE) 1882 break; 1883 1884 usec_delay(10); 1885 } 1886 if (i == NGBE_SPI_TIMEOUT) 1887 return NGBE_ERR_TIMEOUT; 1888 1889 return 0; 1890 } 1891 1892 s32 ngbe_flash_read_dword(struct ngbe_hw *hw, u32 addr, u32 *data) 1893 { 1894 s32 status; 1895 1896 status = ngbe_fmgr_cmd_op(hw, 1, addr); 1897 if (status < 0) { 1898 DEBUGOUT("Read flash timeout."); 1899 return status; 1900 } 1901 1902 *data = rd32(hw, NGBE_SPIDAT); 1903 1904 return 0; 1905 } 1906 1907 void ngbe_read_efuse(struct ngbe_hw *hw) 1908 { 1909 u32 efuse[2] = {0, 0}; 1910 u8 lan_id = hw->bus.lan_id; 1911 1912 ngbe_flash_read_dword(hw, 0xfe010 + lan_id * 8, &efuse[0]); 1913 ngbe_flash_read_dword(hw, 0xfe010 + lan_id * 8 + 4, &efuse[1]); 1914 1915 DEBUGOUT("port %d efuse[0] = %08x, efuse[1] = %08x", 1916 lan_id, efuse[0], efuse[1]); 1917 1918 hw->gphy_efuse[0] = efuse[0]; 1919 hw->gphy_efuse[1] = efuse[1]; 1920 } 1921 1922 void ngbe_map_device_id(struct ngbe_hw *hw) 1923 { 1924 u16 oem = hw->sub_system_id & NGBE_OEM_MASK; 1925 1926 hw->is_pf = true; 1927 1928 /* move subsystem_device_id to device_id */ 1929 switch (hw->device_id) { 1930 case NGBE_DEV_ID_EM_WX1860AL_W_VF: 1931 case NGBE_DEV_ID_EM_WX1860A2_VF: 1932 case NGBE_DEV_ID_EM_WX1860A2S_VF: 1933 case NGBE_DEV_ID_EM_WX1860A4_VF: 1934 case NGBE_DEV_ID_EM_WX1860A4S_VF: 1935 case NGBE_DEV_ID_EM_WX1860AL2_VF: 1936 case NGBE_DEV_ID_EM_WX1860AL2S_VF: 1937 case NGBE_DEV_ID_EM_WX1860AL4_VF: 1938 case NGBE_DEV_ID_EM_WX1860AL4S_VF: 1939 case NGBE_DEV_ID_EM_WX1860NCSI_VF: 1940 case NGBE_DEV_ID_EM_WX1860A1_VF: 1941 case NGBE_DEV_ID_EM_WX1860A1L_VF: 1942 hw->device_id = NGBE_DEV_ID_EM_VF; 1943 hw->sub_device_id = NGBE_SUB_DEV_ID_EM_VF; 1944 hw->is_pf = false; 1945 break; 1946 case NGBE_DEV_ID_EM_WX1860AL_W: 1947 case NGBE_DEV_ID_EM_WX1860A2: 1948 case NGBE_DEV_ID_EM_WX1860A2S: 1949 case NGBE_DEV_ID_EM_WX1860A4: 1950 case NGBE_DEV_ID_EM_WX1860A4S: 1951 case NGBE_DEV_ID_EM_WX1860AL2: 1952 case NGBE_DEV_ID_EM_WX1860AL2S: 1953 case NGBE_DEV_ID_EM_WX1860AL4: 1954 case NGBE_DEV_ID_EM_WX1860AL4S: 1955 case NGBE_DEV_ID_EM_WX1860NCSI: 1956 case NGBE_DEV_ID_EM_WX1860A1: 1957 case NGBE_DEV_ID_EM_WX1860A1L: 1958 hw->device_id = NGBE_DEV_ID_EM; 1959 if (oem == NGBE_M88E1512_SFP || oem == NGBE_LY_M88E1512_SFP) 1960 hw->sub_device_id = NGBE_SUB_DEV_ID_EM_MVL_SFP; 1961 else if (oem == NGBE_M88E1512_RJ45 || 1962 (hw->sub_system_id == NGBE_SUB_DEV_ID_EM_M88E1512_RJ45)) 1963 hw->sub_device_id = NGBE_SUB_DEV_ID_EM_MVL_RGMII; 1964 else if (oem == NGBE_M88E1512_MIX) 1965 hw->sub_device_id = NGBE_SUB_DEV_ID_EM_MVL_MIX; 1966 else if (oem == NGBE_YT8521S_SFP || 1967 oem == NGBE_YT8521S_SFP_GPIO || 1968 oem == NGBE_LY_YT8521S_SFP) 1969 hw->sub_device_id = NGBE_SUB_DEV_ID_EM_YT8521S_SFP; 1970 else if (oem == NGBE_INTERNAL_YT8521S_SFP || 1971 oem == NGBE_INTERNAL_YT8521S_SFP_GPIO) 1972 hw->sub_device_id = NGBE_SUB_DEV_ID_EM_RTL_YT8521S_SFP; 1973 else 1974 hw->sub_device_id = NGBE_SUB_DEV_ID_EM_RTL_SGMII; 1975 break; 1976 default: 1977 break; 1978 } 1979 1980 if (oem == NGBE_LY_M88E1512_SFP || oem == NGBE_YT8521S_SFP_GPIO || 1981 oem == NGBE_INTERNAL_YT8521S_SFP_GPIO || 1982 oem == NGBE_LY_YT8521S_SFP) 1983 hw->gpio_ctl = true; 1984 1985 hw->wol_enabled = (hw->sub_system_id & NGBE_WOL_SUP_MASK) ? true : false; 1986 hw->ncsi_enabled = (hw->sub_system_id & NGBE_NCSI_SUP_MASK || 1987 hw->sub_system_id & NGBE_OCP_CARD) ? true : false; 1988 } 1989 1990 /** 1991 * ngbe_init_ops_pf - Inits func ptrs and MAC type 1992 * @hw: pointer to hardware structure 1993 * 1994 * Initialize the function pointers and assign the MAC type. 1995 * Does not touch the hardware. 1996 **/ 1997 s32 ngbe_init_ops_pf(struct ngbe_hw *hw) 1998 { 1999 struct ngbe_bus_info *bus = &hw->bus; 2000 struct ngbe_mac_info *mac = &hw->mac; 2001 struct ngbe_phy_info *phy = &hw->phy; 2002 struct ngbe_rom_info *rom = &hw->rom; 2003 struct ngbe_mbx_info *mbx = &hw->mbx; 2004 2005 /* BUS */ 2006 bus->set_lan_id = ngbe_set_lan_id_multi_port; 2007 2008 /* PHY */ 2009 phy->identify = ngbe_identify_phy; 2010 phy->read_reg = ngbe_read_phy_reg; 2011 phy->write_reg = ngbe_write_phy_reg; 2012 phy->read_reg_unlocked = ngbe_read_phy_reg_mdi; 2013 phy->write_reg_unlocked = ngbe_write_phy_reg_mdi; 2014 phy->reset_hw = ngbe_reset_phy; 2015 phy->led_oem_chk = ngbe_phy_led_oem_chk; 2016 2017 /* MAC */ 2018 mac->init_hw = ngbe_init_hw; 2019 mac->reset_hw = ngbe_reset_hw_em; 2020 mac->start_hw = ngbe_start_hw; 2021 mac->clear_hw_cntrs = ngbe_clear_hw_cntrs; 2022 mac->enable_rx_dma = ngbe_enable_rx_dma; 2023 mac->get_mac_addr = ngbe_get_mac_addr; 2024 mac->stop_hw = ngbe_stop_hw; 2025 mac->acquire_swfw_sync = ngbe_acquire_swfw_sync; 2026 mac->release_swfw_sync = ngbe_release_swfw_sync; 2027 2028 mac->disable_sec_rx_path = ngbe_disable_sec_rx_path; 2029 mac->enable_sec_rx_path = ngbe_enable_sec_rx_path; 2030 2031 /* LEDs */ 2032 mac->led_on = ngbe_led_on; 2033 mac->led_off = ngbe_led_off; 2034 2035 /* RAR, VLAN, Multicast */ 2036 mac->set_rar = ngbe_set_rar; 2037 mac->clear_rar = ngbe_clear_rar; 2038 mac->init_rx_addrs = ngbe_init_rx_addrs; 2039 mac->update_mc_addr_list = ngbe_update_mc_addr_list; 2040 mac->set_vmdq = ngbe_set_vmdq; 2041 mac->clear_vmdq = ngbe_clear_vmdq; 2042 mac->set_vfta = ngbe_set_vfta; 2043 mac->set_vlvf = ngbe_set_vlvf; 2044 mac->clear_vfta = ngbe_clear_vfta; 2045 mac->set_mac_anti_spoofing = ngbe_set_mac_anti_spoofing; 2046 mac->set_vlan_anti_spoofing = ngbe_set_vlan_anti_spoofing; 2047 2048 /* Flow Control */ 2049 mac->fc_enable = ngbe_fc_enable; 2050 mac->fc_autoneg = ngbe_fc_autoneg; 2051 mac->setup_fc = ngbe_setup_fc_em; 2052 2053 /* Link */ 2054 mac->get_link_capabilities = ngbe_get_link_capabilities_em; 2055 mac->check_link = ngbe_check_mac_link_em; 2056 mac->setup_link = ngbe_setup_mac_link_em; 2057 2058 mac->setup_pba = ngbe_set_pba; 2059 2060 /* Manageability interface */ 2061 mac->init_thermal_sensor_thresh = ngbe_init_thermal_sensor_thresh; 2062 mac->check_overtemp = ngbe_mac_check_overtemp; 2063 2064 mbx->init_params = ngbe_init_mbx_params_pf; 2065 mbx->read = ngbe_read_mbx_pf; 2066 mbx->write = ngbe_write_mbx_pf; 2067 mbx->check_for_msg = ngbe_check_for_msg_pf; 2068 mbx->check_for_ack = ngbe_check_for_ack_pf; 2069 mbx->check_for_rst = ngbe_check_for_rst_pf; 2070 2071 /* EEPROM */ 2072 rom->init_params = ngbe_init_eeprom_params; 2073 rom->readw_buffer = ngbe_ee_readw_buffer; 2074 rom->read32 = ngbe_ee_read32; 2075 rom->writew_buffer = ngbe_ee_writew_buffer; 2076 rom->validate_checksum = ngbe_validate_eeprom_checksum_em; 2077 2078 mac->mcft_size = NGBE_EM_MC_TBL_SIZE; 2079 mac->vft_size = NGBE_EM_VFT_TBL_SIZE; 2080 mac->num_rar_entries = NGBE_EM_RAR_ENTRIES; 2081 mac->rx_pb_size = NGBE_EM_RX_PB_SIZE; 2082 mac->max_rx_queues = NGBE_EM_MAX_RX_QUEUES; 2083 mac->max_tx_queues = NGBE_EM_MAX_TX_QUEUES; 2084 2085 mac->default_speeds = NGBE_LINK_SPEED_10M_FULL | 2086 NGBE_LINK_SPEED_100M_FULL | 2087 NGBE_LINK_SPEED_1GB_FULL; 2088 2089 return 0; 2090 } 2091 2092 /** 2093 * ngbe_init_shared_code - Initialize the shared code 2094 * @hw: pointer to hardware structure 2095 * 2096 * This will assign function pointers and assign the MAC type and PHY code. 2097 * Does not touch the hardware. This function must be called prior to any 2098 * other function in the shared code. The ngbe_hw structure should be 2099 * memset to 0 prior to calling this function. The following fields in 2100 * hw structure should be filled in prior to calling this function: 2101 * hw_addr, back, device_id, vendor_id, subsystem_device_id 2102 **/ 2103 s32 ngbe_init_shared_code(struct ngbe_hw *hw) 2104 { 2105 s32 status = 0; 2106 2107 /* 2108 * Set the mac type 2109 */ 2110 ngbe_set_mac_type(hw); 2111 2112 ngbe_init_ops_dummy(hw); 2113 switch (hw->mac.type) { 2114 case ngbe_mac_em: 2115 ngbe_init_ops_pf(hw); 2116 break; 2117 case ngbe_mac_em_vf: 2118 ngbe_init_ops_vf(hw); 2119 break; 2120 default: 2121 status = NGBE_ERR_DEVICE_NOT_SUPPORTED; 2122 break; 2123 } 2124 hw->mac.max_link_up_time = NGBE_LINK_UP_TIME; 2125 2126 hw->bus.set_lan_id(hw); 2127 2128 return status; 2129 } 2130 2131 void ngbe_set_ncsi_status(struct ngbe_hw *hw) 2132 { 2133 u16 ncsi_pin = 0; 2134 s32 err = 0; 2135 2136 /* need to check ncsi pin status for oem ncsi card */ 2137 if (hw->ncsi_enabled || hw->wol_enabled) 2138 return; 2139 2140 err = hw->rom.readw_buffer(hw, FW_READ_SHADOW_RAM_GPIO, 1, &ncsi_pin); 2141 if (err) { 2142 DEBUGOUT("get ncsi pin status failed"); 2143 return; 2144 } 2145 2146 if (ncsi_pin == 1) { 2147 hw->ncsi_enabled = true; 2148 hw->wol_enabled = true; 2149 } 2150 } 2151