xref: /dpdk/drivers/net/mvpp2/mrvl_ethdev.h (revision 200bc52e5aa0d72e70464c9cd22b55cf536ed13c)
1 /* SPDX-License-Identifier: BSD-3-Clause
2  * Copyright(c) 2017 Marvell International Ltd.
3  * Copyright(c) 2017 Semihalf.
4  * All rights reserved.
5  */
6 
7 #ifndef _MRVL_ETHDEV_H_
8 #define _MRVL_ETHDEV_H_
9 
10 #include <rte_spinlock.h>
11 #include <rte_flow_driver.h>
12 #include <rte_mtr_driver.h>
13 #include <rte_tm_driver.h>
14 
15 /*
16  * container_of is defined by both DPDK and MUSDK,
17  * we'll declare only one version.
18  *
19  * Note that it is not used in this PMD anyway.
20  */
21 #ifdef container_of
22 #undef container_of
23 #endif
24 
25 #include <env/mv_autogen_comp_flags.h>
26 #include <drivers/mv_pp2.h>
27 #include <drivers/mv_pp2_bpool.h>
28 #include <drivers/mv_pp2_cls.h>
29 #include <drivers/mv_pp2_hif.h>
30 #include <drivers/mv_pp2_ppio.h>
31 #include "env/mv_common.h" /* for BIT() */
32 
33 /** Maximum number of rx queues per port */
34 #define MRVL_PP2_RXQ_MAX 32
35 
36 /** Maximum number of tx queues per port */
37 #define MRVL_PP2_TXQ_MAX 8
38 
39 /** Minimum number of descriptors in tx queue */
40 #define MRVL_PP2_TXD_MIN 16
41 
42 /** Maximum number of descriptors in tx queue */
43 #define MRVL_PP2_TXD_MAX 2048
44 
45 /** Tx queue descriptors alignment */
46 #define MRVL_PP2_TXD_ALIGN 16
47 
48 /** Minimum number of descriptors in rx queue */
49 #define MRVL_PP2_RXD_MIN 16
50 
51 /** Maximum number of descriptors in rx queue */
52 #define MRVL_PP2_RXD_MAX 2048
53 
54 /** Rx queue descriptors alignment */
55 #define MRVL_PP2_RXD_ALIGN 16
56 
57 /** Maximum number of descriptors in tx aggregated queue */
58 #define MRVL_PP2_AGGR_TXQD_MAX 2048
59 
60 /** Maximum number of Traffic Classes. */
61 #define MRVL_PP2_TC_MAX 8
62 
63 /** Packet offset inside RX buffer. */
64 #define MRVL_PKT_OFFS 64
65 
66 /** Maximum number of descriptors in shadow queue. Must be power of 2 */
67 #define MRVL_PP2_TX_SHADOWQ_SIZE MRVL_PP2_TXD_MAX
68 
69 /** Shadow queue size mask (since shadow queue size is power of 2) */
70 #define MRVL_PP2_TX_SHADOWQ_MASK (MRVL_PP2_TX_SHADOWQ_SIZE - 1)
71 
72 /** Minimum number of sent buffers to release from shadow queue to BM */
73 #define MRVL_PP2_BUF_RELEASE_BURST_SIZE	64
74 
75 #define MRVL_PP2_VLAN_TAG_LEN	4
76 #define MRVL_PP2_ETH_HDRS_LEN	(RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN + \
77 				(2 * MRVL_PP2_VLAN_TAG_LEN))
78 #define MRVL_PP2_HDRS_LEN		(MV_MH_SIZE + MRVL_PP2_ETH_HDRS_LEN)
79 #define MRVL_PP2_MTU_TO_MRU(mtu)	((mtu) + MRVL_PP2_HDRS_LEN)
80 #define MRVL_PP2_MRU_TO_MTU(mru)	((mru) - MRVL_PP2_HDRS_LEN)
81 
82 /** Maximum length of a match string */
83 #define MRVL_MATCH_LEN 16
84 
85 /** Parsed fields in processed rte_flow_item. */
86 enum mrvl_parsed_fields {
87 	/* eth flags */
88 	F_DMAC =         BIT(0),
89 	F_SMAC =         BIT(1),
90 	F_TYPE =         BIT(2),
91 	/* vlan flags */
92 	F_VLAN_PRI =     BIT(3),
93 	F_VLAN_ID =      BIT(4),
94 	F_VLAN_TCI =     BIT(5), /* not supported by MUSDK yet */
95 	/* ip4 flags */
96 	F_IP4_TOS =      BIT(6),
97 	F_IP4_SIP =      BIT(7),
98 	F_IP4_DIP =      BIT(8),
99 	F_IP4_PROTO =    BIT(9),
100 	/* ip6 flags */
101 	F_IP6_TC =       BIT(10), /* not supported by MUSDK yet */
102 	F_IP6_SIP =      BIT(11),
103 	F_IP6_DIP =      BIT(12),
104 	F_IP6_FLOW =     BIT(13),
105 	F_IP6_NEXT_HDR = BIT(14),
106 	/* tcp flags */
107 	F_TCP_SPORT =    BIT(15),
108 	F_TCP_DPORT =    BIT(16),
109 	/* udp flags */
110 	F_UDP_SPORT =    BIT(17),
111 	F_UDP_DPORT =    BIT(18),
112 };
113 
114 /** PMD-specific definition of a flow rule handle. */
115 struct mrvl_mtr;
116 struct rte_flow {
117 	LIST_ENTRY(rte_flow) next;
118 	struct mrvl_mtr *mtr;
119 
120 	enum mrvl_parsed_fields pattern;
121 
122 	struct pp2_cls_tbl_rule rule;
123 	struct pp2_cls_cos_desc cos;
124 	struct pp2_cls_tbl_action action;
125 };
126 
127 struct mrvl_mtr_profile {
128 	LIST_ENTRY(mrvl_mtr_profile) next;
129 	uint32_t profile_id;
130 	int refcnt;
131 	struct rte_mtr_meter_profile profile;
132 };
133 
134 struct mrvl_mtr {
135 	LIST_ENTRY(mrvl_mtr) next;
136 	uint32_t mtr_id;
137 	int refcnt;
138 	int shared;
139 	int enabled;
140 	int plcr_bit;
141 	struct mrvl_mtr_profile *profile;
142 	struct pp2_cls_plcr *plcr;
143 };
144 
145 struct mrvl_tm_shaper_profile {
146 	LIST_ENTRY(mrvl_tm_shaper_profile) next;
147 	uint32_t id;
148 	int refcnt;
149 	struct rte_tm_shaper_params params;
150 };
151 
152 enum {
153 	MRVL_NODE_PORT,
154 	MRVL_NODE_QUEUE,
155 };
156 
157 struct mrvl_tm_node {
158 	LIST_ENTRY(mrvl_tm_node) next;
159 	uint32_t id;
160 	uint32_t type;
161 	int refcnt;
162 	struct mrvl_tm_node *parent;
163 	struct mrvl_tm_shaper_profile *profile;
164 	uint8_t weight;
165 	uint64_t stats_mask;
166 };
167 
168 struct mrvl_priv {
169 	/* Hot fields, used in fast path. */
170 	struct pp2_bpool *bpool;  /**< BPool pointer */
171 	struct pp2_ppio	*ppio;    /**< Port handler pointer */
172 	rte_spinlock_t lock;	  /**< Spinlock for checking bpool status */
173 	uint16_t bpool_max_size;  /**< BPool maximum size */
174 	uint16_t bpool_min_size;  /**< BPool minimum size  */
175 	uint16_t bpool_init_size; /**< Configured BPool size  */
176 
177 	/** Mapping for DPDK rx queue->(TC, MRVL relative inq) */
178 	struct {
179 		uint8_t tc;  /**< Traffic Class */
180 		uint8_t inq; /**< Relative in-queue number */
181 	} rxq_map[MRVL_PP2_RXQ_MAX] __rte_cache_aligned;
182 
183 	/* Configuration data, used sporadically. */
184 	uint8_t pp_id;
185 	uint8_t ppio_id;
186 	uint8_t bpool_bit;
187 	uint8_t rss_hf_tcp;
188 	uint8_t uc_mc_flushed;
189 	uint8_t vlan_flushed;
190 	uint8_t isolated;
191 	uint8_t multiseg;
192 
193 	struct pp2_ppio_params ppio_params;
194 	struct pp2_cls_qos_tbl_params qos_tbl_params;
195 	struct pp2_cls_tbl *qos_tbl;
196 	uint16_t nb_rx_queues;
197 
198 	struct pp2_cls_tbl_params cls_tbl_params;
199 	struct pp2_cls_tbl *cls_tbl;
200 	uint32_t cls_tbl_pattern;
201 	LIST_HEAD(mrvl_flows, rte_flow) flows;
202 
203 	struct pp2_cls_plcr *default_policer;
204 
205 	LIST_HEAD(profiles, mrvl_mtr_profile) profiles;
206 	LIST_HEAD(mtrs, mrvl_mtr) mtrs;
207 	uint32_t used_plcrs;
208 
209 	LIST_HEAD(shaper_profiles, mrvl_tm_shaper_profile) shaper_profiles;
210 	LIST_HEAD(nodes, mrvl_tm_node) nodes;
211 	uint64_t rate_max;
212 };
213 
214 /** Flow operations forward declaration. */
215 extern const struct rte_flow_ops mrvl_flow_ops;
216 
217 /** Meter operations forward declaration. */
218 extern const struct rte_mtr_ops mrvl_mtr_ops;
219 
220 /** Traffic manager operations forward declaration. */
221 extern const struct rte_tm_ops mrvl_tm_ops;
222 
223 /** Current log type. */
224 extern int mrvl_logtype;
225 
226 #define MRVL_LOG(level, fmt, args...) \
227 	rte_log(RTE_LOG_ ## level, mrvl_logtype, "%s(): " fmt "\n", \
228 		__func__, ##args)
229 
230 #endif /* _MRVL_ETHDEV_H_ */
231