1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2020 Mellanox Technologies, Ltd 3 */ 4 #include <fcntl.h> 5 #include <stdint.h> 6 7 #include <rte_ether.h> 8 #include <ethdev_driver.h> 9 #include <rte_interrupts.h> 10 #include <rte_alarm.h> 11 #include <rte_malloc.h> 12 #include <rte_cycles.h> 13 #include <rte_eal_paging.h> 14 15 #include <mlx5_malloc.h> 16 #include <mlx5_common_devx.h> 17 18 #include "mlx5.h" 19 #include "mlx5_rx.h" 20 #include "mlx5_tx.h" 21 #include "mlx5_common_os.h" 22 23 static_assert(sizeof(struct mlx5_cqe_ts) == sizeof(rte_int128_t), 24 "Wrong timestamp CQE part size"); 25 26 static const char * const mlx5_txpp_stat_names[] = { 27 "tx_pp_missed_interrupt_errors", /* Missed service interrupt. */ 28 "tx_pp_rearm_queue_errors", /* Rearm Queue errors. */ 29 "tx_pp_clock_queue_errors", /* Clock Queue errors. */ 30 "tx_pp_timestamp_past_errors", /* Timestamp in the past. */ 31 "tx_pp_timestamp_future_errors", /* Timestamp in the distant future. */ 32 "tx_pp_jitter", /* Timestamp jitter (one Clock Queue completion). */ 33 "tx_pp_wander", /* Timestamp wander (half of Clock Queue CQEs). */ 34 "tx_pp_sync_lost", /* Scheduling synchronization lost. */ 35 }; 36 37 /* Destroy Event Queue Notification Channel. */ 38 static void 39 mlx5_txpp_destroy_event_channel(struct mlx5_dev_ctx_shared *sh) 40 { 41 if (sh->txpp.echan) { 42 mlx5_os_devx_destroy_event_channel(sh->txpp.echan); 43 sh->txpp.echan = NULL; 44 } 45 } 46 47 /* Create Event Queue Notification Channel. */ 48 static int 49 mlx5_txpp_create_event_channel(struct mlx5_dev_ctx_shared *sh) 50 { 51 MLX5_ASSERT(!sh->txpp.echan); 52 sh->txpp.echan = mlx5_os_devx_create_event_channel(sh->ctx, 53 MLX5DV_DEVX_CREATE_EVENT_CHANNEL_FLAGS_OMIT_EV_DATA); 54 if (!sh->txpp.echan) { 55 rte_errno = errno; 56 DRV_LOG(ERR, "Failed to create event channel %d.", rte_errno); 57 return -rte_errno; 58 } 59 return 0; 60 } 61 62 static void 63 mlx5_txpp_free_pp_index(struct mlx5_dev_ctx_shared *sh) 64 { 65 #ifdef HAVE_MLX5DV_PP_ALLOC 66 if (sh->txpp.pp) { 67 mlx5_glue->dv_free_pp(sh->txpp.pp); 68 sh->txpp.pp = NULL; 69 sh->txpp.pp_id = 0; 70 } 71 #else 72 RTE_SET_USED(sh); 73 DRV_LOG(ERR, "Freeing pacing index is not supported."); 74 #endif 75 } 76 77 /* Allocate Packet Pacing index from kernel via mlx5dv call. */ 78 static int 79 mlx5_txpp_alloc_pp_index(struct mlx5_dev_ctx_shared *sh) 80 { 81 #ifdef HAVE_MLX5DV_PP_ALLOC 82 uint32_t pp[MLX5_ST_SZ_DW(set_pp_rate_limit_context)]; 83 uint64_t rate; 84 85 MLX5_ASSERT(!sh->txpp.pp); 86 memset(&pp, 0, sizeof(pp)); 87 rate = NS_PER_S / sh->txpp.tick; 88 if (rate * sh->txpp.tick != NS_PER_S) 89 DRV_LOG(WARNING, "Packet pacing frequency is not precise."); 90 if (sh->txpp.test) { 91 uint32_t len; 92 93 len = RTE_MAX(MLX5_TXPP_TEST_PKT_SIZE, 94 (size_t)RTE_ETHER_MIN_LEN); 95 MLX5_SET(set_pp_rate_limit_context, &pp, 96 burst_upper_bound, len); 97 MLX5_SET(set_pp_rate_limit_context, &pp, 98 typical_packet_size, len); 99 /* Convert packets per second into kilobits. */ 100 rate = (rate * len) / (1000ul / CHAR_BIT); 101 DRV_LOG(INFO, "Packet pacing rate set to %" PRIu64, rate); 102 } 103 MLX5_SET(set_pp_rate_limit_context, &pp, rate_limit, rate); 104 MLX5_SET(set_pp_rate_limit_context, &pp, rate_mode, 105 sh->txpp.test ? MLX5_DATA_RATE : MLX5_WQE_RATE); 106 sh->txpp.pp = mlx5_glue->dv_alloc_pp 107 (sh->ctx, sizeof(pp), &pp, 108 MLX5DV_PP_ALLOC_FLAGS_DEDICATED_INDEX); 109 if (sh->txpp.pp == NULL) { 110 DRV_LOG(ERR, "Failed to allocate packet pacing index."); 111 rte_errno = errno; 112 return -errno; 113 } 114 if (!((struct mlx5dv_pp *)sh->txpp.pp)->index) { 115 DRV_LOG(ERR, "Zero packet pacing index allocated."); 116 mlx5_txpp_free_pp_index(sh); 117 rte_errno = ENOTSUP; 118 return -ENOTSUP; 119 } 120 sh->txpp.pp_id = ((struct mlx5dv_pp *)(sh->txpp.pp))->index; 121 return 0; 122 #else 123 RTE_SET_USED(sh); 124 DRV_LOG(ERR, "Allocating pacing index is not supported."); 125 rte_errno = ENOTSUP; 126 return -ENOTSUP; 127 #endif 128 } 129 130 static void 131 mlx5_txpp_destroy_send_queue(struct mlx5_txpp_wq *wq) 132 { 133 mlx5_devx_sq_destroy(&wq->sq_obj); 134 mlx5_devx_cq_destroy(&wq->cq_obj); 135 memset(wq, 0, sizeof(*wq)); 136 } 137 138 static void 139 mlx5_txpp_destroy_rearm_queue(struct mlx5_dev_ctx_shared *sh) 140 { 141 struct mlx5_txpp_wq *wq = &sh->txpp.rearm_queue; 142 143 mlx5_txpp_destroy_send_queue(wq); 144 } 145 146 static void 147 mlx5_txpp_destroy_clock_queue(struct mlx5_dev_ctx_shared *sh) 148 { 149 struct mlx5_txpp_wq *wq = &sh->txpp.clock_queue; 150 151 mlx5_txpp_destroy_send_queue(wq); 152 if (sh->txpp.tsa) { 153 mlx5_free(sh->txpp.tsa); 154 sh->txpp.tsa = NULL; 155 } 156 } 157 158 static void 159 mlx5_txpp_doorbell_rearm_queue(struct mlx5_dev_ctx_shared *sh, uint16_t ci) 160 { 161 struct mlx5_txpp_wq *wq = &sh->txpp.rearm_queue; 162 struct mlx5_wqe *wqe = (struct mlx5_wqe *)(uintptr_t)wq->sq_obj.wqes; 163 union { 164 uint32_t w32[2]; 165 uint64_t w64; 166 } cs; 167 void *reg_addr; 168 169 wq->sq_ci = ci + 1; 170 cs.w32[0] = rte_cpu_to_be_32(rte_be_to_cpu_32 171 (wqe[ci & (wq->sq_size - 1)].ctrl[0]) | (ci - 1) << 8); 172 cs.w32[1] = wqe[ci & (wq->sq_size - 1)].ctrl[1]; 173 /* Update SQ doorbell record with new SQ ci. */ 174 rte_compiler_barrier(); 175 *wq->sq_obj.db_rec = rte_cpu_to_be_32(wq->sq_ci); 176 /* Make sure the doorbell record is updated. */ 177 rte_wmb(); 178 /* Write to doorbel register to start processing. */ 179 reg_addr = mlx5_os_get_devx_uar_reg_addr(sh->tx_uar); 180 __mlx5_uar_write64_relaxed(cs.w64, reg_addr, NULL); 181 rte_wmb(); 182 } 183 184 static void 185 mlx5_txpp_fill_wqe_rearm_queue(struct mlx5_dev_ctx_shared *sh) 186 { 187 struct mlx5_txpp_wq *wq = &sh->txpp.rearm_queue; 188 struct mlx5_wqe *wqe = (struct mlx5_wqe *)(uintptr_t)wq->sq_obj.wqes; 189 uint32_t i; 190 191 for (i = 0; i < wq->sq_size; i += 2) { 192 struct mlx5_wqe_cseg *cs; 193 struct mlx5_wqe_qseg *qs; 194 uint32_t index; 195 196 /* Build SEND_EN request with slave WQE index. */ 197 cs = &wqe[i + 0].cseg; 198 cs->opcode = RTE_BE32(MLX5_OPCODE_SEND_EN | 0); 199 cs->sq_ds = rte_cpu_to_be_32((wq->sq_obj.sq->id << 8) | 2); 200 cs->flags = RTE_BE32(MLX5_COMP_ALWAYS << 201 MLX5_COMP_MODE_OFFSET); 202 cs->misc = RTE_BE32(0); 203 qs = RTE_PTR_ADD(cs, sizeof(struct mlx5_wqe_cseg)); 204 index = (i * MLX5_TXPP_REARM / 2 + MLX5_TXPP_REARM) & 205 ((1 << MLX5_WQ_INDEX_WIDTH) - 1); 206 qs->max_index = rte_cpu_to_be_32(index); 207 qs->qpn_cqn = 208 rte_cpu_to_be_32(sh->txpp.clock_queue.sq_obj.sq->id); 209 /* Build WAIT request with slave CQE index. */ 210 cs = &wqe[i + 1].cseg; 211 cs->opcode = RTE_BE32(MLX5_OPCODE_WAIT | 0); 212 cs->sq_ds = rte_cpu_to_be_32((wq->sq_obj.sq->id << 8) | 2); 213 cs->flags = RTE_BE32(MLX5_COMP_ONLY_ERR << 214 MLX5_COMP_MODE_OFFSET); 215 cs->misc = RTE_BE32(0); 216 qs = RTE_PTR_ADD(cs, sizeof(struct mlx5_wqe_cseg)); 217 index = (i * MLX5_TXPP_REARM / 2 + MLX5_TXPP_REARM / 2) & 218 ((1 << MLX5_CQ_INDEX_WIDTH) - 1); 219 qs->max_index = rte_cpu_to_be_32(index); 220 qs->qpn_cqn = 221 rte_cpu_to_be_32(sh->txpp.clock_queue.cq_obj.cq->id); 222 } 223 } 224 225 /* Creates the Rearm Queue to fire the requests to Clock Queue in realtime. */ 226 static int 227 mlx5_txpp_create_rearm_queue(struct mlx5_dev_ctx_shared *sh) 228 { 229 struct mlx5_devx_create_sq_attr sq_attr = { 230 .cd_master = 1, 231 .state = MLX5_SQC_STATE_RST, 232 .tis_lst_sz = 1, 233 .tis_num = sh->tis->id, 234 .wq_attr = (struct mlx5_devx_wq_attr){ 235 .pd = sh->pdn, 236 .uar_page = mlx5_os_get_devx_uar_page_id(sh->tx_uar), 237 }, 238 .ts_format = mlx5_ts_format_conv(sh->sq_ts_format), 239 }; 240 struct mlx5_devx_modify_sq_attr msq_attr = { 0 }; 241 struct mlx5_devx_cq_attr cq_attr = { 242 .uar_page_id = mlx5_os_get_devx_uar_page_id(sh->tx_uar), 243 }; 244 struct mlx5_txpp_wq *wq = &sh->txpp.rearm_queue; 245 int ret; 246 247 /* Create completion queue object for Rearm Queue. */ 248 ret = mlx5_devx_cq_create(sh->ctx, &wq->cq_obj, 249 log2above(MLX5_TXPP_REARM_CQ_SIZE), &cq_attr, 250 sh->numa_node); 251 if (ret) { 252 DRV_LOG(ERR, "Failed to create CQ for Rearm Queue."); 253 return ret; 254 } 255 wq->cq_ci = 0; 256 wq->arm_sn = 0; 257 wq->sq_size = MLX5_TXPP_REARM_SQ_SIZE; 258 MLX5_ASSERT(wq->sq_size == (1 << log2above(wq->sq_size))); 259 /* Create send queue object for Rearm Queue. */ 260 sq_attr.cqn = wq->cq_obj.cq->id; 261 /* There should be no WQE leftovers in the cyclic queue. */ 262 ret = mlx5_devx_sq_create(sh->ctx, &wq->sq_obj, 263 log2above(MLX5_TXPP_REARM_SQ_SIZE), &sq_attr, 264 sh->numa_node); 265 if (ret) { 266 rte_errno = errno; 267 DRV_LOG(ERR, "Failed to create SQ for Rearm Queue."); 268 goto error; 269 } 270 /* Build the WQEs in the Send Queue before goto Ready state. */ 271 mlx5_txpp_fill_wqe_rearm_queue(sh); 272 /* Change queue state to ready. */ 273 msq_attr.sq_state = MLX5_SQC_STATE_RST; 274 msq_attr.state = MLX5_SQC_STATE_RDY; 275 ret = mlx5_devx_cmd_modify_sq(wq->sq_obj.sq, &msq_attr); 276 if (ret) { 277 DRV_LOG(ERR, "Failed to set SQ ready state Rearm Queue."); 278 goto error; 279 } 280 return 0; 281 error: 282 ret = -rte_errno; 283 mlx5_txpp_destroy_rearm_queue(sh); 284 rte_errno = -ret; 285 return ret; 286 } 287 288 static void 289 mlx5_txpp_fill_wqe_clock_queue(struct mlx5_dev_ctx_shared *sh) 290 { 291 struct mlx5_txpp_wq *wq = &sh->txpp.clock_queue; 292 struct mlx5_wqe *wqe = (struct mlx5_wqe *)(uintptr_t)wq->sq_obj.wqes; 293 struct mlx5_wqe_cseg *cs = &wqe->cseg; 294 uint32_t wqe_size, opcode, i; 295 uint8_t *dst; 296 297 /* For test purposes fill the WQ with SEND inline packet. */ 298 if (sh->txpp.test) { 299 wqe_size = RTE_ALIGN(MLX5_TXPP_TEST_PKT_SIZE + 300 MLX5_WQE_CSEG_SIZE + 301 2 * MLX5_WQE_ESEG_SIZE - 302 MLX5_ESEG_MIN_INLINE_SIZE, 303 MLX5_WSEG_SIZE); 304 opcode = MLX5_OPCODE_SEND; 305 } else { 306 wqe_size = MLX5_WSEG_SIZE; 307 opcode = MLX5_OPCODE_NOP; 308 } 309 cs->opcode = rte_cpu_to_be_32(opcode | 0); /* Index is ignored. */ 310 cs->sq_ds = rte_cpu_to_be_32((wq->sq_obj.sq->id << 8) | 311 (wqe_size / MLX5_WSEG_SIZE)); 312 cs->flags = RTE_BE32(MLX5_COMP_ALWAYS << MLX5_COMP_MODE_OFFSET); 313 cs->misc = RTE_BE32(0); 314 wqe_size = RTE_ALIGN(wqe_size, MLX5_WQE_SIZE); 315 if (sh->txpp.test) { 316 struct mlx5_wqe_eseg *es = &wqe->eseg; 317 struct rte_ether_hdr *eth_hdr; 318 struct rte_ipv4_hdr *ip_hdr; 319 struct rte_udp_hdr *udp_hdr; 320 321 /* Build the inline test packet pattern. */ 322 MLX5_ASSERT(wqe_size <= MLX5_WQE_SIZE_MAX); 323 MLX5_ASSERT(MLX5_TXPP_TEST_PKT_SIZE >= 324 (sizeof(struct rte_ether_hdr) + 325 sizeof(struct rte_ipv4_hdr))); 326 es->flags = 0; 327 es->cs_flags = MLX5_ETH_WQE_L3_CSUM | MLX5_ETH_WQE_L4_CSUM; 328 es->swp_offs = 0; 329 es->metadata = 0; 330 es->swp_flags = 0; 331 es->mss = 0; 332 es->inline_hdr_sz = RTE_BE16(MLX5_TXPP_TEST_PKT_SIZE); 333 /* Build test packet L2 header (Ethernet). */ 334 dst = (uint8_t *)&es->inline_data; 335 eth_hdr = (struct rte_ether_hdr *)dst; 336 rte_eth_random_addr(ð_hdr->dst_addr.addr_bytes[0]); 337 rte_eth_random_addr(ð_hdr->src_addr.addr_bytes[0]); 338 eth_hdr->ether_type = rte_cpu_to_be_16(RTE_ETHER_TYPE_IPV4); 339 /* Build test packet L3 header (IP v4). */ 340 dst += sizeof(struct rte_ether_hdr); 341 ip_hdr = (struct rte_ipv4_hdr *)dst; 342 ip_hdr->version_ihl = RTE_IPV4_VHL_DEF; 343 ip_hdr->type_of_service = 0; 344 ip_hdr->fragment_offset = 0; 345 ip_hdr->time_to_live = 64; 346 ip_hdr->next_proto_id = IPPROTO_UDP; 347 ip_hdr->packet_id = 0; 348 ip_hdr->total_length = RTE_BE16(MLX5_TXPP_TEST_PKT_SIZE - 349 sizeof(struct rte_ether_hdr)); 350 /* use RFC5735 / RFC2544 reserved network test addresses */ 351 ip_hdr->src_addr = RTE_BE32((198U << 24) | (18 << 16) | 352 (0 << 8) | 1); 353 ip_hdr->dst_addr = RTE_BE32((198U << 24) | (18 << 16) | 354 (0 << 8) | 2); 355 if (MLX5_TXPP_TEST_PKT_SIZE < 356 (sizeof(struct rte_ether_hdr) + 357 sizeof(struct rte_ipv4_hdr) + 358 sizeof(struct rte_udp_hdr))) 359 goto wcopy; 360 /* Build test packet L4 header (UDP). */ 361 dst += sizeof(struct rte_ipv4_hdr); 362 udp_hdr = (struct rte_udp_hdr *)dst; 363 udp_hdr->src_port = RTE_BE16(9); /* RFC863 Discard. */ 364 udp_hdr->dst_port = RTE_BE16(9); 365 udp_hdr->dgram_len = RTE_BE16(MLX5_TXPP_TEST_PKT_SIZE - 366 sizeof(struct rte_ether_hdr) - 367 sizeof(struct rte_ipv4_hdr)); 368 udp_hdr->dgram_cksum = 0; 369 /* Fill the test packet data. */ 370 dst += sizeof(struct rte_udp_hdr); 371 for (i = sizeof(struct rte_ether_hdr) + 372 sizeof(struct rte_ipv4_hdr) + 373 sizeof(struct rte_udp_hdr); 374 i < MLX5_TXPP_TEST_PKT_SIZE; i++) 375 *dst++ = (uint8_t)(i & 0xFF); 376 } 377 wcopy: 378 /* Duplicate the pattern to the next WQEs. */ 379 dst = (uint8_t *)(uintptr_t)wq->sq_obj.umem_buf; 380 for (i = 1; i < MLX5_TXPP_CLKQ_SIZE; i++) { 381 dst += wqe_size; 382 rte_memcpy(dst, (void *)(uintptr_t)wq->sq_obj.umem_buf, 383 wqe_size); 384 } 385 } 386 387 /* Creates the Clock Queue for packet pacing, returns zero on success. */ 388 static int 389 mlx5_txpp_create_clock_queue(struct mlx5_dev_ctx_shared *sh) 390 { 391 struct mlx5_devx_create_sq_attr sq_attr = { 0 }; 392 struct mlx5_devx_modify_sq_attr msq_attr = { 0 }; 393 struct mlx5_devx_cq_attr cq_attr = { 394 .use_first_only = 1, 395 .overrun_ignore = 1, 396 .uar_page_id = mlx5_os_get_devx_uar_page_id(sh->tx_uar), 397 }; 398 struct mlx5_txpp_wq *wq = &sh->txpp.clock_queue; 399 int ret; 400 401 sh->txpp.tsa = mlx5_malloc(MLX5_MEM_RTE | MLX5_MEM_ZERO, 402 MLX5_TXPP_REARM_SQ_SIZE * 403 sizeof(struct mlx5_txpp_ts), 404 0, sh->numa_node); 405 if (!sh->txpp.tsa) { 406 DRV_LOG(ERR, "Failed to allocate memory for CQ stats."); 407 return -ENOMEM; 408 } 409 sh->txpp.ts_p = 0; 410 sh->txpp.ts_n = 0; 411 /* Create completion queue object for Clock Queue. */ 412 ret = mlx5_devx_cq_create(sh->ctx, &wq->cq_obj, 413 log2above(MLX5_TXPP_CLKQ_SIZE), &cq_attr, 414 sh->numa_node); 415 if (ret) { 416 DRV_LOG(ERR, "Failed to create CQ for Clock Queue."); 417 goto error; 418 } 419 wq->cq_ci = 0; 420 /* Allocate memory buffer for Send Queue WQEs. */ 421 if (sh->txpp.test) { 422 wq->sq_size = RTE_ALIGN(MLX5_TXPP_TEST_PKT_SIZE + 423 MLX5_WQE_CSEG_SIZE + 424 2 * MLX5_WQE_ESEG_SIZE - 425 MLX5_ESEG_MIN_INLINE_SIZE, 426 MLX5_WQE_SIZE) / MLX5_WQE_SIZE; 427 wq->sq_size *= MLX5_TXPP_CLKQ_SIZE; 428 } else { 429 wq->sq_size = MLX5_TXPP_CLKQ_SIZE; 430 } 431 /* There should not be WQE leftovers in the cyclic queue. */ 432 MLX5_ASSERT(wq->sq_size == (1 << log2above(wq->sq_size))); 433 /* Create send queue object for Clock Queue. */ 434 if (sh->txpp.test) { 435 sq_attr.tis_lst_sz = 1; 436 sq_attr.tis_num = sh->tis->id; 437 sq_attr.non_wire = 0; 438 sq_attr.static_sq_wq = 1; 439 } else { 440 sq_attr.non_wire = 1; 441 sq_attr.static_sq_wq = 1; 442 } 443 sq_attr.cqn = wq->cq_obj.cq->id; 444 sq_attr.packet_pacing_rate_limit_index = sh->txpp.pp_id; 445 sq_attr.wq_attr.cd_slave = 1; 446 sq_attr.wq_attr.uar_page = mlx5_os_get_devx_uar_page_id(sh->tx_uar); 447 sq_attr.wq_attr.pd = sh->pdn; 448 sq_attr.ts_format = mlx5_ts_format_conv(sh->sq_ts_format); 449 ret = mlx5_devx_sq_create(sh->ctx, &wq->sq_obj, log2above(wq->sq_size), 450 &sq_attr, sh->numa_node); 451 if (ret) { 452 rte_errno = errno; 453 DRV_LOG(ERR, "Failed to create SQ for Clock Queue."); 454 goto error; 455 } 456 /* Build the WQEs in the Send Queue before goto Ready state. */ 457 mlx5_txpp_fill_wqe_clock_queue(sh); 458 /* Change queue state to ready. */ 459 msq_attr.sq_state = MLX5_SQC_STATE_RST; 460 msq_attr.state = MLX5_SQC_STATE_RDY; 461 wq->sq_ci = 0; 462 ret = mlx5_devx_cmd_modify_sq(wq->sq_obj.sq, &msq_attr); 463 if (ret) { 464 DRV_LOG(ERR, "Failed to set SQ ready state Clock Queue."); 465 goto error; 466 } 467 return 0; 468 error: 469 ret = -rte_errno; 470 mlx5_txpp_destroy_clock_queue(sh); 471 rte_errno = -ret; 472 return ret; 473 } 474 475 /* Enable notification from the Rearm Queue CQ. */ 476 static inline void 477 mlx5_txpp_cq_arm(struct mlx5_dev_ctx_shared *sh) 478 { 479 void *base_addr; 480 481 struct mlx5_txpp_wq *aq = &sh->txpp.rearm_queue; 482 uint32_t arm_sn = aq->arm_sn << MLX5_CQ_SQN_OFFSET; 483 uint32_t db_hi = arm_sn | MLX5_CQ_DBR_CMD_ALL | aq->cq_ci; 484 uint64_t db_be = 485 rte_cpu_to_be_64(((uint64_t)db_hi << 32) | aq->cq_obj.cq->id); 486 base_addr = mlx5_os_get_devx_uar_base_addr(sh->tx_uar); 487 uint32_t *addr = RTE_PTR_ADD(base_addr, MLX5_CQ_DOORBELL); 488 489 rte_compiler_barrier(); 490 aq->cq_obj.db_rec[MLX5_CQ_ARM_DB] = rte_cpu_to_be_32(db_hi); 491 rte_wmb(); 492 #ifdef RTE_ARCH_64 493 *(uint64_t *)addr = db_be; 494 #else 495 *(uint32_t *)addr = db_be; 496 rte_io_wmb(); 497 *((uint32_t *)addr + 1) = db_be >> 32; 498 #endif 499 aq->arm_sn++; 500 } 501 502 #if defined(RTE_ARCH_X86_64) 503 static inline int 504 mlx5_atomic128_compare_exchange(rte_int128_t *dst, 505 rte_int128_t *exp, 506 const rte_int128_t *src) 507 { 508 uint8_t res; 509 510 asm volatile (MPLOCKED 511 "cmpxchg16b %[dst];" 512 " sete %[res]" 513 : [dst] "=m" (dst->val[0]), 514 "=a" (exp->val[0]), 515 "=d" (exp->val[1]), 516 [res] "=r" (res) 517 : "b" (src->val[0]), 518 "c" (src->val[1]), 519 "a" (exp->val[0]), 520 "d" (exp->val[1]), 521 "m" (dst->val[0]) 522 : "memory"); 523 524 return res; 525 } 526 #endif 527 528 static inline void 529 mlx5_atomic_read_cqe(rte_int128_t *from, rte_int128_t *ts) 530 { 531 /* 532 * The only CQE of Clock Queue is being continuously 533 * updated by hardware with specified rate. We must 534 * read timestamp and WQE completion index atomically. 535 */ 536 #if defined(RTE_ARCH_X86_64) 537 rte_int128_t src; 538 539 memset(&src, 0, sizeof(src)); 540 *ts = src; 541 /* if (*from == *ts) *from = *src else *ts = *from; */ 542 mlx5_atomic128_compare_exchange(from, ts, &src); 543 #else 544 uint64_t *cqe = (uint64_t *)from; 545 546 /* 547 * Power architecture does not support 16B compare-and-swap. 548 * ARM implements it in software, code below is more relevant. 549 */ 550 for (;;) { 551 uint64_t tm, op; 552 uint64_t *ps; 553 554 rte_compiler_barrier(); 555 tm = __atomic_load_n(cqe + 0, __ATOMIC_RELAXED); 556 op = __atomic_load_n(cqe + 1, __ATOMIC_RELAXED); 557 rte_compiler_barrier(); 558 if (tm != __atomic_load_n(cqe + 0, __ATOMIC_RELAXED)) 559 continue; 560 if (op != __atomic_load_n(cqe + 1, __ATOMIC_RELAXED)) 561 continue; 562 ps = (uint64_t *)ts; 563 ps[0] = tm; 564 ps[1] = op; 565 return; 566 } 567 #endif 568 } 569 570 /* Stores timestamp in the cache structure to share data with datapath. */ 571 static inline void 572 mlx5_txpp_cache_timestamp(struct mlx5_dev_ctx_shared *sh, 573 uint64_t ts, uint64_t ci) 574 { 575 ci = ci << (64 - MLX5_CQ_INDEX_WIDTH); 576 ci |= (ts << MLX5_CQ_INDEX_WIDTH) >> MLX5_CQ_INDEX_WIDTH; 577 rte_compiler_barrier(); 578 __atomic_store_n(&sh->txpp.ts.ts, ts, __ATOMIC_RELAXED); 579 __atomic_store_n(&sh->txpp.ts.ci_ts, ci, __ATOMIC_RELAXED); 580 rte_wmb(); 581 } 582 583 /* Reads timestamp from Clock Queue CQE and stores in the cache. */ 584 static inline void 585 mlx5_txpp_update_timestamp(struct mlx5_dev_ctx_shared *sh) 586 { 587 struct mlx5_txpp_wq *wq = &sh->txpp.clock_queue; 588 struct mlx5_cqe *cqe = (struct mlx5_cqe *)(uintptr_t)wq->cq_obj.cqes; 589 union { 590 rte_int128_t u128; 591 struct mlx5_cqe_ts cts; 592 } to; 593 uint64_t ts; 594 uint16_t ci; 595 uint8_t opcode; 596 597 mlx5_atomic_read_cqe((rte_int128_t *)&cqe->timestamp, &to.u128); 598 opcode = MLX5_CQE_OPCODE(to.cts.op_own); 599 if (opcode) { 600 if (opcode != MLX5_CQE_INVALID) { 601 /* 602 * Commit the error state if and only if 603 * we have got at least one actual completion. 604 */ 605 DRV_LOG(DEBUG, 606 "Clock Queue error sync lost (%X).", opcode); 607 __atomic_fetch_add(&sh->txpp.err_clock_queue, 608 1, __ATOMIC_RELAXED); 609 sh->txpp.sync_lost = 1; 610 } 611 return; 612 } 613 ci = rte_be_to_cpu_16(to.cts.wqe_counter); 614 ts = rte_be_to_cpu_64(to.cts.timestamp); 615 ts = mlx5_txpp_convert_rx_ts(sh, ts); 616 wq->cq_ci += (ci - wq->sq_ci) & UINT16_MAX; 617 wq->sq_ci = ci; 618 mlx5_txpp_cache_timestamp(sh, ts, wq->cq_ci); 619 } 620 621 /* Waits for the first completion on Clock Queue to init timestamp. */ 622 static inline void 623 mlx5_txpp_init_timestamp(struct mlx5_dev_ctx_shared *sh) 624 { 625 struct mlx5_txpp_wq *wq = &sh->txpp.clock_queue; 626 uint32_t wait; 627 628 sh->txpp.ts_p = 0; 629 sh->txpp.ts_n = 0; 630 for (wait = 0; wait < MLX5_TXPP_WAIT_INIT_TS; wait++) { 631 mlx5_txpp_update_timestamp(sh); 632 if (wq->sq_ci) 633 return; 634 /* Wait one millisecond and try again. */ 635 rte_delay_us_sleep(US_PER_S / MS_PER_S); 636 } 637 DRV_LOG(ERR, "Unable to initialize timestamp."); 638 sh->txpp.sync_lost = 1; 639 } 640 641 #ifdef HAVE_IBV_DEVX_EVENT 642 /* Gather statistics for timestamp from Clock Queue CQE. */ 643 static inline void 644 mlx5_txpp_gather_timestamp(struct mlx5_dev_ctx_shared *sh) 645 { 646 /* Check whether we have a valid timestamp. */ 647 if (!sh->txpp.clock_queue.sq_ci && !sh->txpp.ts_n) 648 return; 649 MLX5_ASSERT(sh->txpp.ts_p < MLX5_TXPP_REARM_SQ_SIZE); 650 __atomic_store_n(&sh->txpp.tsa[sh->txpp.ts_p].ts, 651 sh->txpp.ts.ts, __ATOMIC_RELAXED); 652 __atomic_store_n(&sh->txpp.tsa[sh->txpp.ts_p].ci_ts, 653 sh->txpp.ts.ci_ts, __ATOMIC_RELAXED); 654 if (++sh->txpp.ts_p >= MLX5_TXPP_REARM_SQ_SIZE) 655 sh->txpp.ts_p = 0; 656 if (sh->txpp.ts_n < MLX5_TXPP_REARM_SQ_SIZE) 657 ++sh->txpp.ts_n; 658 } 659 660 /* Handles Rearm Queue completions in periodic service. */ 661 static __rte_always_inline void 662 mlx5_txpp_handle_rearm_queue(struct mlx5_dev_ctx_shared *sh) 663 { 664 struct mlx5_txpp_wq *wq = &sh->txpp.rearm_queue; 665 uint32_t cq_ci = wq->cq_ci; 666 bool error = false; 667 int ret; 668 669 do { 670 volatile struct mlx5_cqe *cqe; 671 672 cqe = &wq->cq_obj.cqes[cq_ci & (MLX5_TXPP_REARM_CQ_SIZE - 1)]; 673 ret = check_cqe(cqe, MLX5_TXPP_REARM_CQ_SIZE, cq_ci); 674 switch (ret) { 675 case MLX5_CQE_STATUS_ERR: 676 error = true; 677 ++cq_ci; 678 break; 679 case MLX5_CQE_STATUS_SW_OWN: 680 wq->sq_ci += 2; 681 ++cq_ci; 682 break; 683 case MLX5_CQE_STATUS_HW_OWN: 684 break; 685 default: 686 MLX5_ASSERT(false); 687 break; 688 } 689 } while (ret != MLX5_CQE_STATUS_HW_OWN); 690 if (likely(cq_ci != wq->cq_ci)) { 691 /* Check whether we have missed interrupts. */ 692 if (cq_ci - wq->cq_ci != 1) { 693 DRV_LOG(DEBUG, "Rearm Queue missed interrupt."); 694 __atomic_fetch_add(&sh->txpp.err_miss_int, 695 1, __ATOMIC_RELAXED); 696 /* Check sync lost on wqe index. */ 697 if (cq_ci - wq->cq_ci >= 698 (((1UL << MLX5_WQ_INDEX_WIDTH) / 699 MLX5_TXPP_REARM) - 1)) 700 error = 1; 701 } 702 /* Update doorbell record to notify hardware. */ 703 rte_compiler_barrier(); 704 *wq->cq_obj.db_rec = rte_cpu_to_be_32(cq_ci); 705 rte_wmb(); 706 wq->cq_ci = cq_ci; 707 /* Fire new requests to Rearm Queue. */ 708 if (error) { 709 DRV_LOG(DEBUG, "Rearm Queue error sync lost."); 710 __atomic_fetch_add(&sh->txpp.err_rearm_queue, 711 1, __ATOMIC_RELAXED); 712 sh->txpp.sync_lost = 1; 713 } 714 } 715 } 716 717 /* Handles Clock Queue completions in periodic service. */ 718 static __rte_always_inline void 719 mlx5_txpp_handle_clock_queue(struct mlx5_dev_ctx_shared *sh) 720 { 721 mlx5_txpp_update_timestamp(sh); 722 mlx5_txpp_gather_timestamp(sh); 723 } 724 #endif 725 726 /* Invoked periodically on Rearm Queue completions. */ 727 void 728 mlx5_txpp_interrupt_handler(void *cb_arg) 729 { 730 #ifndef HAVE_IBV_DEVX_EVENT 731 RTE_SET_USED(cb_arg); 732 return; 733 #else 734 struct mlx5_dev_ctx_shared *sh = cb_arg; 735 union { 736 struct mlx5dv_devx_async_event_hdr event_resp; 737 uint8_t buf[sizeof(struct mlx5dv_devx_async_event_hdr) + 128]; 738 } out; 739 740 MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY); 741 /* Process events in the loop. Only rearm completions are expected. */ 742 while (mlx5_glue->devx_get_event 743 (sh->txpp.echan, 744 &out.event_resp, 745 sizeof(out.buf)) >= 746 (ssize_t)sizeof(out.event_resp.cookie)) { 747 mlx5_txpp_handle_rearm_queue(sh); 748 mlx5_txpp_handle_clock_queue(sh); 749 mlx5_txpp_cq_arm(sh); 750 mlx5_txpp_doorbell_rearm_queue 751 (sh, sh->txpp.rearm_queue.sq_ci - 1); 752 } 753 #endif /* HAVE_IBV_DEVX_ASYNC */ 754 } 755 756 static void 757 mlx5_txpp_stop_service(struct mlx5_dev_ctx_shared *sh) 758 { 759 if (!sh->txpp.intr_handle.fd) 760 return; 761 mlx5_intr_callback_unregister(&sh->txpp.intr_handle, 762 mlx5_txpp_interrupt_handler, sh); 763 sh->txpp.intr_handle.fd = 0; 764 } 765 766 /* Attach interrupt handler and fires first request to Rearm Queue. */ 767 static int 768 mlx5_txpp_start_service(struct mlx5_dev_ctx_shared *sh) 769 { 770 uint16_t event_nums[1] = {0}; 771 int ret; 772 int fd; 773 774 sh->txpp.err_miss_int = 0; 775 sh->txpp.err_rearm_queue = 0; 776 sh->txpp.err_clock_queue = 0; 777 sh->txpp.err_ts_past = 0; 778 sh->txpp.err_ts_future = 0; 779 /* Attach interrupt handler to process Rearm Queue completions. */ 780 fd = mlx5_os_get_devx_channel_fd(sh->txpp.echan); 781 ret = mlx5_os_set_nonblock_channel_fd(fd); 782 if (ret) { 783 DRV_LOG(ERR, "Failed to change event channel FD."); 784 rte_errno = errno; 785 return -rte_errno; 786 } 787 memset(&sh->txpp.intr_handle, 0, sizeof(sh->txpp.intr_handle)); 788 fd = mlx5_os_get_devx_channel_fd(sh->txpp.echan); 789 sh->txpp.intr_handle.fd = fd; 790 sh->txpp.intr_handle.type = RTE_INTR_HANDLE_EXT; 791 if (rte_intr_callback_register(&sh->txpp.intr_handle, 792 mlx5_txpp_interrupt_handler, sh)) { 793 sh->txpp.intr_handle.fd = 0; 794 DRV_LOG(ERR, "Failed to register CQE interrupt %d.", rte_errno); 795 return -rte_errno; 796 } 797 /* Subscribe CQ event to the event channel controlled by the driver. */ 798 ret = mlx5_os_devx_subscribe_devx_event(sh->txpp.echan, 799 sh->txpp.rearm_queue.cq_obj.cq->obj, 800 sizeof(event_nums), event_nums, 0); 801 if (ret) { 802 DRV_LOG(ERR, "Failed to subscribe CQE event."); 803 rte_errno = errno; 804 return -errno; 805 } 806 /* Enable interrupts in the CQ. */ 807 mlx5_txpp_cq_arm(sh); 808 /* Fire the first request on Rearm Queue. */ 809 mlx5_txpp_doorbell_rearm_queue(sh, sh->txpp.rearm_queue.sq_size - 1); 810 mlx5_txpp_init_timestamp(sh); 811 return 0; 812 } 813 814 /* 815 * The routine initializes the packet pacing infrastructure: 816 * - allocates PP context 817 * - Clock CQ/SQ 818 * - Rearm CQ/SQ 819 * - attaches rearm interrupt handler 820 * - starts Clock Queue 821 * 822 * Returns 0 on success, negative otherwise 823 */ 824 static int 825 mlx5_txpp_create(struct mlx5_dev_ctx_shared *sh, struct mlx5_priv *priv) 826 { 827 int tx_pp = priv->config.tx_pp; 828 int ret; 829 830 /* Store the requested pacing parameters. */ 831 sh->txpp.tick = tx_pp >= 0 ? tx_pp : -tx_pp; 832 sh->txpp.test = !!(tx_pp < 0); 833 sh->txpp.skew = priv->config.tx_skew; 834 sh->txpp.freq = priv->config.hca_attr.dev_freq_khz; 835 ret = mlx5_txpp_create_event_channel(sh); 836 if (ret) 837 goto exit; 838 ret = mlx5_txpp_alloc_pp_index(sh); 839 if (ret) 840 goto exit; 841 ret = mlx5_txpp_create_clock_queue(sh); 842 if (ret) 843 goto exit; 844 ret = mlx5_txpp_create_rearm_queue(sh); 845 if (ret) 846 goto exit; 847 ret = mlx5_txpp_start_service(sh); 848 if (ret) 849 goto exit; 850 exit: 851 if (ret) { 852 mlx5_txpp_stop_service(sh); 853 mlx5_txpp_destroy_rearm_queue(sh); 854 mlx5_txpp_destroy_clock_queue(sh); 855 mlx5_txpp_free_pp_index(sh); 856 mlx5_txpp_destroy_event_channel(sh); 857 sh->txpp.tick = 0; 858 sh->txpp.test = 0; 859 sh->txpp.skew = 0; 860 } 861 return ret; 862 } 863 864 /* 865 * The routine destroys the packet pacing infrastructure: 866 * - detaches rearm interrupt handler 867 * - Rearm CQ/SQ 868 * - Clock CQ/SQ 869 * - PP context 870 */ 871 static void 872 mlx5_txpp_destroy(struct mlx5_dev_ctx_shared *sh) 873 { 874 mlx5_txpp_stop_service(sh); 875 mlx5_txpp_destroy_rearm_queue(sh); 876 mlx5_txpp_destroy_clock_queue(sh); 877 mlx5_txpp_free_pp_index(sh); 878 mlx5_txpp_destroy_event_channel(sh); 879 sh->txpp.tick = 0; 880 sh->txpp.test = 0; 881 sh->txpp.skew = 0; 882 } 883 884 /** 885 * Creates and starts packet pacing infrastructure on specified device. 886 * 887 * @param dev 888 * Pointer to Ethernet device structure. 889 * 890 * @return 891 * 0 on success, a negative errno value otherwise and rte_errno is set. 892 */ 893 int 894 mlx5_txpp_start(struct rte_eth_dev *dev) 895 { 896 struct mlx5_priv *priv = dev->data->dev_private; 897 struct mlx5_dev_ctx_shared *sh = priv->sh; 898 int err = 0; 899 int ret; 900 901 if (!priv->config.tx_pp) { 902 /* Packet pacing is not requested for the device. */ 903 MLX5_ASSERT(priv->txpp_en == 0); 904 return 0; 905 } 906 if (priv->txpp_en) { 907 /* Packet pacing is already enabled for the device. */ 908 MLX5_ASSERT(sh->txpp.refcnt); 909 return 0; 910 } 911 if (priv->config.tx_pp > 0) { 912 ret = rte_mbuf_dynflag_lookup 913 (RTE_MBUF_DYNFLAG_TX_TIMESTAMP_NAME, NULL); 914 if (ret < 0) 915 return 0; 916 } 917 ret = pthread_mutex_lock(&sh->txpp.mutex); 918 MLX5_ASSERT(!ret); 919 RTE_SET_USED(ret); 920 if (sh->txpp.refcnt) { 921 priv->txpp_en = 1; 922 ++sh->txpp.refcnt; 923 } else { 924 err = mlx5_txpp_create(sh, priv); 925 if (!err) { 926 MLX5_ASSERT(sh->txpp.tick); 927 priv->txpp_en = 1; 928 sh->txpp.refcnt = 1; 929 } else { 930 rte_errno = -err; 931 } 932 } 933 ret = pthread_mutex_unlock(&sh->txpp.mutex); 934 MLX5_ASSERT(!ret); 935 RTE_SET_USED(ret); 936 return err; 937 } 938 939 /** 940 * Stops and destroys packet pacing infrastructure on specified device. 941 * 942 * @param dev 943 * Pointer to Ethernet device structure. 944 * 945 * @return 946 * 0 on success, a negative errno value otherwise and rte_errno is set. 947 */ 948 void 949 mlx5_txpp_stop(struct rte_eth_dev *dev) 950 { 951 struct mlx5_priv *priv = dev->data->dev_private; 952 struct mlx5_dev_ctx_shared *sh = priv->sh; 953 int ret; 954 955 if (!priv->txpp_en) { 956 /* Packet pacing is already disabled for the device. */ 957 return; 958 } 959 priv->txpp_en = 0; 960 ret = pthread_mutex_lock(&sh->txpp.mutex); 961 MLX5_ASSERT(!ret); 962 RTE_SET_USED(ret); 963 MLX5_ASSERT(sh->txpp.refcnt); 964 if (!sh->txpp.refcnt || --sh->txpp.refcnt) 965 return; 966 /* No references any more, do actual destroy. */ 967 mlx5_txpp_destroy(sh); 968 ret = pthread_mutex_unlock(&sh->txpp.mutex); 969 MLX5_ASSERT(!ret); 970 RTE_SET_USED(ret); 971 } 972 973 /* 974 * Read the current clock counter of an Ethernet device 975 * 976 * This returns the current raw clock value of an Ethernet device. It is 977 * a raw amount of ticks, with no given time reference. 978 * The value returned here is from the same clock than the one 979 * filling timestamp field of Rx/Tx packets when using hardware timestamp 980 * offload. Therefore it can be used to compute a precise conversion of 981 * the device clock to the real time. 982 * 983 * @param dev 984 * Pointer to Ethernet device structure. 985 * @param clock 986 * Pointer to the uint64_t that holds the raw clock value. 987 * 988 * @return 989 * - 0: Success. 990 * - -ENOTSUP: The function is not supported in this mode. Requires 991 * packet pacing module configured and started (tx_pp devarg) 992 */ 993 int 994 mlx5_txpp_read_clock(struct rte_eth_dev *dev, uint64_t *timestamp) 995 { 996 struct mlx5_priv *priv = dev->data->dev_private; 997 struct mlx5_dev_ctx_shared *sh = priv->sh; 998 int ret; 999 1000 if (sh->txpp.refcnt) { 1001 struct mlx5_txpp_wq *wq = &sh->txpp.clock_queue; 1002 struct mlx5_cqe *cqe = 1003 (struct mlx5_cqe *)(uintptr_t)wq->cq_obj.cqes; 1004 union { 1005 rte_int128_t u128; 1006 struct mlx5_cqe_ts cts; 1007 } to; 1008 uint64_t ts; 1009 1010 mlx5_atomic_read_cqe((rte_int128_t *)&cqe->timestamp, &to.u128); 1011 if (to.cts.op_own >> 4) { 1012 DRV_LOG(DEBUG, "Clock Queue error sync lost."); 1013 __atomic_fetch_add(&sh->txpp.err_clock_queue, 1014 1, __ATOMIC_RELAXED); 1015 sh->txpp.sync_lost = 1; 1016 return -EIO; 1017 } 1018 ts = rte_be_to_cpu_64(to.cts.timestamp); 1019 ts = mlx5_txpp_convert_rx_ts(sh, ts); 1020 *timestamp = ts; 1021 return 0; 1022 } 1023 /* Not supported in isolated mode - kernel does not see the CQEs. */ 1024 if (priv->isolated || rte_eal_process_type() != RTE_PROC_PRIMARY) 1025 return -ENOTSUP; 1026 ret = mlx5_read_clock(dev, timestamp); 1027 return ret; 1028 } 1029 1030 /** 1031 * DPDK callback to clear device extended statistics. 1032 * 1033 * @param dev 1034 * Pointer to Ethernet device structure. 1035 * 1036 * @return 1037 * 0 on success and stats is reset, negative errno value otherwise and 1038 * rte_errno is set. 1039 */ 1040 int mlx5_txpp_xstats_reset(struct rte_eth_dev *dev) 1041 { 1042 struct mlx5_priv *priv = dev->data->dev_private; 1043 struct mlx5_dev_ctx_shared *sh = priv->sh; 1044 1045 __atomic_store_n(&sh->txpp.err_miss_int, 0, __ATOMIC_RELAXED); 1046 __atomic_store_n(&sh->txpp.err_rearm_queue, 0, __ATOMIC_RELAXED); 1047 __atomic_store_n(&sh->txpp.err_clock_queue, 0, __ATOMIC_RELAXED); 1048 __atomic_store_n(&sh->txpp.err_ts_past, 0, __ATOMIC_RELAXED); 1049 __atomic_store_n(&sh->txpp.err_ts_future, 0, __ATOMIC_RELAXED); 1050 return 0; 1051 } 1052 1053 /** 1054 * Routine to retrieve names of extended device statistics 1055 * for packet send scheduling. It appends the specific stats names 1056 * after the parts filled by preceding modules (eth stats, etc.) 1057 * 1058 * @param dev 1059 * Pointer to Ethernet device structure. 1060 * @param[out] xstats_names 1061 * Buffer to insert names into. 1062 * @param n 1063 * Number of names. 1064 * @param n_used 1065 * Number of names filled by preceding statistics modules. 1066 * 1067 * @return 1068 * Number of xstats names. 1069 */ 1070 int mlx5_txpp_xstats_get_names(struct rte_eth_dev *dev __rte_unused, 1071 struct rte_eth_xstat_name *xstats_names, 1072 unsigned int n, unsigned int n_used) 1073 { 1074 unsigned int n_txpp = RTE_DIM(mlx5_txpp_stat_names); 1075 unsigned int i; 1076 1077 if (n >= n_used + n_txpp && xstats_names) { 1078 for (i = 0; i < n_txpp; ++i) { 1079 strncpy(xstats_names[i + n_used].name, 1080 mlx5_txpp_stat_names[i], 1081 RTE_ETH_XSTATS_NAME_SIZE); 1082 xstats_names[i + n_used].name 1083 [RTE_ETH_XSTATS_NAME_SIZE - 1] = 0; 1084 } 1085 } 1086 return n_used + n_txpp; 1087 } 1088 1089 static inline void 1090 mlx5_txpp_read_tsa(struct mlx5_dev_txpp *txpp, 1091 struct mlx5_txpp_ts *tsa, uint16_t idx) 1092 { 1093 do { 1094 uint64_t ts, ci; 1095 1096 ts = __atomic_load_n(&txpp->tsa[idx].ts, __ATOMIC_RELAXED); 1097 ci = __atomic_load_n(&txpp->tsa[idx].ci_ts, __ATOMIC_RELAXED); 1098 rte_compiler_barrier(); 1099 if ((ci ^ ts) << MLX5_CQ_INDEX_WIDTH != 0) 1100 continue; 1101 if (__atomic_load_n(&txpp->tsa[idx].ts, 1102 __ATOMIC_RELAXED) != ts) 1103 continue; 1104 if (__atomic_load_n(&txpp->tsa[idx].ci_ts, 1105 __ATOMIC_RELAXED) != ci) 1106 continue; 1107 tsa->ts = ts; 1108 tsa->ci_ts = ci; 1109 return; 1110 } while (true); 1111 } 1112 1113 /* 1114 * Jitter reflects the clock change between 1115 * neighbours Clock Queue completions. 1116 */ 1117 static uint64_t 1118 mlx5_txpp_xstats_jitter(struct mlx5_dev_txpp *txpp) 1119 { 1120 struct mlx5_txpp_ts tsa0, tsa1; 1121 int64_t dts, dci; 1122 uint16_t ts_p; 1123 1124 if (txpp->ts_n < 2) { 1125 /* No gathered enough reports yet. */ 1126 return 0; 1127 } 1128 do { 1129 int ts_0, ts_1; 1130 1131 ts_p = txpp->ts_p; 1132 rte_compiler_barrier(); 1133 ts_0 = ts_p - 2; 1134 if (ts_0 < 0) 1135 ts_0 += MLX5_TXPP_REARM_SQ_SIZE; 1136 ts_1 = ts_p - 1; 1137 if (ts_1 < 0) 1138 ts_1 += MLX5_TXPP_REARM_SQ_SIZE; 1139 mlx5_txpp_read_tsa(txpp, &tsa0, ts_0); 1140 mlx5_txpp_read_tsa(txpp, &tsa1, ts_1); 1141 rte_compiler_barrier(); 1142 } while (ts_p != txpp->ts_p); 1143 /* We have two neighbor reports, calculate the jitter. */ 1144 dts = tsa1.ts - tsa0.ts; 1145 dci = (tsa1.ci_ts >> (64 - MLX5_CQ_INDEX_WIDTH)) - 1146 (tsa0.ci_ts >> (64 - MLX5_CQ_INDEX_WIDTH)); 1147 if (dci < 0) 1148 dci += 1 << MLX5_CQ_INDEX_WIDTH; 1149 dci *= txpp->tick; 1150 return (dts > dci) ? dts - dci : dci - dts; 1151 } 1152 1153 /* 1154 * Wander reflects the long-term clock change 1155 * over the entire length of all Clock Queue completions. 1156 */ 1157 static uint64_t 1158 mlx5_txpp_xstats_wander(struct mlx5_dev_txpp *txpp) 1159 { 1160 struct mlx5_txpp_ts tsa0, tsa1; 1161 int64_t dts, dci; 1162 uint16_t ts_p; 1163 1164 if (txpp->ts_n < MLX5_TXPP_REARM_SQ_SIZE) { 1165 /* No gathered enough reports yet. */ 1166 return 0; 1167 } 1168 do { 1169 int ts_0, ts_1; 1170 1171 ts_p = txpp->ts_p; 1172 rte_compiler_barrier(); 1173 ts_0 = ts_p - MLX5_TXPP_REARM_SQ_SIZE / 2 - 1; 1174 if (ts_0 < 0) 1175 ts_0 += MLX5_TXPP_REARM_SQ_SIZE; 1176 ts_1 = ts_p - 1; 1177 if (ts_1 < 0) 1178 ts_1 += MLX5_TXPP_REARM_SQ_SIZE; 1179 mlx5_txpp_read_tsa(txpp, &tsa0, ts_0); 1180 mlx5_txpp_read_tsa(txpp, &tsa1, ts_1); 1181 rte_compiler_barrier(); 1182 } while (ts_p != txpp->ts_p); 1183 /* We have two neighbor reports, calculate the jitter. */ 1184 dts = tsa1.ts - tsa0.ts; 1185 dci = (tsa1.ci_ts >> (64 - MLX5_CQ_INDEX_WIDTH)) - 1186 (tsa0.ci_ts >> (64 - MLX5_CQ_INDEX_WIDTH)); 1187 dci += 1 << MLX5_CQ_INDEX_WIDTH; 1188 dci *= txpp->tick; 1189 return (dts > dci) ? dts - dci : dci - dts; 1190 } 1191 1192 /** 1193 * Routine to retrieve extended device statistics 1194 * for packet send scheduling. It appends the specific statistics 1195 * after the parts filled by preceding modules (eth stats, etc.) 1196 * 1197 * @param dev 1198 * Pointer to Ethernet device. 1199 * @param[out] stats 1200 * Pointer to rte extended stats table. 1201 * @param n 1202 * The size of the stats table. 1203 * @param n_used 1204 * Number of stats filled by preceding statistics modules. 1205 * 1206 * @return 1207 * Number of extended stats on success and stats is filled, 1208 * negative on error and rte_errno is set. 1209 */ 1210 int 1211 mlx5_txpp_xstats_get(struct rte_eth_dev *dev, 1212 struct rte_eth_xstat *stats, 1213 unsigned int n, unsigned int n_used) 1214 { 1215 unsigned int n_txpp = RTE_DIM(mlx5_txpp_stat_names); 1216 1217 if (n >= n_used + n_txpp && stats) { 1218 struct mlx5_priv *priv = dev->data->dev_private; 1219 struct mlx5_dev_ctx_shared *sh = priv->sh; 1220 unsigned int i; 1221 1222 for (i = 0; i < n_txpp; ++i) 1223 stats[n_used + i].id = n_used + i; 1224 stats[n_used + 0].value = 1225 __atomic_load_n(&sh->txpp.err_miss_int, 1226 __ATOMIC_RELAXED); 1227 stats[n_used + 1].value = 1228 __atomic_load_n(&sh->txpp.err_rearm_queue, 1229 __ATOMIC_RELAXED); 1230 stats[n_used + 2].value = 1231 __atomic_load_n(&sh->txpp.err_clock_queue, 1232 __ATOMIC_RELAXED); 1233 stats[n_used + 3].value = 1234 __atomic_load_n(&sh->txpp.err_ts_past, 1235 __ATOMIC_RELAXED); 1236 stats[n_used + 4].value = 1237 __atomic_load_n(&sh->txpp.err_ts_future, 1238 __ATOMIC_RELAXED); 1239 stats[n_used + 5].value = mlx5_txpp_xstats_jitter(&sh->txpp); 1240 stats[n_used + 6].value = mlx5_txpp_xstats_wander(&sh->txpp); 1241 stats[n_used + 7].value = sh->txpp.sync_lost; 1242 } 1243 return n_used + n_txpp; 1244 } 1245