1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2017 6WIND S.A. 3 * Copyright 2017 Mellanox Technologies, Ltd 4 */ 5 6 #ifndef RTE_PMD_MLX5_RXTX_VEC_NEON_H_ 7 #define RTE_PMD_MLX5_RXTX_VEC_NEON_H_ 8 9 #include <stdint.h> 10 #include <string.h> 11 #include <stdlib.h> 12 #include <arm_neon.h> 13 14 #include <rte_mbuf.h> 15 #include <rte_mempool.h> 16 #include <rte_prefetch.h> 17 18 #include <mlx5_prm.h> 19 20 #include "mlx5_defs.h" 21 #include "mlx5.h" 22 #include "mlx5_utils.h" 23 #include "mlx5_rxtx.h" 24 #include "mlx5_rxtx_vec.h" 25 #include "mlx5_autoconf.h" 26 27 #pragma GCC diagnostic ignored "-Wcast-qual" 28 29 /** 30 * Store free buffers to RX SW ring. 31 * 32 * @param rxq 33 * Pointer to RX queue structure. 34 * @param pkts 35 * Pointer to array of packets to be stored. 36 * @param pkts_n 37 * Number of packets to be stored. 38 */ 39 static inline void 40 rxq_copy_mbuf_v(struct mlx5_rxq_data *rxq, struct rte_mbuf **pkts, uint16_t n) 41 { 42 const uint16_t q_mask = (1 << rxq->elts_n) - 1; 43 struct rte_mbuf **elts = &(*rxq->elts)[rxq->rq_pi & q_mask]; 44 unsigned int pos; 45 uint16_t p = n & -2; 46 47 for (pos = 0; pos < p; pos += 2) { 48 uint64x2_t mbp; 49 50 mbp = vld1q_u64((void *)&elts[pos]); 51 vst1q_u64((void *)&pkts[pos], mbp); 52 } 53 if (n & 1) 54 pkts[pos] = elts[pos]; 55 } 56 57 /** 58 * Decompress a compressed completion and fill in mbufs in RX SW ring with data 59 * extracted from the title completion descriptor. 60 * 61 * @param rxq 62 * Pointer to RX queue structure. 63 * @param cq 64 * Pointer to completion array having a compressed completion at first. 65 * @param elts 66 * Pointer to SW ring to be filled. The first mbuf has to be pre-built from 67 * the title completion descriptor to be copied to the rest of mbufs. 68 * 69 * @return 70 * Number of mini-CQEs successfully decompressed. 71 */ 72 static inline uint16_t 73 rxq_cq_decompress_v(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cq, 74 struct rte_mbuf **elts) 75 { 76 volatile struct mlx5_mini_cqe8 *mcq = (void *)&(cq + 1)->pkt_info; 77 struct rte_mbuf *t_pkt = elts[0]; /* Title packet is pre-built. */ 78 unsigned int pos; 79 unsigned int i; 80 unsigned int inv = 0; 81 /* Mask to shuffle from extracted mini CQE to mbuf. */ 82 const uint8x16_t mcqe_shuf_m1 = { 83 -1, -1, -1, -1, /* skip packet_type */ 84 7, 6, -1, -1, /* pkt_len, bswap16 */ 85 7, 6, /* data_len, bswap16 */ 86 -1, -1, /* skip vlan_tci */ 87 3, 2, 1, 0 /* hash.rss, bswap32 */ 88 }; 89 const uint8x16_t mcqe_shuf_m2 = { 90 -1, -1, -1, -1, /* skip packet_type */ 91 15, 14, -1, -1, /* pkt_len, bswap16 */ 92 15, 14, /* data_len, bswap16 */ 93 -1, -1, /* skip vlan_tci */ 94 11, 10, 9, 8 /* hash.rss, bswap32 */ 95 }; 96 /* Restore the compressed count. Must be 16 bits. */ 97 const uint16_t mcqe_n = t_pkt->data_len + 98 (rxq->crc_present * RTE_ETHER_CRC_LEN); 99 const uint64x2_t rearm = 100 vld1q_u64((void *)&t_pkt->rearm_data); 101 const uint32x4_t rxdf_mask = { 102 0xffffffff, /* packet_type */ 103 0, /* skip pkt_len */ 104 0xffff0000, /* vlan_tci, skip data_len */ 105 0, /* skip hash.rss */ 106 }; 107 const uint8x16_t rxdf = 108 vandq_u8(vld1q_u8((void *)&t_pkt->rx_descriptor_fields1), 109 vreinterpretq_u8_u32(rxdf_mask)); 110 const uint16x8_t crc_adj = { 111 0, 0, 112 rxq->crc_present * RTE_ETHER_CRC_LEN, 0, 113 rxq->crc_present * RTE_ETHER_CRC_LEN, 0, 114 0, 0 115 }; 116 const uint32_t flow_tag = t_pkt->hash.fdir.hi; 117 #ifdef MLX5_PMD_SOFT_COUNTERS 118 uint32_t rcvd_byte = 0; 119 #endif 120 /* Mask to shuffle byte_cnt to add up stats. Do bswap16 for all. */ 121 const uint8x8_t len_shuf_m = { 122 7, 6, /* 1st mCQE */ 123 15, 14, /* 2nd mCQE */ 124 23, 22, /* 3rd mCQE */ 125 31, 30 /* 4th mCQE */ 126 }; 127 128 /* 129 * A. load mCQEs into a 128bit register. 130 * B. store rearm data to mbuf. 131 * C. combine data from mCQEs with rx_descriptor_fields1. 132 * D. store rx_descriptor_fields1. 133 * E. store flow tag (rte_flow mark). 134 */ 135 for (pos = 0; pos < mcqe_n; ) { 136 uint8_t *p = (void *)&mcq[pos % 8]; 137 uint8_t *e0 = (void *)&elts[pos]->rearm_data; 138 uint8_t *e1 = (void *)&elts[pos + 1]->rearm_data; 139 uint8_t *e2 = (void *)&elts[pos + 2]->rearm_data; 140 uint8_t *e3 = (void *)&elts[pos + 3]->rearm_data; 141 uint16x4_t byte_cnt; 142 #ifdef MLX5_PMD_SOFT_COUNTERS 143 uint16x4_t invalid_mask = 144 vcreate_u16(mcqe_n - pos < MLX5_VPMD_DESCS_PER_LOOP ? 145 -1UL << ((mcqe_n - pos) * 146 sizeof(uint16_t) * 8) : 0); 147 #endif 148 for (i = 0; i < MLX5_VPMD_DESCS_PER_LOOP; ++i) 149 if (likely(pos + i < mcqe_n)) 150 rte_prefetch0((void *)(cq + pos + i)); 151 __asm__ volatile ( 152 /* A.1 load mCQEs into a 128bit register. */ 153 "ld1 {v16.16b - v17.16b}, [%[mcq]] \n\t" 154 /* B.1 store rearm data to mbuf. */ 155 "st1 {%[rearm].2d}, [%[e0]] \n\t" 156 "add %[e0], %[e0], #16 \n\t" 157 "st1 {%[rearm].2d}, [%[e1]] \n\t" 158 "add %[e1], %[e1], #16 \n\t" 159 /* C.1 combine data from mCQEs with rx_descriptor_fields1. */ 160 "tbl v18.16b, {v16.16b}, %[mcqe_shuf_m1].16b \n\t" 161 "tbl v19.16b, {v16.16b}, %[mcqe_shuf_m2].16b \n\t" 162 "sub v18.8h, v18.8h, %[crc_adj].8h \n\t" 163 "sub v19.8h, v19.8h, %[crc_adj].8h \n\t" 164 "orr v18.16b, v18.16b, %[rxdf].16b \n\t" 165 "orr v19.16b, v19.16b, %[rxdf].16b \n\t" 166 /* D.1 store rx_descriptor_fields1. */ 167 "st1 {v18.2d}, [%[e0]] \n\t" 168 "st1 {v19.2d}, [%[e1]] \n\t" 169 /* B.1 store rearm data to mbuf. */ 170 "st1 {%[rearm].2d}, [%[e2]] \n\t" 171 "add %[e2], %[e2], #16 \n\t" 172 "st1 {%[rearm].2d}, [%[e3]] \n\t" 173 "add %[e3], %[e3], #16 \n\t" 174 /* C.1 combine data from mCQEs with rx_descriptor_fields1. */ 175 "tbl v18.16b, {v17.16b}, %[mcqe_shuf_m1].16b \n\t" 176 "tbl v19.16b, {v17.16b}, %[mcqe_shuf_m2].16b \n\t" 177 "sub v18.8h, v18.8h, %[crc_adj].8h \n\t" 178 "sub v19.8h, v19.8h, %[crc_adj].8h \n\t" 179 "orr v18.16b, v18.16b, %[rxdf].16b \n\t" 180 "orr v19.16b, v19.16b, %[rxdf].16b \n\t" 181 /* D.1 store rx_descriptor_fields1. */ 182 "st1 {v18.2d}, [%[e2]] \n\t" 183 "st1 {v19.2d}, [%[e3]] \n\t" 184 #ifdef MLX5_PMD_SOFT_COUNTERS 185 "tbl %[byte_cnt].8b, {v16.16b - v17.16b}, %[len_shuf_m].8b \n\t" 186 #endif 187 :[byte_cnt]"=&w"(byte_cnt) 188 :[mcq]"r"(p), 189 [rxdf]"w"(rxdf), 190 [rearm]"w"(rearm), 191 [e3]"r"(e3), [e2]"r"(e2), [e1]"r"(e1), [e0]"r"(e0), 192 [mcqe_shuf_m1]"w"(mcqe_shuf_m1), 193 [mcqe_shuf_m2]"w"(mcqe_shuf_m2), 194 [crc_adj]"w"(crc_adj), 195 [len_shuf_m]"w"(len_shuf_m) 196 :"memory", "v16", "v17", "v18", "v19"); 197 #ifdef MLX5_PMD_SOFT_COUNTERS 198 byte_cnt = vbic_u16(byte_cnt, invalid_mask); 199 rcvd_byte += vget_lane_u64(vpaddl_u32(vpaddl_u16(byte_cnt)), 0); 200 #endif 201 if (rxq->mark) { 202 /* E.1 store flow tag (rte_flow mark). */ 203 elts[pos]->hash.fdir.hi = flow_tag; 204 elts[pos + 1]->hash.fdir.hi = flow_tag; 205 elts[pos + 2]->hash.fdir.hi = flow_tag; 206 elts[pos + 3]->hash.fdir.hi = flow_tag; 207 } 208 if (rxq->dynf_meta) { 209 int32_t offs = rxq->flow_meta_offset; 210 const uint32_t meta = 211 *RTE_MBUF_DYNFIELD(t_pkt, offs, uint32_t *); 212 213 /* Check if title packet has valid metadata. */ 214 if (meta) { 215 MLX5_ASSERT(t_pkt->ol_flags & 216 rxq->flow_meta_mask); 217 *RTE_MBUF_DYNFIELD(elts[pos], offs, 218 uint32_t *) = meta; 219 *RTE_MBUF_DYNFIELD(elts[pos + 1], offs, 220 uint32_t *) = meta; 221 *RTE_MBUF_DYNFIELD(elts[pos + 2], offs, 222 uint32_t *) = meta; 223 *RTE_MBUF_DYNFIELD(elts[pos + 3], offs, 224 uint32_t *) = meta; 225 } 226 } 227 pos += MLX5_VPMD_DESCS_PER_LOOP; 228 /* Move to next CQE and invalidate consumed CQEs. */ 229 if (!(pos & 0x7) && pos < mcqe_n) { 230 mcq = (void *)&(cq + pos)->pkt_info; 231 for (i = 0; i < 8; ++i) 232 cq[inv++].op_own = MLX5_CQE_INVALIDATE; 233 } 234 } 235 /* Invalidate the rest of CQEs. */ 236 for (; inv < mcqe_n; ++inv) 237 cq[inv].op_own = MLX5_CQE_INVALIDATE; 238 #ifdef MLX5_PMD_SOFT_COUNTERS 239 rxq->stats.ipackets += mcqe_n; 240 rxq->stats.ibytes += rcvd_byte; 241 #endif 242 rxq->cq_ci += mcqe_n; 243 return mcqe_n; 244 } 245 246 /** 247 * Calculate packet type and offload flag for mbuf and store it. 248 * 249 * @param rxq 250 * Pointer to RX queue structure. 251 * @param ptype_info 252 * Array of four 4bytes packet type info extracted from the original 253 * completion descriptor. 254 * @param flow_tag 255 * Array of four 4bytes flow ID extracted from the original completion 256 * descriptor. 257 * @param op_err 258 * Opcode vector having responder error status. Each field is 4B. 259 * @param pkts 260 * Pointer to array of packets to be filled. 261 */ 262 static inline void 263 rxq_cq_to_ptype_oflags_v(struct mlx5_rxq_data *rxq, 264 uint32x4_t ptype_info, uint32x4_t flow_tag, 265 uint16x4_t op_err, struct rte_mbuf **pkts) 266 { 267 uint16x4_t ptype; 268 uint32x4_t pinfo, cv_flags; 269 uint32x4_t ol_flags = 270 vdupq_n_u32(rxq->rss_hash * PKT_RX_RSS_HASH | 271 rxq->hw_timestamp * PKT_RX_TIMESTAMP); 272 const uint32x4_t ptype_ol_mask = { 0x106, 0x106, 0x106, 0x106 }; 273 const uint8x16_t cv_flag_sel = { 274 0, 275 (uint8_t)(PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED), 276 (uint8_t)(PKT_RX_IP_CKSUM_GOOD >> 1), 277 0, 278 (uint8_t)(PKT_RX_L4_CKSUM_GOOD >> 1), 279 0, 280 (uint8_t)((PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD) >> 1), 281 0, 0, 0, 0, 0, 0, 0, 0, 0 282 }; 283 const uint32x4_t cv_mask = 284 vdupq_n_u32(PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD | 285 PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED); 286 const uint64x2_t mbuf_init = vld1q_u64 287 ((const uint64_t *)&rxq->mbuf_initializer); 288 uint64x2_t rearm0, rearm1, rearm2, rearm3; 289 uint8_t pt_idx0, pt_idx1, pt_idx2, pt_idx3; 290 291 if (rxq->mark) { 292 const uint32x4_t ft_def = vdupq_n_u32(MLX5_FLOW_MARK_DEFAULT); 293 const uint32x4_t fdir_flags = vdupq_n_u32(PKT_RX_FDIR); 294 uint32x4_t fdir_id_flags = vdupq_n_u32(PKT_RX_FDIR_ID); 295 uint32x4_t invalid_mask; 296 297 /* Check if flow tag is non-zero then set PKT_RX_FDIR. */ 298 invalid_mask = vceqzq_u32(flow_tag); 299 ol_flags = vorrq_u32(ol_flags, 300 vbicq_u32(fdir_flags, invalid_mask)); 301 /* Mask out invalid entries. */ 302 fdir_id_flags = vbicq_u32(fdir_id_flags, invalid_mask); 303 /* Check if flow tag MLX5_FLOW_MARK_DEFAULT. */ 304 ol_flags = vorrq_u32(ol_flags, 305 vbicq_u32(fdir_id_flags, 306 vceqq_u32(flow_tag, ft_def))); 307 } 308 /* 309 * ptype_info has the following: 310 * bit[1] = l3_ok 311 * bit[2] = l4_ok 312 * bit[8] = cv 313 * bit[11:10] = l3_hdr_type 314 * bit[14:12] = l4_hdr_type 315 * bit[15] = ip_frag 316 * bit[16] = tunneled 317 * bit[17] = outer_l3_type 318 */ 319 ptype = vshrn_n_u32(ptype_info, 10); 320 /* Errored packets will have RTE_PTYPE_ALL_MASK. */ 321 ptype = vorr_u16(ptype, op_err); 322 pt_idx0 = vget_lane_u8(vreinterpret_u8_u16(ptype), 6); 323 pt_idx1 = vget_lane_u8(vreinterpret_u8_u16(ptype), 4); 324 pt_idx2 = vget_lane_u8(vreinterpret_u8_u16(ptype), 2); 325 pt_idx3 = vget_lane_u8(vreinterpret_u8_u16(ptype), 0); 326 pkts[0]->packet_type = mlx5_ptype_table[pt_idx0] | 327 !!(pt_idx0 & (1 << 6)) * rxq->tunnel; 328 pkts[1]->packet_type = mlx5_ptype_table[pt_idx1] | 329 !!(pt_idx1 & (1 << 6)) * rxq->tunnel; 330 pkts[2]->packet_type = mlx5_ptype_table[pt_idx2] | 331 !!(pt_idx2 & (1 << 6)) * rxq->tunnel; 332 pkts[3]->packet_type = mlx5_ptype_table[pt_idx3] | 333 !!(pt_idx3 & (1 << 6)) * rxq->tunnel; 334 /* Fill flags for checksum and VLAN. */ 335 pinfo = vandq_u32(ptype_info, ptype_ol_mask); 336 pinfo = vreinterpretq_u32_u8( 337 vqtbl1q_u8(cv_flag_sel, vreinterpretq_u8_u32(pinfo))); 338 /* Locate checksum flags at byte[2:1] and merge with VLAN flags. */ 339 cv_flags = vshlq_n_u32(pinfo, 9); 340 cv_flags = vorrq_u32(pinfo, cv_flags); 341 /* Move back flags to start from byte[0]. */ 342 cv_flags = vshrq_n_u32(cv_flags, 8); 343 /* Mask out garbage bits. */ 344 cv_flags = vandq_u32(cv_flags, cv_mask); 345 /* Merge to ol_flags. */ 346 ol_flags = vorrq_u32(ol_flags, cv_flags); 347 /* Merge mbuf_init and ol_flags, and store. */ 348 rearm0 = vreinterpretq_u64_u32(vsetq_lane_u32 349 (vgetq_lane_u32(ol_flags, 3), 350 vreinterpretq_u32_u64(mbuf_init), 2)); 351 rearm1 = vreinterpretq_u64_u32(vsetq_lane_u32 352 (vgetq_lane_u32(ol_flags, 2), 353 vreinterpretq_u32_u64(mbuf_init), 2)); 354 rearm2 = vreinterpretq_u64_u32(vsetq_lane_u32 355 (vgetq_lane_u32(ol_flags, 1), 356 vreinterpretq_u32_u64(mbuf_init), 2)); 357 rearm3 = vreinterpretq_u64_u32(vsetq_lane_u32 358 (vgetq_lane_u32(ol_flags, 0), 359 vreinterpretq_u32_u64(mbuf_init), 2)); 360 361 vst1q_u64((void *)&pkts[0]->rearm_data, rearm0); 362 vst1q_u64((void *)&pkts[1]->rearm_data, rearm1); 363 vst1q_u64((void *)&pkts[2]->rearm_data, rearm2); 364 vst1q_u64((void *)&pkts[3]->rearm_data, rearm3); 365 } 366 367 /** 368 * Receive burst of packets. An errored completion also consumes a mbuf, but the 369 * packet_type is set to be RTE_PTYPE_ALL_MASK. Marked mbufs should be freed 370 * before returning to application. 371 * 372 * @param rxq 373 * Pointer to RX queue structure. 374 * @param[out] pkts 375 * Array to store received packets. 376 * @param pkts_n 377 * Maximum number of packets in array. 378 * @param[out] err 379 * Pointer to a flag. Set non-zero value if pkts array has at least one error 380 * packet to handle. 381 * 382 * @return 383 * Number of packets received including errors (<= pkts_n). 384 */ 385 static inline uint16_t 386 rxq_burst_v(struct mlx5_rxq_data *rxq, struct rte_mbuf **pkts, uint16_t pkts_n, 387 uint64_t *err) 388 { 389 const uint16_t q_n = 1 << rxq->cqe_n; 390 const uint16_t q_mask = q_n - 1; 391 volatile struct mlx5_cqe *cq; 392 struct rte_mbuf **elts; 393 unsigned int pos; 394 uint64_t n; 395 uint16_t repl_n; 396 uint64_t comp_idx = MLX5_VPMD_DESCS_PER_LOOP; 397 uint16_t nocmp_n = 0; 398 uint16_t rcvd_pkt = 0; 399 unsigned int cq_idx = rxq->cq_ci & q_mask; 400 unsigned int elts_idx; 401 const uint16x4_t ownership = vdup_n_u16(!(rxq->cq_ci & (q_mask + 1))); 402 const uint16x4_t owner_check = vcreate_u16(0x0001000100010001); 403 const uint16x4_t opcode_check = vcreate_u16(0x00f000f000f000f0); 404 const uint16x4_t format_check = vcreate_u16(0x000c000c000c000c); 405 const uint16x4_t resp_err_check = vcreate_u16(0x00e000e000e000e0); 406 #ifdef MLX5_PMD_SOFT_COUNTERS 407 uint32_t rcvd_byte = 0; 408 #endif 409 /* Mask to generate 16B length vector. */ 410 const uint8x8_t len_shuf_m = { 411 52, 53, /* 4th CQE */ 412 36, 37, /* 3rd CQE */ 413 20, 21, /* 2nd CQE */ 414 4, 5 /* 1st CQE */ 415 }; 416 /* Mask to extract 16B data from a 64B CQE. */ 417 const uint8x16_t cqe_shuf_m = { 418 28, 29, /* hdr_type_etc */ 419 0, /* pkt_info */ 420 -1, /* null */ 421 47, 46, /* byte_cnt, bswap16 */ 422 31, 30, /* vlan_info, bswap16 */ 423 15, 14, 13, 12, /* rx_hash_res, bswap32 */ 424 57, 58, 59, /* flow_tag */ 425 63 /* op_own */ 426 }; 427 /* Mask to generate 16B data for mbuf. */ 428 const uint8x16_t mb_shuf_m = { 429 4, 5, -1, -1, /* pkt_len */ 430 4, 5, /* data_len */ 431 6, 7, /* vlan_tci */ 432 8, 9, 10, 11, /* hash.rss */ 433 12, 13, 14, -1 /* hash.fdir.hi */ 434 }; 435 /* Mask to generate 16B owner vector. */ 436 const uint8x8_t owner_shuf_m = { 437 63, -1, /* 4th CQE */ 438 47, -1, /* 3rd CQE */ 439 31, -1, /* 2nd CQE */ 440 15, -1 /* 1st CQE */ 441 }; 442 /* Mask to generate a vector having packet_type/ol_flags. */ 443 const uint8x16_t ptype_shuf_m = { 444 48, 49, 50, -1, /* 4th CQE */ 445 32, 33, 34, -1, /* 3rd CQE */ 446 16, 17, 18, -1, /* 2nd CQE */ 447 0, 1, 2, -1 /* 1st CQE */ 448 }; 449 /* Mask to generate a vector having flow tags. */ 450 const uint8x16_t ftag_shuf_m = { 451 60, 61, 62, -1, /* 4th CQE */ 452 44, 45, 46, -1, /* 3rd CQE */ 453 28, 29, 30, -1, /* 2nd CQE */ 454 12, 13, 14, -1 /* 1st CQE */ 455 }; 456 const uint16x8_t crc_adj = { 457 0, 0, rxq->crc_present * RTE_ETHER_CRC_LEN, 0, 0, 0, 0, 0 458 }; 459 const uint32x4_t flow_mark_adj = { 0, 0, 0, rxq->mark * (-1) }; 460 461 MLX5_ASSERT(rxq->sges_n == 0); 462 MLX5_ASSERT(rxq->cqe_n == rxq->elts_n); 463 cq = &(*rxq->cqes)[cq_idx]; 464 rte_prefetch_non_temporal(cq); 465 rte_prefetch_non_temporal(cq + 1); 466 rte_prefetch_non_temporal(cq + 2); 467 rte_prefetch_non_temporal(cq + 3); 468 pkts_n = RTE_MIN(pkts_n, MLX5_VPMD_RX_MAX_BURST); 469 repl_n = q_n - (rxq->rq_ci - rxq->rq_pi); 470 if (repl_n >= rxq->rq_repl_thresh) 471 mlx5_rx_replenish_bulk_mbuf(rxq, repl_n); 472 /* See if there're unreturned mbufs from compressed CQE. */ 473 rcvd_pkt = rxq->decompressed; 474 if (rcvd_pkt > 0) { 475 rcvd_pkt = RTE_MIN(rcvd_pkt, pkts_n); 476 rxq_copy_mbuf_v(rxq, pkts, rcvd_pkt); 477 rxq->rq_pi += rcvd_pkt; 478 pkts += rcvd_pkt; 479 rxq->decompressed -= rcvd_pkt; 480 } 481 elts_idx = rxq->rq_pi & q_mask; 482 elts = &(*rxq->elts)[elts_idx]; 483 /* Not to overflow pkts array. */ 484 pkts_n = RTE_ALIGN_FLOOR(pkts_n - rcvd_pkt, MLX5_VPMD_DESCS_PER_LOOP); 485 /* Not to cross queue end. */ 486 pkts_n = RTE_MIN(pkts_n, q_n - elts_idx); 487 pkts_n = RTE_MIN(pkts_n, q_n - cq_idx); 488 if (!pkts_n) 489 return rcvd_pkt; 490 /* At this point, there shouldn't be any remained packets. */ 491 MLX5_ASSERT(rxq->decompressed == 0); 492 /* 493 * Note that vectors have reverse order - {v3, v2, v1, v0}, because 494 * there's no instruction to count trailing zeros. __builtin_clzl() is 495 * used instead. 496 * 497 * A. copy 4 mbuf pointers from elts ring to returing pkts. 498 * B. load 64B CQE and extract necessary fields 499 * Final 16bytes cqes[] extracted from original 64bytes CQE has the 500 * following structure: 501 * struct { 502 * uint16_t hdr_type_etc; 503 * uint8_t pkt_info; 504 * uint8_t rsvd; 505 * uint16_t byte_cnt; 506 * uint16_t vlan_info; 507 * uint32_t rx_has_res; 508 * uint8_t flow_tag[3]; 509 * uint8_t op_own; 510 * } c; 511 * C. fill in mbuf. 512 * D. get valid CQEs. 513 * E. find compressed CQE. 514 */ 515 for (pos = 0; 516 pos < pkts_n; 517 pos += MLX5_VPMD_DESCS_PER_LOOP) { 518 uint16x4_t op_own; 519 uint16x4_t opcode, owner_mask, invalid_mask; 520 uint16x4_t comp_mask; 521 uint16x4_t mask; 522 uint16x4_t byte_cnt; 523 uint32x4_t ptype_info, flow_tag; 524 register uint64x2_t c0, c1, c2, c3; 525 uint8_t *p0, *p1, *p2, *p3; 526 uint8_t *e0 = (void *)&elts[pos]->pkt_len; 527 uint8_t *e1 = (void *)&elts[pos + 1]->pkt_len; 528 uint8_t *e2 = (void *)&elts[pos + 2]->pkt_len; 529 uint8_t *e3 = (void *)&elts[pos + 3]->pkt_len; 530 void *elts_p = (void *)&elts[pos]; 531 void *pkts_p = (void *)&pkts[pos]; 532 533 /* A.0 do not cross the end of CQ. */ 534 mask = vcreate_u16(pkts_n - pos < MLX5_VPMD_DESCS_PER_LOOP ? 535 -1UL >> ((pkts_n - pos) * 536 sizeof(uint16_t) * 8) : 0); 537 p0 = (void *)&cq[pos].pkt_info; 538 p1 = p0 + (pkts_n - pos > 1) * sizeof(struct mlx5_cqe); 539 p2 = p1 + (pkts_n - pos > 2) * sizeof(struct mlx5_cqe); 540 p3 = p2 + (pkts_n - pos > 3) * sizeof(struct mlx5_cqe); 541 /* B.0 (CQE 3) load a block having op_own. */ 542 c3 = vld1q_u64((uint64_t *)(p3 + 48)); 543 /* B.0 (CQE 2) load a block having op_own. */ 544 c2 = vld1q_u64((uint64_t *)(p2 + 48)); 545 /* B.0 (CQE 1) load a block having op_own. */ 546 c1 = vld1q_u64((uint64_t *)(p1 + 48)); 547 /* B.0 (CQE 0) load a block having op_own. */ 548 c0 = vld1q_u64((uint64_t *)(p0 + 48)); 549 /* Synchronize for loading the rest of blocks. */ 550 rte_cio_rmb(); 551 /* Prefetch next 4 CQEs. */ 552 if (pkts_n - pos >= 2 * MLX5_VPMD_DESCS_PER_LOOP) { 553 unsigned int next = pos + MLX5_VPMD_DESCS_PER_LOOP; 554 rte_prefetch_non_temporal(&cq[next]); 555 rte_prefetch_non_temporal(&cq[next + 1]); 556 rte_prefetch_non_temporal(&cq[next + 2]); 557 rte_prefetch_non_temporal(&cq[next + 3]); 558 } 559 __asm__ volatile ( 560 /* B.1 (CQE 3) load the rest of blocks. */ 561 "ld1 {v16.16b - v18.16b}, [%[p3]] \n\t" 562 /* B.2 (CQE 3) move the block having op_own. */ 563 "mov v19.16b, %[c3].16b \n\t" 564 /* B.3 (CQE 3) extract 16B fields. */ 565 "tbl v23.16b, {v16.16b - v19.16b}, %[cqe_shuf_m].16b \n\t" 566 /* B.1 (CQE 2) load the rest of blocks. */ 567 "ld1 {v16.16b - v18.16b}, [%[p2]] \n\t" 568 /* B.4 (CQE 3) adjust CRC length. */ 569 "sub v23.8h, v23.8h, %[crc_adj].8h \n\t" 570 /* C.1 (CQE 3) generate final structure for mbuf. */ 571 "tbl v15.16b, {v23.16b}, %[mb_shuf_m].16b \n\t" 572 /* B.2 (CQE 2) move the block having op_own. */ 573 "mov v19.16b, %[c2].16b \n\t" 574 /* B.3 (CQE 2) extract 16B fields. */ 575 "tbl v22.16b, {v16.16b - v19.16b}, %[cqe_shuf_m].16b \n\t" 576 /* B.1 (CQE 1) load the rest of blocks. */ 577 "ld1 {v16.16b - v18.16b}, [%[p1]] \n\t" 578 /* B.4 (CQE 2) adjust CRC length. */ 579 "sub v22.8h, v22.8h, %[crc_adj].8h \n\t" 580 /* C.1 (CQE 2) generate final structure for mbuf. */ 581 "tbl v14.16b, {v22.16b}, %[mb_shuf_m].16b \n\t" 582 /* B.2 (CQE 1) move the block having op_own. */ 583 "mov v19.16b, %[c1].16b \n\t" 584 /* B.3 (CQE 1) extract 16B fields. */ 585 "tbl v21.16b, {v16.16b - v19.16b}, %[cqe_shuf_m].16b \n\t" 586 /* B.1 (CQE 0) load the rest of blocks. */ 587 "ld1 {v16.16b - v18.16b}, [%[p0]] \n\t" 588 /* B.4 (CQE 1) adjust CRC length. */ 589 "sub v21.8h, v21.8h, %[crc_adj].8h \n\t" 590 /* C.1 (CQE 1) generate final structure for mbuf. */ 591 "tbl v13.16b, {v21.16b}, %[mb_shuf_m].16b \n\t" 592 /* B.2 (CQE 0) move the block having op_own. */ 593 "mov v19.16b, %[c0].16b \n\t" 594 /* A.1 load mbuf pointers. */ 595 "ld1 {v24.2d - v25.2d}, [%[elts_p]] \n\t" 596 /* B.3 (CQE 0) extract 16B fields. */ 597 "tbl v20.16b, {v16.16b - v19.16b}, %[cqe_shuf_m].16b \n\t" 598 /* B.4 (CQE 0) adjust CRC length. */ 599 "sub v20.8h, v20.8h, %[crc_adj].8h \n\t" 600 /* D.1 extract op_own byte. */ 601 "tbl %[op_own].8b, {v20.16b - v23.16b}, %[owner_shuf_m].8b \n\t" 602 /* C.2 (CQE 3) adjust flow mark. */ 603 "add v15.4s, v15.4s, %[flow_mark_adj].4s \n\t" 604 /* C.3 (CQE 3) fill in mbuf - rx_descriptor_fields1. */ 605 "st1 {v15.2d}, [%[e3]] \n\t" 606 /* C.2 (CQE 2) adjust flow mark. */ 607 "add v14.4s, v14.4s, %[flow_mark_adj].4s \n\t" 608 /* C.3 (CQE 2) fill in mbuf - rx_descriptor_fields1. */ 609 "st1 {v14.2d}, [%[e2]] \n\t" 610 /* C.1 (CQE 0) generate final structure for mbuf. */ 611 "tbl v12.16b, {v20.16b}, %[mb_shuf_m].16b \n\t" 612 /* C.2 (CQE 1) adjust flow mark. */ 613 "add v13.4s, v13.4s, %[flow_mark_adj].4s \n\t" 614 /* C.3 (CQE 1) fill in mbuf - rx_descriptor_fields1. */ 615 "st1 {v13.2d}, [%[e1]] \n\t" 616 #ifdef MLX5_PMD_SOFT_COUNTERS 617 /* Extract byte_cnt. */ 618 "tbl %[byte_cnt].8b, {v20.16b - v23.16b}, %[len_shuf_m].8b \n\t" 619 #endif 620 /* Extract ptype_info. */ 621 "tbl %[ptype_info].16b, {v20.16b - v23.16b}, %[ptype_shuf_m].16b \n\t" 622 /* Extract flow_tag. */ 623 "tbl %[flow_tag].16b, {v20.16b - v23.16b}, %[ftag_shuf_m].16b \n\t" 624 /* A.2 copy mbuf pointers. */ 625 "st1 {v24.2d - v25.2d}, [%[pkts_p]] \n\t" 626 /* C.2 (CQE 0) adjust flow mark. */ 627 "add v12.4s, v12.4s, %[flow_mark_adj].4s \n\t" 628 /* C.3 (CQE 1) fill in mbuf - rx_descriptor_fields1. */ 629 "st1 {v12.2d}, [%[e0]] \n\t" 630 :[op_own]"=&w"(op_own), 631 [byte_cnt]"=&w"(byte_cnt), 632 [ptype_info]"=&w"(ptype_info), 633 [flow_tag]"=&w"(flow_tag) 634 :[p3]"r"(p3), [p2]"r"(p2), [p1]"r"(p1), [p0]"r"(p0), 635 [e3]"r"(e3), [e2]"r"(e2), [e1]"r"(e1), [e0]"r"(e0), 636 [c3]"w"(c3), [c2]"w"(c2), [c1]"w"(c1), [c0]"w"(c0), 637 [elts_p]"r"(elts_p), 638 [pkts_p]"r"(pkts_p), 639 [cqe_shuf_m]"w"(cqe_shuf_m), 640 [mb_shuf_m]"w"(mb_shuf_m), 641 [owner_shuf_m]"w"(owner_shuf_m), 642 [len_shuf_m]"w"(len_shuf_m), 643 [ptype_shuf_m]"w"(ptype_shuf_m), 644 [ftag_shuf_m]"w"(ftag_shuf_m), 645 [crc_adj]"w"(crc_adj), 646 [flow_mark_adj]"w"(flow_mark_adj) 647 :"memory", 648 "v12", "v13", "v14", "v15", 649 "v16", "v17", "v18", "v19", 650 "v20", "v21", "v22", "v23", 651 "v24", "v25"); 652 /* D.2 flip owner bit to mark CQEs from last round. */ 653 owner_mask = vand_u16(op_own, owner_check); 654 owner_mask = vceq_u16(owner_mask, ownership); 655 /* D.3 get mask for invalidated CQEs. */ 656 opcode = vand_u16(op_own, opcode_check); 657 invalid_mask = vceq_u16(opcode_check, opcode); 658 /* E.1 find compressed CQE format. */ 659 comp_mask = vand_u16(op_own, format_check); 660 comp_mask = vceq_u16(comp_mask, format_check); 661 /* D.4 mask out beyond boundary. */ 662 invalid_mask = vorr_u16(invalid_mask, mask); 663 /* D.5 merge invalid_mask with invalid owner. */ 664 invalid_mask = vorr_u16(invalid_mask, owner_mask); 665 /* E.2 mask out invalid entries. */ 666 comp_mask = vbic_u16(comp_mask, invalid_mask); 667 /* E.3 get the first compressed CQE. */ 668 comp_idx = __builtin_clzl(vget_lane_u64(vreinterpret_u64_u16( 669 comp_mask), 0)) / 670 (sizeof(uint16_t) * 8); 671 /* D.6 mask out entries after the compressed CQE. */ 672 mask = vcreate_u16(comp_idx < MLX5_VPMD_DESCS_PER_LOOP ? 673 -1UL >> (comp_idx * sizeof(uint16_t) * 8) : 674 0); 675 invalid_mask = vorr_u16(invalid_mask, mask); 676 /* D.7 count non-compressed valid CQEs. */ 677 n = __builtin_clzl(vget_lane_u64(vreinterpret_u64_u16( 678 invalid_mask), 0)) / (sizeof(uint16_t) * 8); 679 nocmp_n += n; 680 /* D.2 get the final invalid mask. */ 681 mask = vcreate_u16(n < MLX5_VPMD_DESCS_PER_LOOP ? 682 -1UL >> (n * sizeof(uint16_t) * 8) : 0); 683 invalid_mask = vorr_u16(invalid_mask, mask); 684 /* D.3 check error in opcode. */ 685 opcode = vceq_u16(resp_err_check, opcode); 686 opcode = vbic_u16(opcode, invalid_mask); 687 /* D.4 mark if any error is set */ 688 *err |= vget_lane_u64(vreinterpret_u64_u16(opcode), 0); 689 /* C.4 fill in mbuf - rearm_data and packet_type. */ 690 rxq_cq_to_ptype_oflags_v(rxq, ptype_info, flow_tag, 691 opcode, &elts[pos]); 692 if (rxq->hw_timestamp) { 693 elts[pos]->timestamp = 694 rte_be_to_cpu_64( 695 container_of(p0, struct mlx5_cqe, 696 pkt_info)->timestamp); 697 elts[pos + 1]->timestamp = 698 rte_be_to_cpu_64( 699 container_of(p1, struct mlx5_cqe, 700 pkt_info)->timestamp); 701 elts[pos + 2]->timestamp = 702 rte_be_to_cpu_64( 703 container_of(p2, struct mlx5_cqe, 704 pkt_info)->timestamp); 705 elts[pos + 3]->timestamp = 706 rte_be_to_cpu_64( 707 container_of(p3, struct mlx5_cqe, 708 pkt_info)->timestamp); 709 } 710 if (!!rxq->flow_meta_mask) { 711 /* This code is subject for futher optimization. */ 712 int32_t offs = rxq->flow_meta_offset; 713 714 *RTE_MBUF_DYNFIELD(pkts[pos], offs, uint32_t *) = 715 container_of(p0, struct mlx5_cqe, 716 pkt_info)->flow_table_metadata; 717 *RTE_MBUF_DYNFIELD(pkts[pos], offs, uint32_t *) = 718 container_of(p1, struct mlx5_cqe, 719 pkt_info)->flow_table_metadata; 720 *RTE_MBUF_DYNFIELD(pkts[pos], offs, uint32_t *) = 721 container_of(p2, struct mlx5_cqe, 722 pkt_info)->flow_table_metadata; 723 *RTE_MBUF_DYNFIELD(pkts[pos], offs, uint32_t *) = 724 container_of(p3, struct mlx5_cqe, 725 pkt_info)->flow_table_metadata; 726 if (*RTE_MBUF_DYNFIELD(pkts[pos], offs, uint32_t *)) 727 elts[pos]->ol_flags |= rxq->flow_meta_mask; 728 if (*RTE_MBUF_DYNFIELD(pkts[pos + 1], offs, uint32_t *)) 729 elts[pos + 1]->ol_flags |= rxq->flow_meta_mask; 730 if (*RTE_MBUF_DYNFIELD(pkts[pos + 2], offs, uint32_t *)) 731 elts[pos + 2]->ol_flags |= rxq->flow_meta_mask; 732 if (*RTE_MBUF_DYNFIELD(pkts[pos + 3], offs, uint32_t *)) 733 elts[pos + 3]->ol_flags |= rxq->flow_meta_mask; 734 } 735 #ifdef MLX5_PMD_SOFT_COUNTERS 736 /* Add up received bytes count. */ 737 byte_cnt = vbic_u16(byte_cnt, invalid_mask); 738 rcvd_byte += vget_lane_u64(vpaddl_u32(vpaddl_u16(byte_cnt)), 0); 739 #endif 740 /* 741 * Break the loop unless more valid CQE is expected, or if 742 * there's a compressed CQE. 743 */ 744 if (n != MLX5_VPMD_DESCS_PER_LOOP) 745 break; 746 } 747 /* If no new CQE seen, return without updating cq_db. */ 748 if (unlikely(!nocmp_n && comp_idx == MLX5_VPMD_DESCS_PER_LOOP)) 749 return rcvd_pkt; 750 /* Update the consumer indexes for non-compressed CQEs. */ 751 MLX5_ASSERT(nocmp_n <= pkts_n); 752 rxq->cq_ci += nocmp_n; 753 rxq->rq_pi += nocmp_n; 754 rcvd_pkt += nocmp_n; 755 #ifdef MLX5_PMD_SOFT_COUNTERS 756 rxq->stats.ipackets += nocmp_n; 757 rxq->stats.ibytes += rcvd_byte; 758 #endif 759 /* Decompress the last CQE if compressed. */ 760 if (comp_idx < MLX5_VPMD_DESCS_PER_LOOP && comp_idx == n) { 761 MLX5_ASSERT(comp_idx == (nocmp_n % MLX5_VPMD_DESCS_PER_LOOP)); 762 rxq->decompressed = rxq_cq_decompress_v(rxq, &cq[nocmp_n], 763 &elts[nocmp_n]); 764 /* Return more packets if needed. */ 765 if (nocmp_n < pkts_n) { 766 uint16_t n = rxq->decompressed; 767 768 n = RTE_MIN(n, pkts_n - nocmp_n); 769 rxq_copy_mbuf_v(rxq, &pkts[nocmp_n], n); 770 rxq->rq_pi += n; 771 rcvd_pkt += n; 772 rxq->decompressed -= n; 773 } 774 } 775 rte_cio_wmb(); 776 *rxq->cq_db = rte_cpu_to_be_32(rxq->cq_ci); 777 return rcvd_pkt; 778 } 779 780 #endif /* RTE_PMD_MLX5_RXTX_VEC_NEON_H_ */ 781