1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2017 6WIND S.A. 3 * Copyright 2017 Mellanox Technologies, Ltd 4 */ 5 6 #ifndef RTE_PMD_MLX5_RXTX_VEC_NEON_H_ 7 #define RTE_PMD_MLX5_RXTX_VEC_NEON_H_ 8 9 #include <stdint.h> 10 #include <string.h> 11 #include <stdlib.h> 12 #include <arm_neon.h> 13 14 #include <rte_bitops.h> 15 #include <rte_mbuf.h> 16 #include <rte_mempool.h> 17 #include <rte_prefetch.h> 18 19 #include <mlx5_prm.h> 20 21 #include "mlx5_defs.h" 22 #include "mlx5.h" 23 #include "mlx5_utils.h" 24 #include "mlx5_rxtx.h" 25 #include "mlx5_rxtx_vec.h" 26 #include "mlx5_autoconf.h" 27 28 /** 29 * Store free buffers to RX SW ring. 30 * 31 * @param elts 32 * Pointer to SW ring to be filled. 33 * @param pkts 34 * Pointer to array of packets to be stored. 35 * @param pkts_n 36 * Number of packets to be stored. 37 */ 38 static inline void 39 rxq_copy_mbuf_v(struct rte_mbuf **elts, struct rte_mbuf **pkts, uint16_t n) 40 { 41 unsigned int pos; 42 uint16_t p = n & -2; 43 44 for (pos = 0; pos < p; pos += 2) { 45 uint64x2_t mbp; 46 47 mbp = vld1q_u64((void *)&elts[pos]); 48 vst1q_u64((void *)&pkts[pos], mbp); 49 } 50 if (n & 1) 51 pkts[pos] = elts[pos]; 52 } 53 54 /** 55 * Decompress a compressed completion and fill in mbufs in RX SW ring with data 56 * extracted from the title completion descriptor. 57 * 58 * @param rxq 59 * Pointer to RX queue structure. 60 * @param cq 61 * Pointer to completion array having a compressed completion at first. 62 * @param elts 63 * Pointer to SW ring to be filled. The first mbuf has to be pre-built from 64 * the title completion descriptor to be copied to the rest of mbufs. 65 * @param keep 66 * Keep unzipping if the next CQE is the miniCQE array. 67 * 68 * @return 69 * Number of mini-CQEs successfully decompressed. 70 */ 71 static inline uint16_t 72 rxq_cq_decompress_v(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cq, 73 struct rte_mbuf **elts, bool keep) 74 { 75 volatile struct mlx5_mini_cqe8 *mcq = 76 (volatile struct mlx5_mini_cqe8 *)&(cq + !rxq->cqe_comp_layout)->pkt_info; 77 /* Title packet is pre-built. */ 78 struct rte_mbuf *t_pkt = rxq->cqe_comp_layout ? &rxq->title_pkt : elts[0]; 79 unsigned int pos; 80 unsigned int i; 81 unsigned int inv = 0; 82 /* Mask to shuffle from extracted mini CQE to mbuf. */ 83 const uint8x16_t mcqe_shuf_m1 = { 84 -1, -1, -1, -1, /* skip packet_type */ 85 7, 6, -1, -1, /* pkt_len, bswap16 */ 86 7, 6, /* data_len, bswap16 */ 87 -1, -1, /* skip vlan_tci */ 88 3, 2, 1, 0 /* hash.rss, bswap32 */ 89 }; 90 const uint8x16_t mcqe_shuf_m2 = { 91 -1, -1, -1, -1, /* skip packet_type */ 92 15, 14, -1, -1, /* pkt_len, bswap16 */ 93 15, 14, /* data_len, bswap16 */ 94 -1, -1, /* skip vlan_tci */ 95 11, 10, 9, 8 /* hash.rss, bswap32 */ 96 }; 97 /* Restore the compressed count. Must be 16 bits. */ 98 uint16_t mcqe_n = (rxq->cqe_comp_layout) ? 99 (MLX5_CQE_NUM_MINIS(cq->op_own) + 1U) : rte_be_to_cpu_32(cq->byte_cnt); 100 uint16_t pkts_n = mcqe_n; 101 const uint64x2_t rearm = 102 vld1q_u64((void *)&t_pkt->rearm_data); 103 const uint32x4_t rxdf_mask = { 104 0xffffffff, /* packet_type */ 105 0, /* skip pkt_len */ 106 0xffff0000, /* vlan_tci, skip data_len */ 107 0, /* skip hash.rss */ 108 }; 109 const uint8x16_t rxdf = 110 vandq_u8(vld1q_u8((void *)&t_pkt->rx_descriptor_fields1), 111 vreinterpretq_u8_u32(rxdf_mask)); 112 const uint16x8_t crc_adj = { 113 0, 0, 114 rxq->crc_present * RTE_ETHER_CRC_LEN, 0, 115 rxq->crc_present * RTE_ETHER_CRC_LEN, 0, 116 0, 0 117 }; 118 uint32x4_t ol_flags = {0, 0, 0, 0}; 119 uint32x4_t ol_flags_mask = {0, 0, 0, 0}; 120 #ifdef MLX5_PMD_SOFT_COUNTERS 121 uint32_t rcvd_byte = 0; 122 #endif 123 /* Mask to shuffle byte_cnt to add up stats. Do bswap16 for all. */ 124 const uint8x8_t len_shuf_m = { 125 7, 6, /* 1st mCQE */ 126 15, 14, /* 2nd mCQE */ 127 23, 22, /* 3rd mCQE */ 128 31, 30 /* 4th mCQE */ 129 }; 130 131 /* 132 * A. load mCQEs into a 128bit register. 133 * B. store rearm data to mbuf. 134 * C. combine data from mCQEs with rx_descriptor_fields1. 135 * D. store rx_descriptor_fields1. 136 * E. store flow tag (rte_flow mark). 137 */ 138 cycle: 139 if (rxq->cqe_comp_layout) 140 rte_prefetch0((volatile void *)(cq + mcqe_n)); 141 for (pos = 0; pos < mcqe_n; ) { 142 uint8_t *p = RTE_CAST_PTR(uint8_t *, &mcq[pos % 8]); 143 uint8_t *e0 = (void *)&elts[pos]->rearm_data; 144 uint8_t *e1 = (void *)&elts[pos + 1]->rearm_data; 145 uint8_t *e2 = (void *)&elts[pos + 2]->rearm_data; 146 uint8_t *e3 = (void *)&elts[pos + 3]->rearm_data; 147 uint16x4_t byte_cnt; 148 #ifdef MLX5_PMD_SOFT_COUNTERS 149 uint16x4_t invalid_mask = 150 vcreate_u16(mcqe_n - pos < MLX5_VPMD_DESCS_PER_LOOP ? 151 -1UL << ((mcqe_n - pos) * 152 sizeof(uint16_t) * 8) : 0); 153 #endif 154 155 if (!rxq->cqe_comp_layout) 156 for (i = 0; i < MLX5_VPMD_DESCS_PER_LOOP; ++i) 157 if (likely(pos + i < mcqe_n)) 158 rte_prefetch0((volatile void *)(cq + pos + i)); 159 __asm__ volatile ( 160 /* A.1 load mCQEs into a 128bit register. */ 161 "ld1 {v16.16b - v17.16b}, [%[mcq]] \n\t" 162 /* B.1 store rearm data to mbuf. */ 163 "st1 {%[rearm].2d}, [%[e0]] \n\t" 164 "add %[e0], %[e0], #16 \n\t" 165 "st1 {%[rearm].2d}, [%[e1]] \n\t" 166 "add %[e1], %[e1], #16 \n\t" 167 /* C.1 combine data from mCQEs with rx_descriptor_fields1. */ 168 "tbl v18.16b, {v16.16b}, %[mcqe_shuf_m1].16b \n\t" 169 "tbl v19.16b, {v16.16b}, %[mcqe_shuf_m2].16b \n\t" 170 "sub v18.8h, v18.8h, %[crc_adj].8h \n\t" 171 "sub v19.8h, v19.8h, %[crc_adj].8h \n\t" 172 "orr v18.16b, v18.16b, %[rxdf].16b \n\t" 173 "orr v19.16b, v19.16b, %[rxdf].16b \n\t" 174 /* D.1 store rx_descriptor_fields1. */ 175 "st1 {v18.2d}, [%[e0]] \n\t" 176 "st1 {v19.2d}, [%[e1]] \n\t" 177 /* B.1 store rearm data to mbuf. */ 178 "st1 {%[rearm].2d}, [%[e2]] \n\t" 179 "add %[e2], %[e2], #16 \n\t" 180 "st1 {%[rearm].2d}, [%[e3]] \n\t" 181 "add %[e3], %[e3], #16 \n\t" 182 /* C.1 combine data from mCQEs with rx_descriptor_fields1. */ 183 "tbl v18.16b, {v17.16b}, %[mcqe_shuf_m1].16b \n\t" 184 "tbl v19.16b, {v17.16b}, %[mcqe_shuf_m2].16b \n\t" 185 "sub v18.8h, v18.8h, %[crc_adj].8h \n\t" 186 "sub v19.8h, v19.8h, %[crc_adj].8h \n\t" 187 "orr v18.16b, v18.16b, %[rxdf].16b \n\t" 188 "orr v19.16b, v19.16b, %[rxdf].16b \n\t" 189 /* D.1 store rx_descriptor_fields1. */ 190 "st1 {v18.2d}, [%[e2]] \n\t" 191 "st1 {v19.2d}, [%[e3]] \n\t" 192 #ifdef MLX5_PMD_SOFT_COUNTERS 193 "tbl %[byte_cnt].8b, {v16.16b - v17.16b}, %[len_shuf_m].8b \n\t" 194 #endif 195 :[byte_cnt]"=&w"(byte_cnt) 196 :[mcq]"r"(p), 197 [rxdf]"w"(rxdf), 198 [rearm]"w"(rearm), 199 [e3]"r"(e3), [e2]"r"(e2), [e1]"r"(e1), [e0]"r"(e0), 200 [mcqe_shuf_m1]"w"(mcqe_shuf_m1), 201 [mcqe_shuf_m2]"w"(mcqe_shuf_m2), 202 [crc_adj]"w"(crc_adj), 203 [len_shuf_m]"w"(len_shuf_m) 204 :"memory", "v16", "v17", "v18", "v19"); 205 #ifdef MLX5_PMD_SOFT_COUNTERS 206 byte_cnt = vbic_u16(byte_cnt, invalid_mask); 207 rcvd_byte += vget_lane_u64(vpaddl_u32(vpaddl_u16(byte_cnt)), 0); 208 #endif 209 if (rxq->mark) { 210 if (rxq->mcqe_format != 211 MLX5_CQE_RESP_FORMAT_FTAG_STRIDX) { 212 const uint32_t flow_tag = t_pkt->hash.fdir.hi; 213 214 /* E.1 store flow tag (rte_flow mark). */ 215 elts[pos]->hash.fdir.hi = flow_tag; 216 elts[pos + 1]->hash.fdir.hi = flow_tag; 217 elts[pos + 2]->hash.fdir.hi = flow_tag; 218 elts[pos + 3]->hash.fdir.hi = flow_tag; 219 } else { 220 const uint32x4_t flow_mark_adj = { 221 -1, -1, -1, -1 }; 222 const uint8x16_t flow_mark_shuf = { 223 28, 24, 25, -1, 224 20, 16, 17, -1, 225 12, 8, 9, -1, 226 4, 0, 1, -1}; 227 /* Extract flow_tag field. */ 228 const uint32x4_t ft_mask = 229 vdupq_n_u32(MLX5_FLOW_MARK_DEFAULT); 230 const uint32x4_t fdir_flags = 231 vdupq_n_u32(RTE_MBUF_F_RX_FDIR); 232 const uint32x4_t fdir_all_flags = 233 vdupq_n_u32(RTE_MBUF_F_RX_FDIR | 234 rxq->mark_flag); 235 uint32x4_t fdir_id_flags = 236 vdupq_n_u32(rxq->mark_flag); 237 uint32x4_t invalid_mask, ftag; 238 239 __asm__ volatile 240 /* A.1 load mCQEs into a 128bit register. */ 241 ("ld1 {v16.16b - v17.16b}, [%[mcq]]\n\t" 242 /* Extract flow_tag. */ 243 "tbl %[ftag].16b, {v16.16b - v17.16b}, %[flow_mark_shuf].16b\n\t" 244 : [ftag]"=&w"(ftag) 245 : [mcq]"r"(p), 246 [flow_mark_shuf]"w"(flow_mark_shuf) 247 : "memory", "v16", "v17"); 248 invalid_mask = vceqzq_u32(ftag); 249 ol_flags_mask = vorrq_u32(ol_flags_mask, 250 fdir_all_flags); 251 /* Set RTE_MBUF_F_RX_FDIR if flow tag is non-zero. */ 252 ol_flags = vorrq_u32(ol_flags, 253 vbicq_u32(fdir_flags, invalid_mask)); 254 /* Mask out invalid entries. */ 255 fdir_id_flags = vbicq_u32(fdir_id_flags, 256 invalid_mask); 257 /* Check if flow tag MLX5_FLOW_MARK_DEFAULT. */ 258 ol_flags = vorrq_u32(ol_flags, 259 vbicq_u32(fdir_id_flags, 260 vceqq_u32(ftag, ft_mask))); 261 ftag = vaddq_u32(ftag, flow_mark_adj); 262 elts[pos]->hash.fdir.hi = 263 vgetq_lane_u32(ftag, 3); 264 elts[pos + 1]->hash.fdir.hi = 265 vgetq_lane_u32(ftag, 2); 266 elts[pos + 2]->hash.fdir.hi = 267 vgetq_lane_u32(ftag, 1); 268 elts[pos + 3]->hash.fdir.hi = 269 vgetq_lane_u32(ftag, 0); 270 } 271 } 272 if (unlikely(rxq->mcqe_format != 273 MLX5_CQE_RESP_FORMAT_HASH)) { 274 if (rxq->mcqe_format == 275 MLX5_CQE_RESP_FORMAT_L34H_STRIDX) { 276 const uint8_t pkt_info = 277 (cq->pkt_info & 0x3) << 6; 278 const uint8_t pkt_hdr0 = 279 mcq[pos % 8].hdr_type; 280 const uint8_t pkt_hdr1 = 281 mcq[pos % 8 + 1].hdr_type; 282 const uint8_t pkt_hdr2 = 283 mcq[pos % 8 + 2].hdr_type; 284 const uint8_t pkt_hdr3 = 285 mcq[pos % 8 + 3].hdr_type; 286 const uint32x4_t vlan_mask = 287 vdupq_n_u32(RTE_MBUF_F_RX_VLAN | 288 RTE_MBUF_F_RX_VLAN_STRIPPED); 289 const uint32x4_t cv_mask = 290 vdupq_n_u32(MLX5_CQE_VLAN_STRIPPED); 291 const uint32x4_t pkt_cv = { 292 pkt_hdr0 & 0x1, pkt_hdr1 & 0x1, 293 pkt_hdr2 & 0x1, pkt_hdr3 & 0x1}; 294 295 ol_flags_mask = vorrq_u32(ol_flags_mask, 296 vlan_mask); 297 ol_flags = vorrq_u32(ol_flags, 298 vandq_u32(vlan_mask, 299 vceqq_u32(pkt_cv, cv_mask))); 300 elts[pos]->packet_type = 301 mlx5_ptype_table[(pkt_hdr0 >> 2) | 302 pkt_info]; 303 elts[pos + 1]->packet_type = 304 mlx5_ptype_table[(pkt_hdr1 >> 2) | 305 pkt_info]; 306 elts[pos + 2]->packet_type = 307 mlx5_ptype_table[(pkt_hdr2 >> 2) | 308 pkt_info]; 309 elts[pos + 3]->packet_type = 310 mlx5_ptype_table[(pkt_hdr3 >> 2) | 311 pkt_info]; 312 if (rxq->tunnel) { 313 elts[pos]->packet_type |= 314 !!(((pkt_hdr0 >> 2) | 315 pkt_info) & (1 << 6)); 316 elts[pos + 1]->packet_type |= 317 !!(((pkt_hdr1 >> 2) | 318 pkt_info) & (1 << 6)); 319 elts[pos + 2]->packet_type |= 320 !!(((pkt_hdr2 >> 2) | 321 pkt_info) & (1 << 6)); 322 elts[pos + 3]->packet_type |= 323 !!(((pkt_hdr3 >> 2) | 324 pkt_info) & (1 << 6)); 325 } 326 } 327 const uint32x4_t hash_flags = 328 vdupq_n_u32(RTE_MBUF_F_RX_RSS_HASH); 329 const uint32x4_t rearm_flags = 330 vdupq_n_u32((uint32_t)t_pkt->ol_flags); 331 332 ol_flags_mask = vorrq_u32(ol_flags_mask, hash_flags); 333 ol_flags = vorrq_u32(ol_flags, 334 vbicq_u32(rearm_flags, ol_flags_mask)); 335 elts[pos]->ol_flags = vgetq_lane_u32(ol_flags, 3); 336 elts[pos + 1]->ol_flags = vgetq_lane_u32(ol_flags, 2); 337 elts[pos + 2]->ol_flags = vgetq_lane_u32(ol_flags, 1); 338 elts[pos + 3]->ol_flags = vgetq_lane_u32(ol_flags, 0); 339 elts[pos]->hash.rss = 0; 340 elts[pos + 1]->hash.rss = 0; 341 elts[pos + 2]->hash.rss = 0; 342 elts[pos + 3]->hash.rss = 0; 343 } 344 if (rxq->dynf_meta) { 345 int32_t offs = rxq->flow_meta_offset; 346 const uint32_t meta = 347 *RTE_MBUF_DYNFIELD(t_pkt, offs, uint32_t *); 348 349 /* Check if title packet has valid metadata. */ 350 if (meta) { 351 MLX5_ASSERT(t_pkt->ol_flags & 352 rxq->flow_meta_mask); 353 *RTE_MBUF_DYNFIELD(elts[pos], offs, 354 uint32_t *) = meta; 355 *RTE_MBUF_DYNFIELD(elts[pos + 1], offs, 356 uint32_t *) = meta; 357 *RTE_MBUF_DYNFIELD(elts[pos + 2], offs, 358 uint32_t *) = meta; 359 *RTE_MBUF_DYNFIELD(elts[pos + 3], offs, 360 uint32_t *) = meta; 361 } 362 } 363 pos += MLX5_VPMD_DESCS_PER_LOOP; 364 /* Move to next CQE and invalidate consumed CQEs. */ 365 if (!rxq->cqe_comp_layout) { 366 if (!(pos & 0x7) && pos < mcqe_n) { 367 if (pos + 8 < mcqe_n) 368 rte_prefetch0((volatile void *)(cq + pos + 8)); 369 mcq = (volatile struct mlx5_mini_cqe8 *)&(cq + pos)->pkt_info; 370 for (i = 0; i < 8; ++i) 371 cq[inv++].op_own = MLX5_CQE_INVALIDATE; 372 } 373 } 374 } 375 if (rxq->cqe_comp_layout && keep) { 376 int ret; 377 /* Keep unzipping if the next CQE is the miniCQE array. */ 378 cq = &cq[mcqe_n]; 379 ret = check_cqe_iteration(cq, rxq->cqe_n, rxq->cq_ci + pkts_n); 380 if (ret == MLX5_CQE_STATUS_SW_OWN && 381 MLX5_CQE_FORMAT(cq->op_own) == MLX5_COMPRESSED) { 382 pos = 0; 383 elts = &elts[mcqe_n]; 384 mcq = (volatile struct mlx5_mini_cqe8 *)cq; 385 mcqe_n = MLX5_CQE_NUM_MINIS(cq->op_own) + 1; 386 pkts_n += mcqe_n; 387 goto cycle; 388 } 389 } else { 390 /* Invalidate the rest of CQEs. */ 391 for (; inv < pkts_n; ++inv) 392 cq[inv].op_own = MLX5_CQE_INVALIDATE; 393 } 394 #ifdef MLX5_PMD_SOFT_COUNTERS 395 rxq->stats.ipackets += pkts_n; 396 rxq->stats.ibytes += rcvd_byte; 397 #endif 398 return pkts_n; 399 } 400 401 /** 402 * Calculate packet type and offload flag for mbuf and store it. 403 * 404 * @param rxq 405 * Pointer to RX queue structure. 406 * @param ptype_info 407 * Array of four 4bytes packet type info extracted from the original 408 * completion descriptor. 409 * @param flow_tag 410 * Array of four 4bytes flow ID extracted from the original completion 411 * descriptor. 412 * @param op_err 413 * Opcode vector having responder error status. Each field is 4B. 414 * @param pkts 415 * Pointer to array of packets to be filled. 416 */ 417 static inline void 418 rxq_cq_to_ptype_oflags_v(struct mlx5_rxq_data *rxq, 419 uint32x4_t ptype_info, uint32x4_t flow_tag, 420 uint16x4_t op_err, struct rte_mbuf **pkts) 421 { 422 uint16x4_t ptype; 423 uint32x4_t pinfo, cv_flags; 424 uint32x4_t ol_flags = 425 vdupq_n_u32(rxq->rss_hash * RTE_MBUF_F_RX_RSS_HASH | 426 rxq->hw_timestamp * rxq->timestamp_rx_flag); 427 const uint32x4_t ptype_ol_mask = { 0x106, 0x106, 0x106, 0x106 }; 428 const uint8x16_t cv_flag_sel = { 429 0, 430 (uint8_t)(RTE_MBUF_F_RX_VLAN | RTE_MBUF_F_RX_VLAN_STRIPPED), 431 (uint8_t)(RTE_MBUF_F_RX_IP_CKSUM_GOOD >> 1), 432 0, 433 (uint8_t)(RTE_MBUF_F_RX_L4_CKSUM_GOOD >> 1), 434 0, 435 (uint8_t)((RTE_MBUF_F_RX_IP_CKSUM_GOOD | RTE_MBUF_F_RX_L4_CKSUM_GOOD) >> 1), 436 0, 0, 0, 0, 0, 0, 0, 0, 0 437 }; 438 const uint32x4_t cv_mask = 439 vdupq_n_u32(RTE_MBUF_F_RX_IP_CKSUM_GOOD | RTE_MBUF_F_RX_L4_CKSUM_GOOD | 440 RTE_MBUF_F_RX_VLAN | RTE_MBUF_F_RX_VLAN_STRIPPED); 441 const uint64x2_t mbuf_init = vld1q_u64 442 ((const uint64_t *)&rxq->mbuf_initializer); 443 uint64x2_t rearm0, rearm1, rearm2, rearm3; 444 uint8_t pt_idx0, pt_idx1, pt_idx2, pt_idx3; 445 446 if (rxq->mark) { 447 const uint32x4_t ft_def = vdupq_n_u32(MLX5_FLOW_MARK_DEFAULT); 448 const uint32x4_t fdir_flags = vdupq_n_u32(RTE_MBUF_F_RX_FDIR); 449 uint32x4_t fdir_id_flags = vdupq_n_u32(rxq->mark_flag); 450 uint32x4_t invalid_mask; 451 452 /* Check if flow tag is non-zero then set RTE_MBUF_F_RX_FDIR. */ 453 invalid_mask = vceqzq_u32(flow_tag); 454 ol_flags = vorrq_u32(ol_flags, 455 vbicq_u32(fdir_flags, invalid_mask)); 456 /* Mask out invalid entries. */ 457 fdir_id_flags = vbicq_u32(fdir_id_flags, invalid_mask); 458 /* Check if flow tag MLX5_FLOW_MARK_DEFAULT. */ 459 ol_flags = vorrq_u32(ol_flags, 460 vbicq_u32(fdir_id_flags, 461 vceqq_u32(flow_tag, ft_def))); 462 } 463 /* 464 * ptype_info has the following: 465 * bit[1] = l3_ok 466 * bit[2] = l4_ok 467 * bit[8] = cv 468 * bit[11:10] = l3_hdr_type 469 * bit[14:12] = l4_hdr_type 470 * bit[15] = ip_frag 471 * bit[16] = tunneled 472 * bit[17] = outer_l3_type 473 */ 474 ptype = vshrn_n_u32(ptype_info, 10); 475 /* Errored packets will have RTE_PTYPE_ALL_MASK. */ 476 ptype = vorr_u16(ptype, op_err); 477 pt_idx0 = vget_lane_u8(vreinterpret_u8_u16(ptype), 6); 478 pt_idx1 = vget_lane_u8(vreinterpret_u8_u16(ptype), 4); 479 pt_idx2 = vget_lane_u8(vreinterpret_u8_u16(ptype), 2); 480 pt_idx3 = vget_lane_u8(vreinterpret_u8_u16(ptype), 0); 481 pkts[0]->packet_type = mlx5_ptype_table[pt_idx0] | 482 !!(pt_idx0 & (1 << 6)) * rxq->tunnel; 483 pkts[1]->packet_type = mlx5_ptype_table[pt_idx1] | 484 !!(pt_idx1 & (1 << 6)) * rxq->tunnel; 485 pkts[2]->packet_type = mlx5_ptype_table[pt_idx2] | 486 !!(pt_idx2 & (1 << 6)) * rxq->tunnel; 487 pkts[3]->packet_type = mlx5_ptype_table[pt_idx3] | 488 !!(pt_idx3 & (1 << 6)) * rxq->tunnel; 489 /* Fill flags for checksum and VLAN. */ 490 pinfo = vandq_u32(ptype_info, ptype_ol_mask); 491 pinfo = vreinterpretq_u32_u8( 492 vqtbl1q_u8(cv_flag_sel, vreinterpretq_u8_u32(pinfo))); 493 /* Locate checksum flags at byte[2:1] and merge with VLAN flags. */ 494 cv_flags = vshlq_n_u32(pinfo, 9); 495 cv_flags = vorrq_u32(pinfo, cv_flags); 496 /* Move back flags to start from byte[0]. */ 497 cv_flags = vshrq_n_u32(cv_flags, 8); 498 /* Mask out garbage bits. */ 499 cv_flags = vandq_u32(cv_flags, cv_mask); 500 /* Merge to ol_flags. */ 501 ol_flags = vorrq_u32(ol_flags, cv_flags); 502 /* Merge mbuf_init and ol_flags, and store. */ 503 rearm0 = vreinterpretq_u64_u32(vsetq_lane_u32 504 (vgetq_lane_u32(ol_flags, 3), 505 vreinterpretq_u32_u64(mbuf_init), 2)); 506 rearm1 = vreinterpretq_u64_u32(vsetq_lane_u32 507 (vgetq_lane_u32(ol_flags, 2), 508 vreinterpretq_u32_u64(mbuf_init), 2)); 509 rearm2 = vreinterpretq_u64_u32(vsetq_lane_u32 510 (vgetq_lane_u32(ol_flags, 1), 511 vreinterpretq_u32_u64(mbuf_init), 2)); 512 rearm3 = vreinterpretq_u64_u32(vsetq_lane_u32 513 (vgetq_lane_u32(ol_flags, 0), 514 vreinterpretq_u32_u64(mbuf_init), 2)); 515 516 vst1q_u64((void *)&pkts[0]->rearm_data, rearm0); 517 vst1q_u64((void *)&pkts[1]->rearm_data, rearm1); 518 vst1q_u64((void *)&pkts[2]->rearm_data, rearm2); 519 vst1q_u64((void *)&pkts[3]->rearm_data, rearm3); 520 } 521 522 /** 523 * Process a non-compressed completion and fill in mbufs in RX SW ring 524 * with data extracted from the title completion descriptor. 525 * 526 * @param rxq 527 * Pointer to RX queue structure. 528 * @param cq 529 * Pointer to completion array having a non-compressed completion at first. 530 * @param elts 531 * Pointer to SW ring to be filled. The first mbuf has to be pre-built from 532 * the title completion descriptor to be copied to the rest of mbufs. 533 * @param[out] pkts 534 * Array to store received packets. 535 * @param pkts_n 536 * Maximum number of packets in array. 537 * @param[out] err 538 * Pointer to a flag. Set non-zero value if pkts array has at least one error 539 * packet to handle. 540 * @param[out] comp 541 * Pointer to a index. Set it to the first compressed completion if any. 542 * 543 * @return 544 * Number of CQEs successfully processed. 545 */ 546 static inline uint16_t 547 rxq_cq_process_v(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cq, 548 struct rte_mbuf **elts, struct rte_mbuf **pkts, 549 uint16_t pkts_n, uint64_t *err, uint64_t *comp) 550 { 551 const uint16_t q_n = 1 << rxq->cqe_n; 552 const uint16_t q_mask = q_n - 1; 553 unsigned int pos, adj; 554 uint64_t n = 0; 555 uint64_t comp_idx = MLX5_VPMD_DESCS_PER_LOOP; 556 uint16_t nocmp_n = 0; 557 const uint16x4_t validity = vdup_n_u16((rxq->cq_ci >> rxq->cqe_n) << 8); 558 const uint16x4_t ownership = vdup_n_u16(!(rxq->cq_ci & (q_mask + 1))); 559 const uint16x4_t vic_check = vcreate_u16(0xff00ff00ff00ff00); 560 const uint16x4_t owner_check = vcreate_u16(0x0001000100010001); 561 const uint16x4_t opcode_check = vcreate_u16(0x00f000f000f000f0); 562 const uint16x4_t format_check = vcreate_u16(0x000c000c000c000c); 563 const uint16x4_t resp_err_check = vcreate_u16(0x00e000e000e000e0); 564 #ifdef MLX5_PMD_SOFT_COUNTERS 565 uint32_t rcvd_byte = 0; 566 #endif 567 /* Mask to generate 16B length vector. */ 568 const uint8x8_t len_shuf_m = { 569 52, 53, /* 4th CQE */ 570 36, 37, /* 3rd CQE */ 571 20, 21, /* 2nd CQE */ 572 4, 5 /* 1st CQE */ 573 }; 574 /* Mask to extract 16B data from a 64B CQE. */ 575 const uint8x16_t cqe_shuf_m = { 576 28, 29, /* hdr_type_etc */ 577 0, /* pkt_info */ 578 62, /* validity_iteration_count */ 579 47, 46, /* byte_cnt, bswap16 */ 580 31, 30, /* vlan_info, bswap16 */ 581 15, 14, 13, 12, /* rx_hash_res, bswap32 */ 582 57, 58, 59, /* flow_tag */ 583 63 /* op_own */ 584 }; 585 /* Mask to generate 16B data for mbuf. */ 586 const uint8x16_t mb_shuf_m = { 587 4, 5, -1, -1, /* pkt_len */ 588 4, 5, /* data_len */ 589 6, 7, /* vlan_tci */ 590 8, 9, 10, 11, /* hash.rss */ 591 12, 13, 14, -1 /* hash.fdir.hi */ 592 }; 593 /* Mask to generate 16B owner vector. */ 594 const uint8x8_t owner_shuf_m = { 595 63, 51, /* 4th CQE */ 596 47, 35, /* 3rd CQE */ 597 31, 19, /* 2nd CQE */ 598 15, 3 /* 1st CQE */ 599 }; 600 /* Mask to generate a vector having packet_type/ol_flags. */ 601 const uint8x16_t ptype_shuf_m = { 602 48, 49, 50, -1, /* 4th CQE */ 603 32, 33, 34, -1, /* 3rd CQE */ 604 16, 17, 18, -1, /* 2nd CQE */ 605 0, 1, 2, -1 /* 1st CQE */ 606 }; 607 /* Mask to generate a vector having flow tags. */ 608 const uint8x16_t ftag_shuf_m = { 609 60, 61, 62, -1, /* 4th CQE */ 610 44, 45, 46, -1, /* 3rd CQE */ 611 28, 29, 30, -1, /* 2nd CQE */ 612 12, 13, 14, -1 /* 1st CQE */ 613 }; 614 const uint16x8_t crc_adj = { 615 0, 0, rxq->crc_present * RTE_ETHER_CRC_LEN, 0, 0, 0, 0, 0 616 }; 617 const uint32x4_t flow_mark_adj = { 0, 0, 0, rxq->mark * (-1) }; 618 619 /* 620 * Note that vectors have reverse order - {v3, v2, v1, v0}, because 621 * there's no instruction to count trailing zeros. rte_clz64() is 622 * used instead. 623 * 624 * A. copy 4 mbuf pointers from elts ring to returning pkts. 625 * B. load 64B CQE and extract necessary fields 626 * Final 16bytes cqes[] extracted from original 64bytes CQE has the 627 * following structure: 628 * struct { 629 * uint16_t hdr_type_etc; 630 * uint8_t pkt_info; 631 * uint8_t validity_iteration_count; 632 * uint16_t byte_cnt; 633 * uint16_t vlan_info; 634 * uint32_t rx_has_res; 635 * uint8_t flow_tag[3]; 636 * uint8_t op_own; 637 * } c; 638 * C. fill in mbuf. 639 * D. get valid CQEs. 640 * E. find compressed CQE. 641 */ 642 for (pos = 0; 643 pos < pkts_n; 644 pos += MLX5_VPMD_DESCS_PER_LOOP) { 645 uint16x4_t op_own; 646 uint16x4_t opcode, owner_mask, invalid_mask; 647 uint16x4_t comp_mask, mini_mask; 648 uint16x4_t mask; 649 uint16x4_t byte_cnt; 650 uint32x4_t ptype_info, flow_tag; 651 register uint64x2_t c0, c1, c2, c3; 652 uint8_t *p0, *p1, *p2, *p3; 653 uint8_t *e0 = (void *)&elts[pos]->pkt_len; 654 uint8_t *e1 = (void *)&elts[pos + 1]->pkt_len; 655 uint8_t *e2 = (void *)&elts[pos + 2]->pkt_len; 656 uint8_t *e3 = (void *)&elts[pos + 3]->pkt_len; 657 void *elts_p = (void *)&elts[pos]; 658 void *pkts_p = (void *)&pkts[pos]; 659 660 /* A.0 do not cross the end of CQ. */ 661 mask = vcreate_u16(pkts_n - pos < MLX5_VPMD_DESCS_PER_LOOP ? 662 -1UL >> ((pkts_n - pos) * 663 sizeof(uint16_t) * 8) : 0); 664 p0 = RTE_PTR_UNQUAL(&cq[pos].pkt_info); 665 p1 = p0 + (pkts_n - pos > 1) * sizeof(struct mlx5_cqe); 666 p2 = p1 + (pkts_n - pos > 2) * sizeof(struct mlx5_cqe); 667 p3 = p2 + (pkts_n - pos > 3) * sizeof(struct mlx5_cqe); 668 /* B.0 (CQE 3) load a block having op_own. */ 669 c3 = vld1q_u64((uint64_t *)(p3 + 48)); 670 /* B.0 (CQE 2) load a block having op_own. */ 671 c2 = vld1q_u64((uint64_t *)(p2 + 48)); 672 /* B.0 (CQE 1) load a block having op_own. */ 673 c1 = vld1q_u64((uint64_t *)(p1 + 48)); 674 /* B.0 (CQE 0) load a block having op_own. */ 675 c0 = vld1q_u64((uint64_t *)(p0 + 48)); 676 /* Synchronize for loading the rest of blocks. */ 677 rte_io_rmb(); 678 /* B.0 (CQE 3) reload lower half of the block. */ 679 c3 = vld1q_lane_u64((uint64_t *)(p3 + 48), c3, 0); 680 /* B.0 (CQE 2) reload lower half of the block. */ 681 c2 = vld1q_lane_u64((uint64_t *)(p2 + 48), c2, 0); 682 /* B.0 (CQE 1) reload lower half of the block. */ 683 c1 = vld1q_lane_u64((uint64_t *)(p1 + 48), c1, 0); 684 /* B.0 (CQE 0) reload lower half of the block. */ 685 c0 = vld1q_lane_u64((uint64_t *)(p0 + 48), c0, 0); 686 /* Prefetch next 4 CQEs. */ 687 if (pkts_n - pos >= 2 * MLX5_VPMD_DESCS_PER_LOOP) { 688 unsigned int next = pos + MLX5_VPMD_DESCS_PER_LOOP; 689 rte_prefetch_non_temporal(&cq[next]); 690 rte_prefetch_non_temporal(&cq[next + 1]); 691 rte_prefetch_non_temporal(&cq[next + 2]); 692 rte_prefetch_non_temporal(&cq[next + 3]); 693 } 694 __asm__ volatile ( 695 /* B.1 (CQE 3) load the rest of blocks. */ 696 "ld1 {v16.16b - v18.16b}, [%[p3]] \n\t" 697 /* B.2 (CQE 3) move the block having op_own. */ 698 "mov v19.16b, %[c3].16b \n\t" 699 /* B.3 (CQE 3) extract 16B fields. */ 700 "tbl v23.16b, {v16.16b - v19.16b}, %[cqe_shuf_m].16b \n\t" 701 /* B.1 (CQE 2) load the rest of blocks. */ 702 "ld1 {v16.16b - v18.16b}, [%[p2]] \n\t" 703 /* B.4 (CQE 3) adjust CRC length. */ 704 "sub v23.8h, v23.8h, %[crc_adj].8h \n\t" 705 /* C.1 (CQE 3) generate final structure for mbuf. */ 706 "tbl v15.16b, {v23.16b}, %[mb_shuf_m].16b \n\t" 707 /* B.2 (CQE 2) move the block having op_own. */ 708 "mov v19.16b, %[c2].16b \n\t" 709 /* B.3 (CQE 2) extract 16B fields. */ 710 "tbl v22.16b, {v16.16b - v19.16b}, %[cqe_shuf_m].16b \n\t" 711 /* B.1 (CQE 1) load the rest of blocks. */ 712 "ld1 {v16.16b - v18.16b}, [%[p1]] \n\t" 713 /* B.4 (CQE 2) adjust CRC length. */ 714 "sub v22.8h, v22.8h, %[crc_adj].8h \n\t" 715 /* C.1 (CQE 2) generate final structure for mbuf. */ 716 "tbl v14.16b, {v22.16b}, %[mb_shuf_m].16b \n\t" 717 /* B.2 (CQE 1) move the block having op_own. */ 718 "mov v19.16b, %[c1].16b \n\t" 719 /* B.3 (CQE 1) extract 16B fields. */ 720 "tbl v21.16b, {v16.16b - v19.16b}, %[cqe_shuf_m].16b \n\t" 721 /* B.1 (CQE 0) load the rest of blocks. */ 722 "ld1 {v16.16b - v18.16b}, [%[p0]] \n\t" 723 /* B.4 (CQE 1) adjust CRC length. */ 724 "sub v21.8h, v21.8h, %[crc_adj].8h \n\t" 725 /* C.1 (CQE 1) generate final structure for mbuf. */ 726 "tbl v13.16b, {v21.16b}, %[mb_shuf_m].16b \n\t" 727 /* B.2 (CQE 0) move the block having op_own. */ 728 "mov v19.16b, %[c0].16b \n\t" 729 /* A.1 load mbuf pointers. */ 730 "ld1 {v24.2d - v25.2d}, [%[elts_p]] \n\t" 731 /* B.3 (CQE 0) extract 16B fields. */ 732 "tbl v20.16b, {v16.16b - v19.16b}, %[cqe_shuf_m].16b \n\t" 733 /* B.4 (CQE 0) adjust CRC length. */ 734 "sub v20.8h, v20.8h, %[crc_adj].8h \n\t" 735 /* D.1 extract op_own byte. */ 736 "tbl %[op_own].8b, {v20.16b - v23.16b}, %[owner_shuf_m].8b \n\t" 737 /* C.2 (CQE 3) adjust flow mark. */ 738 "add v15.4s, v15.4s, %[flow_mark_adj].4s \n\t" 739 /* C.3 (CQE 3) fill in mbuf - rx_descriptor_fields1. */ 740 "st1 {v15.2d}, [%[e3]] \n\t" 741 /* C.2 (CQE 2) adjust flow mark. */ 742 "add v14.4s, v14.4s, %[flow_mark_adj].4s \n\t" 743 /* C.3 (CQE 2) fill in mbuf - rx_descriptor_fields1. */ 744 "st1 {v14.2d}, [%[e2]] \n\t" 745 /* C.1 (CQE 0) generate final structure for mbuf. */ 746 "tbl v12.16b, {v20.16b}, %[mb_shuf_m].16b \n\t" 747 /* C.2 (CQE 1) adjust flow mark. */ 748 "add v13.4s, v13.4s, %[flow_mark_adj].4s \n\t" 749 /* C.3 (CQE 1) fill in mbuf - rx_descriptor_fields1. */ 750 "st1 {v13.2d}, [%[e1]] \n\t" 751 #ifdef MLX5_PMD_SOFT_COUNTERS 752 /* Extract byte_cnt. */ 753 "tbl %[byte_cnt].8b, {v20.16b - v23.16b}, %[len_shuf_m].8b \n\t" 754 #endif 755 /* Extract ptype_info. */ 756 "tbl %[ptype_info].16b, {v20.16b - v23.16b}, %[ptype_shuf_m].16b \n\t" 757 /* Extract flow_tag. */ 758 "tbl %[flow_tag].16b, {v20.16b - v23.16b}, %[ftag_shuf_m].16b \n\t" 759 /* A.2 copy mbuf pointers. */ 760 "st1 {v24.2d - v25.2d}, [%[pkts_p]] \n\t" 761 /* C.2 (CQE 0) adjust flow mark. */ 762 "add v12.4s, v12.4s, %[flow_mark_adj].4s \n\t" 763 /* C.3 (CQE 1) fill in mbuf - rx_descriptor_fields1. */ 764 "st1 {v12.2d}, [%[e0]] \n\t" 765 :[op_own]"=&w"(op_own), 766 [byte_cnt]"=&w"(byte_cnt), 767 [ptype_info]"=&w"(ptype_info), 768 [flow_tag]"=&w"(flow_tag) 769 :[p3]"r"(p3), [p2]"r"(p2), [p1]"r"(p1), [p0]"r"(p0), 770 [e3]"r"(e3), [e2]"r"(e2), [e1]"r"(e1), [e0]"r"(e0), 771 [c3]"w"(c3), [c2]"w"(c2), [c1]"w"(c1), [c0]"w"(c0), 772 [elts_p]"r"(elts_p), 773 [pkts_p]"r"(pkts_p), 774 [cqe_shuf_m]"w"(cqe_shuf_m), 775 [mb_shuf_m]"w"(mb_shuf_m), 776 [owner_shuf_m]"w"(owner_shuf_m), 777 [len_shuf_m]"w"(len_shuf_m), 778 [ptype_shuf_m]"w"(ptype_shuf_m), 779 [ftag_shuf_m]"w"(ftag_shuf_m), 780 [crc_adj]"w"(crc_adj), 781 [flow_mark_adj]"w"(flow_mark_adj) 782 :"memory", 783 "v12", "v13", "v14", "v15", 784 "v16", "v17", "v18", "v19", 785 "v20", "v21", "v22", "v23", 786 "v24", "v25"); 787 /* D.2 mask out CQEs belonging to HW. */ 788 if (rxq->cqe_comp_layout) { 789 owner_mask = vand_u16(op_own, vic_check); 790 owner_mask = vceq_u16(owner_mask, validity); 791 owner_mask = vmvn_u16(owner_mask); 792 } else { 793 owner_mask = vand_u16(op_own, owner_check); 794 owner_mask = vceq_u16(owner_mask, ownership); 795 } 796 /* D.3 get mask for invalidated CQEs. */ 797 opcode = vand_u16(op_own, opcode_check); 798 invalid_mask = vceq_u16(opcode_check, opcode); 799 /* E.1 find compressed CQE format. */ 800 comp_mask = vand_u16(op_own, format_check); 801 comp_mask = vceq_u16(comp_mask, format_check); 802 /* D.4 mask out beyond boundary. */ 803 invalid_mask = vorr_u16(invalid_mask, mask); 804 /* D.5 merge invalid_mask with invalid owner. */ 805 invalid_mask = vorr_u16(invalid_mask, owner_mask); 806 /* E.2 mask out invalid entries. */ 807 comp_mask = vbic_u16(comp_mask, invalid_mask); 808 /* E.3 get the first compressed CQE. */ 809 comp_idx = rte_clz64(vget_lane_u64(vreinterpret_u64_u16(comp_mask), 0)) / 810 (sizeof(uint16_t) * 8); 811 invalid_mask = vorr_u16(invalid_mask, comp_mask); 812 /* D.7 count non-compressed valid CQEs. */ 813 n = rte_clz64(vget_lane_u64(vreinterpret_u64_u16(invalid_mask), 0)) / 814 (sizeof(uint16_t) * 8); 815 nocmp_n += n; 816 /* 817 * D.2 mask out entries after the compressed CQE. 818 * get the final invalid mask. 819 */ 820 mask = vcreate_u16(n < MLX5_VPMD_DESCS_PER_LOOP ? 821 -1UL >> (n * sizeof(uint16_t) * 8) : 0); 822 invalid_mask = vorr_u16(invalid_mask, mask); 823 /* D.3 check error in opcode. */ 824 adj = (!rxq->cqe_comp_layout && 825 comp_idx != MLX5_VPMD_DESCS_PER_LOOP && comp_idx == n); 826 mask = vcreate_u16(adj ? 827 -1UL >> ((n + 1) * sizeof(uint16_t) * 8) : -1UL); 828 mini_mask = vand_u16(invalid_mask, mask); 829 opcode = vceq_u16(resp_err_check, opcode); 830 opcode = vbic_u16(opcode, mini_mask); 831 /* D.4 mark if any error is set */ 832 *err |= vget_lane_u64(vreinterpret_u64_u16(opcode), 0); 833 /* C.4 fill in mbuf - rearm_data and packet_type. */ 834 rxq_cq_to_ptype_oflags_v(rxq, ptype_info, flow_tag, 835 opcode, &elts[pos]); 836 if (unlikely(rxq->shared)) { 837 pkts[pos]->port = container_of(p0, struct mlx5_cqe, 838 pkt_info)->user_index_low; 839 pkts[pos + 1]->port = container_of(p1, struct mlx5_cqe, 840 pkt_info)->user_index_low; 841 pkts[pos + 2]->port = container_of(p2, struct mlx5_cqe, 842 pkt_info)->user_index_low; 843 pkts[pos + 3]->port = container_of(p3, struct mlx5_cqe, 844 pkt_info)->user_index_low; 845 } 846 if (unlikely(rxq->hw_timestamp)) { 847 int offset = rxq->timestamp_offset; 848 if (rxq->rt_timestamp) { 849 struct mlx5_dev_ctx_shared *sh = rxq->sh; 850 uint64_t ts; 851 852 ts = rte_be_to_cpu_64 853 (container_of(p0, struct mlx5_cqe, 854 pkt_info)->timestamp); 855 mlx5_timestamp_set(pkts[pos], offset, 856 mlx5_txpp_convert_rx_ts(sh, ts)); 857 ts = rte_be_to_cpu_64 858 (container_of(p1, struct mlx5_cqe, 859 pkt_info)->timestamp); 860 mlx5_timestamp_set(pkts[pos + 1], offset, 861 mlx5_txpp_convert_rx_ts(sh, ts)); 862 ts = rte_be_to_cpu_64 863 (container_of(p2, struct mlx5_cqe, 864 pkt_info)->timestamp); 865 mlx5_timestamp_set(pkts[pos + 2], offset, 866 mlx5_txpp_convert_rx_ts(sh, ts)); 867 ts = rte_be_to_cpu_64 868 (container_of(p3, struct mlx5_cqe, 869 pkt_info)->timestamp); 870 mlx5_timestamp_set(pkts[pos + 3], offset, 871 mlx5_txpp_convert_rx_ts(sh, ts)); 872 } else { 873 mlx5_timestamp_set(pkts[pos], offset, 874 rte_be_to_cpu_64(container_of(p0, 875 struct mlx5_cqe, pkt_info)->timestamp)); 876 mlx5_timestamp_set(pkts[pos + 1], offset, 877 rte_be_to_cpu_64(container_of(p1, 878 struct mlx5_cqe, pkt_info)->timestamp)); 879 mlx5_timestamp_set(pkts[pos + 2], offset, 880 rte_be_to_cpu_64(container_of(p2, 881 struct mlx5_cqe, pkt_info)->timestamp)); 882 mlx5_timestamp_set(pkts[pos + 3], offset, 883 rte_be_to_cpu_64(container_of(p3, 884 struct mlx5_cqe, pkt_info)->timestamp)); 885 } 886 } 887 if (rxq->dynf_meta) { 888 /* This code is subject for further optimization. */ 889 int32_t offs = rxq->flow_meta_offset; 890 uint32_t mask = rxq->flow_meta_port_mask; 891 892 *RTE_MBUF_DYNFIELD(pkts[pos], offs, uint32_t *) = 893 rte_be_to_cpu_32(container_of 894 (p0, struct mlx5_cqe, 895 pkt_info)->flow_table_metadata) & mask; 896 *RTE_MBUF_DYNFIELD(pkts[pos + 1], offs, uint32_t *) = 897 rte_be_to_cpu_32(container_of 898 (p1, struct mlx5_cqe, 899 pkt_info)->flow_table_metadata) & mask; 900 *RTE_MBUF_DYNFIELD(pkts[pos + 2], offs, uint32_t *) = 901 rte_be_to_cpu_32(container_of 902 (p2, struct mlx5_cqe, 903 pkt_info)->flow_table_metadata) & mask; 904 *RTE_MBUF_DYNFIELD(pkts[pos + 3], offs, uint32_t *) = 905 rte_be_to_cpu_32(container_of 906 (p3, struct mlx5_cqe, 907 pkt_info)->flow_table_metadata) & mask; 908 if (*RTE_MBUF_DYNFIELD(pkts[pos], offs, uint32_t *)) 909 elts[pos]->ol_flags |= rxq->flow_meta_mask; 910 if (*RTE_MBUF_DYNFIELD(pkts[pos + 1], offs, uint32_t *)) 911 elts[pos + 1]->ol_flags |= rxq->flow_meta_mask; 912 if (*RTE_MBUF_DYNFIELD(pkts[pos + 2], offs, uint32_t *)) 913 elts[pos + 2]->ol_flags |= rxq->flow_meta_mask; 914 if (*RTE_MBUF_DYNFIELD(pkts[pos + 3], offs, uint32_t *)) 915 elts[pos + 3]->ol_flags |= rxq->flow_meta_mask; 916 } 917 #ifdef MLX5_PMD_SOFT_COUNTERS 918 /* Add up received bytes count. */ 919 byte_cnt = vbic_u16(byte_cnt, invalid_mask); 920 rcvd_byte += vget_lane_u64(vpaddl_u32(vpaddl_u16(byte_cnt)), 0); 921 #endif 922 /* 923 * Break the loop unless more valid CQE is expected, or if 924 * there's a compressed CQE. 925 */ 926 if (n != MLX5_VPMD_DESCS_PER_LOOP) 927 break; 928 } 929 #ifdef MLX5_PMD_SOFT_COUNTERS 930 rxq->stats.ipackets += nocmp_n; 931 rxq->stats.ibytes += rcvd_byte; 932 #endif 933 if (comp_idx == n) 934 *comp = comp_idx; 935 return nocmp_n; 936 } 937 938 #endif /* RTE_PMD_MLX5_RXTX_VEC_NEON_H_ */ 939