1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2017 6WIND S.A. 3 * Copyright 2017 Mellanox Technologies, Ltd 4 */ 5 6 #ifndef RTE_PMD_MLX5_RXTX_VEC_NEON_H_ 7 #define RTE_PMD_MLX5_RXTX_VEC_NEON_H_ 8 9 #include <assert.h> 10 #include <stdint.h> 11 #include <string.h> 12 #include <stdlib.h> 13 #include <arm_neon.h> 14 15 #include <rte_mbuf.h> 16 #include <rte_mempool.h> 17 #include <rte_prefetch.h> 18 19 #include "mlx5.h" 20 #include "mlx5_utils.h" 21 #include "mlx5_rxtx.h" 22 #include "mlx5_rxtx_vec.h" 23 #include "mlx5_autoconf.h" 24 #include "mlx5_defs.h" 25 #include "mlx5_prm.h" 26 27 #pragma GCC diagnostic ignored "-Wcast-qual" 28 29 /** 30 * Fill in buffer descriptors in a multi-packet send descriptor. 31 * 32 * @param txq 33 * Pointer to TX queue structure. 34 * @param dseg 35 * Pointer to buffer descriptor to be written. 36 * @param pkts 37 * Pointer to array of packets to be sent. 38 * @param n 39 * Number of packets to be filled. 40 */ 41 static inline void 42 txq_wr_dseg_v(struct mlx5_txq_data *txq, uint8_t *dseg, 43 struct rte_mbuf **pkts, unsigned int n) 44 { 45 unsigned int pos; 46 uintptr_t addr; 47 const uint8x16_t dseg_shuf_m = { 48 3, 2, 1, 0, /* length, bswap32 */ 49 4, 5, 6, 7, /* lkey */ 50 15, 14, 13, 12, /* addr, bswap64 */ 51 11, 10, 9, 8 52 }; 53 #ifdef MLX5_PMD_SOFT_COUNTERS 54 uint32_t tx_byte = 0; 55 #endif 56 57 for (pos = 0; pos < n; ++pos, dseg += MLX5_WQE_DWORD_SIZE) { 58 uint8x16_t desc; 59 struct rte_mbuf *pkt = pkts[pos]; 60 61 addr = rte_pktmbuf_mtod(pkt, uintptr_t); 62 desc = vreinterpretq_u8_u32((uint32x4_t) { 63 DATA_LEN(pkt), 64 mlx5_tx_mb2mr(txq, pkt), 65 addr, 66 addr >> 32 }); 67 desc = vqtbl1q_u8(desc, dseg_shuf_m); 68 vst1q_u8(dseg, desc); 69 #ifdef MLX5_PMD_SOFT_COUNTERS 70 tx_byte += DATA_LEN(pkt); 71 #endif 72 } 73 #ifdef MLX5_PMD_SOFT_COUNTERS 74 txq->stats.obytes += tx_byte; 75 #endif 76 } 77 78 /** 79 * Send multi-segmented packets until it encounters a single segment packet in 80 * the pkts list. 81 * 82 * @param txq 83 * Pointer to TX queue structure. 84 * @param pkts 85 * Pointer to array of packets to be sent. 86 * @param pkts_n 87 * Number of packets to be sent. 88 * 89 * @return 90 * Number of packets successfully transmitted (<= pkts_n). 91 */ 92 static uint16_t 93 txq_scatter_v(struct mlx5_txq_data *txq, struct rte_mbuf **pkts, 94 uint16_t pkts_n) 95 { 96 uint16_t elts_head = txq->elts_head; 97 const uint16_t elts_n = 1 << txq->elts_n; 98 const uint16_t elts_m = elts_n - 1; 99 const uint16_t wq_n = 1 << txq->wqe_n; 100 const uint16_t wq_mask = wq_n - 1; 101 const unsigned int nb_dword_per_wqebb = 102 MLX5_WQE_SIZE / MLX5_WQE_DWORD_SIZE; 103 const unsigned int nb_dword_in_hdr = 104 sizeof(struct mlx5_wqe) / MLX5_WQE_DWORD_SIZE; 105 unsigned int n; 106 volatile struct mlx5_wqe *wqe = NULL; 107 108 assert(elts_n > pkts_n); 109 mlx5_tx_complete(txq); 110 if (unlikely(!pkts_n)) 111 return 0; 112 for (n = 0; n < pkts_n; ++n) { 113 struct rte_mbuf *buf = pkts[n]; 114 unsigned int segs_n = buf->nb_segs; 115 unsigned int ds = nb_dword_in_hdr; 116 unsigned int len = PKT_LEN(buf); 117 uint16_t wqe_ci = txq->wqe_ci; 118 const uint8x16_t ctrl_shuf_m = { 119 3, 2, 1, 0, /* bswap32 */ 120 7, 6, 5, 4, /* bswap32 */ 121 11, 10, 9, 8, /* bswap32 */ 122 12, 13, 14, 15 123 }; 124 uint8_t cs_flags; 125 uint16_t max_elts; 126 uint16_t max_wqe; 127 uint8x16_t *t_wqe; 128 uint8_t *dseg; 129 uint8x16_t ctrl; 130 131 assert(segs_n); 132 max_elts = elts_n - (elts_head - txq->elts_tail); 133 max_wqe = wq_n - (txq->wqe_ci - txq->wqe_pi); 134 /* 135 * A MPW session consumes 2 WQEs at most to 136 * include MLX5_MPW_DSEG_MAX pointers. 137 */ 138 if (segs_n == 1 || 139 max_elts < segs_n || max_wqe < 2) 140 break; 141 wqe = &((volatile struct mlx5_wqe64 *) 142 txq->wqes)[wqe_ci & wq_mask].hdr; 143 cs_flags = txq_ol_cksum_to_cs(buf); 144 /* Title WQEBB pointer. */ 145 t_wqe = (uint8x16_t *)wqe; 146 dseg = (uint8_t *)(wqe + 1); 147 do { 148 if (!(ds++ % nb_dword_per_wqebb)) { 149 dseg = (uint8_t *) 150 &((volatile struct mlx5_wqe64 *) 151 txq->wqes)[++wqe_ci & wq_mask]; 152 } 153 txq_wr_dseg_v(txq, dseg, &buf, 1); 154 dseg += MLX5_WQE_DWORD_SIZE; 155 (*txq->elts)[elts_head++ & elts_m] = buf; 156 buf = buf->next; 157 } while (--segs_n); 158 ++wqe_ci; 159 /* Fill CTRL in the header. */ 160 ctrl = vreinterpretq_u8_u32((uint32x4_t) { 161 MLX5_OPC_MOD_MPW << 24 | 162 txq->wqe_ci << 8 | MLX5_OPCODE_TSO, 163 txq->qp_num_8s | ds, 0, 0}); 164 ctrl = vqtbl1q_u8(ctrl, ctrl_shuf_m); 165 vst1q_u8((void *)t_wqe, ctrl); 166 /* Fill ESEG in the header. */ 167 vst1q_u16((void *)(t_wqe + 1), 168 ((uint16x8_t) { 0, 0, cs_flags, rte_cpu_to_be_16(len), 169 0, 0, 0, 0 })); 170 txq->wqe_ci = wqe_ci; 171 } 172 if (!n) 173 return 0; 174 txq->elts_comp += (uint16_t)(elts_head - txq->elts_head); 175 txq->elts_head = elts_head; 176 if (txq->elts_comp >= MLX5_TX_COMP_THRESH) { 177 /* A CQE slot must always be available. */ 178 assert((1u << txq->cqe_n) - (txq->cq_pi++ - txq->cq_ci)); 179 wqe->ctrl[2] = rte_cpu_to_be_32(8); 180 wqe->ctrl[3] = txq->elts_head; 181 txq->elts_comp = 0; 182 } 183 #ifdef MLX5_PMD_SOFT_COUNTERS 184 txq->stats.opackets += n; 185 #endif 186 mlx5_tx_dbrec(txq, wqe); 187 return n; 188 } 189 190 /** 191 * Send burst of packets with Enhanced MPW. If it encounters a multi-seg packet, 192 * it returns to make it processed by txq_scatter_v(). All the packets in 193 * the pkts list should be single segment packets having same offload flags. 194 * This must be checked by txq_count_contig_single_seg() and txq_calc_offload(). 195 * 196 * @param txq 197 * Pointer to TX queue structure. 198 * @param pkts 199 * Pointer to array of packets to be sent. 200 * @param pkts_n 201 * Number of packets to be sent (<= MLX5_VPMD_TX_MAX_BURST). 202 * @param cs_flags 203 * Checksum offload flags to be written in the descriptor. 204 * @param metadata 205 * Metadata value to be written in the descriptor. 206 * 207 * @return 208 * Number of packets successfully transmitted (<= pkts_n). 209 */ 210 static inline uint16_t 211 txq_burst_v(struct mlx5_txq_data *txq, struct rte_mbuf **pkts, uint16_t pkts_n, 212 uint8_t cs_flags, rte_be32_t metadata) 213 { 214 struct rte_mbuf **elts; 215 uint16_t elts_head = txq->elts_head; 216 const uint16_t elts_n = 1 << txq->elts_n; 217 const uint16_t elts_m = elts_n - 1; 218 const unsigned int nb_dword_per_wqebb = 219 MLX5_WQE_SIZE / MLX5_WQE_DWORD_SIZE; 220 const unsigned int nb_dword_in_hdr = 221 sizeof(struct mlx5_wqe) / MLX5_WQE_DWORD_SIZE; 222 unsigned int n = 0; 223 unsigned int pos; 224 uint16_t max_elts; 225 uint16_t max_wqe; 226 uint32_t comp_req = 0; 227 const uint16_t wq_n = 1 << txq->wqe_n; 228 const uint16_t wq_mask = wq_n - 1; 229 uint16_t wq_idx = txq->wqe_ci & wq_mask; 230 volatile struct mlx5_wqe64 *wq = 231 &((volatile struct mlx5_wqe64 *)txq->wqes)[wq_idx]; 232 volatile struct mlx5_wqe *wqe = (volatile struct mlx5_wqe *)wq; 233 const uint8x16_t ctrl_shuf_m = { 234 3, 2, 1, 0, /* bswap32 */ 235 7, 6, 5, 4, /* bswap32 */ 236 11, 10, 9, 8, /* bswap32 */ 237 12, 13, 14, 15 238 }; 239 uint8x16_t *t_wqe; 240 uint8_t *dseg; 241 uint8x16_t ctrl; 242 243 /* Make sure all packets can fit into a single WQE. */ 244 assert(elts_n > pkts_n); 245 mlx5_tx_complete(txq); 246 max_elts = (elts_n - (elts_head - txq->elts_tail)); 247 max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi); 248 pkts_n = RTE_MIN((unsigned int)RTE_MIN(pkts_n, max_wqe), max_elts); 249 if (unlikely(!pkts_n)) 250 return 0; 251 elts = &(*txq->elts)[elts_head & elts_m]; 252 /* Loop for available tailroom first. */ 253 n = RTE_MIN(elts_n - (elts_head & elts_m), pkts_n); 254 for (pos = 0; pos < (n & -2); pos += 2) 255 vst1q_u64((void *)&elts[pos], vld1q_u64((void *)&pkts[pos])); 256 if (n & 1) 257 elts[pos] = pkts[pos]; 258 /* Check if it crosses the end of the queue. */ 259 if (unlikely(n < pkts_n)) { 260 elts = &(*txq->elts)[0]; 261 for (pos = 0; pos < pkts_n - n; ++pos) 262 elts[pos] = pkts[n + pos]; 263 } 264 txq->elts_head += pkts_n; 265 /* Save title WQEBB pointer. */ 266 t_wqe = (uint8x16_t *)wqe; 267 dseg = (uint8_t *)(wqe + 1); 268 /* Calculate the number of entries to the end. */ 269 n = RTE_MIN( 270 (wq_n - wq_idx) * nb_dword_per_wqebb - nb_dword_in_hdr, 271 pkts_n); 272 /* Fill DSEGs. */ 273 txq_wr_dseg_v(txq, dseg, pkts, n); 274 /* Check if it crosses the end of the queue. */ 275 if (n < pkts_n) { 276 dseg = (uint8_t *)txq->wqes; 277 txq_wr_dseg_v(txq, dseg, &pkts[n], pkts_n - n); 278 } 279 if (txq->elts_comp + pkts_n < MLX5_TX_COMP_THRESH) { 280 txq->elts_comp += pkts_n; 281 } else { 282 /* A CQE slot must always be available. */ 283 assert((1u << txq->cqe_n) - (txq->cq_pi++ - txq->cq_ci)); 284 /* Request a completion. */ 285 txq->elts_comp = 0; 286 comp_req = 8; 287 } 288 /* Fill CTRL in the header. */ 289 ctrl = vreinterpretq_u8_u32((uint32x4_t) { 290 MLX5_OPC_MOD_ENHANCED_MPSW << 24 | 291 txq->wqe_ci << 8 | MLX5_OPCODE_ENHANCED_MPSW, 292 txq->qp_num_8s | (pkts_n + 2), 293 comp_req, 294 txq->elts_head }); 295 ctrl = vqtbl1q_u8(ctrl, ctrl_shuf_m); 296 vst1q_u8((void *)t_wqe, ctrl); 297 /* Fill ESEG in the header. */ 298 vst1q_u32((void *)(t_wqe + 1), 299 ((uint32x4_t) { 0, cs_flags, metadata, 0 })); 300 #ifdef MLX5_PMD_SOFT_COUNTERS 301 txq->stats.opackets += pkts_n; 302 #endif 303 txq->wqe_ci += (nb_dword_in_hdr + pkts_n + (nb_dword_per_wqebb - 1)) / 304 nb_dword_per_wqebb; 305 /* Ring QP doorbell. */ 306 mlx5_tx_dbrec_cond_wmb(txq, wqe, pkts_n < MLX5_VPMD_TX_MAX_BURST); 307 return pkts_n; 308 } 309 310 /** 311 * Store free buffers to RX SW ring. 312 * 313 * @param rxq 314 * Pointer to RX queue structure. 315 * @param pkts 316 * Pointer to array of packets to be stored. 317 * @param pkts_n 318 * Number of packets to be stored. 319 */ 320 static inline void 321 rxq_copy_mbuf_v(struct mlx5_rxq_data *rxq, struct rte_mbuf **pkts, uint16_t n) 322 { 323 const uint16_t q_mask = (1 << rxq->elts_n) - 1; 324 struct rte_mbuf **elts = &(*rxq->elts)[rxq->rq_pi & q_mask]; 325 unsigned int pos; 326 uint16_t p = n & -2; 327 328 for (pos = 0; pos < p; pos += 2) { 329 uint64x2_t mbp; 330 331 mbp = vld1q_u64((void *)&elts[pos]); 332 vst1q_u64((void *)&pkts[pos], mbp); 333 } 334 if (n & 1) 335 pkts[pos] = elts[pos]; 336 } 337 338 /** 339 * Decompress a compressed completion and fill in mbufs in RX SW ring with data 340 * extracted from the title completion descriptor. 341 * 342 * @param rxq 343 * Pointer to RX queue structure. 344 * @param cq 345 * Pointer to completion array having a compressed completion at first. 346 * @param elts 347 * Pointer to SW ring to be filled. The first mbuf has to be pre-built from 348 * the title completion descriptor to be copied to the rest of mbufs. 349 */ 350 static inline void 351 rxq_cq_decompress_v(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cq, 352 struct rte_mbuf **elts) 353 { 354 volatile struct mlx5_mini_cqe8 *mcq = (void *)&(cq + 1)->pkt_info; 355 struct rte_mbuf *t_pkt = elts[0]; /* Title packet is pre-built. */ 356 unsigned int pos; 357 unsigned int i; 358 unsigned int inv = 0; 359 /* Mask to shuffle from extracted mini CQE to mbuf. */ 360 const uint8x16_t mcqe_shuf_m1 = { 361 -1, -1, -1, -1, /* skip packet_type */ 362 7, 6, -1, -1, /* pkt_len, bswap16 */ 363 7, 6, /* data_len, bswap16 */ 364 -1, -1, /* skip vlan_tci */ 365 3, 2, 1, 0 /* hash.rss, bswap32 */ 366 }; 367 const uint8x16_t mcqe_shuf_m2 = { 368 -1, -1, -1, -1, /* skip packet_type */ 369 15, 14, -1, -1, /* pkt_len, bswap16 */ 370 15, 14, /* data_len, bswap16 */ 371 -1, -1, /* skip vlan_tci */ 372 11, 10, 9, 8 /* hash.rss, bswap32 */ 373 }; 374 /* Restore the compressed count. Must be 16 bits. */ 375 const uint16_t mcqe_n = t_pkt->data_len + 376 (rxq->crc_present * ETHER_CRC_LEN); 377 const uint64x2_t rearm = 378 vld1q_u64((void *)&t_pkt->rearm_data); 379 const uint32x4_t rxdf_mask = { 380 0xffffffff, /* packet_type */ 381 0, /* skip pkt_len */ 382 0xffff0000, /* vlan_tci, skip data_len */ 383 0, /* skip hash.rss */ 384 }; 385 const uint8x16_t rxdf = 386 vandq_u8(vld1q_u8((void *)&t_pkt->rx_descriptor_fields1), 387 vreinterpretq_u8_u32(rxdf_mask)); 388 const uint16x8_t crc_adj = { 389 0, 0, 390 rxq->crc_present * ETHER_CRC_LEN, 0, 391 rxq->crc_present * ETHER_CRC_LEN, 0, 392 0, 0 393 }; 394 const uint32_t flow_tag = t_pkt->hash.fdir.hi; 395 #ifdef MLX5_PMD_SOFT_COUNTERS 396 uint32_t rcvd_byte = 0; 397 #endif 398 /* Mask to shuffle byte_cnt to add up stats. Do bswap16 for all. */ 399 const uint8x8_t len_shuf_m = { 400 7, 6, /* 1st mCQE */ 401 15, 14, /* 2nd mCQE */ 402 23, 22, /* 3rd mCQE */ 403 31, 30 /* 4th mCQE */ 404 }; 405 406 /* 407 * A. load mCQEs into a 128bit register. 408 * B. store rearm data to mbuf. 409 * C. combine data from mCQEs with rx_descriptor_fields1. 410 * D. store rx_descriptor_fields1. 411 * E. store flow tag (rte_flow mark). 412 */ 413 for (pos = 0; pos < mcqe_n; ) { 414 uint8_t *p = (void *)&mcq[pos % 8]; 415 uint8_t *e0 = (void *)&elts[pos]->rearm_data; 416 uint8_t *e1 = (void *)&elts[pos + 1]->rearm_data; 417 uint8_t *e2 = (void *)&elts[pos + 2]->rearm_data; 418 uint8_t *e3 = (void *)&elts[pos + 3]->rearm_data; 419 uint16x4_t byte_cnt; 420 #ifdef MLX5_PMD_SOFT_COUNTERS 421 uint16x4_t invalid_mask = 422 vcreate_u16(mcqe_n - pos < MLX5_VPMD_DESCS_PER_LOOP ? 423 -1UL << ((mcqe_n - pos) * 424 sizeof(uint16_t) * 8) : 0); 425 #endif 426 427 if (!(pos & 0x7) && pos + 8 < mcqe_n) 428 rte_prefetch0((void *)(cq + pos + 8)); 429 __asm__ volatile ( 430 /* A.1 load mCQEs into a 128bit register. */ 431 "ld1 {v16.16b - v17.16b}, [%[mcq]] \n\t" 432 /* B.1 store rearm data to mbuf. */ 433 "st1 {%[rearm].2d}, [%[e0]] \n\t" 434 "add %[e0], %[e0], #16 \n\t" 435 "st1 {%[rearm].2d}, [%[e1]] \n\t" 436 "add %[e1], %[e1], #16 \n\t" 437 /* C.1 combine data from mCQEs with rx_descriptor_fields1. */ 438 "tbl v18.16b, {v16.16b}, %[mcqe_shuf_m1].16b \n\t" 439 "tbl v19.16b, {v16.16b}, %[mcqe_shuf_m2].16b \n\t" 440 "sub v18.8h, v18.8h, %[crc_adj].8h \n\t" 441 "sub v19.8h, v19.8h, %[crc_adj].8h \n\t" 442 "orr v18.16b, v18.16b, %[rxdf].16b \n\t" 443 "orr v19.16b, v19.16b, %[rxdf].16b \n\t" 444 /* D.1 store rx_descriptor_fields1. */ 445 "st1 {v18.2d}, [%[e0]] \n\t" 446 "st1 {v19.2d}, [%[e1]] \n\t" 447 /* B.1 store rearm data to mbuf. */ 448 "st1 {%[rearm].2d}, [%[e2]] \n\t" 449 "add %[e2], %[e2], #16 \n\t" 450 "st1 {%[rearm].2d}, [%[e3]] \n\t" 451 "add %[e3], %[e3], #16 \n\t" 452 /* C.1 combine data from mCQEs with rx_descriptor_fields1. */ 453 "tbl v18.16b, {v17.16b}, %[mcqe_shuf_m1].16b \n\t" 454 "tbl v19.16b, {v17.16b}, %[mcqe_shuf_m2].16b \n\t" 455 "sub v18.8h, v18.8h, %[crc_adj].8h \n\t" 456 "sub v19.8h, v19.8h, %[crc_adj].8h \n\t" 457 "orr v18.16b, v18.16b, %[rxdf].16b \n\t" 458 "orr v19.16b, v19.16b, %[rxdf].16b \n\t" 459 /* D.1 store rx_descriptor_fields1. */ 460 "st1 {v18.2d}, [%[e2]] \n\t" 461 "st1 {v19.2d}, [%[e3]] \n\t" 462 #ifdef MLX5_PMD_SOFT_COUNTERS 463 "tbl %[byte_cnt].8b, {v16.16b - v17.16b}, %[len_shuf_m].8b \n\t" 464 #endif 465 :[byte_cnt]"=&w"(byte_cnt) 466 :[mcq]"r"(p), 467 [rxdf]"w"(rxdf), 468 [rearm]"w"(rearm), 469 [e3]"r"(e3), [e2]"r"(e2), [e1]"r"(e1), [e0]"r"(e0), 470 [mcqe_shuf_m1]"w"(mcqe_shuf_m1), 471 [mcqe_shuf_m2]"w"(mcqe_shuf_m2), 472 [crc_adj]"w"(crc_adj), 473 [len_shuf_m]"w"(len_shuf_m) 474 :"memory", "v16", "v17", "v18", "v19"); 475 #ifdef MLX5_PMD_SOFT_COUNTERS 476 byte_cnt = vbic_u16(byte_cnt, invalid_mask); 477 rcvd_byte += vget_lane_u64(vpaddl_u32(vpaddl_u16(byte_cnt)), 0); 478 #endif 479 if (rxq->mark) { 480 /* E.1 store flow tag (rte_flow mark). */ 481 elts[pos]->hash.fdir.hi = flow_tag; 482 elts[pos + 1]->hash.fdir.hi = flow_tag; 483 elts[pos + 2]->hash.fdir.hi = flow_tag; 484 elts[pos + 3]->hash.fdir.hi = flow_tag; 485 } 486 pos += MLX5_VPMD_DESCS_PER_LOOP; 487 /* Move to next CQE and invalidate consumed CQEs. */ 488 if (!(pos & 0x7) && pos < mcqe_n) { 489 mcq = (void *)&(cq + pos)->pkt_info; 490 for (i = 0; i < 8; ++i) 491 cq[inv++].op_own = MLX5_CQE_INVALIDATE; 492 } 493 } 494 /* Invalidate the rest of CQEs. */ 495 for (; inv < mcqe_n; ++inv) 496 cq[inv].op_own = MLX5_CQE_INVALIDATE; 497 #ifdef MLX5_PMD_SOFT_COUNTERS 498 rxq->stats.ipackets += mcqe_n; 499 rxq->stats.ibytes += rcvd_byte; 500 #endif 501 rxq->cq_ci += mcqe_n; 502 } 503 504 /** 505 * Calculate packet type and offload flag for mbuf and store it. 506 * 507 * @param rxq 508 * Pointer to RX queue structure. 509 * @param ptype_info 510 * Array of four 4bytes packet type info extracted from the original 511 * completion descriptor. 512 * @param flow_tag 513 * Array of four 4bytes flow ID extracted from the original completion 514 * descriptor. 515 * @param op_err 516 * Opcode vector having responder error status. Each field is 4B. 517 * @param pkts 518 * Pointer to array of packets to be filled. 519 */ 520 static inline void 521 rxq_cq_to_ptype_oflags_v(struct mlx5_rxq_data *rxq, 522 uint32x4_t ptype_info, uint32x4_t flow_tag, 523 uint16x4_t op_err, struct rte_mbuf **pkts) 524 { 525 uint16x4_t ptype; 526 uint32x4_t pinfo, cv_flags; 527 uint32x4_t ol_flags = 528 vdupq_n_u32(rxq->rss_hash * PKT_RX_RSS_HASH | 529 rxq->hw_timestamp * PKT_RX_TIMESTAMP); 530 const uint32x4_t ptype_ol_mask = { 0x106, 0x106, 0x106, 0x106 }; 531 const uint8x16_t cv_flag_sel = { 532 0, 533 (uint8_t)(PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED), 534 (uint8_t)(PKT_RX_IP_CKSUM_GOOD >> 1), 535 0, 536 (uint8_t)(PKT_RX_L4_CKSUM_GOOD >> 1), 537 0, 538 (uint8_t)((PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD) >> 1), 539 0, 0, 0, 0, 0, 0, 0, 0, 0 540 }; 541 const uint32x4_t cv_mask = 542 vdupq_n_u32(PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD | 543 PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED); 544 const uint64x1_t mbuf_init = vld1_u64(&rxq->mbuf_initializer); 545 const uint64x1_t r32_mask = vcreate_u64(0xffffffff); 546 uint64x2_t rearm0, rearm1, rearm2, rearm3; 547 uint8_t pt_idx0, pt_idx1, pt_idx2, pt_idx3; 548 549 if (rxq->mark) { 550 const uint32x4_t ft_def = vdupq_n_u32(MLX5_FLOW_MARK_DEFAULT); 551 const uint32x4_t fdir_flags = vdupq_n_u32(PKT_RX_FDIR); 552 uint32x4_t fdir_id_flags = vdupq_n_u32(PKT_RX_FDIR_ID); 553 uint32x4_t invalid_mask; 554 555 /* Check if flow tag is non-zero then set PKT_RX_FDIR. */ 556 invalid_mask = vceqzq_u32(flow_tag); 557 ol_flags = vorrq_u32(ol_flags, 558 vbicq_u32(fdir_flags, invalid_mask)); 559 /* Mask out invalid entries. */ 560 fdir_id_flags = vbicq_u32(fdir_id_flags, invalid_mask); 561 /* Check if flow tag MLX5_FLOW_MARK_DEFAULT. */ 562 ol_flags = vorrq_u32(ol_flags, 563 vbicq_u32(fdir_id_flags, 564 vceqq_u32(flow_tag, ft_def))); 565 } 566 /* 567 * ptype_info has the following: 568 * bit[1] = l3_ok 569 * bit[2] = l4_ok 570 * bit[8] = cv 571 * bit[11:10] = l3_hdr_type 572 * bit[14:12] = l4_hdr_type 573 * bit[15] = ip_frag 574 * bit[16] = tunneled 575 * bit[17] = outer_l3_type 576 */ 577 ptype = vshrn_n_u32(ptype_info, 10); 578 /* Errored packets will have RTE_PTYPE_ALL_MASK. */ 579 ptype = vorr_u16(ptype, op_err); 580 pt_idx0 = vget_lane_u8(vreinterpret_u8_u16(ptype), 6); 581 pt_idx1 = vget_lane_u8(vreinterpret_u8_u16(ptype), 4); 582 pt_idx2 = vget_lane_u8(vreinterpret_u8_u16(ptype), 2); 583 pt_idx3 = vget_lane_u8(vreinterpret_u8_u16(ptype), 0); 584 pkts[0]->packet_type = mlx5_ptype_table[pt_idx0] | 585 !!(pt_idx0 & (1 << 6)) * rxq->tunnel; 586 pkts[1]->packet_type = mlx5_ptype_table[pt_idx1] | 587 !!(pt_idx1 & (1 << 6)) * rxq->tunnel; 588 pkts[2]->packet_type = mlx5_ptype_table[pt_idx2] | 589 !!(pt_idx2 & (1 << 6)) * rxq->tunnel; 590 pkts[3]->packet_type = mlx5_ptype_table[pt_idx3] | 591 !!(pt_idx3 & (1 << 6)) * rxq->tunnel; 592 /* Fill flags for checksum and VLAN. */ 593 pinfo = vandq_u32(ptype_info, ptype_ol_mask); 594 pinfo = vreinterpretq_u32_u8( 595 vqtbl1q_u8(cv_flag_sel, vreinterpretq_u8_u32(pinfo))); 596 /* Locate checksum flags at byte[2:1] and merge with VLAN flags. */ 597 cv_flags = vshlq_n_u32(pinfo, 9); 598 cv_flags = vorrq_u32(pinfo, cv_flags); 599 /* Move back flags to start from byte[0]. */ 600 cv_flags = vshrq_n_u32(cv_flags, 8); 601 /* Mask out garbage bits. */ 602 cv_flags = vandq_u32(cv_flags, cv_mask); 603 /* Merge to ol_flags. */ 604 ol_flags = vorrq_u32(ol_flags, cv_flags); 605 /* Merge mbuf_init and ol_flags, and store. */ 606 rearm0 = vcombine_u64(mbuf_init, 607 vshr_n_u64(vget_high_u64(vreinterpretq_u64_u32( 608 ol_flags)), 32)); 609 rearm1 = vcombine_u64(mbuf_init, 610 vand_u64(vget_high_u64(vreinterpretq_u64_u32( 611 ol_flags)), r32_mask)); 612 rearm2 = vcombine_u64(mbuf_init, 613 vshr_n_u64(vget_low_u64(vreinterpretq_u64_u32( 614 ol_flags)), 32)); 615 rearm3 = vcombine_u64(mbuf_init, 616 vand_u64(vget_low_u64(vreinterpretq_u64_u32( 617 ol_flags)), r32_mask)); 618 vst1q_u64((void *)&pkts[0]->rearm_data, rearm0); 619 vst1q_u64((void *)&pkts[1]->rearm_data, rearm1); 620 vst1q_u64((void *)&pkts[2]->rearm_data, rearm2); 621 vst1q_u64((void *)&pkts[3]->rearm_data, rearm3); 622 } 623 624 /** 625 * Receive burst of packets. An errored completion also consumes a mbuf, but the 626 * packet_type is set to be RTE_PTYPE_ALL_MASK. Marked mbufs should be freed 627 * before returning to application. 628 * 629 * @param rxq 630 * Pointer to RX queue structure. 631 * @param[out] pkts 632 * Array to store received packets. 633 * @param pkts_n 634 * Maximum number of packets in array. 635 * @param[out] err 636 * Pointer to a flag. Set non-zero value if pkts array has at least one error 637 * packet to handle. 638 * 639 * @return 640 * Number of packets received including errors (<= pkts_n). 641 */ 642 static inline uint16_t 643 rxq_burst_v(struct mlx5_rxq_data *rxq, struct rte_mbuf **pkts, uint16_t pkts_n, 644 uint64_t *err) 645 { 646 const uint16_t q_n = 1 << rxq->cqe_n; 647 const uint16_t q_mask = q_n - 1; 648 volatile struct mlx5_cqe *cq; 649 struct rte_mbuf **elts; 650 unsigned int pos; 651 uint64_t n; 652 uint16_t repl_n; 653 uint64_t comp_idx = MLX5_VPMD_DESCS_PER_LOOP; 654 uint16_t nocmp_n = 0; 655 uint16_t rcvd_pkt = 0; 656 unsigned int cq_idx = rxq->cq_ci & q_mask; 657 unsigned int elts_idx; 658 const uint16x4_t ownership = vdup_n_u16(!(rxq->cq_ci & (q_mask + 1))); 659 const uint16x4_t owner_check = vcreate_u16(0x0001000100010001); 660 const uint16x4_t opcode_check = vcreate_u16(0x00f000f000f000f0); 661 const uint16x4_t format_check = vcreate_u16(0x000c000c000c000c); 662 const uint16x4_t resp_err_check = vcreate_u16(0x00e000e000e000e0); 663 #ifdef MLX5_PMD_SOFT_COUNTERS 664 uint32_t rcvd_byte = 0; 665 #endif 666 /* Mask to generate 16B length vector. */ 667 const uint8x8_t len_shuf_m = { 668 52, 53, /* 4th CQE */ 669 36, 37, /* 3rd CQE */ 670 20, 21, /* 2nd CQE */ 671 4, 5 /* 1st CQE */ 672 }; 673 /* Mask to extract 16B data from a 64B CQE. */ 674 const uint8x16_t cqe_shuf_m = { 675 28, 29, /* hdr_type_etc */ 676 0, /* pkt_info */ 677 -1, /* null */ 678 47, 46, /* byte_cnt, bswap16 */ 679 31, 30, /* vlan_info, bswap16 */ 680 15, 14, 13, 12, /* rx_hash_res, bswap32 */ 681 57, 58, 59, /* flow_tag */ 682 63 /* op_own */ 683 }; 684 /* Mask to generate 16B data for mbuf. */ 685 const uint8x16_t mb_shuf_m = { 686 4, 5, -1, -1, /* pkt_len */ 687 4, 5, /* data_len */ 688 6, 7, /* vlan_tci */ 689 8, 9, 10, 11, /* hash.rss */ 690 12, 13, 14, -1 /* hash.fdir.hi */ 691 }; 692 /* Mask to generate 16B owner vector. */ 693 const uint8x8_t owner_shuf_m = { 694 63, -1, /* 4th CQE */ 695 47, -1, /* 3rd CQE */ 696 31, -1, /* 2nd CQE */ 697 15, -1 /* 1st CQE */ 698 }; 699 /* Mask to generate a vector having packet_type/ol_flags. */ 700 const uint8x16_t ptype_shuf_m = { 701 48, 49, 50, -1, /* 4th CQE */ 702 32, 33, 34, -1, /* 3rd CQE */ 703 16, 17, 18, -1, /* 2nd CQE */ 704 0, 1, 2, -1 /* 1st CQE */ 705 }; 706 /* Mask to generate a vector having flow tags. */ 707 const uint8x16_t ftag_shuf_m = { 708 60, 61, 62, -1, /* 4th CQE */ 709 44, 45, 46, -1, /* 3rd CQE */ 710 28, 29, 30, -1, /* 2nd CQE */ 711 12, 13, 14, -1 /* 1st CQE */ 712 }; 713 const uint16x8_t crc_adj = { 714 0, 0, rxq->crc_present * ETHER_CRC_LEN, 0, 0, 0, 0, 0 715 }; 716 const uint32x4_t flow_mark_adj = { 0, 0, 0, rxq->mark * (-1) }; 717 718 assert(rxq->sges_n == 0); 719 assert(rxq->cqe_n == rxq->elts_n); 720 cq = &(*rxq->cqes)[cq_idx]; 721 rte_prefetch_non_temporal(cq); 722 rte_prefetch_non_temporal(cq + 1); 723 rte_prefetch_non_temporal(cq + 2); 724 rte_prefetch_non_temporal(cq + 3); 725 pkts_n = RTE_MIN(pkts_n, MLX5_VPMD_RX_MAX_BURST); 726 /* 727 * Order of indexes: 728 * rq_ci >= cq_ci >= rq_pi 729 * Definition of indexes: 730 * rq_ci - cq_ci := # of buffers owned by HW (posted). 731 * cq_ci - rq_pi := # of buffers not returned to app (decompressed). 732 * N - (rq_ci - rq_pi) := # of buffers consumed (to be replenished). 733 */ 734 repl_n = q_n - (rxq->rq_ci - rxq->rq_pi); 735 if (repl_n >= rxq->rq_repl_thresh) 736 mlx5_rx_replenish_bulk_mbuf(rxq, repl_n); 737 /* See if there're unreturned mbufs from compressed CQE. */ 738 rcvd_pkt = rxq->cq_ci - rxq->rq_pi; 739 if (rcvd_pkt > 0) { 740 rcvd_pkt = RTE_MIN(rcvd_pkt, pkts_n); 741 rxq_copy_mbuf_v(rxq, pkts, rcvd_pkt); 742 rxq->rq_pi += rcvd_pkt; 743 pkts += rcvd_pkt; 744 } 745 elts_idx = rxq->rq_pi & q_mask; 746 elts = &(*rxq->elts)[elts_idx]; 747 /* Not to overflow pkts array. */ 748 pkts_n = RTE_ALIGN_FLOOR(pkts_n - rcvd_pkt, MLX5_VPMD_DESCS_PER_LOOP); 749 /* Not to cross queue end. */ 750 pkts_n = RTE_MIN(pkts_n, q_n - elts_idx); 751 if (!pkts_n) 752 return rcvd_pkt; 753 /* At this point, there shouldn't be any remained packets. */ 754 assert(rxq->rq_pi == rxq->cq_ci); 755 /* 756 * Note that vectors have reverse order - {v3, v2, v1, v0}, because 757 * there's no instruction to count trailing zeros. __builtin_clzl() is 758 * used instead. 759 * 760 * A. copy 4 mbuf pointers from elts ring to returing pkts. 761 * B. load 64B CQE and extract necessary fields 762 * Final 16bytes cqes[] extracted from original 64bytes CQE has the 763 * following structure: 764 * struct { 765 * uint16_t hdr_type_etc; 766 * uint8_t pkt_info; 767 * uint8_t rsvd; 768 * uint16_t byte_cnt; 769 * uint16_t vlan_info; 770 * uint32_t rx_has_res; 771 * uint8_t flow_tag[3]; 772 * uint8_t op_own; 773 * } c; 774 * C. fill in mbuf. 775 * D. get valid CQEs. 776 * E. find compressed CQE. 777 */ 778 for (pos = 0; 779 pos < pkts_n; 780 pos += MLX5_VPMD_DESCS_PER_LOOP) { 781 uint16x4_t op_own; 782 uint16x4_t opcode, owner_mask, invalid_mask; 783 uint16x4_t comp_mask; 784 uint16x4_t mask; 785 uint16x4_t byte_cnt; 786 uint32x4_t ptype_info, flow_tag; 787 register uint64x2_t c0, c1, c2, c3; 788 uint8_t *p0, *p1, *p2, *p3; 789 uint8_t *e0 = (void *)&elts[pos]->pkt_len; 790 uint8_t *e1 = (void *)&elts[pos + 1]->pkt_len; 791 uint8_t *e2 = (void *)&elts[pos + 2]->pkt_len; 792 uint8_t *e3 = (void *)&elts[pos + 3]->pkt_len; 793 void *elts_p = (void *)&elts[pos]; 794 void *pkts_p = (void *)&pkts[pos]; 795 796 /* A.0 do not cross the end of CQ. */ 797 mask = vcreate_u16(pkts_n - pos < MLX5_VPMD_DESCS_PER_LOOP ? 798 -1UL >> ((pkts_n - pos) * 799 sizeof(uint16_t) * 8) : 0); 800 p0 = (void *)&cq[pos].pkt_info; 801 p1 = p0 + (pkts_n - pos > 1) * sizeof(struct mlx5_cqe); 802 p2 = p1 + (pkts_n - pos > 2) * sizeof(struct mlx5_cqe); 803 p3 = p2 + (pkts_n - pos > 3) * sizeof(struct mlx5_cqe); 804 /* B.0 (CQE 3) load a block having op_own. */ 805 c3 = vld1q_u64((uint64_t *)(p3 + 48)); 806 /* B.0 (CQE 2) load a block having op_own. */ 807 c2 = vld1q_u64((uint64_t *)(p2 + 48)); 808 /* B.0 (CQE 1) load a block having op_own. */ 809 c1 = vld1q_u64((uint64_t *)(p1 + 48)); 810 /* B.0 (CQE 0) load a block having op_own. */ 811 c0 = vld1q_u64((uint64_t *)(p0 + 48)); 812 /* Synchronize for loading the rest of blocks. */ 813 rte_cio_rmb(); 814 /* Prefetch next 4 CQEs. */ 815 if (pkts_n - pos >= 2 * MLX5_VPMD_DESCS_PER_LOOP) { 816 unsigned int next = pos + MLX5_VPMD_DESCS_PER_LOOP; 817 rte_prefetch_non_temporal(&cq[next]); 818 rte_prefetch_non_temporal(&cq[next + 1]); 819 rte_prefetch_non_temporal(&cq[next + 2]); 820 rte_prefetch_non_temporal(&cq[next + 3]); 821 } 822 __asm__ volatile ( 823 /* B.1 (CQE 3) load the rest of blocks. */ 824 "ld1 {v16.16b - v18.16b}, [%[p3]] \n\t" 825 /* B.2 (CQE 3) move the block having op_own. */ 826 "mov v19.16b, %[c3].16b \n\t" 827 /* B.3 (CQE 3) extract 16B fields. */ 828 "tbl v23.16b, {v16.16b - v19.16b}, %[cqe_shuf_m].16b \n\t" 829 /* B.1 (CQE 2) load the rest of blocks. */ 830 "ld1 {v16.16b - v18.16b}, [%[p2]] \n\t" 831 /* B.4 (CQE 3) adjust CRC length. */ 832 "sub v23.8h, v23.8h, %[crc_adj].8h \n\t" 833 /* C.1 (CQE 3) generate final structure for mbuf. */ 834 "tbl v15.16b, {v23.16b}, %[mb_shuf_m].16b \n\t" 835 /* B.2 (CQE 2) move the block having op_own. */ 836 "mov v19.16b, %[c2].16b \n\t" 837 /* B.3 (CQE 2) extract 16B fields. */ 838 "tbl v22.16b, {v16.16b - v19.16b}, %[cqe_shuf_m].16b \n\t" 839 /* B.1 (CQE 1) load the rest of blocks. */ 840 "ld1 {v16.16b - v18.16b}, [%[p1]] \n\t" 841 /* B.4 (CQE 2) adjust CRC length. */ 842 "sub v22.8h, v22.8h, %[crc_adj].8h \n\t" 843 /* C.1 (CQE 2) generate final structure for mbuf. */ 844 "tbl v14.16b, {v22.16b}, %[mb_shuf_m].16b \n\t" 845 /* B.2 (CQE 1) move the block having op_own. */ 846 "mov v19.16b, %[c1].16b \n\t" 847 /* B.3 (CQE 1) extract 16B fields. */ 848 "tbl v21.16b, {v16.16b - v19.16b}, %[cqe_shuf_m].16b \n\t" 849 /* B.1 (CQE 0) load the rest of blocks. */ 850 "ld1 {v16.16b - v18.16b}, [%[p0]] \n\t" 851 /* B.4 (CQE 1) adjust CRC length. */ 852 "sub v21.8h, v21.8h, %[crc_adj].8h \n\t" 853 /* C.1 (CQE 1) generate final structure for mbuf. */ 854 "tbl v13.16b, {v21.16b}, %[mb_shuf_m].16b \n\t" 855 /* B.2 (CQE 0) move the block having op_own. */ 856 "mov v19.16b, %[c0].16b \n\t" 857 /* A.1 load mbuf pointers. */ 858 "ld1 {v24.2d - v25.2d}, [%[elts_p]] \n\t" 859 /* B.3 (CQE 0) extract 16B fields. */ 860 "tbl v20.16b, {v16.16b - v19.16b}, %[cqe_shuf_m].16b \n\t" 861 /* B.4 (CQE 0) adjust CRC length. */ 862 "sub v20.8h, v20.8h, %[crc_adj].8h \n\t" 863 /* D.1 extract op_own byte. */ 864 "tbl %[op_own].8b, {v20.16b - v23.16b}, %[owner_shuf_m].8b \n\t" 865 /* C.2 (CQE 3) adjust flow mark. */ 866 "add v15.4s, v15.4s, %[flow_mark_adj].4s \n\t" 867 /* C.3 (CQE 3) fill in mbuf - rx_descriptor_fields1. */ 868 "st1 {v15.2d}, [%[e3]] \n\t" 869 /* C.2 (CQE 2) adjust flow mark. */ 870 "add v14.4s, v14.4s, %[flow_mark_adj].4s \n\t" 871 /* C.3 (CQE 2) fill in mbuf - rx_descriptor_fields1. */ 872 "st1 {v14.2d}, [%[e2]] \n\t" 873 /* C.1 (CQE 0) generate final structure for mbuf. */ 874 "tbl v12.16b, {v20.16b}, %[mb_shuf_m].16b \n\t" 875 /* C.2 (CQE 1) adjust flow mark. */ 876 "add v13.4s, v13.4s, %[flow_mark_adj].4s \n\t" 877 /* C.3 (CQE 1) fill in mbuf - rx_descriptor_fields1. */ 878 "st1 {v13.2d}, [%[e1]] \n\t" 879 #ifdef MLX5_PMD_SOFT_COUNTERS 880 /* Extract byte_cnt. */ 881 "tbl %[byte_cnt].8b, {v20.16b - v23.16b}, %[len_shuf_m].8b \n\t" 882 #endif 883 /* Extract ptype_info. */ 884 "tbl %[ptype_info].16b, {v20.16b - v23.16b}, %[ptype_shuf_m].16b \n\t" 885 /* Extract flow_tag. */ 886 "tbl %[flow_tag].16b, {v20.16b - v23.16b}, %[ftag_shuf_m].16b \n\t" 887 /* A.2 copy mbuf pointers. */ 888 "st1 {v24.2d - v25.2d}, [%[pkts_p]] \n\t" 889 /* C.2 (CQE 0) adjust flow mark. */ 890 "add v12.4s, v12.4s, %[flow_mark_adj].4s \n\t" 891 /* C.3 (CQE 1) fill in mbuf - rx_descriptor_fields1. */ 892 "st1 {v12.2d}, [%[e0]] \n\t" 893 :[op_own]"=&w"(op_own), 894 [byte_cnt]"=&w"(byte_cnt), 895 [ptype_info]"=&w"(ptype_info), 896 [flow_tag]"=&w"(flow_tag) 897 :[p3]"r"(p3), [p2]"r"(p2), [p1]"r"(p1), [p0]"r"(p0), 898 [e3]"r"(e3), [e2]"r"(e2), [e1]"r"(e1), [e0]"r"(e0), 899 [c3]"w"(c3), [c2]"w"(c2), [c1]"w"(c1), [c0]"w"(c0), 900 [elts_p]"r"(elts_p), 901 [pkts_p]"r"(pkts_p), 902 [cqe_shuf_m]"w"(cqe_shuf_m), 903 [mb_shuf_m]"w"(mb_shuf_m), 904 [owner_shuf_m]"w"(owner_shuf_m), 905 [len_shuf_m]"w"(len_shuf_m), 906 [ptype_shuf_m]"w"(ptype_shuf_m), 907 [ftag_shuf_m]"w"(ftag_shuf_m), 908 [crc_adj]"w"(crc_adj), 909 [flow_mark_adj]"w"(flow_mark_adj) 910 :"memory", 911 "v12", "v13", "v14", "v15", 912 "v16", "v17", "v18", "v19", 913 "v20", "v21", "v22", "v23", 914 "v24", "v25"); 915 /* D.2 flip owner bit to mark CQEs from last round. */ 916 owner_mask = vand_u16(op_own, owner_check); 917 owner_mask = vceq_u16(owner_mask, ownership); 918 /* D.3 get mask for invalidated CQEs. */ 919 opcode = vand_u16(op_own, opcode_check); 920 invalid_mask = vceq_u16(opcode_check, opcode); 921 /* E.1 find compressed CQE format. */ 922 comp_mask = vand_u16(op_own, format_check); 923 comp_mask = vceq_u16(comp_mask, format_check); 924 /* D.4 mask out beyond boundary. */ 925 invalid_mask = vorr_u16(invalid_mask, mask); 926 /* D.5 merge invalid_mask with invalid owner. */ 927 invalid_mask = vorr_u16(invalid_mask, owner_mask); 928 /* E.2 mask out invalid entries. */ 929 comp_mask = vbic_u16(comp_mask, invalid_mask); 930 /* E.3 get the first compressed CQE. */ 931 comp_idx = __builtin_clzl(vget_lane_u64(vreinterpret_u64_u16( 932 comp_mask), 0)) / 933 (sizeof(uint16_t) * 8); 934 /* D.6 mask out entries after the compressed CQE. */ 935 mask = vcreate_u16(comp_idx < MLX5_VPMD_DESCS_PER_LOOP ? 936 -1UL >> (comp_idx * sizeof(uint16_t) * 8) : 937 0); 938 invalid_mask = vorr_u16(invalid_mask, mask); 939 /* D.7 count non-compressed valid CQEs. */ 940 n = __builtin_clzl(vget_lane_u64(vreinterpret_u64_u16( 941 invalid_mask), 0)) / (sizeof(uint16_t) * 8); 942 nocmp_n += n; 943 /* D.2 get the final invalid mask. */ 944 mask = vcreate_u16(n < MLX5_VPMD_DESCS_PER_LOOP ? 945 -1UL >> (n * sizeof(uint16_t) * 8) : 0); 946 invalid_mask = vorr_u16(invalid_mask, mask); 947 /* D.3 check error in opcode. */ 948 opcode = vceq_u16(resp_err_check, opcode); 949 opcode = vbic_u16(opcode, invalid_mask); 950 /* D.4 mark if any error is set */ 951 *err |= vget_lane_u64(vreinterpret_u64_u16(opcode), 0); 952 /* C.4 fill in mbuf - rearm_data and packet_type. */ 953 rxq_cq_to_ptype_oflags_v(rxq, ptype_info, flow_tag, 954 opcode, &elts[pos]); 955 if (rxq->hw_timestamp) { 956 elts[pos]->timestamp = 957 rte_be_to_cpu_64( 958 container_of(p0, struct mlx5_cqe, 959 pkt_info)->timestamp); 960 elts[pos + 1]->timestamp = 961 rte_be_to_cpu_64( 962 container_of(p1, struct mlx5_cqe, 963 pkt_info)->timestamp); 964 elts[pos + 2]->timestamp = 965 rte_be_to_cpu_64( 966 container_of(p2, struct mlx5_cqe, 967 pkt_info)->timestamp); 968 elts[pos + 3]->timestamp = 969 rte_be_to_cpu_64( 970 container_of(p3, struct mlx5_cqe, 971 pkt_info)->timestamp); 972 } 973 #ifdef MLX5_PMD_SOFT_COUNTERS 974 /* Add up received bytes count. */ 975 byte_cnt = vbic_u16(byte_cnt, invalid_mask); 976 rcvd_byte += vget_lane_u64(vpaddl_u32(vpaddl_u16(byte_cnt)), 0); 977 #endif 978 /* 979 * Break the loop unless more valid CQE is expected, or if 980 * there's a compressed CQE. 981 */ 982 if (n != MLX5_VPMD_DESCS_PER_LOOP) 983 break; 984 } 985 /* If no new CQE seen, return without updating cq_db. */ 986 if (unlikely(!nocmp_n && comp_idx == MLX5_VPMD_DESCS_PER_LOOP)) 987 return rcvd_pkt; 988 /* Update the consumer indexes for non-compressed CQEs. */ 989 assert(nocmp_n <= pkts_n); 990 rxq->cq_ci += nocmp_n; 991 rxq->rq_pi += nocmp_n; 992 rcvd_pkt += nocmp_n; 993 #ifdef MLX5_PMD_SOFT_COUNTERS 994 rxq->stats.ipackets += nocmp_n; 995 rxq->stats.ibytes += rcvd_byte; 996 #endif 997 /* Decompress the last CQE if compressed. */ 998 if (comp_idx < MLX5_VPMD_DESCS_PER_LOOP && comp_idx == n) { 999 assert(comp_idx == (nocmp_n % MLX5_VPMD_DESCS_PER_LOOP)); 1000 rxq_cq_decompress_v(rxq, &cq[nocmp_n], &elts[nocmp_n]); 1001 /* Return more packets if needed. */ 1002 if (nocmp_n < pkts_n) { 1003 uint16_t n = rxq->cq_ci - rxq->rq_pi; 1004 1005 n = RTE_MIN(n, pkts_n - nocmp_n); 1006 rxq_copy_mbuf_v(rxq, &pkts[nocmp_n], n); 1007 rxq->rq_pi += n; 1008 rcvd_pkt += n; 1009 } 1010 } 1011 rte_compiler_barrier(); 1012 *rxq->cq_db = rte_cpu_to_be_32(rxq->cq_ci); 1013 return rcvd_pkt; 1014 } 1015 1016 #endif /* RTE_PMD_MLX5_RXTX_VEC_NEON_H_ */ 1017