1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2017 6WIND S.A. 3 * Copyright 2017 Mellanox Technologies, Ltd 4 */ 5 6 #ifndef RTE_PMD_MLX5_RXTX_VEC_NEON_H_ 7 #define RTE_PMD_MLX5_RXTX_VEC_NEON_H_ 8 9 #include <stdint.h> 10 #include <string.h> 11 #include <stdlib.h> 12 #include <arm_neon.h> 13 14 #include <rte_bitops.h> 15 #include <rte_mbuf.h> 16 #include <rte_mempool.h> 17 #include <rte_prefetch.h> 18 19 #include <mlx5_prm.h> 20 21 #include "mlx5_defs.h" 22 #include "mlx5.h" 23 #include "mlx5_utils.h" 24 #include "mlx5_rxtx.h" 25 #include "mlx5_rxtx_vec.h" 26 #include "mlx5_autoconf.h" 27 28 #pragma GCC diagnostic ignored "-Wcast-qual" 29 30 /** 31 * Store free buffers to RX SW ring. 32 * 33 * @param elts 34 * Pointer to SW ring to be filled. 35 * @param pkts 36 * Pointer to array of packets to be stored. 37 * @param pkts_n 38 * Number of packets to be stored. 39 */ 40 static inline void 41 rxq_copy_mbuf_v(struct rte_mbuf **elts, struct rte_mbuf **pkts, uint16_t n) 42 { 43 unsigned int pos; 44 uint16_t p = n & -2; 45 46 for (pos = 0; pos < p; pos += 2) { 47 uint64x2_t mbp; 48 49 mbp = vld1q_u64((void *)&elts[pos]); 50 vst1q_u64((void *)&pkts[pos], mbp); 51 } 52 if (n & 1) 53 pkts[pos] = elts[pos]; 54 } 55 56 /** 57 * Decompress a compressed completion and fill in mbufs in RX SW ring with data 58 * extracted from the title completion descriptor. 59 * 60 * @param rxq 61 * Pointer to RX queue structure. 62 * @param cq 63 * Pointer to completion array having a compressed completion at first. 64 * @param elts 65 * Pointer to SW ring to be filled. The first mbuf has to be pre-built from 66 * the title completion descriptor to be copied to the rest of mbufs. 67 * @param keep 68 * Keep unzipping if the next CQE is the miniCQE array. 69 * 70 * @return 71 * Number of mini-CQEs successfully decompressed. 72 */ 73 static inline uint16_t 74 rxq_cq_decompress_v(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cq, 75 struct rte_mbuf **elts, bool keep) 76 { 77 volatile struct mlx5_mini_cqe8 *mcq = 78 (void *)&(cq + !rxq->cqe_comp_layout)->pkt_info; 79 /* Title packet is pre-built. */ 80 struct rte_mbuf *t_pkt = rxq->cqe_comp_layout ? &rxq->title_pkt : elts[0]; 81 unsigned int pos; 82 unsigned int i; 83 unsigned int inv = 0; 84 /* Mask to shuffle from extracted mini CQE to mbuf. */ 85 const uint8x16_t mcqe_shuf_m1 = { 86 -1, -1, -1, -1, /* skip packet_type */ 87 7, 6, -1, -1, /* pkt_len, bswap16 */ 88 7, 6, /* data_len, bswap16 */ 89 -1, -1, /* skip vlan_tci */ 90 3, 2, 1, 0 /* hash.rss, bswap32 */ 91 }; 92 const uint8x16_t mcqe_shuf_m2 = { 93 -1, -1, -1, -1, /* skip packet_type */ 94 15, 14, -1, -1, /* pkt_len, bswap16 */ 95 15, 14, /* data_len, bswap16 */ 96 -1, -1, /* skip vlan_tci */ 97 11, 10, 9, 8 /* hash.rss, bswap32 */ 98 }; 99 /* Restore the compressed count. Must be 16 bits. */ 100 uint16_t mcqe_n = (rxq->cqe_comp_layout) ? 101 (MLX5_CQE_NUM_MINIS(cq->op_own) + 1U) : rte_be_to_cpu_32(cq->byte_cnt); 102 uint16_t pkts_n = mcqe_n; 103 const uint64x2_t rearm = 104 vld1q_u64((void *)&t_pkt->rearm_data); 105 const uint32x4_t rxdf_mask = { 106 0xffffffff, /* packet_type */ 107 0, /* skip pkt_len */ 108 0xffff0000, /* vlan_tci, skip data_len */ 109 0, /* skip hash.rss */ 110 }; 111 const uint8x16_t rxdf = 112 vandq_u8(vld1q_u8((void *)&t_pkt->rx_descriptor_fields1), 113 vreinterpretq_u8_u32(rxdf_mask)); 114 const uint16x8_t crc_adj = { 115 0, 0, 116 rxq->crc_present * RTE_ETHER_CRC_LEN, 0, 117 rxq->crc_present * RTE_ETHER_CRC_LEN, 0, 118 0, 0 119 }; 120 uint32x4_t ol_flags = {0, 0, 0, 0}; 121 uint32x4_t ol_flags_mask = {0, 0, 0, 0}; 122 #ifdef MLX5_PMD_SOFT_COUNTERS 123 uint32_t rcvd_byte = 0; 124 #endif 125 /* Mask to shuffle byte_cnt to add up stats. Do bswap16 for all. */ 126 const uint8x8_t len_shuf_m = { 127 7, 6, /* 1st mCQE */ 128 15, 14, /* 2nd mCQE */ 129 23, 22, /* 3rd mCQE */ 130 31, 30 /* 4th mCQE */ 131 }; 132 133 /* 134 * A. load mCQEs into a 128bit register. 135 * B. store rearm data to mbuf. 136 * C. combine data from mCQEs with rx_descriptor_fields1. 137 * D. store rx_descriptor_fields1. 138 * E. store flow tag (rte_flow mark). 139 */ 140 cycle: 141 if (rxq->cqe_comp_layout) 142 rte_prefetch0((void *)(cq + mcqe_n)); 143 for (pos = 0; pos < mcqe_n; ) { 144 uint8_t *p = (void *)&mcq[pos % 8]; 145 uint8_t *e0 = (void *)&elts[pos]->rearm_data; 146 uint8_t *e1 = (void *)&elts[pos + 1]->rearm_data; 147 uint8_t *e2 = (void *)&elts[pos + 2]->rearm_data; 148 uint8_t *e3 = (void *)&elts[pos + 3]->rearm_data; 149 uint16x4_t byte_cnt; 150 #ifdef MLX5_PMD_SOFT_COUNTERS 151 uint16x4_t invalid_mask = 152 vcreate_u16(mcqe_n - pos < MLX5_VPMD_DESCS_PER_LOOP ? 153 -1UL << ((mcqe_n - pos) * 154 sizeof(uint16_t) * 8) : 0); 155 #endif 156 157 if (!rxq->cqe_comp_layout) 158 for (i = 0; i < MLX5_VPMD_DESCS_PER_LOOP; ++i) 159 if (likely(pos + i < mcqe_n)) 160 rte_prefetch0((void *)(cq + pos + i)); 161 __asm__ volatile ( 162 /* A.1 load mCQEs into a 128bit register. */ 163 "ld1 {v16.16b - v17.16b}, [%[mcq]] \n\t" 164 /* B.1 store rearm data to mbuf. */ 165 "st1 {%[rearm].2d}, [%[e0]] \n\t" 166 "add %[e0], %[e0], #16 \n\t" 167 "st1 {%[rearm].2d}, [%[e1]] \n\t" 168 "add %[e1], %[e1], #16 \n\t" 169 /* C.1 combine data from mCQEs with rx_descriptor_fields1. */ 170 "tbl v18.16b, {v16.16b}, %[mcqe_shuf_m1].16b \n\t" 171 "tbl v19.16b, {v16.16b}, %[mcqe_shuf_m2].16b \n\t" 172 "sub v18.8h, v18.8h, %[crc_adj].8h \n\t" 173 "sub v19.8h, v19.8h, %[crc_adj].8h \n\t" 174 "orr v18.16b, v18.16b, %[rxdf].16b \n\t" 175 "orr v19.16b, v19.16b, %[rxdf].16b \n\t" 176 /* D.1 store rx_descriptor_fields1. */ 177 "st1 {v18.2d}, [%[e0]] \n\t" 178 "st1 {v19.2d}, [%[e1]] \n\t" 179 /* B.1 store rearm data to mbuf. */ 180 "st1 {%[rearm].2d}, [%[e2]] \n\t" 181 "add %[e2], %[e2], #16 \n\t" 182 "st1 {%[rearm].2d}, [%[e3]] \n\t" 183 "add %[e3], %[e3], #16 \n\t" 184 /* C.1 combine data from mCQEs with rx_descriptor_fields1. */ 185 "tbl v18.16b, {v17.16b}, %[mcqe_shuf_m1].16b \n\t" 186 "tbl v19.16b, {v17.16b}, %[mcqe_shuf_m2].16b \n\t" 187 "sub v18.8h, v18.8h, %[crc_adj].8h \n\t" 188 "sub v19.8h, v19.8h, %[crc_adj].8h \n\t" 189 "orr v18.16b, v18.16b, %[rxdf].16b \n\t" 190 "orr v19.16b, v19.16b, %[rxdf].16b \n\t" 191 /* D.1 store rx_descriptor_fields1. */ 192 "st1 {v18.2d}, [%[e2]] \n\t" 193 "st1 {v19.2d}, [%[e3]] \n\t" 194 #ifdef MLX5_PMD_SOFT_COUNTERS 195 "tbl %[byte_cnt].8b, {v16.16b - v17.16b}, %[len_shuf_m].8b \n\t" 196 #endif 197 :[byte_cnt]"=&w"(byte_cnt) 198 :[mcq]"r"(p), 199 [rxdf]"w"(rxdf), 200 [rearm]"w"(rearm), 201 [e3]"r"(e3), [e2]"r"(e2), [e1]"r"(e1), [e0]"r"(e0), 202 [mcqe_shuf_m1]"w"(mcqe_shuf_m1), 203 [mcqe_shuf_m2]"w"(mcqe_shuf_m2), 204 [crc_adj]"w"(crc_adj), 205 [len_shuf_m]"w"(len_shuf_m) 206 :"memory", "v16", "v17", "v18", "v19"); 207 #ifdef MLX5_PMD_SOFT_COUNTERS 208 byte_cnt = vbic_u16(byte_cnt, invalid_mask); 209 rcvd_byte += vget_lane_u64(vpaddl_u32(vpaddl_u16(byte_cnt)), 0); 210 #endif 211 if (rxq->mark) { 212 if (rxq->mcqe_format != 213 MLX5_CQE_RESP_FORMAT_FTAG_STRIDX) { 214 const uint32_t flow_tag = t_pkt->hash.fdir.hi; 215 216 /* E.1 store flow tag (rte_flow mark). */ 217 elts[pos]->hash.fdir.hi = flow_tag; 218 elts[pos + 1]->hash.fdir.hi = flow_tag; 219 elts[pos + 2]->hash.fdir.hi = flow_tag; 220 elts[pos + 3]->hash.fdir.hi = flow_tag; 221 } else { 222 const uint32x4_t flow_mark_adj = { 223 -1, -1, -1, -1 }; 224 const uint8x16_t flow_mark_shuf = { 225 28, 24, 25, -1, 226 20, 16, 17, -1, 227 12, 8, 9, -1, 228 4, 0, 1, -1}; 229 /* Extract flow_tag field. */ 230 const uint32x4_t ft_mask = 231 vdupq_n_u32(MLX5_FLOW_MARK_DEFAULT); 232 const uint32x4_t fdir_flags = 233 vdupq_n_u32(RTE_MBUF_F_RX_FDIR); 234 const uint32x4_t fdir_all_flags = 235 vdupq_n_u32(RTE_MBUF_F_RX_FDIR | 236 rxq->mark_flag); 237 uint32x4_t fdir_id_flags = 238 vdupq_n_u32(rxq->mark_flag); 239 uint32x4_t invalid_mask, ftag; 240 241 __asm__ volatile 242 /* A.1 load mCQEs into a 128bit register. */ 243 ("ld1 {v16.16b - v17.16b}, [%[mcq]]\n\t" 244 /* Extract flow_tag. */ 245 "tbl %[ftag].16b, {v16.16b - v17.16b}, %[flow_mark_shuf].16b\n\t" 246 : [ftag]"=&w"(ftag) 247 : [mcq]"r"(p), 248 [flow_mark_shuf]"w"(flow_mark_shuf) 249 : "memory", "v16", "v17"); 250 invalid_mask = vceqzq_u32(ftag); 251 ol_flags_mask = vorrq_u32(ol_flags_mask, 252 fdir_all_flags); 253 /* Set RTE_MBUF_F_RX_FDIR if flow tag is non-zero. */ 254 ol_flags = vorrq_u32(ol_flags, 255 vbicq_u32(fdir_flags, invalid_mask)); 256 /* Mask out invalid entries. */ 257 fdir_id_flags = vbicq_u32(fdir_id_flags, 258 invalid_mask); 259 /* Check if flow tag MLX5_FLOW_MARK_DEFAULT. */ 260 ol_flags = vorrq_u32(ol_flags, 261 vbicq_u32(fdir_id_flags, 262 vceqq_u32(ftag, ft_mask))); 263 ftag = vaddq_u32(ftag, flow_mark_adj); 264 elts[pos]->hash.fdir.hi = 265 vgetq_lane_u32(ftag, 3); 266 elts[pos + 1]->hash.fdir.hi = 267 vgetq_lane_u32(ftag, 2); 268 elts[pos + 2]->hash.fdir.hi = 269 vgetq_lane_u32(ftag, 1); 270 elts[pos + 3]->hash.fdir.hi = 271 vgetq_lane_u32(ftag, 0); 272 } 273 } 274 if (unlikely(rxq->mcqe_format != 275 MLX5_CQE_RESP_FORMAT_HASH)) { 276 if (rxq->mcqe_format == 277 MLX5_CQE_RESP_FORMAT_L34H_STRIDX) { 278 const uint8_t pkt_info = 279 (cq->pkt_info & 0x3) << 6; 280 const uint8_t pkt_hdr0 = 281 mcq[pos % 8].hdr_type; 282 const uint8_t pkt_hdr1 = 283 mcq[pos % 8 + 1].hdr_type; 284 const uint8_t pkt_hdr2 = 285 mcq[pos % 8 + 2].hdr_type; 286 const uint8_t pkt_hdr3 = 287 mcq[pos % 8 + 3].hdr_type; 288 const uint32x4_t vlan_mask = 289 vdupq_n_u32(RTE_MBUF_F_RX_VLAN | 290 RTE_MBUF_F_RX_VLAN_STRIPPED); 291 const uint32x4_t cv_mask = 292 vdupq_n_u32(MLX5_CQE_VLAN_STRIPPED); 293 const uint32x4_t pkt_cv = { 294 pkt_hdr0 & 0x1, pkt_hdr1 & 0x1, 295 pkt_hdr2 & 0x1, pkt_hdr3 & 0x1}; 296 297 ol_flags_mask = vorrq_u32(ol_flags_mask, 298 vlan_mask); 299 ol_flags = vorrq_u32(ol_flags, 300 vandq_u32(vlan_mask, 301 vceqq_u32(pkt_cv, cv_mask))); 302 elts[pos]->packet_type = 303 mlx5_ptype_table[(pkt_hdr0 >> 2) | 304 pkt_info]; 305 elts[pos + 1]->packet_type = 306 mlx5_ptype_table[(pkt_hdr1 >> 2) | 307 pkt_info]; 308 elts[pos + 2]->packet_type = 309 mlx5_ptype_table[(pkt_hdr2 >> 2) | 310 pkt_info]; 311 elts[pos + 3]->packet_type = 312 mlx5_ptype_table[(pkt_hdr3 >> 2) | 313 pkt_info]; 314 if (rxq->tunnel) { 315 elts[pos]->packet_type |= 316 !!(((pkt_hdr0 >> 2) | 317 pkt_info) & (1 << 6)); 318 elts[pos + 1]->packet_type |= 319 !!(((pkt_hdr1 >> 2) | 320 pkt_info) & (1 << 6)); 321 elts[pos + 2]->packet_type |= 322 !!(((pkt_hdr2 >> 2) | 323 pkt_info) & (1 << 6)); 324 elts[pos + 3]->packet_type |= 325 !!(((pkt_hdr3 >> 2) | 326 pkt_info) & (1 << 6)); 327 } 328 } 329 const uint32x4_t hash_flags = 330 vdupq_n_u32(RTE_MBUF_F_RX_RSS_HASH); 331 const uint32x4_t rearm_flags = 332 vdupq_n_u32((uint32_t)t_pkt->ol_flags); 333 334 ol_flags_mask = vorrq_u32(ol_flags_mask, hash_flags); 335 ol_flags = vorrq_u32(ol_flags, 336 vbicq_u32(rearm_flags, ol_flags_mask)); 337 elts[pos]->ol_flags = vgetq_lane_u32(ol_flags, 3); 338 elts[pos + 1]->ol_flags = vgetq_lane_u32(ol_flags, 2); 339 elts[pos + 2]->ol_flags = vgetq_lane_u32(ol_flags, 1); 340 elts[pos + 3]->ol_flags = vgetq_lane_u32(ol_flags, 0); 341 elts[pos]->hash.rss = 0; 342 elts[pos + 1]->hash.rss = 0; 343 elts[pos + 2]->hash.rss = 0; 344 elts[pos + 3]->hash.rss = 0; 345 } 346 if (rxq->dynf_meta) { 347 int32_t offs = rxq->flow_meta_offset; 348 const uint32_t meta = 349 *RTE_MBUF_DYNFIELD(t_pkt, offs, uint32_t *); 350 351 /* Check if title packet has valid metadata. */ 352 if (meta) { 353 MLX5_ASSERT(t_pkt->ol_flags & 354 rxq->flow_meta_mask); 355 *RTE_MBUF_DYNFIELD(elts[pos], offs, 356 uint32_t *) = meta; 357 *RTE_MBUF_DYNFIELD(elts[pos + 1], offs, 358 uint32_t *) = meta; 359 *RTE_MBUF_DYNFIELD(elts[pos + 2], offs, 360 uint32_t *) = meta; 361 *RTE_MBUF_DYNFIELD(elts[pos + 3], offs, 362 uint32_t *) = meta; 363 } 364 } 365 pos += MLX5_VPMD_DESCS_PER_LOOP; 366 /* Move to next CQE and invalidate consumed CQEs. */ 367 if (!rxq->cqe_comp_layout) { 368 if (!(pos & 0x7) && pos < mcqe_n) { 369 if (pos + 8 < mcqe_n) 370 rte_prefetch0((void *)(cq + pos + 8)); 371 mcq = (void *)&(cq + pos)->pkt_info; 372 for (i = 0; i < 8; ++i) 373 cq[inv++].op_own = MLX5_CQE_INVALIDATE; 374 } 375 } 376 } 377 if (rxq->cqe_comp_layout && keep) { 378 int ret; 379 /* Keep unzipping if the next CQE is the miniCQE array. */ 380 cq = &cq[mcqe_n]; 381 ret = check_cqe_iteration(cq, rxq->cqe_n, rxq->cq_ci + pkts_n); 382 if (ret == MLX5_CQE_STATUS_SW_OWN && 383 MLX5_CQE_FORMAT(cq->op_own) == MLX5_COMPRESSED) { 384 pos = 0; 385 elts = &elts[mcqe_n]; 386 mcq = (void *)cq; 387 mcqe_n = MLX5_CQE_NUM_MINIS(cq->op_own) + 1; 388 pkts_n += mcqe_n; 389 goto cycle; 390 } 391 } else { 392 /* Invalidate the rest of CQEs. */ 393 for (; inv < pkts_n; ++inv) 394 cq[inv].op_own = MLX5_CQE_INVALIDATE; 395 } 396 #ifdef MLX5_PMD_SOFT_COUNTERS 397 rxq->stats.ipackets += pkts_n; 398 rxq->stats.ibytes += rcvd_byte; 399 #endif 400 return pkts_n; 401 } 402 403 /** 404 * Calculate packet type and offload flag for mbuf and store it. 405 * 406 * @param rxq 407 * Pointer to RX queue structure. 408 * @param ptype_info 409 * Array of four 4bytes packet type info extracted from the original 410 * completion descriptor. 411 * @param flow_tag 412 * Array of four 4bytes flow ID extracted from the original completion 413 * descriptor. 414 * @param op_err 415 * Opcode vector having responder error status. Each field is 4B. 416 * @param pkts 417 * Pointer to array of packets to be filled. 418 */ 419 static inline void 420 rxq_cq_to_ptype_oflags_v(struct mlx5_rxq_data *rxq, 421 uint32x4_t ptype_info, uint32x4_t flow_tag, 422 uint16x4_t op_err, struct rte_mbuf **pkts) 423 { 424 uint16x4_t ptype; 425 uint32x4_t pinfo, cv_flags; 426 uint32x4_t ol_flags = 427 vdupq_n_u32(rxq->rss_hash * RTE_MBUF_F_RX_RSS_HASH | 428 rxq->hw_timestamp * rxq->timestamp_rx_flag); 429 const uint32x4_t ptype_ol_mask = { 0x106, 0x106, 0x106, 0x106 }; 430 const uint8x16_t cv_flag_sel = { 431 0, 432 (uint8_t)(RTE_MBUF_F_RX_VLAN | RTE_MBUF_F_RX_VLAN_STRIPPED), 433 (uint8_t)(RTE_MBUF_F_RX_IP_CKSUM_GOOD >> 1), 434 0, 435 (uint8_t)(RTE_MBUF_F_RX_L4_CKSUM_GOOD >> 1), 436 0, 437 (uint8_t)((RTE_MBUF_F_RX_IP_CKSUM_GOOD | RTE_MBUF_F_RX_L4_CKSUM_GOOD) >> 1), 438 0, 0, 0, 0, 0, 0, 0, 0, 0 439 }; 440 const uint32x4_t cv_mask = 441 vdupq_n_u32(RTE_MBUF_F_RX_IP_CKSUM_GOOD | RTE_MBUF_F_RX_L4_CKSUM_GOOD | 442 RTE_MBUF_F_RX_VLAN | RTE_MBUF_F_RX_VLAN_STRIPPED); 443 const uint64x2_t mbuf_init = vld1q_u64 444 ((const uint64_t *)&rxq->mbuf_initializer); 445 uint64x2_t rearm0, rearm1, rearm2, rearm3; 446 uint8_t pt_idx0, pt_idx1, pt_idx2, pt_idx3; 447 448 if (rxq->mark) { 449 const uint32x4_t ft_def = vdupq_n_u32(MLX5_FLOW_MARK_DEFAULT); 450 const uint32x4_t fdir_flags = vdupq_n_u32(RTE_MBUF_F_RX_FDIR); 451 uint32x4_t fdir_id_flags = vdupq_n_u32(rxq->mark_flag); 452 uint32x4_t invalid_mask; 453 454 /* Check if flow tag is non-zero then set RTE_MBUF_F_RX_FDIR. */ 455 invalid_mask = vceqzq_u32(flow_tag); 456 ol_flags = vorrq_u32(ol_flags, 457 vbicq_u32(fdir_flags, invalid_mask)); 458 /* Mask out invalid entries. */ 459 fdir_id_flags = vbicq_u32(fdir_id_flags, invalid_mask); 460 /* Check if flow tag MLX5_FLOW_MARK_DEFAULT. */ 461 ol_flags = vorrq_u32(ol_flags, 462 vbicq_u32(fdir_id_flags, 463 vceqq_u32(flow_tag, ft_def))); 464 } 465 /* 466 * ptype_info has the following: 467 * bit[1] = l3_ok 468 * bit[2] = l4_ok 469 * bit[8] = cv 470 * bit[11:10] = l3_hdr_type 471 * bit[14:12] = l4_hdr_type 472 * bit[15] = ip_frag 473 * bit[16] = tunneled 474 * bit[17] = outer_l3_type 475 */ 476 ptype = vshrn_n_u32(ptype_info, 10); 477 /* Errored packets will have RTE_PTYPE_ALL_MASK. */ 478 ptype = vorr_u16(ptype, op_err); 479 pt_idx0 = vget_lane_u8(vreinterpret_u8_u16(ptype), 6); 480 pt_idx1 = vget_lane_u8(vreinterpret_u8_u16(ptype), 4); 481 pt_idx2 = vget_lane_u8(vreinterpret_u8_u16(ptype), 2); 482 pt_idx3 = vget_lane_u8(vreinterpret_u8_u16(ptype), 0); 483 pkts[0]->packet_type = mlx5_ptype_table[pt_idx0] | 484 !!(pt_idx0 & (1 << 6)) * rxq->tunnel; 485 pkts[1]->packet_type = mlx5_ptype_table[pt_idx1] | 486 !!(pt_idx1 & (1 << 6)) * rxq->tunnel; 487 pkts[2]->packet_type = mlx5_ptype_table[pt_idx2] | 488 !!(pt_idx2 & (1 << 6)) * rxq->tunnel; 489 pkts[3]->packet_type = mlx5_ptype_table[pt_idx3] | 490 !!(pt_idx3 & (1 << 6)) * rxq->tunnel; 491 /* Fill flags for checksum and VLAN. */ 492 pinfo = vandq_u32(ptype_info, ptype_ol_mask); 493 pinfo = vreinterpretq_u32_u8( 494 vqtbl1q_u8(cv_flag_sel, vreinterpretq_u8_u32(pinfo))); 495 /* Locate checksum flags at byte[2:1] and merge with VLAN flags. */ 496 cv_flags = vshlq_n_u32(pinfo, 9); 497 cv_flags = vorrq_u32(pinfo, cv_flags); 498 /* Move back flags to start from byte[0]. */ 499 cv_flags = vshrq_n_u32(cv_flags, 8); 500 /* Mask out garbage bits. */ 501 cv_flags = vandq_u32(cv_flags, cv_mask); 502 /* Merge to ol_flags. */ 503 ol_flags = vorrq_u32(ol_flags, cv_flags); 504 /* Merge mbuf_init and ol_flags, and store. */ 505 rearm0 = vreinterpretq_u64_u32(vsetq_lane_u32 506 (vgetq_lane_u32(ol_flags, 3), 507 vreinterpretq_u32_u64(mbuf_init), 2)); 508 rearm1 = vreinterpretq_u64_u32(vsetq_lane_u32 509 (vgetq_lane_u32(ol_flags, 2), 510 vreinterpretq_u32_u64(mbuf_init), 2)); 511 rearm2 = vreinterpretq_u64_u32(vsetq_lane_u32 512 (vgetq_lane_u32(ol_flags, 1), 513 vreinterpretq_u32_u64(mbuf_init), 2)); 514 rearm3 = vreinterpretq_u64_u32(vsetq_lane_u32 515 (vgetq_lane_u32(ol_flags, 0), 516 vreinterpretq_u32_u64(mbuf_init), 2)); 517 518 vst1q_u64((void *)&pkts[0]->rearm_data, rearm0); 519 vst1q_u64((void *)&pkts[1]->rearm_data, rearm1); 520 vst1q_u64((void *)&pkts[2]->rearm_data, rearm2); 521 vst1q_u64((void *)&pkts[3]->rearm_data, rearm3); 522 } 523 524 /** 525 * Process a non-compressed completion and fill in mbufs in RX SW ring 526 * with data extracted from the title completion descriptor. 527 * 528 * @param rxq 529 * Pointer to RX queue structure. 530 * @param cq 531 * Pointer to completion array having a non-compressed completion at first. 532 * @param elts 533 * Pointer to SW ring to be filled. The first mbuf has to be pre-built from 534 * the title completion descriptor to be copied to the rest of mbufs. 535 * @param[out] pkts 536 * Array to store received packets. 537 * @param pkts_n 538 * Maximum number of packets in array. 539 * @param[out] err 540 * Pointer to a flag. Set non-zero value if pkts array has at least one error 541 * packet to handle. 542 * @param[out] comp 543 * Pointer to a index. Set it to the first compressed completion if any. 544 * 545 * @return 546 * Number of CQEs successfully processed. 547 */ 548 static inline uint16_t 549 rxq_cq_process_v(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cq, 550 struct rte_mbuf **elts, struct rte_mbuf **pkts, 551 uint16_t pkts_n, uint64_t *err, uint64_t *comp) 552 { 553 const uint16_t q_n = 1 << rxq->cqe_n; 554 const uint16_t q_mask = q_n - 1; 555 unsigned int pos, adj; 556 uint64_t n = 0; 557 uint64_t comp_idx = MLX5_VPMD_DESCS_PER_LOOP; 558 uint16_t nocmp_n = 0; 559 const uint16x4_t validity = vdup_n_u16((rxq->cq_ci >> rxq->cqe_n) << 8); 560 const uint16x4_t ownership = vdup_n_u16(!(rxq->cq_ci & (q_mask + 1))); 561 const uint16x4_t vic_check = vcreate_u16(0xff00ff00ff00ff00); 562 const uint16x4_t owner_check = vcreate_u16(0x0001000100010001); 563 const uint16x4_t opcode_check = vcreate_u16(0x00f000f000f000f0); 564 const uint16x4_t format_check = vcreate_u16(0x000c000c000c000c); 565 const uint16x4_t resp_err_check = vcreate_u16(0x00e000e000e000e0); 566 #ifdef MLX5_PMD_SOFT_COUNTERS 567 uint32_t rcvd_byte = 0; 568 #endif 569 /* Mask to generate 16B length vector. */ 570 const uint8x8_t len_shuf_m = { 571 52, 53, /* 4th CQE */ 572 36, 37, /* 3rd CQE */ 573 20, 21, /* 2nd CQE */ 574 4, 5 /* 1st CQE */ 575 }; 576 /* Mask to extract 16B data from a 64B CQE. */ 577 const uint8x16_t cqe_shuf_m = { 578 28, 29, /* hdr_type_etc */ 579 0, /* pkt_info */ 580 62, /* validity_iteration_count */ 581 47, 46, /* byte_cnt, bswap16 */ 582 31, 30, /* vlan_info, bswap16 */ 583 15, 14, 13, 12, /* rx_hash_res, bswap32 */ 584 57, 58, 59, /* flow_tag */ 585 63 /* op_own */ 586 }; 587 /* Mask to generate 16B data for mbuf. */ 588 const uint8x16_t mb_shuf_m = { 589 4, 5, -1, -1, /* pkt_len */ 590 4, 5, /* data_len */ 591 6, 7, /* vlan_tci */ 592 8, 9, 10, 11, /* hash.rss */ 593 12, 13, 14, -1 /* hash.fdir.hi */ 594 }; 595 /* Mask to generate 16B owner vector. */ 596 const uint8x8_t owner_shuf_m = { 597 63, 51, /* 4th CQE */ 598 47, 35, /* 3rd CQE */ 599 31, 19, /* 2nd CQE */ 600 15, 3 /* 1st CQE */ 601 }; 602 /* Mask to generate a vector having packet_type/ol_flags. */ 603 const uint8x16_t ptype_shuf_m = { 604 48, 49, 50, -1, /* 4th CQE */ 605 32, 33, 34, -1, /* 3rd CQE */ 606 16, 17, 18, -1, /* 2nd CQE */ 607 0, 1, 2, -1 /* 1st CQE */ 608 }; 609 /* Mask to generate a vector having flow tags. */ 610 const uint8x16_t ftag_shuf_m = { 611 60, 61, 62, -1, /* 4th CQE */ 612 44, 45, 46, -1, /* 3rd CQE */ 613 28, 29, 30, -1, /* 2nd CQE */ 614 12, 13, 14, -1 /* 1st CQE */ 615 }; 616 const uint16x8_t crc_adj = { 617 0, 0, rxq->crc_present * RTE_ETHER_CRC_LEN, 0, 0, 0, 0, 0 618 }; 619 const uint32x4_t flow_mark_adj = { 0, 0, 0, rxq->mark * (-1) }; 620 621 /* 622 * Note that vectors have reverse order - {v3, v2, v1, v0}, because 623 * there's no instruction to count trailing zeros. rte_clz64() is 624 * used instead. 625 * 626 * A. copy 4 mbuf pointers from elts ring to returning pkts. 627 * B. load 64B CQE and extract necessary fields 628 * Final 16bytes cqes[] extracted from original 64bytes CQE has the 629 * following structure: 630 * struct { 631 * uint16_t hdr_type_etc; 632 * uint8_t pkt_info; 633 * uint8_t validity_iteration_count; 634 * uint16_t byte_cnt; 635 * uint16_t vlan_info; 636 * uint32_t rx_has_res; 637 * uint8_t flow_tag[3]; 638 * uint8_t op_own; 639 * } c; 640 * C. fill in mbuf. 641 * D. get valid CQEs. 642 * E. find compressed CQE. 643 */ 644 for (pos = 0; 645 pos < pkts_n; 646 pos += MLX5_VPMD_DESCS_PER_LOOP) { 647 uint16x4_t op_own; 648 uint16x4_t opcode, owner_mask, invalid_mask; 649 uint16x4_t comp_mask, mini_mask; 650 uint16x4_t mask; 651 uint16x4_t byte_cnt; 652 uint32x4_t ptype_info, flow_tag; 653 register uint64x2_t c0, c1, c2, c3; 654 uint8_t *p0, *p1, *p2, *p3; 655 uint8_t *e0 = (void *)&elts[pos]->pkt_len; 656 uint8_t *e1 = (void *)&elts[pos + 1]->pkt_len; 657 uint8_t *e2 = (void *)&elts[pos + 2]->pkt_len; 658 uint8_t *e3 = (void *)&elts[pos + 3]->pkt_len; 659 void *elts_p = (void *)&elts[pos]; 660 void *pkts_p = (void *)&pkts[pos]; 661 662 /* A.0 do not cross the end of CQ. */ 663 mask = vcreate_u16(pkts_n - pos < MLX5_VPMD_DESCS_PER_LOOP ? 664 -1UL >> ((pkts_n - pos) * 665 sizeof(uint16_t) * 8) : 0); 666 p0 = (void *)&cq[pos].pkt_info; 667 p1 = p0 + (pkts_n - pos > 1) * sizeof(struct mlx5_cqe); 668 p2 = p1 + (pkts_n - pos > 2) * sizeof(struct mlx5_cqe); 669 p3 = p2 + (pkts_n - pos > 3) * sizeof(struct mlx5_cqe); 670 /* B.0 (CQE 3) load a block having op_own. */ 671 c3 = vld1q_u64((uint64_t *)(p3 + 48)); 672 /* B.0 (CQE 2) load a block having op_own. */ 673 c2 = vld1q_u64((uint64_t *)(p2 + 48)); 674 /* B.0 (CQE 1) load a block having op_own. */ 675 c1 = vld1q_u64((uint64_t *)(p1 + 48)); 676 /* B.0 (CQE 0) load a block having op_own. */ 677 c0 = vld1q_u64((uint64_t *)(p0 + 48)); 678 /* Synchronize for loading the rest of blocks. */ 679 rte_io_rmb(); 680 /* B.0 (CQE 3) reload lower half of the block. */ 681 c3 = vld1q_lane_u64((uint64_t *)(p3 + 48), c3, 0); 682 /* B.0 (CQE 2) reload lower half of the block. */ 683 c2 = vld1q_lane_u64((uint64_t *)(p2 + 48), c2, 0); 684 /* B.0 (CQE 1) reload lower half of the block. */ 685 c1 = vld1q_lane_u64((uint64_t *)(p1 + 48), c1, 0); 686 /* B.0 (CQE 0) reload lower half of the block. */ 687 c0 = vld1q_lane_u64((uint64_t *)(p0 + 48), c0, 0); 688 /* Prefetch next 4 CQEs. */ 689 if (pkts_n - pos >= 2 * MLX5_VPMD_DESCS_PER_LOOP) { 690 unsigned int next = pos + MLX5_VPMD_DESCS_PER_LOOP; 691 rte_prefetch_non_temporal(&cq[next]); 692 rte_prefetch_non_temporal(&cq[next + 1]); 693 rte_prefetch_non_temporal(&cq[next + 2]); 694 rte_prefetch_non_temporal(&cq[next + 3]); 695 } 696 __asm__ volatile ( 697 /* B.1 (CQE 3) load the rest of blocks. */ 698 "ld1 {v16.16b - v18.16b}, [%[p3]] \n\t" 699 /* B.2 (CQE 3) move the block having op_own. */ 700 "mov v19.16b, %[c3].16b \n\t" 701 /* B.3 (CQE 3) extract 16B fields. */ 702 "tbl v23.16b, {v16.16b - v19.16b}, %[cqe_shuf_m].16b \n\t" 703 /* B.1 (CQE 2) load the rest of blocks. */ 704 "ld1 {v16.16b - v18.16b}, [%[p2]] \n\t" 705 /* B.4 (CQE 3) adjust CRC length. */ 706 "sub v23.8h, v23.8h, %[crc_adj].8h \n\t" 707 /* C.1 (CQE 3) generate final structure for mbuf. */ 708 "tbl v15.16b, {v23.16b}, %[mb_shuf_m].16b \n\t" 709 /* B.2 (CQE 2) move the block having op_own. */ 710 "mov v19.16b, %[c2].16b \n\t" 711 /* B.3 (CQE 2) extract 16B fields. */ 712 "tbl v22.16b, {v16.16b - v19.16b}, %[cqe_shuf_m].16b \n\t" 713 /* B.1 (CQE 1) load the rest of blocks. */ 714 "ld1 {v16.16b - v18.16b}, [%[p1]] \n\t" 715 /* B.4 (CQE 2) adjust CRC length. */ 716 "sub v22.8h, v22.8h, %[crc_adj].8h \n\t" 717 /* C.1 (CQE 2) generate final structure for mbuf. */ 718 "tbl v14.16b, {v22.16b}, %[mb_shuf_m].16b \n\t" 719 /* B.2 (CQE 1) move the block having op_own. */ 720 "mov v19.16b, %[c1].16b \n\t" 721 /* B.3 (CQE 1) extract 16B fields. */ 722 "tbl v21.16b, {v16.16b - v19.16b}, %[cqe_shuf_m].16b \n\t" 723 /* B.1 (CQE 0) load the rest of blocks. */ 724 "ld1 {v16.16b - v18.16b}, [%[p0]] \n\t" 725 /* B.4 (CQE 1) adjust CRC length. */ 726 "sub v21.8h, v21.8h, %[crc_adj].8h \n\t" 727 /* C.1 (CQE 1) generate final structure for mbuf. */ 728 "tbl v13.16b, {v21.16b}, %[mb_shuf_m].16b \n\t" 729 /* B.2 (CQE 0) move the block having op_own. */ 730 "mov v19.16b, %[c0].16b \n\t" 731 /* A.1 load mbuf pointers. */ 732 "ld1 {v24.2d - v25.2d}, [%[elts_p]] \n\t" 733 /* B.3 (CQE 0) extract 16B fields. */ 734 "tbl v20.16b, {v16.16b - v19.16b}, %[cqe_shuf_m].16b \n\t" 735 /* B.4 (CQE 0) adjust CRC length. */ 736 "sub v20.8h, v20.8h, %[crc_adj].8h \n\t" 737 /* D.1 extract op_own byte. */ 738 "tbl %[op_own].8b, {v20.16b - v23.16b}, %[owner_shuf_m].8b \n\t" 739 /* C.2 (CQE 3) adjust flow mark. */ 740 "add v15.4s, v15.4s, %[flow_mark_adj].4s \n\t" 741 /* C.3 (CQE 3) fill in mbuf - rx_descriptor_fields1. */ 742 "st1 {v15.2d}, [%[e3]] \n\t" 743 /* C.2 (CQE 2) adjust flow mark. */ 744 "add v14.4s, v14.4s, %[flow_mark_adj].4s \n\t" 745 /* C.3 (CQE 2) fill in mbuf - rx_descriptor_fields1. */ 746 "st1 {v14.2d}, [%[e2]] \n\t" 747 /* C.1 (CQE 0) generate final structure for mbuf. */ 748 "tbl v12.16b, {v20.16b}, %[mb_shuf_m].16b \n\t" 749 /* C.2 (CQE 1) adjust flow mark. */ 750 "add v13.4s, v13.4s, %[flow_mark_adj].4s \n\t" 751 /* C.3 (CQE 1) fill in mbuf - rx_descriptor_fields1. */ 752 "st1 {v13.2d}, [%[e1]] \n\t" 753 #ifdef MLX5_PMD_SOFT_COUNTERS 754 /* Extract byte_cnt. */ 755 "tbl %[byte_cnt].8b, {v20.16b - v23.16b}, %[len_shuf_m].8b \n\t" 756 #endif 757 /* Extract ptype_info. */ 758 "tbl %[ptype_info].16b, {v20.16b - v23.16b}, %[ptype_shuf_m].16b \n\t" 759 /* Extract flow_tag. */ 760 "tbl %[flow_tag].16b, {v20.16b - v23.16b}, %[ftag_shuf_m].16b \n\t" 761 /* A.2 copy mbuf pointers. */ 762 "st1 {v24.2d - v25.2d}, [%[pkts_p]] \n\t" 763 /* C.2 (CQE 0) adjust flow mark. */ 764 "add v12.4s, v12.4s, %[flow_mark_adj].4s \n\t" 765 /* C.3 (CQE 1) fill in mbuf - rx_descriptor_fields1. */ 766 "st1 {v12.2d}, [%[e0]] \n\t" 767 :[op_own]"=&w"(op_own), 768 [byte_cnt]"=&w"(byte_cnt), 769 [ptype_info]"=&w"(ptype_info), 770 [flow_tag]"=&w"(flow_tag) 771 :[p3]"r"(p3), [p2]"r"(p2), [p1]"r"(p1), [p0]"r"(p0), 772 [e3]"r"(e3), [e2]"r"(e2), [e1]"r"(e1), [e0]"r"(e0), 773 [c3]"w"(c3), [c2]"w"(c2), [c1]"w"(c1), [c0]"w"(c0), 774 [elts_p]"r"(elts_p), 775 [pkts_p]"r"(pkts_p), 776 [cqe_shuf_m]"w"(cqe_shuf_m), 777 [mb_shuf_m]"w"(mb_shuf_m), 778 [owner_shuf_m]"w"(owner_shuf_m), 779 [len_shuf_m]"w"(len_shuf_m), 780 [ptype_shuf_m]"w"(ptype_shuf_m), 781 [ftag_shuf_m]"w"(ftag_shuf_m), 782 [crc_adj]"w"(crc_adj), 783 [flow_mark_adj]"w"(flow_mark_adj) 784 :"memory", 785 "v12", "v13", "v14", "v15", 786 "v16", "v17", "v18", "v19", 787 "v20", "v21", "v22", "v23", 788 "v24", "v25"); 789 /* D.2 mask out CQEs belonging to HW. */ 790 if (rxq->cqe_comp_layout) { 791 owner_mask = vand_u16(op_own, vic_check); 792 owner_mask = vceq_u16(owner_mask, validity); 793 owner_mask = vmvn_u16(owner_mask); 794 } else { 795 owner_mask = vand_u16(op_own, owner_check); 796 owner_mask = vceq_u16(owner_mask, ownership); 797 } 798 /* D.3 get mask for invalidated CQEs. */ 799 opcode = vand_u16(op_own, opcode_check); 800 invalid_mask = vceq_u16(opcode_check, opcode); 801 /* E.1 find compressed CQE format. */ 802 comp_mask = vand_u16(op_own, format_check); 803 comp_mask = vceq_u16(comp_mask, format_check); 804 /* D.4 mask out beyond boundary. */ 805 invalid_mask = vorr_u16(invalid_mask, mask); 806 /* D.5 merge invalid_mask with invalid owner. */ 807 invalid_mask = vorr_u16(invalid_mask, owner_mask); 808 /* E.2 mask out invalid entries. */ 809 comp_mask = vbic_u16(comp_mask, invalid_mask); 810 /* E.3 get the first compressed CQE. */ 811 comp_idx = rte_clz64(vget_lane_u64(vreinterpret_u64_u16(comp_mask), 0)) / 812 (sizeof(uint16_t) * 8); 813 invalid_mask = vorr_u16(invalid_mask, comp_mask); 814 /* D.7 count non-compressed valid CQEs. */ 815 n = rte_clz64(vget_lane_u64(vreinterpret_u64_u16(invalid_mask), 0)) / 816 (sizeof(uint16_t) * 8); 817 nocmp_n += n; 818 /* 819 * D.2 mask out entries after the compressed CQE. 820 * get the final invalid mask. 821 */ 822 mask = vcreate_u16(n < MLX5_VPMD_DESCS_PER_LOOP ? 823 -1UL >> (n * sizeof(uint16_t) * 8) : 0); 824 invalid_mask = vorr_u16(invalid_mask, mask); 825 /* D.3 check error in opcode. */ 826 adj = (!rxq->cqe_comp_layout && 827 comp_idx != MLX5_VPMD_DESCS_PER_LOOP && comp_idx == n); 828 mask = vcreate_u16(adj ? 829 -1UL >> ((n + 1) * sizeof(uint16_t) * 8) : -1UL); 830 mini_mask = vand_u16(invalid_mask, mask); 831 opcode = vceq_u16(resp_err_check, opcode); 832 opcode = vbic_u16(opcode, mini_mask); 833 /* D.4 mark if any error is set */ 834 *err |= vget_lane_u64(vreinterpret_u64_u16(opcode), 0); 835 /* C.4 fill in mbuf - rearm_data and packet_type. */ 836 rxq_cq_to_ptype_oflags_v(rxq, ptype_info, flow_tag, 837 opcode, &elts[pos]); 838 if (unlikely(rxq->shared)) { 839 pkts[pos]->port = container_of(p0, struct mlx5_cqe, 840 pkt_info)->user_index_low; 841 pkts[pos + 1]->port = container_of(p1, struct mlx5_cqe, 842 pkt_info)->user_index_low; 843 pkts[pos + 2]->port = container_of(p2, struct mlx5_cqe, 844 pkt_info)->user_index_low; 845 pkts[pos + 3]->port = container_of(p3, struct mlx5_cqe, 846 pkt_info)->user_index_low; 847 } 848 if (unlikely(rxq->hw_timestamp)) { 849 int offset = rxq->timestamp_offset; 850 if (rxq->rt_timestamp) { 851 struct mlx5_dev_ctx_shared *sh = rxq->sh; 852 uint64_t ts; 853 854 ts = rte_be_to_cpu_64 855 (container_of(p0, struct mlx5_cqe, 856 pkt_info)->timestamp); 857 mlx5_timestamp_set(pkts[pos], offset, 858 mlx5_txpp_convert_rx_ts(sh, ts)); 859 ts = rte_be_to_cpu_64 860 (container_of(p1, struct mlx5_cqe, 861 pkt_info)->timestamp); 862 mlx5_timestamp_set(pkts[pos + 1], offset, 863 mlx5_txpp_convert_rx_ts(sh, ts)); 864 ts = rte_be_to_cpu_64 865 (container_of(p2, struct mlx5_cqe, 866 pkt_info)->timestamp); 867 mlx5_timestamp_set(pkts[pos + 2], offset, 868 mlx5_txpp_convert_rx_ts(sh, ts)); 869 ts = rte_be_to_cpu_64 870 (container_of(p3, struct mlx5_cqe, 871 pkt_info)->timestamp); 872 mlx5_timestamp_set(pkts[pos + 3], offset, 873 mlx5_txpp_convert_rx_ts(sh, ts)); 874 } else { 875 mlx5_timestamp_set(pkts[pos], offset, 876 rte_be_to_cpu_64(container_of(p0, 877 struct mlx5_cqe, pkt_info)->timestamp)); 878 mlx5_timestamp_set(pkts[pos + 1], offset, 879 rte_be_to_cpu_64(container_of(p1, 880 struct mlx5_cqe, pkt_info)->timestamp)); 881 mlx5_timestamp_set(pkts[pos + 2], offset, 882 rte_be_to_cpu_64(container_of(p2, 883 struct mlx5_cqe, pkt_info)->timestamp)); 884 mlx5_timestamp_set(pkts[pos + 3], offset, 885 rte_be_to_cpu_64(container_of(p3, 886 struct mlx5_cqe, pkt_info)->timestamp)); 887 } 888 } 889 if (rxq->dynf_meta) { 890 /* This code is subject for further optimization. */ 891 int32_t offs = rxq->flow_meta_offset; 892 uint32_t mask = rxq->flow_meta_port_mask; 893 894 *RTE_MBUF_DYNFIELD(pkts[pos], offs, uint32_t *) = 895 rte_be_to_cpu_32(container_of 896 (p0, struct mlx5_cqe, 897 pkt_info)->flow_table_metadata) & mask; 898 *RTE_MBUF_DYNFIELD(pkts[pos + 1], offs, uint32_t *) = 899 rte_be_to_cpu_32(container_of 900 (p1, struct mlx5_cqe, 901 pkt_info)->flow_table_metadata) & mask; 902 *RTE_MBUF_DYNFIELD(pkts[pos + 2], offs, uint32_t *) = 903 rte_be_to_cpu_32(container_of 904 (p2, struct mlx5_cqe, 905 pkt_info)->flow_table_metadata) & mask; 906 *RTE_MBUF_DYNFIELD(pkts[pos + 3], offs, uint32_t *) = 907 rte_be_to_cpu_32(container_of 908 (p3, struct mlx5_cqe, 909 pkt_info)->flow_table_metadata) & mask; 910 if (*RTE_MBUF_DYNFIELD(pkts[pos], offs, uint32_t *)) 911 elts[pos]->ol_flags |= rxq->flow_meta_mask; 912 if (*RTE_MBUF_DYNFIELD(pkts[pos + 1], offs, uint32_t *)) 913 elts[pos + 1]->ol_flags |= rxq->flow_meta_mask; 914 if (*RTE_MBUF_DYNFIELD(pkts[pos + 2], offs, uint32_t *)) 915 elts[pos + 2]->ol_flags |= rxq->flow_meta_mask; 916 if (*RTE_MBUF_DYNFIELD(pkts[pos + 3], offs, uint32_t *)) 917 elts[pos + 3]->ol_flags |= rxq->flow_meta_mask; 918 } 919 #ifdef MLX5_PMD_SOFT_COUNTERS 920 /* Add up received bytes count. */ 921 byte_cnt = vbic_u16(byte_cnt, invalid_mask); 922 rcvd_byte += vget_lane_u64(vpaddl_u32(vpaddl_u16(byte_cnt)), 0); 923 #endif 924 /* 925 * Break the loop unless more valid CQE is expected, or if 926 * there's a compressed CQE. 927 */ 928 if (n != MLX5_VPMD_DESCS_PER_LOOP) 929 break; 930 } 931 #ifdef MLX5_PMD_SOFT_COUNTERS 932 rxq->stats.ipackets += nocmp_n; 933 rxq->stats.ibytes += rcvd_byte; 934 #endif 935 if (comp_idx == n) 936 *comp = comp_idx; 937 return nocmp_n; 938 } 939 940 #endif /* RTE_PMD_MLX5_RXTX_VEC_NEON_H_ */ 941