1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2017 6WIND S.A. 3 * Copyright 2017 Mellanox Technologies, Ltd 4 */ 5 6 #ifndef RTE_PMD_MLX5_RXTX_VEC_NEON_H_ 7 #define RTE_PMD_MLX5_RXTX_VEC_NEON_H_ 8 9 #include <stdint.h> 10 #include <string.h> 11 #include <stdlib.h> 12 #include <arm_neon.h> 13 14 #include <rte_mbuf.h> 15 #include <rte_mempool.h> 16 #include <rte_prefetch.h> 17 18 #include <mlx5_prm.h> 19 20 #include "mlx5_defs.h" 21 #include "mlx5.h" 22 #include "mlx5_utils.h" 23 #include "mlx5_rxtx.h" 24 #include "mlx5_rxtx_vec.h" 25 #include "mlx5_autoconf.h" 26 27 #pragma GCC diagnostic ignored "-Wcast-qual" 28 29 /** 30 * Store free buffers to RX SW ring. 31 * 32 * @param elts 33 * Pointer to SW ring to be filled. 34 * @param pkts 35 * Pointer to array of packets to be stored. 36 * @param pkts_n 37 * Number of packets to be stored. 38 */ 39 static inline void 40 rxq_copy_mbuf_v(struct rte_mbuf **elts, struct rte_mbuf **pkts, uint16_t n) 41 { 42 unsigned int pos; 43 uint16_t p = n & -2; 44 45 for (pos = 0; pos < p; pos += 2) { 46 uint64x2_t mbp; 47 48 mbp = vld1q_u64((void *)&elts[pos]); 49 vst1q_u64((void *)&pkts[pos], mbp); 50 } 51 if (n & 1) 52 pkts[pos] = elts[pos]; 53 } 54 55 /** 56 * Decompress a compressed completion and fill in mbufs in RX SW ring with data 57 * extracted from the title completion descriptor. 58 * 59 * @param rxq 60 * Pointer to RX queue structure. 61 * @param cq 62 * Pointer to completion array having a compressed completion at first. 63 * @param elts 64 * Pointer to SW ring to be filled. The first mbuf has to be pre-built from 65 * the title completion descriptor to be copied to the rest of mbufs. 66 * 67 * @return 68 * Number of mini-CQEs successfully decompressed. 69 */ 70 static inline uint16_t 71 rxq_cq_decompress_v(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cq, 72 struct rte_mbuf **elts) 73 { 74 volatile struct mlx5_mini_cqe8 *mcq = (void *)&(cq + 1)->pkt_info; 75 struct rte_mbuf *t_pkt = elts[0]; /* Title packet is pre-built. */ 76 unsigned int pos; 77 unsigned int i; 78 unsigned int inv = 0; 79 /* Mask to shuffle from extracted mini CQE to mbuf. */ 80 const uint8x16_t mcqe_shuf_m1 = { 81 -1, -1, -1, -1, /* skip packet_type */ 82 7, 6, -1, -1, /* pkt_len, bswap16 */ 83 7, 6, /* data_len, bswap16 */ 84 -1, -1, /* skip vlan_tci */ 85 3, 2, 1, 0 /* hash.rss, bswap32 */ 86 }; 87 const uint8x16_t mcqe_shuf_m2 = { 88 -1, -1, -1, -1, /* skip packet_type */ 89 15, 14, -1, -1, /* pkt_len, bswap16 */ 90 15, 14, /* data_len, bswap16 */ 91 -1, -1, /* skip vlan_tci */ 92 11, 10, 9, 8 /* hash.rss, bswap32 */ 93 }; 94 /* Restore the compressed count. Must be 16 bits. */ 95 const uint16_t mcqe_n = t_pkt->data_len + 96 (rxq->crc_present * RTE_ETHER_CRC_LEN); 97 const uint64x2_t rearm = 98 vld1q_u64((void *)&t_pkt->rearm_data); 99 const uint32x4_t rxdf_mask = { 100 0xffffffff, /* packet_type */ 101 0, /* skip pkt_len */ 102 0xffff0000, /* vlan_tci, skip data_len */ 103 0, /* skip hash.rss */ 104 }; 105 const uint8x16_t rxdf = 106 vandq_u8(vld1q_u8((void *)&t_pkt->rx_descriptor_fields1), 107 vreinterpretq_u8_u32(rxdf_mask)); 108 const uint16x8_t crc_adj = { 109 0, 0, 110 rxq->crc_present * RTE_ETHER_CRC_LEN, 0, 111 rxq->crc_present * RTE_ETHER_CRC_LEN, 0, 112 0, 0 113 }; 114 const uint32_t flow_tag = t_pkt->hash.fdir.hi; 115 #ifdef MLX5_PMD_SOFT_COUNTERS 116 uint32_t rcvd_byte = 0; 117 #endif 118 /* Mask to shuffle byte_cnt to add up stats. Do bswap16 for all. */ 119 const uint8x8_t len_shuf_m = { 120 7, 6, /* 1st mCQE */ 121 15, 14, /* 2nd mCQE */ 122 23, 22, /* 3rd mCQE */ 123 31, 30 /* 4th mCQE */ 124 }; 125 126 /* 127 * A. load mCQEs into a 128bit register. 128 * B. store rearm data to mbuf. 129 * C. combine data from mCQEs with rx_descriptor_fields1. 130 * D. store rx_descriptor_fields1. 131 * E. store flow tag (rte_flow mark). 132 */ 133 for (pos = 0; pos < mcqe_n; ) { 134 uint8_t *p = (void *)&mcq[pos % 8]; 135 uint8_t *e0 = (void *)&elts[pos]->rearm_data; 136 uint8_t *e1 = (void *)&elts[pos + 1]->rearm_data; 137 uint8_t *e2 = (void *)&elts[pos + 2]->rearm_data; 138 uint8_t *e3 = (void *)&elts[pos + 3]->rearm_data; 139 uint16x4_t byte_cnt; 140 #ifdef MLX5_PMD_SOFT_COUNTERS 141 uint16x4_t invalid_mask = 142 vcreate_u16(mcqe_n - pos < MLX5_VPMD_DESCS_PER_LOOP ? 143 -1UL << ((mcqe_n - pos) * 144 sizeof(uint16_t) * 8) : 0); 145 #endif 146 147 for (i = 0; i < MLX5_VPMD_DESCS_PER_LOOP; ++i) 148 if (likely(pos + i < mcqe_n)) 149 rte_prefetch0((void *)(cq + pos + i)); 150 __asm__ volatile ( 151 /* A.1 load mCQEs into a 128bit register. */ 152 "ld1 {v16.16b - v17.16b}, [%[mcq]] \n\t" 153 /* B.1 store rearm data to mbuf. */ 154 "st1 {%[rearm].2d}, [%[e0]] \n\t" 155 "add %[e0], %[e0], #16 \n\t" 156 "st1 {%[rearm].2d}, [%[e1]] \n\t" 157 "add %[e1], %[e1], #16 \n\t" 158 /* C.1 combine data from mCQEs with rx_descriptor_fields1. */ 159 "tbl v18.16b, {v16.16b}, %[mcqe_shuf_m1].16b \n\t" 160 "tbl v19.16b, {v16.16b}, %[mcqe_shuf_m2].16b \n\t" 161 "sub v18.8h, v18.8h, %[crc_adj].8h \n\t" 162 "sub v19.8h, v19.8h, %[crc_adj].8h \n\t" 163 "orr v18.16b, v18.16b, %[rxdf].16b \n\t" 164 "orr v19.16b, v19.16b, %[rxdf].16b \n\t" 165 /* D.1 store rx_descriptor_fields1. */ 166 "st1 {v18.2d}, [%[e0]] \n\t" 167 "st1 {v19.2d}, [%[e1]] \n\t" 168 /* B.1 store rearm data to mbuf. */ 169 "st1 {%[rearm].2d}, [%[e2]] \n\t" 170 "add %[e2], %[e2], #16 \n\t" 171 "st1 {%[rearm].2d}, [%[e3]] \n\t" 172 "add %[e3], %[e3], #16 \n\t" 173 /* C.1 combine data from mCQEs with rx_descriptor_fields1. */ 174 "tbl v18.16b, {v17.16b}, %[mcqe_shuf_m1].16b \n\t" 175 "tbl v19.16b, {v17.16b}, %[mcqe_shuf_m2].16b \n\t" 176 "sub v18.8h, v18.8h, %[crc_adj].8h \n\t" 177 "sub v19.8h, v19.8h, %[crc_adj].8h \n\t" 178 "orr v18.16b, v18.16b, %[rxdf].16b \n\t" 179 "orr v19.16b, v19.16b, %[rxdf].16b \n\t" 180 /* D.1 store rx_descriptor_fields1. */ 181 "st1 {v18.2d}, [%[e2]] \n\t" 182 "st1 {v19.2d}, [%[e3]] \n\t" 183 #ifdef MLX5_PMD_SOFT_COUNTERS 184 "tbl %[byte_cnt].8b, {v16.16b - v17.16b}, %[len_shuf_m].8b \n\t" 185 #endif 186 :[byte_cnt]"=&w"(byte_cnt) 187 :[mcq]"r"(p), 188 [rxdf]"w"(rxdf), 189 [rearm]"w"(rearm), 190 [e3]"r"(e3), [e2]"r"(e2), [e1]"r"(e1), [e0]"r"(e0), 191 [mcqe_shuf_m1]"w"(mcqe_shuf_m1), 192 [mcqe_shuf_m2]"w"(mcqe_shuf_m2), 193 [crc_adj]"w"(crc_adj), 194 [len_shuf_m]"w"(len_shuf_m) 195 :"memory", "v16", "v17", "v18", "v19"); 196 #ifdef MLX5_PMD_SOFT_COUNTERS 197 byte_cnt = vbic_u16(byte_cnt, invalid_mask); 198 rcvd_byte += vget_lane_u64(vpaddl_u32(vpaddl_u16(byte_cnt)), 0); 199 #endif 200 if (rxq->mark) { 201 /* E.1 store flow tag (rte_flow mark). */ 202 elts[pos]->hash.fdir.hi = flow_tag; 203 elts[pos + 1]->hash.fdir.hi = flow_tag; 204 elts[pos + 2]->hash.fdir.hi = flow_tag; 205 elts[pos + 3]->hash.fdir.hi = flow_tag; 206 } 207 if (rxq->dynf_meta) { 208 int32_t offs = rxq->flow_meta_offset; 209 const uint32_t meta = 210 *RTE_MBUF_DYNFIELD(t_pkt, offs, uint32_t *); 211 212 /* Check if title packet has valid metadata. */ 213 if (meta) { 214 MLX5_ASSERT(t_pkt->ol_flags & 215 rxq->flow_meta_mask); 216 *RTE_MBUF_DYNFIELD(elts[pos], offs, 217 uint32_t *) = meta; 218 *RTE_MBUF_DYNFIELD(elts[pos + 1], offs, 219 uint32_t *) = meta; 220 *RTE_MBUF_DYNFIELD(elts[pos + 2], offs, 221 uint32_t *) = meta; 222 *RTE_MBUF_DYNFIELD(elts[pos + 3], offs, 223 uint32_t *) = meta; 224 } 225 } 226 pos += MLX5_VPMD_DESCS_PER_LOOP; 227 /* Move to next CQE and invalidate consumed CQEs. */ 228 if (!(pos & 0x7) && pos < mcqe_n) { 229 if (pos + 8 < mcqe_n) 230 rte_prefetch0((void *)(cq + pos + 8)); 231 mcq = (void *)&(cq + pos)->pkt_info; 232 for (i = 0; i < 8; ++i) 233 cq[inv++].op_own = MLX5_CQE_INVALIDATE; 234 } 235 } 236 /* Invalidate the rest of CQEs. */ 237 for (; inv < mcqe_n; ++inv) 238 cq[inv].op_own = MLX5_CQE_INVALIDATE; 239 #ifdef MLX5_PMD_SOFT_COUNTERS 240 rxq->stats.ipackets += mcqe_n; 241 rxq->stats.ibytes += rcvd_byte; 242 #endif 243 rxq->cq_ci += mcqe_n; 244 return mcqe_n; 245 } 246 247 /** 248 * Calculate packet type and offload flag for mbuf and store it. 249 * 250 * @param rxq 251 * Pointer to RX queue structure. 252 * @param ptype_info 253 * Array of four 4bytes packet type info extracted from the original 254 * completion descriptor. 255 * @param flow_tag 256 * Array of four 4bytes flow ID extracted from the original completion 257 * descriptor. 258 * @param op_err 259 * Opcode vector having responder error status. Each field is 4B. 260 * @param pkts 261 * Pointer to array of packets to be filled. 262 */ 263 static inline void 264 rxq_cq_to_ptype_oflags_v(struct mlx5_rxq_data *rxq, 265 uint32x4_t ptype_info, uint32x4_t flow_tag, 266 uint16x4_t op_err, struct rte_mbuf **pkts) 267 { 268 uint16x4_t ptype; 269 uint32x4_t pinfo, cv_flags; 270 uint32x4_t ol_flags = 271 vdupq_n_u32(rxq->rss_hash * PKT_RX_RSS_HASH | 272 rxq->hw_timestamp * rxq->timestamp_rx_flag); 273 const uint32x4_t ptype_ol_mask = { 0x106, 0x106, 0x106, 0x106 }; 274 const uint8x16_t cv_flag_sel = { 275 0, 276 (uint8_t)(PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED), 277 (uint8_t)(PKT_RX_IP_CKSUM_GOOD >> 1), 278 0, 279 (uint8_t)(PKT_RX_L4_CKSUM_GOOD >> 1), 280 0, 281 (uint8_t)((PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD) >> 1), 282 0, 0, 0, 0, 0, 0, 0, 0, 0 283 }; 284 const uint32x4_t cv_mask = 285 vdupq_n_u32(PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD | 286 PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED); 287 const uint64x2_t mbuf_init = vld1q_u64 288 ((const uint64_t *)&rxq->mbuf_initializer); 289 uint64x2_t rearm0, rearm1, rearm2, rearm3; 290 uint8_t pt_idx0, pt_idx1, pt_idx2, pt_idx3; 291 292 if (rxq->mark) { 293 const uint32x4_t ft_def = vdupq_n_u32(MLX5_FLOW_MARK_DEFAULT); 294 const uint32x4_t fdir_flags = vdupq_n_u32(PKT_RX_FDIR); 295 uint32x4_t fdir_id_flags = vdupq_n_u32(PKT_RX_FDIR_ID); 296 uint32x4_t invalid_mask; 297 298 /* Check if flow tag is non-zero then set PKT_RX_FDIR. */ 299 invalid_mask = vceqzq_u32(flow_tag); 300 ol_flags = vorrq_u32(ol_flags, 301 vbicq_u32(fdir_flags, invalid_mask)); 302 /* Mask out invalid entries. */ 303 fdir_id_flags = vbicq_u32(fdir_id_flags, invalid_mask); 304 /* Check if flow tag MLX5_FLOW_MARK_DEFAULT. */ 305 ol_flags = vorrq_u32(ol_flags, 306 vbicq_u32(fdir_id_flags, 307 vceqq_u32(flow_tag, ft_def))); 308 } 309 /* 310 * ptype_info has the following: 311 * bit[1] = l3_ok 312 * bit[2] = l4_ok 313 * bit[8] = cv 314 * bit[11:10] = l3_hdr_type 315 * bit[14:12] = l4_hdr_type 316 * bit[15] = ip_frag 317 * bit[16] = tunneled 318 * bit[17] = outer_l3_type 319 */ 320 ptype = vshrn_n_u32(ptype_info, 10); 321 /* Errored packets will have RTE_PTYPE_ALL_MASK. */ 322 ptype = vorr_u16(ptype, op_err); 323 pt_idx0 = vget_lane_u8(vreinterpret_u8_u16(ptype), 6); 324 pt_idx1 = vget_lane_u8(vreinterpret_u8_u16(ptype), 4); 325 pt_idx2 = vget_lane_u8(vreinterpret_u8_u16(ptype), 2); 326 pt_idx3 = vget_lane_u8(vreinterpret_u8_u16(ptype), 0); 327 pkts[0]->packet_type = mlx5_ptype_table[pt_idx0] | 328 !!(pt_idx0 & (1 << 6)) * rxq->tunnel; 329 pkts[1]->packet_type = mlx5_ptype_table[pt_idx1] | 330 !!(pt_idx1 & (1 << 6)) * rxq->tunnel; 331 pkts[2]->packet_type = mlx5_ptype_table[pt_idx2] | 332 !!(pt_idx2 & (1 << 6)) * rxq->tunnel; 333 pkts[3]->packet_type = mlx5_ptype_table[pt_idx3] | 334 !!(pt_idx3 & (1 << 6)) * rxq->tunnel; 335 /* Fill flags for checksum and VLAN. */ 336 pinfo = vandq_u32(ptype_info, ptype_ol_mask); 337 pinfo = vreinterpretq_u32_u8( 338 vqtbl1q_u8(cv_flag_sel, vreinterpretq_u8_u32(pinfo))); 339 /* Locate checksum flags at byte[2:1] and merge with VLAN flags. */ 340 cv_flags = vshlq_n_u32(pinfo, 9); 341 cv_flags = vorrq_u32(pinfo, cv_flags); 342 /* Move back flags to start from byte[0]. */ 343 cv_flags = vshrq_n_u32(cv_flags, 8); 344 /* Mask out garbage bits. */ 345 cv_flags = vandq_u32(cv_flags, cv_mask); 346 /* Merge to ol_flags. */ 347 ol_flags = vorrq_u32(ol_flags, cv_flags); 348 /* Merge mbuf_init and ol_flags, and store. */ 349 rearm0 = vreinterpretq_u64_u32(vsetq_lane_u32 350 (vgetq_lane_u32(ol_flags, 3), 351 vreinterpretq_u32_u64(mbuf_init), 2)); 352 rearm1 = vreinterpretq_u64_u32(vsetq_lane_u32 353 (vgetq_lane_u32(ol_flags, 2), 354 vreinterpretq_u32_u64(mbuf_init), 2)); 355 rearm2 = vreinterpretq_u64_u32(vsetq_lane_u32 356 (vgetq_lane_u32(ol_flags, 1), 357 vreinterpretq_u32_u64(mbuf_init), 2)); 358 rearm3 = vreinterpretq_u64_u32(vsetq_lane_u32 359 (vgetq_lane_u32(ol_flags, 0), 360 vreinterpretq_u32_u64(mbuf_init), 2)); 361 362 vst1q_u64((void *)&pkts[0]->rearm_data, rearm0); 363 vst1q_u64((void *)&pkts[1]->rearm_data, rearm1); 364 vst1q_u64((void *)&pkts[2]->rearm_data, rearm2); 365 vst1q_u64((void *)&pkts[3]->rearm_data, rearm3); 366 } 367 368 /** 369 * Process a non-compressed completion and fill in mbufs in RX SW ring 370 * with data extracted from the title completion descriptor. 371 * 372 * @param rxq 373 * Pointer to RX queue structure. 374 * @param cq 375 * Pointer to completion array having a non-compressed completion at first. 376 * @param elts 377 * Pointer to SW ring to be filled. The first mbuf has to be pre-built from 378 * the title completion descriptor to be copied to the rest of mbufs. 379 * @param[out] pkts 380 * Array to store received packets. 381 * @param pkts_n 382 * Maximum number of packets in array. 383 * @param[out] err 384 * Pointer to a flag. Set non-zero value if pkts array has at least one error 385 * packet to handle. 386 * @param[out] comp 387 * Pointer to a index. Set it to the first compressed completion if any. 388 * 389 * @return 390 * Number of CQEs successfully processed. 391 */ 392 static inline uint16_t 393 rxq_cq_process_v(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cq, 394 struct rte_mbuf **elts, struct rte_mbuf **pkts, 395 uint16_t pkts_n, uint64_t *err, uint64_t *comp) 396 { 397 const uint16_t q_n = 1 << rxq->cqe_n; 398 const uint16_t q_mask = q_n - 1; 399 unsigned int pos; 400 uint64_t n = 0; 401 uint64_t comp_idx = MLX5_VPMD_DESCS_PER_LOOP; 402 uint16_t nocmp_n = 0; 403 const uint16x4_t ownership = vdup_n_u16(!(rxq->cq_ci & (q_mask + 1))); 404 const uint16x4_t owner_check = vcreate_u16(0x0001000100010001); 405 const uint16x4_t opcode_check = vcreate_u16(0x00f000f000f000f0); 406 const uint16x4_t format_check = vcreate_u16(0x000c000c000c000c); 407 const uint16x4_t resp_err_check = vcreate_u16(0x00e000e000e000e0); 408 #ifdef MLX5_PMD_SOFT_COUNTERS 409 uint32_t rcvd_byte = 0; 410 #endif 411 /* Mask to generate 16B length vector. */ 412 const uint8x8_t len_shuf_m = { 413 52, 53, /* 4th CQE */ 414 36, 37, /* 3rd CQE */ 415 20, 21, /* 2nd CQE */ 416 4, 5 /* 1st CQE */ 417 }; 418 /* Mask to extract 16B data from a 64B CQE. */ 419 const uint8x16_t cqe_shuf_m = { 420 28, 29, /* hdr_type_etc */ 421 0, /* pkt_info */ 422 -1, /* null */ 423 47, 46, /* byte_cnt, bswap16 */ 424 31, 30, /* vlan_info, bswap16 */ 425 15, 14, 13, 12, /* rx_hash_res, bswap32 */ 426 57, 58, 59, /* flow_tag */ 427 63 /* op_own */ 428 }; 429 /* Mask to generate 16B data for mbuf. */ 430 const uint8x16_t mb_shuf_m = { 431 4, 5, -1, -1, /* pkt_len */ 432 4, 5, /* data_len */ 433 6, 7, /* vlan_tci */ 434 8, 9, 10, 11, /* hash.rss */ 435 12, 13, 14, -1 /* hash.fdir.hi */ 436 }; 437 /* Mask to generate 16B owner vector. */ 438 const uint8x8_t owner_shuf_m = { 439 63, -1, /* 4th CQE */ 440 47, -1, /* 3rd CQE */ 441 31, -1, /* 2nd CQE */ 442 15, -1 /* 1st CQE */ 443 }; 444 /* Mask to generate a vector having packet_type/ol_flags. */ 445 const uint8x16_t ptype_shuf_m = { 446 48, 49, 50, -1, /* 4th CQE */ 447 32, 33, 34, -1, /* 3rd CQE */ 448 16, 17, 18, -1, /* 2nd CQE */ 449 0, 1, 2, -1 /* 1st CQE */ 450 }; 451 /* Mask to generate a vector having flow tags. */ 452 const uint8x16_t ftag_shuf_m = { 453 60, 61, 62, -1, /* 4th CQE */ 454 44, 45, 46, -1, /* 3rd CQE */ 455 28, 29, 30, -1, /* 2nd CQE */ 456 12, 13, 14, -1 /* 1st CQE */ 457 }; 458 const uint16x8_t crc_adj = { 459 0, 0, rxq->crc_present * RTE_ETHER_CRC_LEN, 0, 0, 0, 0, 0 460 }; 461 const uint32x4_t flow_mark_adj = { 0, 0, 0, rxq->mark * (-1) }; 462 463 /* 464 * Note that vectors have reverse order - {v3, v2, v1, v0}, because 465 * there's no instruction to count trailing zeros. __builtin_clzl() is 466 * used instead. 467 * 468 * A. copy 4 mbuf pointers from elts ring to returing pkts. 469 * B. load 64B CQE and extract necessary fields 470 * Final 16bytes cqes[] extracted from original 64bytes CQE has the 471 * following structure: 472 * struct { 473 * uint16_t hdr_type_etc; 474 * uint8_t pkt_info; 475 * uint8_t rsvd; 476 * uint16_t byte_cnt; 477 * uint16_t vlan_info; 478 * uint32_t rx_has_res; 479 * uint8_t flow_tag[3]; 480 * uint8_t op_own; 481 * } c; 482 * C. fill in mbuf. 483 * D. get valid CQEs. 484 * E. find compressed CQE. 485 */ 486 for (pos = 0; 487 pos < pkts_n; 488 pos += MLX5_VPMD_DESCS_PER_LOOP) { 489 uint16x4_t op_own; 490 uint16x4_t opcode, owner_mask, invalid_mask; 491 uint16x4_t comp_mask; 492 uint16x4_t mask; 493 uint16x4_t byte_cnt; 494 uint32x4_t ptype_info, flow_tag; 495 register uint64x2_t c0, c1, c2, c3; 496 uint8_t *p0, *p1, *p2, *p3; 497 uint8_t *e0 = (void *)&elts[pos]->pkt_len; 498 uint8_t *e1 = (void *)&elts[pos + 1]->pkt_len; 499 uint8_t *e2 = (void *)&elts[pos + 2]->pkt_len; 500 uint8_t *e3 = (void *)&elts[pos + 3]->pkt_len; 501 void *elts_p = (void *)&elts[pos]; 502 void *pkts_p = (void *)&pkts[pos]; 503 504 /* A.0 do not cross the end of CQ. */ 505 mask = vcreate_u16(pkts_n - pos < MLX5_VPMD_DESCS_PER_LOOP ? 506 -1UL >> ((pkts_n - pos) * 507 sizeof(uint16_t) * 8) : 0); 508 p0 = (void *)&cq[pos].pkt_info; 509 p1 = p0 + (pkts_n - pos > 1) * sizeof(struct mlx5_cqe); 510 p2 = p1 + (pkts_n - pos > 2) * sizeof(struct mlx5_cqe); 511 p3 = p2 + (pkts_n - pos > 3) * sizeof(struct mlx5_cqe); 512 /* B.0 (CQE 3) load a block having op_own. */ 513 c3 = vld1q_u64((uint64_t *)(p3 + 48)); 514 /* B.0 (CQE 2) load a block having op_own. */ 515 c2 = vld1q_u64((uint64_t *)(p2 + 48)); 516 /* B.0 (CQE 1) load a block having op_own. */ 517 c1 = vld1q_u64((uint64_t *)(p1 + 48)); 518 /* B.0 (CQE 0) load a block having op_own. */ 519 c0 = vld1q_u64((uint64_t *)(p0 + 48)); 520 /* Synchronize for loading the rest of blocks. */ 521 rte_io_rmb(); 522 /* Prefetch next 4 CQEs. */ 523 if (pkts_n - pos >= 2 * MLX5_VPMD_DESCS_PER_LOOP) { 524 unsigned int next = pos + MLX5_VPMD_DESCS_PER_LOOP; 525 rte_prefetch_non_temporal(&cq[next]); 526 rte_prefetch_non_temporal(&cq[next + 1]); 527 rte_prefetch_non_temporal(&cq[next + 2]); 528 rte_prefetch_non_temporal(&cq[next + 3]); 529 } 530 __asm__ volatile ( 531 /* B.1 (CQE 3) load the rest of blocks. */ 532 "ld1 {v16.16b - v18.16b}, [%[p3]] \n\t" 533 /* B.2 (CQE 3) move the block having op_own. */ 534 "mov v19.16b, %[c3].16b \n\t" 535 /* B.3 (CQE 3) extract 16B fields. */ 536 "tbl v23.16b, {v16.16b - v19.16b}, %[cqe_shuf_m].16b \n\t" 537 /* B.1 (CQE 2) load the rest of blocks. */ 538 "ld1 {v16.16b - v18.16b}, [%[p2]] \n\t" 539 /* B.4 (CQE 3) adjust CRC length. */ 540 "sub v23.8h, v23.8h, %[crc_adj].8h \n\t" 541 /* C.1 (CQE 3) generate final structure for mbuf. */ 542 "tbl v15.16b, {v23.16b}, %[mb_shuf_m].16b \n\t" 543 /* B.2 (CQE 2) move the block having op_own. */ 544 "mov v19.16b, %[c2].16b \n\t" 545 /* B.3 (CQE 2) extract 16B fields. */ 546 "tbl v22.16b, {v16.16b - v19.16b}, %[cqe_shuf_m].16b \n\t" 547 /* B.1 (CQE 1) load the rest of blocks. */ 548 "ld1 {v16.16b - v18.16b}, [%[p1]] \n\t" 549 /* B.4 (CQE 2) adjust CRC length. */ 550 "sub v22.8h, v22.8h, %[crc_adj].8h \n\t" 551 /* C.1 (CQE 2) generate final structure for mbuf. */ 552 "tbl v14.16b, {v22.16b}, %[mb_shuf_m].16b \n\t" 553 /* B.2 (CQE 1) move the block having op_own. */ 554 "mov v19.16b, %[c1].16b \n\t" 555 /* B.3 (CQE 1) extract 16B fields. */ 556 "tbl v21.16b, {v16.16b - v19.16b}, %[cqe_shuf_m].16b \n\t" 557 /* B.1 (CQE 0) load the rest of blocks. */ 558 "ld1 {v16.16b - v18.16b}, [%[p0]] \n\t" 559 /* B.4 (CQE 1) adjust CRC length. */ 560 "sub v21.8h, v21.8h, %[crc_adj].8h \n\t" 561 /* C.1 (CQE 1) generate final structure for mbuf. */ 562 "tbl v13.16b, {v21.16b}, %[mb_shuf_m].16b \n\t" 563 /* B.2 (CQE 0) move the block having op_own. */ 564 "mov v19.16b, %[c0].16b \n\t" 565 /* A.1 load mbuf pointers. */ 566 "ld1 {v24.2d - v25.2d}, [%[elts_p]] \n\t" 567 /* B.3 (CQE 0) extract 16B fields. */ 568 "tbl v20.16b, {v16.16b - v19.16b}, %[cqe_shuf_m].16b \n\t" 569 /* B.4 (CQE 0) adjust CRC length. */ 570 "sub v20.8h, v20.8h, %[crc_adj].8h \n\t" 571 /* D.1 extract op_own byte. */ 572 "tbl %[op_own].8b, {v20.16b - v23.16b}, %[owner_shuf_m].8b \n\t" 573 /* C.2 (CQE 3) adjust flow mark. */ 574 "add v15.4s, v15.4s, %[flow_mark_adj].4s \n\t" 575 /* C.3 (CQE 3) fill in mbuf - rx_descriptor_fields1. */ 576 "st1 {v15.2d}, [%[e3]] \n\t" 577 /* C.2 (CQE 2) adjust flow mark. */ 578 "add v14.4s, v14.4s, %[flow_mark_adj].4s \n\t" 579 /* C.3 (CQE 2) fill in mbuf - rx_descriptor_fields1. */ 580 "st1 {v14.2d}, [%[e2]] \n\t" 581 /* C.1 (CQE 0) generate final structure for mbuf. */ 582 "tbl v12.16b, {v20.16b}, %[mb_shuf_m].16b \n\t" 583 /* C.2 (CQE 1) adjust flow mark. */ 584 "add v13.4s, v13.4s, %[flow_mark_adj].4s \n\t" 585 /* C.3 (CQE 1) fill in mbuf - rx_descriptor_fields1. */ 586 "st1 {v13.2d}, [%[e1]] \n\t" 587 #ifdef MLX5_PMD_SOFT_COUNTERS 588 /* Extract byte_cnt. */ 589 "tbl %[byte_cnt].8b, {v20.16b - v23.16b}, %[len_shuf_m].8b \n\t" 590 #endif 591 /* Extract ptype_info. */ 592 "tbl %[ptype_info].16b, {v20.16b - v23.16b}, %[ptype_shuf_m].16b \n\t" 593 /* Extract flow_tag. */ 594 "tbl %[flow_tag].16b, {v20.16b - v23.16b}, %[ftag_shuf_m].16b \n\t" 595 /* A.2 copy mbuf pointers. */ 596 "st1 {v24.2d - v25.2d}, [%[pkts_p]] \n\t" 597 /* C.2 (CQE 0) adjust flow mark. */ 598 "add v12.4s, v12.4s, %[flow_mark_adj].4s \n\t" 599 /* C.3 (CQE 1) fill in mbuf - rx_descriptor_fields1. */ 600 "st1 {v12.2d}, [%[e0]] \n\t" 601 :[op_own]"=&w"(op_own), 602 [byte_cnt]"=&w"(byte_cnt), 603 [ptype_info]"=&w"(ptype_info), 604 [flow_tag]"=&w"(flow_tag) 605 :[p3]"r"(p3), [p2]"r"(p2), [p1]"r"(p1), [p0]"r"(p0), 606 [e3]"r"(e3), [e2]"r"(e2), [e1]"r"(e1), [e0]"r"(e0), 607 [c3]"w"(c3), [c2]"w"(c2), [c1]"w"(c1), [c0]"w"(c0), 608 [elts_p]"r"(elts_p), 609 [pkts_p]"r"(pkts_p), 610 [cqe_shuf_m]"w"(cqe_shuf_m), 611 [mb_shuf_m]"w"(mb_shuf_m), 612 [owner_shuf_m]"w"(owner_shuf_m), 613 [len_shuf_m]"w"(len_shuf_m), 614 [ptype_shuf_m]"w"(ptype_shuf_m), 615 [ftag_shuf_m]"w"(ftag_shuf_m), 616 [crc_adj]"w"(crc_adj), 617 [flow_mark_adj]"w"(flow_mark_adj) 618 :"memory", 619 "v12", "v13", "v14", "v15", 620 "v16", "v17", "v18", "v19", 621 "v20", "v21", "v22", "v23", 622 "v24", "v25"); 623 /* D.2 flip owner bit to mark CQEs from last round. */ 624 owner_mask = vand_u16(op_own, owner_check); 625 owner_mask = vceq_u16(owner_mask, ownership); 626 /* D.3 get mask for invalidated CQEs. */ 627 opcode = vand_u16(op_own, opcode_check); 628 invalid_mask = vceq_u16(opcode_check, opcode); 629 /* E.1 find compressed CQE format. */ 630 comp_mask = vand_u16(op_own, format_check); 631 comp_mask = vceq_u16(comp_mask, format_check); 632 /* D.4 mask out beyond boundary. */ 633 invalid_mask = vorr_u16(invalid_mask, mask); 634 /* D.5 merge invalid_mask with invalid owner. */ 635 invalid_mask = vorr_u16(invalid_mask, owner_mask); 636 /* E.2 mask out invalid entries. */ 637 comp_mask = vbic_u16(comp_mask, invalid_mask); 638 /* E.3 get the first compressed CQE. */ 639 comp_idx = __builtin_clzl(vget_lane_u64(vreinterpret_u64_u16( 640 comp_mask), 0)) / 641 (sizeof(uint16_t) * 8); 642 /* D.6 mask out entries after the compressed CQE. */ 643 mask = vcreate_u16(comp_idx < MLX5_VPMD_DESCS_PER_LOOP ? 644 -1UL >> (comp_idx * sizeof(uint16_t) * 8) : 645 0); 646 invalid_mask = vorr_u16(invalid_mask, mask); 647 /* D.7 count non-compressed valid CQEs. */ 648 n = __builtin_clzl(vget_lane_u64(vreinterpret_u64_u16( 649 invalid_mask), 0)) / (sizeof(uint16_t) * 8); 650 nocmp_n += n; 651 /* D.2 get the final invalid mask. */ 652 mask = vcreate_u16(n < MLX5_VPMD_DESCS_PER_LOOP ? 653 -1UL >> (n * sizeof(uint16_t) * 8) : 0); 654 invalid_mask = vorr_u16(invalid_mask, mask); 655 /* D.3 check error in opcode. */ 656 opcode = vceq_u16(resp_err_check, opcode); 657 opcode = vbic_u16(opcode, invalid_mask); 658 /* D.4 mark if any error is set */ 659 *err |= vget_lane_u64(vreinterpret_u64_u16(opcode), 0); 660 /* C.4 fill in mbuf - rearm_data and packet_type. */ 661 rxq_cq_to_ptype_oflags_v(rxq, ptype_info, flow_tag, 662 opcode, &elts[pos]); 663 if (rxq->hw_timestamp) { 664 int offset = rxq->timestamp_offset; 665 if (rxq->rt_timestamp) { 666 struct mlx5_dev_ctx_shared *sh = rxq->sh; 667 uint64_t ts; 668 669 ts = rte_be_to_cpu_64 670 (container_of(p0, struct mlx5_cqe, 671 pkt_info)->timestamp); 672 mlx5_timestamp_set(elts[pos], offset, 673 mlx5_txpp_convert_rx_ts(sh, ts)); 674 ts = rte_be_to_cpu_64 675 (container_of(p1, struct mlx5_cqe, 676 pkt_info)->timestamp); 677 mlx5_timestamp_set(elts[pos + 1], offset, 678 mlx5_txpp_convert_rx_ts(sh, ts)); 679 ts = rte_be_to_cpu_64 680 (container_of(p2, struct mlx5_cqe, 681 pkt_info)->timestamp); 682 mlx5_timestamp_set(elts[pos + 2], offset, 683 mlx5_txpp_convert_rx_ts(sh, ts)); 684 ts = rte_be_to_cpu_64 685 (container_of(p3, struct mlx5_cqe, 686 pkt_info)->timestamp); 687 mlx5_timestamp_set(elts[pos + 3], offset, 688 mlx5_txpp_convert_rx_ts(sh, ts)); 689 } else { 690 mlx5_timestamp_set(elts[pos], offset, 691 rte_be_to_cpu_64(container_of(p0, 692 struct mlx5_cqe, pkt_info)->timestamp)); 693 mlx5_timestamp_set(elts[pos + 1], offset, 694 rte_be_to_cpu_64(container_of(p1, 695 struct mlx5_cqe, pkt_info)->timestamp)); 696 mlx5_timestamp_set(elts[pos + 2], offset, 697 rte_be_to_cpu_64(container_of(p2, 698 struct mlx5_cqe, pkt_info)->timestamp)); 699 mlx5_timestamp_set(elts[pos + 3], offset, 700 rte_be_to_cpu_64(container_of(p3, 701 struct mlx5_cqe, pkt_info)->timestamp)); 702 } 703 } 704 if (rxq->dynf_meta) { 705 /* This code is subject for futher optimization. */ 706 int32_t offs = rxq->flow_meta_offset; 707 708 *RTE_MBUF_DYNFIELD(pkts[pos], offs, uint32_t *) = 709 container_of(p0, struct mlx5_cqe, 710 pkt_info)->flow_table_metadata; 711 *RTE_MBUF_DYNFIELD(pkts[pos + 1], offs, uint32_t *) = 712 container_of(p1, struct mlx5_cqe, 713 pkt_info)->flow_table_metadata; 714 *RTE_MBUF_DYNFIELD(pkts[pos + 2], offs, uint32_t *) = 715 container_of(p2, struct mlx5_cqe, 716 pkt_info)->flow_table_metadata; 717 *RTE_MBUF_DYNFIELD(pkts[pos + 3], offs, uint32_t *) = 718 container_of(p3, struct mlx5_cqe, 719 pkt_info)->flow_table_metadata; 720 if (*RTE_MBUF_DYNFIELD(pkts[pos], offs, uint32_t *)) 721 elts[pos]->ol_flags |= rxq->flow_meta_mask; 722 if (*RTE_MBUF_DYNFIELD(pkts[pos + 1], offs, uint32_t *)) 723 elts[pos + 1]->ol_flags |= rxq->flow_meta_mask; 724 if (*RTE_MBUF_DYNFIELD(pkts[pos + 2], offs, uint32_t *)) 725 elts[pos + 2]->ol_flags |= rxq->flow_meta_mask; 726 if (*RTE_MBUF_DYNFIELD(pkts[pos + 3], offs, uint32_t *)) 727 elts[pos + 3]->ol_flags |= rxq->flow_meta_mask; 728 } 729 #ifdef MLX5_PMD_SOFT_COUNTERS 730 /* Add up received bytes count. */ 731 byte_cnt = vbic_u16(byte_cnt, invalid_mask); 732 rcvd_byte += vget_lane_u64(vpaddl_u32(vpaddl_u16(byte_cnt)), 0); 733 #endif 734 /* 735 * Break the loop unless more valid CQE is expected, or if 736 * there's a compressed CQE. 737 */ 738 if (n != MLX5_VPMD_DESCS_PER_LOOP) 739 break; 740 } 741 #ifdef MLX5_PMD_SOFT_COUNTERS 742 rxq->stats.ipackets += nocmp_n; 743 rxq->stats.ibytes += rcvd_byte; 744 #endif 745 if (comp_idx == n) 746 *comp = comp_idx; 747 return nocmp_n; 748 } 749 750 #endif /* RTE_PMD_MLX5_RXTX_VEC_NEON_H_ */ 751