1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2017 6WIND S.A. 3 * Copyright 2017 Mellanox Technologies, Ltd 4 */ 5 6 #ifndef RTE_PMD_MLX5_RXTX_VEC_NEON_H_ 7 #define RTE_PMD_MLX5_RXTX_VEC_NEON_H_ 8 9 #include <stdint.h> 10 #include <string.h> 11 #include <stdlib.h> 12 #include <arm_neon.h> 13 14 #include <rte_mbuf.h> 15 #include <rte_mempool.h> 16 #include <rte_prefetch.h> 17 18 #include <mlx5_prm.h> 19 20 #include "mlx5_defs.h" 21 #include "mlx5.h" 22 #include "mlx5_utils.h" 23 #include "mlx5_rxtx.h" 24 #include "mlx5_rxtx_vec.h" 25 #include "mlx5_autoconf.h" 26 27 #pragma GCC diagnostic ignored "-Wcast-qual" 28 29 /** 30 * Store free buffers to RX SW ring. 31 * 32 * @param rxq 33 * Pointer to RX queue structure. 34 * @param pkts 35 * Pointer to array of packets to be stored. 36 * @param pkts_n 37 * Number of packets to be stored. 38 */ 39 static inline void 40 rxq_copy_mbuf_v(struct mlx5_rxq_data *rxq, struct rte_mbuf **pkts, uint16_t n) 41 { 42 const uint16_t q_mask = (1 << rxq->elts_n) - 1; 43 struct rte_mbuf **elts = &(*rxq->elts)[rxq->rq_pi & q_mask]; 44 unsigned int pos; 45 uint16_t p = n & -2; 46 47 for (pos = 0; pos < p; pos += 2) { 48 uint64x2_t mbp; 49 50 mbp = vld1q_u64((void *)&elts[pos]); 51 vst1q_u64((void *)&pkts[pos], mbp); 52 } 53 if (n & 1) 54 pkts[pos] = elts[pos]; 55 } 56 57 /** 58 * Decompress a compressed completion and fill in mbufs in RX SW ring with data 59 * extracted from the title completion descriptor. 60 * 61 * @param rxq 62 * Pointer to RX queue structure. 63 * @param cq 64 * Pointer to completion array having a compressed completion at first. 65 * @param elts 66 * Pointer to SW ring to be filled. The first mbuf has to be pre-built from 67 * the title completion descriptor to be copied to the rest of mbufs. 68 * 69 * @return 70 * Number of mini-CQEs successfully decompressed. 71 */ 72 static inline uint16_t 73 rxq_cq_decompress_v(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cq, 74 struct rte_mbuf **elts) 75 { 76 volatile struct mlx5_mini_cqe8 *mcq = (void *)&(cq + 1)->pkt_info; 77 struct rte_mbuf *t_pkt = elts[0]; /* Title packet is pre-built. */ 78 unsigned int pos; 79 unsigned int i; 80 unsigned int inv = 0; 81 /* Mask to shuffle from extracted mini CQE to mbuf. */ 82 const uint8x16_t mcqe_shuf_m1 = { 83 -1, -1, -1, -1, /* skip packet_type */ 84 7, 6, -1, -1, /* pkt_len, bswap16 */ 85 7, 6, /* data_len, bswap16 */ 86 -1, -1, /* skip vlan_tci */ 87 3, 2, 1, 0 /* hash.rss, bswap32 */ 88 }; 89 const uint8x16_t mcqe_shuf_m2 = { 90 -1, -1, -1, -1, /* skip packet_type */ 91 15, 14, -1, -1, /* pkt_len, bswap16 */ 92 15, 14, /* data_len, bswap16 */ 93 -1, -1, /* skip vlan_tci */ 94 11, 10, 9, 8 /* hash.rss, bswap32 */ 95 }; 96 /* Restore the compressed count. Must be 16 bits. */ 97 const uint16_t mcqe_n = t_pkt->data_len + 98 (rxq->crc_present * RTE_ETHER_CRC_LEN); 99 const uint64x2_t rearm = 100 vld1q_u64((void *)&t_pkt->rearm_data); 101 const uint32x4_t rxdf_mask = { 102 0xffffffff, /* packet_type */ 103 0, /* skip pkt_len */ 104 0xffff0000, /* vlan_tci, skip data_len */ 105 0, /* skip hash.rss */ 106 }; 107 const uint8x16_t rxdf = 108 vandq_u8(vld1q_u8((void *)&t_pkt->rx_descriptor_fields1), 109 vreinterpretq_u8_u32(rxdf_mask)); 110 const uint16x8_t crc_adj = { 111 0, 0, 112 rxq->crc_present * RTE_ETHER_CRC_LEN, 0, 113 rxq->crc_present * RTE_ETHER_CRC_LEN, 0, 114 0, 0 115 }; 116 const uint32_t flow_tag = t_pkt->hash.fdir.hi; 117 #ifdef MLX5_PMD_SOFT_COUNTERS 118 uint32_t rcvd_byte = 0; 119 #endif 120 /* Mask to shuffle byte_cnt to add up stats. Do bswap16 for all. */ 121 const uint8x8_t len_shuf_m = { 122 7, 6, /* 1st mCQE */ 123 15, 14, /* 2nd mCQE */ 124 23, 22, /* 3rd mCQE */ 125 31, 30 /* 4th mCQE */ 126 }; 127 128 /* 129 * A. load mCQEs into a 128bit register. 130 * B. store rearm data to mbuf. 131 * C. combine data from mCQEs with rx_descriptor_fields1. 132 * D. store rx_descriptor_fields1. 133 * E. store flow tag (rte_flow mark). 134 */ 135 for (pos = 0; pos < mcqe_n; ) { 136 uint8_t *p = (void *)&mcq[pos % 8]; 137 uint8_t *e0 = (void *)&elts[pos]->rearm_data; 138 uint8_t *e1 = (void *)&elts[pos + 1]->rearm_data; 139 uint8_t *e2 = (void *)&elts[pos + 2]->rearm_data; 140 uint8_t *e3 = (void *)&elts[pos + 3]->rearm_data; 141 uint16x4_t byte_cnt; 142 #ifdef MLX5_PMD_SOFT_COUNTERS 143 uint16x4_t invalid_mask = 144 vcreate_u16(mcqe_n - pos < MLX5_VPMD_DESCS_PER_LOOP ? 145 -1UL << ((mcqe_n - pos) * 146 sizeof(uint16_t) * 8) : 0); 147 #endif 148 149 if (!(pos & 0x7) && pos + 8 < mcqe_n) 150 rte_prefetch0((void *)(cq + pos + 8)); 151 __asm__ volatile ( 152 /* A.1 load mCQEs into a 128bit register. */ 153 "ld1 {v16.16b - v17.16b}, [%[mcq]] \n\t" 154 /* B.1 store rearm data to mbuf. */ 155 "st1 {%[rearm].2d}, [%[e0]] \n\t" 156 "add %[e0], %[e0], #16 \n\t" 157 "st1 {%[rearm].2d}, [%[e1]] \n\t" 158 "add %[e1], %[e1], #16 \n\t" 159 /* C.1 combine data from mCQEs with rx_descriptor_fields1. */ 160 "tbl v18.16b, {v16.16b}, %[mcqe_shuf_m1].16b \n\t" 161 "tbl v19.16b, {v16.16b}, %[mcqe_shuf_m2].16b \n\t" 162 "sub v18.8h, v18.8h, %[crc_adj].8h \n\t" 163 "sub v19.8h, v19.8h, %[crc_adj].8h \n\t" 164 "orr v18.16b, v18.16b, %[rxdf].16b \n\t" 165 "orr v19.16b, v19.16b, %[rxdf].16b \n\t" 166 /* D.1 store rx_descriptor_fields1. */ 167 "st1 {v18.2d}, [%[e0]] \n\t" 168 "st1 {v19.2d}, [%[e1]] \n\t" 169 /* B.1 store rearm data to mbuf. */ 170 "st1 {%[rearm].2d}, [%[e2]] \n\t" 171 "add %[e2], %[e2], #16 \n\t" 172 "st1 {%[rearm].2d}, [%[e3]] \n\t" 173 "add %[e3], %[e3], #16 \n\t" 174 /* C.1 combine data from mCQEs with rx_descriptor_fields1. */ 175 "tbl v18.16b, {v17.16b}, %[mcqe_shuf_m1].16b \n\t" 176 "tbl v19.16b, {v17.16b}, %[mcqe_shuf_m2].16b \n\t" 177 "sub v18.8h, v18.8h, %[crc_adj].8h \n\t" 178 "sub v19.8h, v19.8h, %[crc_adj].8h \n\t" 179 "orr v18.16b, v18.16b, %[rxdf].16b \n\t" 180 "orr v19.16b, v19.16b, %[rxdf].16b \n\t" 181 /* D.1 store rx_descriptor_fields1. */ 182 "st1 {v18.2d}, [%[e2]] \n\t" 183 "st1 {v19.2d}, [%[e3]] \n\t" 184 #ifdef MLX5_PMD_SOFT_COUNTERS 185 "tbl %[byte_cnt].8b, {v16.16b - v17.16b}, %[len_shuf_m].8b \n\t" 186 #endif 187 :[byte_cnt]"=&w"(byte_cnt) 188 :[mcq]"r"(p), 189 [rxdf]"w"(rxdf), 190 [rearm]"w"(rearm), 191 [e3]"r"(e3), [e2]"r"(e2), [e1]"r"(e1), [e0]"r"(e0), 192 [mcqe_shuf_m1]"w"(mcqe_shuf_m1), 193 [mcqe_shuf_m2]"w"(mcqe_shuf_m2), 194 [crc_adj]"w"(crc_adj), 195 [len_shuf_m]"w"(len_shuf_m) 196 :"memory", "v16", "v17", "v18", "v19"); 197 #ifdef MLX5_PMD_SOFT_COUNTERS 198 byte_cnt = vbic_u16(byte_cnt, invalid_mask); 199 rcvd_byte += vget_lane_u64(vpaddl_u32(vpaddl_u16(byte_cnt)), 0); 200 #endif 201 if (rxq->mark) { 202 /* E.1 store flow tag (rte_flow mark). */ 203 elts[pos]->hash.fdir.hi = flow_tag; 204 elts[pos + 1]->hash.fdir.hi = flow_tag; 205 elts[pos + 2]->hash.fdir.hi = flow_tag; 206 elts[pos + 3]->hash.fdir.hi = flow_tag; 207 } 208 pos += MLX5_VPMD_DESCS_PER_LOOP; 209 /* Move to next CQE and invalidate consumed CQEs. */ 210 if (!(pos & 0x7) && pos < mcqe_n) { 211 mcq = (void *)&(cq + pos)->pkt_info; 212 for (i = 0; i < 8; ++i) 213 cq[inv++].op_own = MLX5_CQE_INVALIDATE; 214 } 215 } 216 /* Invalidate the rest of CQEs. */ 217 for (; inv < mcqe_n; ++inv) 218 cq[inv].op_own = MLX5_CQE_INVALIDATE; 219 #ifdef MLX5_PMD_SOFT_COUNTERS 220 rxq->stats.ipackets += mcqe_n; 221 rxq->stats.ibytes += rcvd_byte; 222 #endif 223 rxq->cq_ci += mcqe_n; 224 return mcqe_n; 225 } 226 227 /** 228 * Calculate packet type and offload flag for mbuf and store it. 229 * 230 * @param rxq 231 * Pointer to RX queue structure. 232 * @param ptype_info 233 * Array of four 4bytes packet type info extracted from the original 234 * completion descriptor. 235 * @param flow_tag 236 * Array of four 4bytes flow ID extracted from the original completion 237 * descriptor. 238 * @param op_err 239 * Opcode vector having responder error status. Each field is 4B. 240 * @param pkts 241 * Pointer to array of packets to be filled. 242 */ 243 static inline void 244 rxq_cq_to_ptype_oflags_v(struct mlx5_rxq_data *rxq, 245 uint32x4_t ptype_info, uint32x4_t flow_tag, 246 uint16x4_t op_err, struct rte_mbuf **pkts) 247 { 248 uint16x4_t ptype; 249 uint32x4_t pinfo, cv_flags; 250 uint32x4_t ol_flags = 251 vdupq_n_u32(rxq->rss_hash * PKT_RX_RSS_HASH | 252 rxq->hw_timestamp * PKT_RX_TIMESTAMP); 253 const uint32x4_t ptype_ol_mask = { 0x106, 0x106, 0x106, 0x106 }; 254 const uint8x16_t cv_flag_sel = { 255 0, 256 (uint8_t)(PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED), 257 (uint8_t)(PKT_RX_IP_CKSUM_GOOD >> 1), 258 0, 259 (uint8_t)(PKT_RX_L4_CKSUM_GOOD >> 1), 260 0, 261 (uint8_t)((PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD) >> 1), 262 0, 0, 0, 0, 0, 0, 0, 0, 0 263 }; 264 const uint32x4_t cv_mask = 265 vdupq_n_u32(PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD | 266 PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED); 267 const uint64x2_t mbuf_init = vld1q_u64 268 ((const uint64_t *)&rxq->mbuf_initializer); 269 uint64x2_t rearm0, rearm1, rearm2, rearm3; 270 uint8_t pt_idx0, pt_idx1, pt_idx2, pt_idx3; 271 272 if (rxq->mark) { 273 const uint32x4_t ft_def = vdupq_n_u32(MLX5_FLOW_MARK_DEFAULT); 274 const uint32x4_t fdir_flags = vdupq_n_u32(PKT_RX_FDIR); 275 uint32x4_t fdir_id_flags = vdupq_n_u32(PKT_RX_FDIR_ID); 276 uint32x4_t invalid_mask; 277 278 /* Check if flow tag is non-zero then set PKT_RX_FDIR. */ 279 invalid_mask = vceqzq_u32(flow_tag); 280 ol_flags = vorrq_u32(ol_flags, 281 vbicq_u32(fdir_flags, invalid_mask)); 282 /* Mask out invalid entries. */ 283 fdir_id_flags = vbicq_u32(fdir_id_flags, invalid_mask); 284 /* Check if flow tag MLX5_FLOW_MARK_DEFAULT. */ 285 ol_flags = vorrq_u32(ol_flags, 286 vbicq_u32(fdir_id_flags, 287 vceqq_u32(flow_tag, ft_def))); 288 } 289 /* 290 * ptype_info has the following: 291 * bit[1] = l3_ok 292 * bit[2] = l4_ok 293 * bit[8] = cv 294 * bit[11:10] = l3_hdr_type 295 * bit[14:12] = l4_hdr_type 296 * bit[15] = ip_frag 297 * bit[16] = tunneled 298 * bit[17] = outer_l3_type 299 */ 300 ptype = vshrn_n_u32(ptype_info, 10); 301 /* Errored packets will have RTE_PTYPE_ALL_MASK. */ 302 ptype = vorr_u16(ptype, op_err); 303 pt_idx0 = vget_lane_u8(vreinterpret_u8_u16(ptype), 6); 304 pt_idx1 = vget_lane_u8(vreinterpret_u8_u16(ptype), 4); 305 pt_idx2 = vget_lane_u8(vreinterpret_u8_u16(ptype), 2); 306 pt_idx3 = vget_lane_u8(vreinterpret_u8_u16(ptype), 0); 307 pkts[0]->packet_type = mlx5_ptype_table[pt_idx0] | 308 !!(pt_idx0 & (1 << 6)) * rxq->tunnel; 309 pkts[1]->packet_type = mlx5_ptype_table[pt_idx1] | 310 !!(pt_idx1 & (1 << 6)) * rxq->tunnel; 311 pkts[2]->packet_type = mlx5_ptype_table[pt_idx2] | 312 !!(pt_idx2 & (1 << 6)) * rxq->tunnel; 313 pkts[3]->packet_type = mlx5_ptype_table[pt_idx3] | 314 !!(pt_idx3 & (1 << 6)) * rxq->tunnel; 315 /* Fill flags for checksum and VLAN. */ 316 pinfo = vandq_u32(ptype_info, ptype_ol_mask); 317 pinfo = vreinterpretq_u32_u8( 318 vqtbl1q_u8(cv_flag_sel, vreinterpretq_u8_u32(pinfo))); 319 /* Locate checksum flags at byte[2:1] and merge with VLAN flags. */ 320 cv_flags = vshlq_n_u32(pinfo, 9); 321 cv_flags = vorrq_u32(pinfo, cv_flags); 322 /* Move back flags to start from byte[0]. */ 323 cv_flags = vshrq_n_u32(cv_flags, 8); 324 /* Mask out garbage bits. */ 325 cv_flags = vandq_u32(cv_flags, cv_mask); 326 /* Merge to ol_flags. */ 327 ol_flags = vorrq_u32(ol_flags, cv_flags); 328 /* Merge mbuf_init and ol_flags, and store. */ 329 rearm0 = vreinterpretq_u64_u32(vsetq_lane_u32 330 (vgetq_lane_u32(ol_flags, 3), 331 vreinterpretq_u32_u64(mbuf_init), 2)); 332 rearm1 = vreinterpretq_u64_u32(vsetq_lane_u32 333 (vgetq_lane_u32(ol_flags, 2), 334 vreinterpretq_u32_u64(mbuf_init), 2)); 335 rearm2 = vreinterpretq_u64_u32(vsetq_lane_u32 336 (vgetq_lane_u32(ol_flags, 1), 337 vreinterpretq_u32_u64(mbuf_init), 2)); 338 rearm3 = vreinterpretq_u64_u32(vsetq_lane_u32 339 (vgetq_lane_u32(ol_flags, 0), 340 vreinterpretq_u32_u64(mbuf_init), 2)); 341 342 vst1q_u64((void *)&pkts[0]->rearm_data, rearm0); 343 vst1q_u64((void *)&pkts[1]->rearm_data, rearm1); 344 vst1q_u64((void *)&pkts[2]->rearm_data, rearm2); 345 vst1q_u64((void *)&pkts[3]->rearm_data, rearm3); 346 } 347 348 /** 349 * Receive burst of packets. An errored completion also consumes a mbuf, but the 350 * packet_type is set to be RTE_PTYPE_ALL_MASK. Marked mbufs should be freed 351 * before returning to application. 352 * 353 * @param rxq 354 * Pointer to RX queue structure. 355 * @param[out] pkts 356 * Array to store received packets. 357 * @param pkts_n 358 * Maximum number of packets in array. 359 * @param[out] err 360 * Pointer to a flag. Set non-zero value if pkts array has at least one error 361 * packet to handle. 362 * 363 * @return 364 * Number of packets received including errors (<= pkts_n). 365 */ 366 static inline uint16_t 367 rxq_burst_v(struct mlx5_rxq_data *rxq, struct rte_mbuf **pkts, uint16_t pkts_n, 368 uint64_t *err) 369 { 370 const uint16_t q_n = 1 << rxq->cqe_n; 371 const uint16_t q_mask = q_n - 1; 372 volatile struct mlx5_cqe *cq; 373 struct rte_mbuf **elts; 374 unsigned int pos; 375 uint64_t n; 376 uint16_t repl_n; 377 uint64_t comp_idx = MLX5_VPMD_DESCS_PER_LOOP; 378 uint16_t nocmp_n = 0; 379 uint16_t rcvd_pkt = 0; 380 unsigned int cq_idx = rxq->cq_ci & q_mask; 381 unsigned int elts_idx; 382 const uint16x4_t ownership = vdup_n_u16(!(rxq->cq_ci & (q_mask + 1))); 383 const uint16x4_t owner_check = vcreate_u16(0x0001000100010001); 384 const uint16x4_t opcode_check = vcreate_u16(0x00f000f000f000f0); 385 const uint16x4_t format_check = vcreate_u16(0x000c000c000c000c); 386 const uint16x4_t resp_err_check = vcreate_u16(0x00e000e000e000e0); 387 #ifdef MLX5_PMD_SOFT_COUNTERS 388 uint32_t rcvd_byte = 0; 389 #endif 390 /* Mask to generate 16B length vector. */ 391 const uint8x8_t len_shuf_m = { 392 52, 53, /* 4th CQE */ 393 36, 37, /* 3rd CQE */ 394 20, 21, /* 2nd CQE */ 395 4, 5 /* 1st CQE */ 396 }; 397 /* Mask to extract 16B data from a 64B CQE. */ 398 const uint8x16_t cqe_shuf_m = { 399 28, 29, /* hdr_type_etc */ 400 0, /* pkt_info */ 401 -1, /* null */ 402 47, 46, /* byte_cnt, bswap16 */ 403 31, 30, /* vlan_info, bswap16 */ 404 15, 14, 13, 12, /* rx_hash_res, bswap32 */ 405 57, 58, 59, /* flow_tag */ 406 63 /* op_own */ 407 }; 408 /* Mask to generate 16B data for mbuf. */ 409 const uint8x16_t mb_shuf_m = { 410 4, 5, -1, -1, /* pkt_len */ 411 4, 5, /* data_len */ 412 6, 7, /* vlan_tci */ 413 8, 9, 10, 11, /* hash.rss */ 414 12, 13, 14, -1 /* hash.fdir.hi */ 415 }; 416 /* Mask to generate 16B owner vector. */ 417 const uint8x8_t owner_shuf_m = { 418 63, -1, /* 4th CQE */ 419 47, -1, /* 3rd CQE */ 420 31, -1, /* 2nd CQE */ 421 15, -1 /* 1st CQE */ 422 }; 423 /* Mask to generate a vector having packet_type/ol_flags. */ 424 const uint8x16_t ptype_shuf_m = { 425 48, 49, 50, -1, /* 4th CQE */ 426 32, 33, 34, -1, /* 3rd CQE */ 427 16, 17, 18, -1, /* 2nd CQE */ 428 0, 1, 2, -1 /* 1st CQE */ 429 }; 430 /* Mask to generate a vector having flow tags. */ 431 const uint8x16_t ftag_shuf_m = { 432 60, 61, 62, -1, /* 4th CQE */ 433 44, 45, 46, -1, /* 3rd CQE */ 434 28, 29, 30, -1, /* 2nd CQE */ 435 12, 13, 14, -1 /* 1st CQE */ 436 }; 437 const uint16x8_t crc_adj = { 438 0, 0, rxq->crc_present * RTE_ETHER_CRC_LEN, 0, 0, 0, 0, 0 439 }; 440 const uint32x4_t flow_mark_adj = { 0, 0, 0, rxq->mark * (-1) }; 441 442 MLX5_ASSERT(rxq->sges_n == 0); 443 MLX5_ASSERT(rxq->cqe_n == rxq->elts_n); 444 cq = &(*rxq->cqes)[cq_idx]; 445 rte_prefetch_non_temporal(cq); 446 rte_prefetch_non_temporal(cq + 1); 447 rte_prefetch_non_temporal(cq + 2); 448 rte_prefetch_non_temporal(cq + 3); 449 pkts_n = RTE_MIN(pkts_n, MLX5_VPMD_RX_MAX_BURST); 450 repl_n = q_n - (rxq->rq_ci - rxq->rq_pi); 451 if (repl_n >= rxq->rq_repl_thresh) 452 mlx5_rx_replenish_bulk_mbuf(rxq, repl_n); 453 /* See if there're unreturned mbufs from compressed CQE. */ 454 rcvd_pkt = rxq->decompressed; 455 if (rcvd_pkt > 0) { 456 rcvd_pkt = RTE_MIN(rcvd_pkt, pkts_n); 457 rxq_copy_mbuf_v(rxq, pkts, rcvd_pkt); 458 rxq->rq_pi += rcvd_pkt; 459 pkts += rcvd_pkt; 460 rxq->decompressed -= rcvd_pkt; 461 } 462 elts_idx = rxq->rq_pi & q_mask; 463 elts = &(*rxq->elts)[elts_idx]; 464 /* Not to overflow pkts array. */ 465 pkts_n = RTE_ALIGN_FLOOR(pkts_n - rcvd_pkt, MLX5_VPMD_DESCS_PER_LOOP); 466 /* Not to cross queue end. */ 467 pkts_n = RTE_MIN(pkts_n, q_n - elts_idx); 468 pkts_n = RTE_MIN(pkts_n, q_n - cq_idx); 469 if (!pkts_n) 470 return rcvd_pkt; 471 /* At this point, there shouldn't be any remained packets. */ 472 MLX5_ASSERT(rxq->decompressed == 0); 473 /* 474 * Note that vectors have reverse order - {v3, v2, v1, v0}, because 475 * there's no instruction to count trailing zeros. __builtin_clzl() is 476 * used instead. 477 * 478 * A. copy 4 mbuf pointers from elts ring to returing pkts. 479 * B. load 64B CQE and extract necessary fields 480 * Final 16bytes cqes[] extracted from original 64bytes CQE has the 481 * following structure: 482 * struct { 483 * uint16_t hdr_type_etc; 484 * uint8_t pkt_info; 485 * uint8_t rsvd; 486 * uint16_t byte_cnt; 487 * uint16_t vlan_info; 488 * uint32_t rx_has_res; 489 * uint8_t flow_tag[3]; 490 * uint8_t op_own; 491 * } c; 492 * C. fill in mbuf. 493 * D. get valid CQEs. 494 * E. find compressed CQE. 495 */ 496 for (pos = 0; 497 pos < pkts_n; 498 pos += MLX5_VPMD_DESCS_PER_LOOP) { 499 uint16x4_t op_own; 500 uint16x4_t opcode, owner_mask, invalid_mask; 501 uint16x4_t comp_mask; 502 uint16x4_t mask; 503 uint16x4_t byte_cnt; 504 uint32x4_t ptype_info, flow_tag; 505 register uint64x2_t c0, c1, c2, c3; 506 uint8_t *p0, *p1, *p2, *p3; 507 uint8_t *e0 = (void *)&elts[pos]->pkt_len; 508 uint8_t *e1 = (void *)&elts[pos + 1]->pkt_len; 509 uint8_t *e2 = (void *)&elts[pos + 2]->pkt_len; 510 uint8_t *e3 = (void *)&elts[pos + 3]->pkt_len; 511 void *elts_p = (void *)&elts[pos]; 512 void *pkts_p = (void *)&pkts[pos]; 513 514 /* A.0 do not cross the end of CQ. */ 515 mask = vcreate_u16(pkts_n - pos < MLX5_VPMD_DESCS_PER_LOOP ? 516 -1UL >> ((pkts_n - pos) * 517 sizeof(uint16_t) * 8) : 0); 518 p0 = (void *)&cq[pos].pkt_info; 519 p1 = p0 + (pkts_n - pos > 1) * sizeof(struct mlx5_cqe); 520 p2 = p1 + (pkts_n - pos > 2) * sizeof(struct mlx5_cqe); 521 p3 = p2 + (pkts_n - pos > 3) * sizeof(struct mlx5_cqe); 522 /* B.0 (CQE 3) load a block having op_own. */ 523 c3 = vld1q_u64((uint64_t *)(p3 + 48)); 524 /* B.0 (CQE 2) load a block having op_own. */ 525 c2 = vld1q_u64((uint64_t *)(p2 + 48)); 526 /* B.0 (CQE 1) load a block having op_own. */ 527 c1 = vld1q_u64((uint64_t *)(p1 + 48)); 528 /* B.0 (CQE 0) load a block having op_own. */ 529 c0 = vld1q_u64((uint64_t *)(p0 + 48)); 530 /* Synchronize for loading the rest of blocks. */ 531 rte_cio_rmb(); 532 /* Prefetch next 4 CQEs. */ 533 if (pkts_n - pos >= 2 * MLX5_VPMD_DESCS_PER_LOOP) { 534 unsigned int next = pos + MLX5_VPMD_DESCS_PER_LOOP; 535 rte_prefetch_non_temporal(&cq[next]); 536 rte_prefetch_non_temporal(&cq[next + 1]); 537 rte_prefetch_non_temporal(&cq[next + 2]); 538 rte_prefetch_non_temporal(&cq[next + 3]); 539 } 540 __asm__ volatile ( 541 /* B.1 (CQE 3) load the rest of blocks. */ 542 "ld1 {v16.16b - v18.16b}, [%[p3]] \n\t" 543 /* B.2 (CQE 3) move the block having op_own. */ 544 "mov v19.16b, %[c3].16b \n\t" 545 /* B.3 (CQE 3) extract 16B fields. */ 546 "tbl v23.16b, {v16.16b - v19.16b}, %[cqe_shuf_m].16b \n\t" 547 /* B.1 (CQE 2) load the rest of blocks. */ 548 "ld1 {v16.16b - v18.16b}, [%[p2]] \n\t" 549 /* B.4 (CQE 3) adjust CRC length. */ 550 "sub v23.8h, v23.8h, %[crc_adj].8h \n\t" 551 /* C.1 (CQE 3) generate final structure for mbuf. */ 552 "tbl v15.16b, {v23.16b}, %[mb_shuf_m].16b \n\t" 553 /* B.2 (CQE 2) move the block having op_own. */ 554 "mov v19.16b, %[c2].16b \n\t" 555 /* B.3 (CQE 2) extract 16B fields. */ 556 "tbl v22.16b, {v16.16b - v19.16b}, %[cqe_shuf_m].16b \n\t" 557 /* B.1 (CQE 1) load the rest of blocks. */ 558 "ld1 {v16.16b - v18.16b}, [%[p1]] \n\t" 559 /* B.4 (CQE 2) adjust CRC length. */ 560 "sub v22.8h, v22.8h, %[crc_adj].8h \n\t" 561 /* C.1 (CQE 2) generate final structure for mbuf. */ 562 "tbl v14.16b, {v22.16b}, %[mb_shuf_m].16b \n\t" 563 /* B.2 (CQE 1) move the block having op_own. */ 564 "mov v19.16b, %[c1].16b \n\t" 565 /* B.3 (CQE 1) extract 16B fields. */ 566 "tbl v21.16b, {v16.16b - v19.16b}, %[cqe_shuf_m].16b \n\t" 567 /* B.1 (CQE 0) load the rest of blocks. */ 568 "ld1 {v16.16b - v18.16b}, [%[p0]] \n\t" 569 /* B.4 (CQE 1) adjust CRC length. */ 570 "sub v21.8h, v21.8h, %[crc_adj].8h \n\t" 571 /* C.1 (CQE 1) generate final structure for mbuf. */ 572 "tbl v13.16b, {v21.16b}, %[mb_shuf_m].16b \n\t" 573 /* B.2 (CQE 0) move the block having op_own. */ 574 "mov v19.16b, %[c0].16b \n\t" 575 /* A.1 load mbuf pointers. */ 576 "ld1 {v24.2d - v25.2d}, [%[elts_p]] \n\t" 577 /* B.3 (CQE 0) extract 16B fields. */ 578 "tbl v20.16b, {v16.16b - v19.16b}, %[cqe_shuf_m].16b \n\t" 579 /* B.4 (CQE 0) adjust CRC length. */ 580 "sub v20.8h, v20.8h, %[crc_adj].8h \n\t" 581 /* D.1 extract op_own byte. */ 582 "tbl %[op_own].8b, {v20.16b - v23.16b}, %[owner_shuf_m].8b \n\t" 583 /* C.2 (CQE 3) adjust flow mark. */ 584 "add v15.4s, v15.4s, %[flow_mark_adj].4s \n\t" 585 /* C.3 (CQE 3) fill in mbuf - rx_descriptor_fields1. */ 586 "st1 {v15.2d}, [%[e3]] \n\t" 587 /* C.2 (CQE 2) adjust flow mark. */ 588 "add v14.4s, v14.4s, %[flow_mark_adj].4s \n\t" 589 /* C.3 (CQE 2) fill in mbuf - rx_descriptor_fields1. */ 590 "st1 {v14.2d}, [%[e2]] \n\t" 591 /* C.1 (CQE 0) generate final structure for mbuf. */ 592 "tbl v12.16b, {v20.16b}, %[mb_shuf_m].16b \n\t" 593 /* C.2 (CQE 1) adjust flow mark. */ 594 "add v13.4s, v13.4s, %[flow_mark_adj].4s \n\t" 595 /* C.3 (CQE 1) fill in mbuf - rx_descriptor_fields1. */ 596 "st1 {v13.2d}, [%[e1]] \n\t" 597 #ifdef MLX5_PMD_SOFT_COUNTERS 598 /* Extract byte_cnt. */ 599 "tbl %[byte_cnt].8b, {v20.16b - v23.16b}, %[len_shuf_m].8b \n\t" 600 #endif 601 /* Extract ptype_info. */ 602 "tbl %[ptype_info].16b, {v20.16b - v23.16b}, %[ptype_shuf_m].16b \n\t" 603 /* Extract flow_tag. */ 604 "tbl %[flow_tag].16b, {v20.16b - v23.16b}, %[ftag_shuf_m].16b \n\t" 605 /* A.2 copy mbuf pointers. */ 606 "st1 {v24.2d - v25.2d}, [%[pkts_p]] \n\t" 607 /* C.2 (CQE 0) adjust flow mark. */ 608 "add v12.4s, v12.4s, %[flow_mark_adj].4s \n\t" 609 /* C.3 (CQE 1) fill in mbuf - rx_descriptor_fields1. */ 610 "st1 {v12.2d}, [%[e0]] \n\t" 611 :[op_own]"=&w"(op_own), 612 [byte_cnt]"=&w"(byte_cnt), 613 [ptype_info]"=&w"(ptype_info), 614 [flow_tag]"=&w"(flow_tag) 615 :[p3]"r"(p3), [p2]"r"(p2), [p1]"r"(p1), [p0]"r"(p0), 616 [e3]"r"(e3), [e2]"r"(e2), [e1]"r"(e1), [e0]"r"(e0), 617 [c3]"w"(c3), [c2]"w"(c2), [c1]"w"(c1), [c0]"w"(c0), 618 [elts_p]"r"(elts_p), 619 [pkts_p]"r"(pkts_p), 620 [cqe_shuf_m]"w"(cqe_shuf_m), 621 [mb_shuf_m]"w"(mb_shuf_m), 622 [owner_shuf_m]"w"(owner_shuf_m), 623 [len_shuf_m]"w"(len_shuf_m), 624 [ptype_shuf_m]"w"(ptype_shuf_m), 625 [ftag_shuf_m]"w"(ftag_shuf_m), 626 [crc_adj]"w"(crc_adj), 627 [flow_mark_adj]"w"(flow_mark_adj) 628 :"memory", 629 "v12", "v13", "v14", "v15", 630 "v16", "v17", "v18", "v19", 631 "v20", "v21", "v22", "v23", 632 "v24", "v25"); 633 /* D.2 flip owner bit to mark CQEs from last round. */ 634 owner_mask = vand_u16(op_own, owner_check); 635 owner_mask = vceq_u16(owner_mask, ownership); 636 /* D.3 get mask for invalidated CQEs. */ 637 opcode = vand_u16(op_own, opcode_check); 638 invalid_mask = vceq_u16(opcode_check, opcode); 639 /* E.1 find compressed CQE format. */ 640 comp_mask = vand_u16(op_own, format_check); 641 comp_mask = vceq_u16(comp_mask, format_check); 642 /* D.4 mask out beyond boundary. */ 643 invalid_mask = vorr_u16(invalid_mask, mask); 644 /* D.5 merge invalid_mask with invalid owner. */ 645 invalid_mask = vorr_u16(invalid_mask, owner_mask); 646 /* E.2 mask out invalid entries. */ 647 comp_mask = vbic_u16(comp_mask, invalid_mask); 648 /* E.3 get the first compressed CQE. */ 649 comp_idx = __builtin_clzl(vget_lane_u64(vreinterpret_u64_u16( 650 comp_mask), 0)) / 651 (sizeof(uint16_t) * 8); 652 /* D.6 mask out entries after the compressed CQE. */ 653 mask = vcreate_u16(comp_idx < MLX5_VPMD_DESCS_PER_LOOP ? 654 -1UL >> (comp_idx * sizeof(uint16_t) * 8) : 655 0); 656 invalid_mask = vorr_u16(invalid_mask, mask); 657 /* D.7 count non-compressed valid CQEs. */ 658 n = __builtin_clzl(vget_lane_u64(vreinterpret_u64_u16( 659 invalid_mask), 0)) / (sizeof(uint16_t) * 8); 660 nocmp_n += n; 661 /* D.2 get the final invalid mask. */ 662 mask = vcreate_u16(n < MLX5_VPMD_DESCS_PER_LOOP ? 663 -1UL >> (n * sizeof(uint16_t) * 8) : 0); 664 invalid_mask = vorr_u16(invalid_mask, mask); 665 /* D.3 check error in opcode. */ 666 opcode = vceq_u16(resp_err_check, opcode); 667 opcode = vbic_u16(opcode, invalid_mask); 668 /* D.4 mark if any error is set */ 669 *err |= vget_lane_u64(vreinterpret_u64_u16(opcode), 0); 670 /* C.4 fill in mbuf - rearm_data and packet_type. */ 671 rxq_cq_to_ptype_oflags_v(rxq, ptype_info, flow_tag, 672 opcode, &elts[pos]); 673 if (rxq->hw_timestamp) { 674 elts[pos]->timestamp = 675 rte_be_to_cpu_64( 676 container_of(p0, struct mlx5_cqe, 677 pkt_info)->timestamp); 678 elts[pos + 1]->timestamp = 679 rte_be_to_cpu_64( 680 container_of(p1, struct mlx5_cqe, 681 pkt_info)->timestamp); 682 elts[pos + 2]->timestamp = 683 rte_be_to_cpu_64( 684 container_of(p2, struct mlx5_cqe, 685 pkt_info)->timestamp); 686 elts[pos + 3]->timestamp = 687 rte_be_to_cpu_64( 688 container_of(p3, struct mlx5_cqe, 689 pkt_info)->timestamp); 690 } 691 if (rte_flow_dynf_metadata_avail()) { 692 /* This code is subject for futher optimization. */ 693 *RTE_FLOW_DYNF_METADATA(elts[pos]) = 694 container_of(p0, struct mlx5_cqe, 695 pkt_info)->flow_table_metadata; 696 *RTE_FLOW_DYNF_METADATA(elts[pos + 1]) = 697 container_of(p1, struct mlx5_cqe, 698 pkt_info)->flow_table_metadata; 699 *RTE_FLOW_DYNF_METADATA(elts[pos + 2]) = 700 container_of(p2, struct mlx5_cqe, 701 pkt_info)->flow_table_metadata; 702 *RTE_FLOW_DYNF_METADATA(elts[pos + 3]) = 703 container_of(p3, struct mlx5_cqe, 704 pkt_info)->flow_table_metadata; 705 if (*RTE_FLOW_DYNF_METADATA(elts[pos])) 706 elts[pos]->ol_flags |= PKT_RX_DYNF_METADATA; 707 if (*RTE_FLOW_DYNF_METADATA(elts[pos + 1])) 708 elts[pos + 1]->ol_flags |= PKT_RX_DYNF_METADATA; 709 if (*RTE_FLOW_DYNF_METADATA(elts[pos + 2])) 710 elts[pos + 2]->ol_flags |= PKT_RX_DYNF_METADATA; 711 if (*RTE_FLOW_DYNF_METADATA(elts[pos + 3])) 712 elts[pos + 3]->ol_flags |= PKT_RX_DYNF_METADATA; 713 } 714 #ifdef MLX5_PMD_SOFT_COUNTERS 715 /* Add up received bytes count. */ 716 byte_cnt = vbic_u16(byte_cnt, invalid_mask); 717 rcvd_byte += vget_lane_u64(vpaddl_u32(vpaddl_u16(byte_cnt)), 0); 718 #endif 719 /* 720 * Break the loop unless more valid CQE is expected, or if 721 * there's a compressed CQE. 722 */ 723 if (n != MLX5_VPMD_DESCS_PER_LOOP) 724 break; 725 } 726 /* If no new CQE seen, return without updating cq_db. */ 727 if (unlikely(!nocmp_n && comp_idx == MLX5_VPMD_DESCS_PER_LOOP)) 728 return rcvd_pkt; 729 /* Update the consumer indexes for non-compressed CQEs. */ 730 MLX5_ASSERT(nocmp_n <= pkts_n); 731 rxq->cq_ci += nocmp_n; 732 rxq->rq_pi += nocmp_n; 733 rcvd_pkt += nocmp_n; 734 #ifdef MLX5_PMD_SOFT_COUNTERS 735 rxq->stats.ipackets += nocmp_n; 736 rxq->stats.ibytes += rcvd_byte; 737 #endif 738 /* Decompress the last CQE if compressed. */ 739 if (comp_idx < MLX5_VPMD_DESCS_PER_LOOP && comp_idx == n) { 740 MLX5_ASSERT(comp_idx == (nocmp_n % MLX5_VPMD_DESCS_PER_LOOP)); 741 rxq->decompressed = rxq_cq_decompress_v(rxq, &cq[nocmp_n], 742 &elts[nocmp_n]); 743 /* Return more packets if needed. */ 744 if (nocmp_n < pkts_n) { 745 uint16_t n = rxq->decompressed; 746 747 n = RTE_MIN(n, pkts_n - nocmp_n); 748 rxq_copy_mbuf_v(rxq, &pkts[nocmp_n], n); 749 rxq->rq_pi += n; 750 rcvd_pkt += n; 751 rxq->decompressed -= n; 752 } 753 } 754 rte_cio_wmb(); 755 *rxq->cq_db = rte_cpu_to_be_32(rxq->cq_ci); 756 return rcvd_pkt; 757 } 758 759 #endif /* RTE_PMD_MLX5_RXTX_VEC_NEON_H_ */ 760