1 /*- 2 * BSD LICENSE 3 * 4 * Copyright 2017 6WIND S.A. 5 * Copyright 2017 Mellanox. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * * Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * * Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in 15 * the documentation and/or other materials provided with the 16 * distribution. 17 * * Neither the name of 6WIND S.A. nor the names of its 18 * contributors may be used to endorse or promote products derived 19 * from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #ifndef RTE_PMD_MLX5_RXTX_VEC_NEON_H_ 35 #define RTE_PMD_MLX5_RXTX_VEC_NEON_H_ 36 37 #include <assert.h> 38 #include <stdint.h> 39 #include <string.h> 40 #include <stdlib.h> 41 #include <arm_neon.h> 42 43 #include <rte_mbuf.h> 44 #include <rte_mempool.h> 45 #include <rte_prefetch.h> 46 47 #include "mlx5.h" 48 #include "mlx5_utils.h" 49 #include "mlx5_rxtx.h" 50 #include "mlx5_rxtx_vec.h" 51 #include "mlx5_autoconf.h" 52 #include "mlx5_defs.h" 53 #include "mlx5_prm.h" 54 55 #pragma GCC diagnostic ignored "-Wcast-qual" 56 57 /** 58 * Fill in buffer descriptors in a multi-packet send descriptor. 59 * 60 * @param txq 61 * Pointer to TX queue structure. 62 * @param dseg 63 * Pointer to buffer descriptor to be written. 64 * @param pkts 65 * Pointer to array of packets to be sent. 66 * @param n 67 * Number of packets to be filled. 68 */ 69 static inline void 70 txq_wr_dseg_v(struct mlx5_txq_data *txq, uint8_t *dseg, 71 struct rte_mbuf **pkts, unsigned int n) 72 { 73 unsigned int pos; 74 uintptr_t addr; 75 const uint8x16_t dseg_shuf_m = { 76 3, 2, 1, 0, /* length, bswap32 */ 77 4, 5, 6, 7, /* lkey */ 78 15, 14, 13, 12, /* addr, bswap64 */ 79 11, 10, 9, 8 80 }; 81 #ifdef MLX5_PMD_SOFT_COUNTERS 82 uint32_t tx_byte = 0; 83 #endif 84 85 for (pos = 0; pos < n; ++pos, dseg += MLX5_WQE_DWORD_SIZE) { 86 uint8x16_t desc; 87 struct rte_mbuf *pkt = pkts[pos]; 88 89 addr = rte_pktmbuf_mtod(pkt, uintptr_t); 90 desc = vreinterpretq_u8_u32((uint32x4_t) { 91 DATA_LEN(pkt), 92 mlx5_tx_mb2mr(txq, pkt), 93 addr, 94 addr >> 32 }); 95 desc = vqtbl1q_u8(desc, dseg_shuf_m); 96 vst1q_u8(dseg, desc); 97 #ifdef MLX5_PMD_SOFT_COUNTERS 98 tx_byte += DATA_LEN(pkt); 99 #endif 100 } 101 #ifdef MLX5_PMD_SOFT_COUNTERS 102 txq->stats.obytes += tx_byte; 103 #endif 104 } 105 106 /** 107 * Send multi-segmented packets until it encounters a single segment packet in 108 * the pkts list. 109 * 110 * @param txq 111 * Pointer to TX queue structure. 112 * @param pkts 113 * Pointer to array of packets to be sent. 114 * @param pkts_n 115 * Number of packets to be sent. 116 * 117 * @return 118 * Number of packets successfully transmitted (<= pkts_n). 119 */ 120 static uint16_t 121 txq_scatter_v(struct mlx5_txq_data *txq, struct rte_mbuf **pkts, 122 uint16_t pkts_n) 123 { 124 uint16_t elts_head = txq->elts_head; 125 const uint16_t elts_n = 1 << txq->elts_n; 126 const uint16_t elts_m = elts_n - 1; 127 const uint16_t wq_n = 1 << txq->wqe_n; 128 const uint16_t wq_mask = wq_n - 1; 129 const unsigned int nb_dword_per_wqebb = 130 MLX5_WQE_SIZE / MLX5_WQE_DWORD_SIZE; 131 const unsigned int nb_dword_in_hdr = 132 sizeof(struct mlx5_wqe) / MLX5_WQE_DWORD_SIZE; 133 unsigned int n; 134 volatile struct mlx5_wqe *wqe = NULL; 135 136 assert(elts_n > pkts_n); 137 mlx5_tx_complete(txq); 138 /* A CQE slot must always be available. */ 139 assert((1u << txq->cqe_n) - (txq->cq_pi - txq->cq_ci)); 140 if (unlikely(!pkts_n)) 141 return 0; 142 for (n = 0; n < pkts_n; ++n) { 143 struct rte_mbuf *buf = pkts[n]; 144 unsigned int segs_n = buf->nb_segs; 145 unsigned int ds = nb_dword_in_hdr; 146 unsigned int len = PKT_LEN(buf); 147 uint16_t wqe_ci = txq->wqe_ci; 148 const uint8x16_t ctrl_shuf_m = { 149 3, 2, 1, 0, /* bswap32 */ 150 7, 6, 5, 4, /* bswap32 */ 151 11, 10, 9, 8, /* bswap32 */ 152 12, 13, 14, 15 153 }; 154 uint8_t cs_flags; 155 uint16_t max_elts; 156 uint16_t max_wqe; 157 uint8x16_t *t_wqe; 158 uint8_t *dseg; 159 uint8x16_t ctrl; 160 161 assert(segs_n); 162 max_elts = elts_n - (elts_head - txq->elts_tail); 163 max_wqe = wq_n - (txq->wqe_ci - txq->wqe_pi); 164 /* 165 * A MPW session consumes 2 WQEs at most to 166 * include MLX5_MPW_DSEG_MAX pointers. 167 */ 168 if (segs_n == 1 || 169 max_elts < segs_n || max_wqe < 2) 170 break; 171 wqe = &((volatile struct mlx5_wqe64 *) 172 txq->wqes)[wqe_ci & wq_mask].hdr; 173 cs_flags = txq_ol_cksum_to_cs(txq, buf); 174 /* Title WQEBB pointer. */ 175 t_wqe = (uint8x16_t *)wqe; 176 dseg = (uint8_t *)(wqe + 1); 177 do { 178 if (!(ds++ % nb_dword_per_wqebb)) { 179 dseg = (uint8_t *) 180 &((volatile struct mlx5_wqe64 *) 181 txq->wqes)[++wqe_ci & wq_mask]; 182 } 183 txq_wr_dseg_v(txq, dseg, &buf, 1); 184 dseg += MLX5_WQE_DWORD_SIZE; 185 (*txq->elts)[elts_head++ & elts_m] = buf; 186 buf = buf->next; 187 } while (--segs_n); 188 ++wqe_ci; 189 /* Fill CTRL in the header. */ 190 ctrl = vreinterpretq_u8_u32((uint32x4_t) { 191 MLX5_OPC_MOD_MPW << 24 | 192 txq->wqe_ci << 8 | MLX5_OPCODE_TSO, 193 txq->qp_num_8s | ds, 0, 0}); 194 ctrl = vqtbl1q_u8(ctrl, ctrl_shuf_m); 195 vst1q_u8((void *)t_wqe, ctrl); 196 /* Fill ESEG in the header. */ 197 vst1q_u16((void *)(t_wqe + 1), 198 (uint16x8_t) { 0, 0, cs_flags, rte_cpu_to_be_16(len), 199 0, 0, 0, 0 }); 200 txq->wqe_ci = wqe_ci; 201 } 202 if (!n) 203 return 0; 204 txq->elts_comp += (uint16_t)(elts_head - txq->elts_head); 205 txq->elts_head = elts_head; 206 if (txq->elts_comp >= MLX5_TX_COMP_THRESH) { 207 wqe->ctrl[2] = rte_cpu_to_be_32(8); 208 wqe->ctrl[3] = txq->elts_head; 209 txq->elts_comp = 0; 210 #ifndef NDEBUG 211 ++txq->cq_pi; 212 #endif 213 } 214 #ifdef MLX5_PMD_SOFT_COUNTERS 215 txq->stats.opackets += n; 216 #endif 217 mlx5_tx_dbrec(txq, wqe); 218 return n; 219 } 220 221 /** 222 * Send burst of packets with Enhanced MPW. If it encounters a multi-seg packet, 223 * it returns to make it processed by txq_scatter_v(). All the packets in 224 * the pkts list should be single segment packets having same offload flags. 225 * This must be checked by txq_count_contig_single_seg() and txq_calc_offload(). 226 * 227 * @param txq 228 * Pointer to TX queue structure. 229 * @param pkts 230 * Pointer to array of packets to be sent. 231 * @param pkts_n 232 * Number of packets to be sent (<= MLX5_VPMD_TX_MAX_BURST). 233 * @param cs_flags 234 * Checksum offload flags to be written in the descriptor. 235 * 236 * @return 237 * Number of packets successfully transmitted (<= pkts_n). 238 */ 239 static inline uint16_t 240 txq_burst_v(struct mlx5_txq_data *txq, struct rte_mbuf **pkts, uint16_t pkts_n, 241 uint8_t cs_flags) 242 { 243 struct rte_mbuf **elts; 244 uint16_t elts_head = txq->elts_head; 245 const uint16_t elts_n = 1 << txq->elts_n; 246 const uint16_t elts_m = elts_n - 1; 247 const unsigned int nb_dword_per_wqebb = 248 MLX5_WQE_SIZE / MLX5_WQE_DWORD_SIZE; 249 const unsigned int nb_dword_in_hdr = 250 sizeof(struct mlx5_wqe) / MLX5_WQE_DWORD_SIZE; 251 unsigned int n = 0; 252 unsigned int pos; 253 uint16_t max_elts; 254 uint16_t max_wqe; 255 uint32_t comp_req = 0; 256 const uint16_t wq_n = 1 << txq->wqe_n; 257 const uint16_t wq_mask = wq_n - 1; 258 uint16_t wq_idx = txq->wqe_ci & wq_mask; 259 volatile struct mlx5_wqe64 *wq = 260 &((volatile struct mlx5_wqe64 *)txq->wqes)[wq_idx]; 261 volatile struct mlx5_wqe *wqe = (volatile struct mlx5_wqe *)wq; 262 const uint8x16_t ctrl_shuf_m = { 263 3, 2, 1, 0, /* bswap32 */ 264 7, 6, 5, 4, /* bswap32 */ 265 11, 10, 9, 8, /* bswap32 */ 266 12, 13, 14, 15 267 }; 268 uint8x16_t *t_wqe; 269 uint8_t *dseg; 270 uint8x16_t ctrl; 271 272 /* Make sure all packets can fit into a single WQE. */ 273 assert(elts_n > pkts_n); 274 mlx5_tx_complete(txq); 275 max_elts = (elts_n - (elts_head - txq->elts_tail)); 276 /* A CQE slot must always be available. */ 277 assert((1u << txq->cqe_n) - (txq->cq_pi - txq->cq_ci)); 278 max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi); 279 pkts_n = RTE_MIN((unsigned int)RTE_MIN(pkts_n, max_wqe), max_elts); 280 if (unlikely(!pkts_n)) 281 return 0; 282 elts = &(*txq->elts)[elts_head & elts_m]; 283 /* Loop for available tailroom first. */ 284 n = RTE_MIN(elts_n - (elts_head & elts_m), pkts_n); 285 for (pos = 0; pos < (n & -2); pos += 2) 286 vst1q_u64((void *)&elts[pos], vld1q_u64((void *)&pkts[pos])); 287 if (n & 1) 288 elts[pos] = pkts[pos]; 289 /* Check if it crosses the end of the queue. */ 290 if (unlikely(n < pkts_n)) { 291 elts = &(*txq->elts)[0]; 292 for (pos = 0; pos < pkts_n - n; ++pos) 293 elts[pos] = pkts[n + pos]; 294 } 295 txq->elts_head += pkts_n; 296 /* Save title WQEBB pointer. */ 297 t_wqe = (uint8x16_t *)wqe; 298 dseg = (uint8_t *)(wqe + 1); 299 /* Calculate the number of entries to the end. */ 300 n = RTE_MIN( 301 (wq_n - wq_idx) * nb_dword_per_wqebb - nb_dword_in_hdr, 302 pkts_n); 303 /* Fill DSEGs. */ 304 txq_wr_dseg_v(txq, dseg, pkts, n); 305 /* Check if it crosses the end of the queue. */ 306 if (n < pkts_n) { 307 dseg = (uint8_t *)txq->wqes; 308 txq_wr_dseg_v(txq, dseg, &pkts[n], pkts_n - n); 309 } 310 if (txq->elts_comp + pkts_n < MLX5_TX_COMP_THRESH) { 311 txq->elts_comp += pkts_n; 312 } else { 313 /* Request a completion. */ 314 txq->elts_comp = 0; 315 #ifndef NDEBUG 316 ++txq->cq_pi; 317 #endif 318 comp_req = 8; 319 } 320 /* Fill CTRL in the header. */ 321 ctrl = vreinterpretq_u8_u32((uint32x4_t) { 322 MLX5_OPC_MOD_ENHANCED_MPSW << 24 | 323 txq->wqe_ci << 8 | MLX5_OPCODE_ENHANCED_MPSW, 324 txq->qp_num_8s | (pkts_n + 2), 325 comp_req, 326 txq->elts_head }); 327 ctrl = vqtbl1q_u8(ctrl, ctrl_shuf_m); 328 vst1q_u8((void *)t_wqe, ctrl); 329 /* Fill ESEG in the header. */ 330 vst1q_u8((void *)(t_wqe + 1), 331 (uint8x16_t) { 0, 0, 0, 0, 332 cs_flags, 0, 0, 0, 333 0, 0, 0, 0, 334 0, 0, 0, 0 }); 335 #ifdef MLX5_PMD_SOFT_COUNTERS 336 txq->stats.opackets += pkts_n; 337 #endif 338 txq->wqe_ci += (nb_dword_in_hdr + pkts_n + (nb_dword_per_wqebb - 1)) / 339 nb_dword_per_wqebb; 340 /* Ring QP doorbell. */ 341 mlx5_tx_dbrec_cond_wmb(txq, wqe, pkts_n < MLX5_VPMD_TX_MAX_BURST); 342 return pkts_n; 343 } 344 345 /** 346 * Store free buffers to RX SW ring. 347 * 348 * @param rxq 349 * Pointer to RX queue structure. 350 * @param pkts 351 * Pointer to array of packets to be stored. 352 * @param pkts_n 353 * Number of packets to be stored. 354 */ 355 static inline void 356 rxq_copy_mbuf_v(struct mlx5_rxq_data *rxq, struct rte_mbuf **pkts, uint16_t n) 357 { 358 const uint16_t q_mask = (1 << rxq->elts_n) - 1; 359 struct rte_mbuf **elts = &(*rxq->elts)[rxq->rq_pi & q_mask]; 360 unsigned int pos; 361 uint16_t p = n & -2; 362 363 for (pos = 0; pos < p; pos += 2) { 364 uint64x2_t mbp; 365 366 mbp = vld1q_u64((void *)&elts[pos]); 367 vst1q_u64((void *)&pkts[pos], mbp); 368 } 369 if (n & 1) 370 pkts[pos] = elts[pos]; 371 } 372 373 /** 374 * Decompress a compressed completion and fill in mbufs in RX SW ring with data 375 * extracted from the title completion descriptor. 376 * 377 * @param rxq 378 * Pointer to RX queue structure. 379 * @param cq 380 * Pointer to completion array having a compressed completion at first. 381 * @param elts 382 * Pointer to SW ring to be filled. The first mbuf has to be pre-built from 383 * the title completion descriptor to be copied to the rest of mbufs. 384 */ 385 static inline void 386 rxq_cq_decompress_v(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cq, 387 struct rte_mbuf **elts) 388 { 389 volatile struct mlx5_mini_cqe8 *mcq = (void *)&(cq + 1)->pkt_info; 390 struct rte_mbuf *t_pkt = elts[0]; /* Title packet is pre-built. */ 391 unsigned int pos; 392 unsigned int i; 393 unsigned int inv = 0; 394 /* Mask to shuffle from extracted mini CQE to mbuf. */ 395 const uint8x16_t mcqe_shuf_m1 = { 396 -1, -1, -1, -1, /* skip packet_type */ 397 7, 6, -1, -1, /* pkt_len, bswap16 */ 398 7, 6, /* data_len, bswap16 */ 399 -1, -1, /* skip vlan_tci */ 400 3, 2, 1, 0 /* hash.rss, bswap32 */ 401 }; 402 const uint8x16_t mcqe_shuf_m2 = { 403 -1, -1, -1, -1, /* skip packet_type */ 404 15, 14, -1, -1, /* pkt_len, bswap16 */ 405 15, 14, /* data_len, bswap16 */ 406 -1, -1, /* skip vlan_tci */ 407 11, 10, 9, 8 /* hash.rss, bswap32 */ 408 }; 409 /* Restore the compressed count. Must be 16 bits. */ 410 const uint16_t mcqe_n = t_pkt->data_len + 411 (rxq->crc_present * ETHER_CRC_LEN); 412 const uint64x2_t rearm = 413 vld1q_u64((void *)&t_pkt->rearm_data); 414 const uint32x4_t rxdf_mask = { 415 0xffffffff, /* packet_type */ 416 0, /* skip pkt_len */ 417 0xffff0000, /* vlan_tci, skip data_len */ 418 0, /* skip hash.rss */ 419 }; 420 const uint8x16_t rxdf = 421 vandq_u8(vld1q_u8((void *)&t_pkt->rx_descriptor_fields1), 422 vreinterpretq_u8_u32(rxdf_mask)); 423 const uint16x8_t crc_adj = { 424 0, 0, 425 rxq->crc_present * ETHER_CRC_LEN, 0, 426 rxq->crc_present * ETHER_CRC_LEN, 0, 427 0, 0 428 }; 429 const uint32_t flow_tag = t_pkt->hash.fdir.hi; 430 #ifdef MLX5_PMD_SOFT_COUNTERS 431 uint32_t rcvd_byte = 0; 432 #endif 433 /* Mask to shuffle byte_cnt to add up stats. Do bswap16 for all. */ 434 const uint8x8_t len_shuf_m = { 435 7, 6, /* 1st mCQE */ 436 15, 14, /* 2nd mCQE */ 437 23, 22, /* 3rd mCQE */ 438 31, 30 /* 4th mCQE */ 439 }; 440 441 /* 442 * A. load mCQEs into a 128bit register. 443 * B. store rearm data to mbuf. 444 * C. combine data from mCQEs with rx_descriptor_fields1. 445 * D. store rx_descriptor_fields1. 446 * E. store flow tag (rte_flow mark). 447 */ 448 for (pos = 0; pos < mcqe_n; ) { 449 uint8_t *p = (void *)&mcq[pos % 8]; 450 uint8_t *e0 = (void *)&elts[pos]->rearm_data; 451 uint8_t *e1 = (void *)&elts[pos + 1]->rearm_data; 452 uint8_t *e2 = (void *)&elts[pos + 2]->rearm_data; 453 uint8_t *e3 = (void *)&elts[pos + 3]->rearm_data; 454 uint16x4_t byte_cnt; 455 #ifdef MLX5_PMD_SOFT_COUNTERS 456 uint16x4_t invalid_mask = 457 vcreate_u16(mcqe_n - pos < MLX5_VPMD_DESCS_PER_LOOP ? 458 -1UL << ((mcqe_n - pos) * 459 sizeof(uint16_t) * 8) : 0); 460 #endif 461 462 if (!(pos & 0x7) && pos + 8 < mcqe_n) 463 rte_prefetch0((void *)(cq + pos + 8)); 464 __asm__ volatile ( 465 /* A.1 load mCQEs into a 128bit register. */ 466 "ld1 {v16.16b - v17.16b}, [%[mcq]] \n\t" 467 /* B.1 store rearm data to mbuf. */ 468 "st1 {%[rearm].2d}, [%[e0]] \n\t" 469 "add %[e0], %[e0], #16 \n\t" 470 "st1 {%[rearm].2d}, [%[e1]] \n\t" 471 "add %[e1], %[e1], #16 \n\t" 472 /* C.1 combine data from mCQEs with rx_descriptor_fields1. */ 473 "tbl v18.16b, {v16.16b}, %[mcqe_shuf_m1].16b \n\t" 474 "tbl v19.16b, {v16.16b}, %[mcqe_shuf_m2].16b \n\t" 475 "sub v18.8h, v18.8h, %[crc_adj].8h \n\t" 476 "sub v19.8h, v19.8h, %[crc_adj].8h \n\t" 477 "orr v18.16b, v18.16b, %[rxdf].16b \n\t" 478 "orr v19.16b, v19.16b, %[rxdf].16b \n\t" 479 /* D.1 store rx_descriptor_fields1. */ 480 "st1 {v18.2d}, [%[e0]] \n\t" 481 "st1 {v19.2d}, [%[e1]] \n\t" 482 /* B.1 store rearm data to mbuf. */ 483 "st1 {%[rearm].2d}, [%[e2]] \n\t" 484 "add %[e2], %[e2], #16 \n\t" 485 "st1 {%[rearm].2d}, [%[e3]] \n\t" 486 "add %[e3], %[e3], #16 \n\t" 487 /* C.1 combine data from mCQEs with rx_descriptor_fields1. */ 488 "tbl v18.16b, {v17.16b}, %[mcqe_shuf_m1].16b \n\t" 489 "tbl v19.16b, {v17.16b}, %[mcqe_shuf_m2].16b \n\t" 490 "sub v18.8h, v18.8h, %[crc_adj].8h \n\t" 491 "sub v19.8h, v19.8h, %[crc_adj].8h \n\t" 492 "orr v18.16b, v18.16b, %[rxdf].16b \n\t" 493 "orr v19.16b, v19.16b, %[rxdf].16b \n\t" 494 /* D.1 store rx_descriptor_fields1. */ 495 "st1 {v18.2d}, [%[e2]] \n\t" 496 "st1 {v19.2d}, [%[e3]] \n\t" 497 #ifdef MLX5_PMD_SOFT_COUNTERS 498 "tbl %[byte_cnt].8b, {v16.16b - v17.16b}, %[len_shuf_m].8b \n\t" 499 #endif 500 :[byte_cnt]"=&w"(byte_cnt) 501 :[mcq]"r"(p), 502 [rxdf]"w"(rxdf), 503 [rearm]"w"(rearm), 504 [e3]"r"(e3), [e2]"r"(e2), [e1]"r"(e1), [e0]"r"(e0), 505 [mcqe_shuf_m1]"w"(mcqe_shuf_m1), 506 [mcqe_shuf_m2]"w"(mcqe_shuf_m2), 507 [crc_adj]"w"(crc_adj), 508 [len_shuf_m]"w"(len_shuf_m) 509 :"memory", "v16", "v17", "v18", "v19"); 510 #ifdef MLX5_PMD_SOFT_COUNTERS 511 byte_cnt = vbic_u16(byte_cnt, invalid_mask); 512 rcvd_byte += vget_lane_u64(vpaddl_u32(vpaddl_u16(byte_cnt)), 0); 513 #endif 514 if (rxq->mark) { 515 /* E.1 store flow tag (rte_flow mark). */ 516 elts[pos]->hash.fdir.hi = flow_tag; 517 elts[pos + 1]->hash.fdir.hi = flow_tag; 518 elts[pos + 2]->hash.fdir.hi = flow_tag; 519 elts[pos + 3]->hash.fdir.hi = flow_tag; 520 } 521 pos += MLX5_VPMD_DESCS_PER_LOOP; 522 /* Move to next CQE and invalidate consumed CQEs. */ 523 if (!(pos & 0x7) && pos < mcqe_n) { 524 mcq = (void *)&(cq + pos)->pkt_info; 525 for (i = 0; i < 8; ++i) 526 cq[inv++].op_own = MLX5_CQE_INVALIDATE; 527 } 528 } 529 /* Invalidate the rest of CQEs. */ 530 for (; inv < mcqe_n; ++inv) 531 cq[inv].op_own = MLX5_CQE_INVALIDATE; 532 #ifdef MLX5_PMD_SOFT_COUNTERS 533 rxq->stats.ipackets += mcqe_n; 534 rxq->stats.ibytes += rcvd_byte; 535 #endif 536 rxq->cq_ci += mcqe_n; 537 } 538 539 /** 540 * Calculate packet type and offload flag for mbuf and store it. 541 * 542 * @param rxq 543 * Pointer to RX queue structure. 544 * @param ptype_info 545 * Array of four 4bytes packet type info extracted from the original 546 * completion descriptor. 547 * @param flow_tag 548 * Array of four 4bytes flow ID extracted from the original completion 549 * descriptor. 550 * @param op_err 551 * Opcode vector having responder error status. Each field is 4B. 552 * @param pkts 553 * Pointer to array of packets to be filled. 554 */ 555 static inline void 556 rxq_cq_to_ptype_oflags_v(struct mlx5_rxq_data *rxq, 557 uint32x4_t ptype_info, uint32x4_t flow_tag, 558 uint16x4_t op_err, struct rte_mbuf **pkts) 559 { 560 uint16x4_t ptype; 561 uint32x4_t pinfo, cv_flags; 562 uint32x4_t ol_flags = 563 vdupq_n_u32(rxq->rss_hash * PKT_RX_RSS_HASH | 564 rxq->hw_timestamp * PKT_RX_TIMESTAMP); 565 const uint32x4_t ptype_ol_mask = { 0x106, 0x106, 0x106, 0x106 }; 566 const uint8x16_t cv_flag_sel = { 567 0, 568 (uint8_t)(PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED), 569 (uint8_t)(PKT_RX_IP_CKSUM_GOOD >> 1), 570 0, 571 (uint8_t)(PKT_RX_L4_CKSUM_GOOD >> 1), 572 0, 573 (uint8_t)((PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD) >> 1), 574 0, 0, 0, 0, 0, 0, 0, 0, 0 575 }; 576 const uint32x4_t cv_mask = 577 vdupq_n_u32(PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD | 578 PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED); 579 const uint64x1_t mbuf_init = vld1_u64(&rxq->mbuf_initializer); 580 const uint64x1_t r32_mask = vcreate_u64(0xffffffff); 581 uint64x2_t rearm0, rearm1, rearm2, rearm3; 582 583 if (rxq->mark) { 584 const uint32x4_t ft_def = vdupq_n_u32(MLX5_FLOW_MARK_DEFAULT); 585 const uint32x4_t fdir_flags = vdupq_n_u32(PKT_RX_FDIR); 586 const uint32x4_t fdir_id_flags = vdupq_n_u32(PKT_RX_FDIR_ID); 587 588 /* Check if flow tag is non-zero then set PKT_RX_FDIR. */ 589 ol_flags = vorrq_u32(ol_flags, vbicq_u32(fdir_flags, 590 vceqzq_u32(flow_tag))); 591 /* Check if flow tag MLX5_FLOW_MARK_DEFAULT. */ 592 ol_flags = vorrq_u32(ol_flags, 593 vbicq_u32(fdir_id_flags, 594 vceqq_u32(flow_tag, ft_def))); 595 } 596 /* 597 * ptype_info has the following: 598 * bit[1] = l3_ok 599 * bit[2] = l4_ok 600 * bit[8] = cv 601 * bit[11:10] = l3_hdr_type 602 * bit[14:12] = l4_hdr_type 603 * bit[15] = ip_frag 604 * bit[16] = tunneled 605 * bit[17] = outer_l3_type 606 */ 607 ptype = vshrn_n_u32(ptype_info, 10); 608 /* Errored packets will have RTE_PTYPE_ALL_MASK. */ 609 ptype = vorr_u16(ptype, op_err); 610 pkts[0]->packet_type = 611 mlx5_ptype_table[vget_lane_u8(vreinterpret_u8_u16(ptype), 6)]; 612 pkts[1]->packet_type = 613 mlx5_ptype_table[vget_lane_u8(vreinterpret_u8_u16(ptype), 4)]; 614 pkts[2]->packet_type = 615 mlx5_ptype_table[vget_lane_u8(vreinterpret_u8_u16(ptype), 2)]; 616 pkts[3]->packet_type = 617 mlx5_ptype_table[vget_lane_u8(vreinterpret_u8_u16(ptype), 0)]; 618 /* Fill flags for checksum and VLAN. */ 619 pinfo = vandq_u32(ptype_info, ptype_ol_mask); 620 pinfo = vreinterpretq_u32_u8( 621 vqtbl1q_u8(cv_flag_sel, vreinterpretq_u8_u32(pinfo))); 622 /* Locate checksum flags at byte[2:1] and merge with VLAN flags. */ 623 cv_flags = vshlq_n_u32(pinfo, 9); 624 cv_flags = vorrq_u32(pinfo, cv_flags); 625 /* Move back flags to start from byte[0]. */ 626 cv_flags = vshrq_n_u32(cv_flags, 8); 627 /* Mask out garbage bits. */ 628 cv_flags = vandq_u32(cv_flags, cv_mask); 629 /* Merge to ol_flags. */ 630 ol_flags = vorrq_u32(ol_flags, cv_flags); 631 /* Merge mbuf_init and ol_flags, and store. */ 632 rearm0 = vcombine_u64(mbuf_init, 633 vshr_n_u64(vget_high_u64(vreinterpretq_u64_u32( 634 ol_flags)), 32)); 635 rearm1 = vcombine_u64(mbuf_init, 636 vand_u64(vget_high_u64(vreinterpretq_u64_u32( 637 ol_flags)), r32_mask)); 638 rearm2 = vcombine_u64(mbuf_init, 639 vshr_n_u64(vget_low_u64(vreinterpretq_u64_u32( 640 ol_flags)), 32)); 641 rearm3 = vcombine_u64(mbuf_init, 642 vand_u64(vget_low_u64(vreinterpretq_u64_u32( 643 ol_flags)), r32_mask)); 644 vst1q_u64((void *)&pkts[0]->rearm_data, rearm0); 645 vst1q_u64((void *)&pkts[1]->rearm_data, rearm1); 646 vst1q_u64((void *)&pkts[2]->rearm_data, rearm2); 647 vst1q_u64((void *)&pkts[3]->rearm_data, rearm3); 648 } 649 650 /** 651 * Receive burst of packets. An errored completion also consumes a mbuf, but the 652 * packet_type is set to be RTE_PTYPE_ALL_MASK. Marked mbufs should be freed 653 * before returning to application. 654 * 655 * @param rxq 656 * Pointer to RX queue structure. 657 * @param[out] pkts 658 * Array to store received packets. 659 * @param pkts_n 660 * Maximum number of packets in array. 661 * 662 * @return 663 * Number of packets received including errors (<= pkts_n). 664 */ 665 static inline uint16_t 666 rxq_burst_v(struct mlx5_rxq_data *rxq, struct rte_mbuf **pkts, uint16_t pkts_n) 667 { 668 const uint16_t q_n = 1 << rxq->cqe_n; 669 const uint16_t q_mask = q_n - 1; 670 volatile struct mlx5_cqe *cq; 671 struct rte_mbuf **elts; 672 unsigned int pos; 673 uint64_t n; 674 uint16_t repl_n; 675 uint64_t comp_idx = MLX5_VPMD_DESCS_PER_LOOP; 676 uint16_t nocmp_n = 0; 677 uint16_t rcvd_pkt = 0; 678 unsigned int cq_idx = rxq->cq_ci & q_mask; 679 unsigned int elts_idx; 680 const uint16x4_t ownership = vdup_n_u16(!(rxq->cq_ci & (q_mask + 1))); 681 const uint16x4_t owner_check = vcreate_u16(0x0001000100010001); 682 const uint16x4_t opcode_check = vcreate_u16(0x00f000f000f000f0); 683 const uint16x4_t format_check = vcreate_u16(0x000c000c000c000c); 684 const uint16x4_t resp_err_check = vcreate_u16(0x00e000e000e000e0); 685 #ifdef MLX5_PMD_SOFT_COUNTERS 686 uint32_t rcvd_byte = 0; 687 #endif 688 /* Mask to generate 16B length vector. */ 689 const uint8x8_t len_shuf_m = { 690 52, 53, /* 4th CQE */ 691 36, 37, /* 3rd CQE */ 692 20, 21, /* 2nd CQE */ 693 4, 5 /* 1st CQE */ 694 }; 695 /* Mask to extract 16B data from a 64B CQE. */ 696 const uint8x16_t cqe_shuf_m = { 697 28, 29, /* hdr_type_etc */ 698 0, /* pkt_info */ 699 -1, /* null */ 700 47, 46, /* byte_cnt, bswap16 */ 701 31, 30, /* vlan_info, bswap16 */ 702 15, 14, 13, 12, /* rx_hash_res, bswap32 */ 703 57, 58, 59, /* flow_tag */ 704 63 /* op_own */ 705 }; 706 /* Mask to generate 16B data for mbuf. */ 707 const uint8x16_t mb_shuf_m = { 708 4, 5, -1, -1, /* pkt_len */ 709 4, 5, /* data_len */ 710 6, 7, /* vlan_tci */ 711 8, 9, 10, 11, /* hash.rss */ 712 12, 13, 14, -1 /* hash.fdir.hi */ 713 }; 714 /* Mask to generate 16B owner vector. */ 715 const uint8x8_t owner_shuf_m = { 716 63, -1, /* 4th CQE */ 717 47, -1, /* 3rd CQE */ 718 31, -1, /* 2nd CQE */ 719 15, -1 /* 1st CQE */ 720 }; 721 /* Mask to generate a vector having packet_type/ol_flags. */ 722 const uint8x16_t ptype_shuf_m = { 723 48, 49, 50, -1, /* 4th CQE */ 724 32, 33, 34, -1, /* 3rd CQE */ 725 16, 17, 18, -1, /* 2nd CQE */ 726 0, 1, 2, -1 /* 1st CQE */ 727 }; 728 /* Mask to generate a vector having flow tags. */ 729 const uint8x16_t ftag_shuf_m = { 730 60, 61, 62, -1, /* 4th CQE */ 731 44, 45, 46, -1, /* 3rd CQE */ 732 28, 29, 30, -1, /* 2nd CQE */ 733 12, 13, 14, -1 /* 1st CQE */ 734 }; 735 const uint16x8_t crc_adj = { 736 0, 0, rxq->crc_present * ETHER_CRC_LEN, 0, 0, 0, 0, 0 737 }; 738 const uint32x4_t flow_mark_adj = { 0, 0, 0, rxq->mark * (-1) }; 739 740 assert(rxq->sges_n == 0); 741 assert(rxq->cqe_n == rxq->elts_n); 742 cq = &(*rxq->cqes)[cq_idx]; 743 rte_prefetch_non_temporal(cq); 744 rte_prefetch_non_temporal(cq + 1); 745 rte_prefetch_non_temporal(cq + 2); 746 rte_prefetch_non_temporal(cq + 3); 747 pkts_n = RTE_MIN(pkts_n, MLX5_VPMD_RX_MAX_BURST); 748 /* 749 * Order of indexes: 750 * rq_ci >= cq_ci >= rq_pi 751 * Definition of indexes: 752 * rq_ci - cq_ci := # of buffers owned by HW (posted). 753 * cq_ci - rq_pi := # of buffers not returned to app (decompressed). 754 * N - (rq_ci - rq_pi) := # of buffers consumed (to be replenished). 755 */ 756 repl_n = q_n - (rxq->rq_ci - rxq->rq_pi); 757 if (repl_n >= MLX5_VPMD_RXQ_RPLNSH_THRESH) 758 mlx5_rx_replenish_bulk_mbuf(rxq, repl_n); 759 /* See if there're unreturned mbufs from compressed CQE. */ 760 rcvd_pkt = rxq->cq_ci - rxq->rq_pi; 761 if (rcvd_pkt > 0) { 762 rcvd_pkt = RTE_MIN(rcvd_pkt, pkts_n); 763 rxq_copy_mbuf_v(rxq, pkts, rcvd_pkt); 764 rxq->rq_pi += rcvd_pkt; 765 pkts += rcvd_pkt; 766 } 767 elts_idx = rxq->rq_pi & q_mask; 768 elts = &(*rxq->elts)[elts_idx]; 769 /* Not to overflow pkts array. */ 770 pkts_n = RTE_ALIGN_FLOOR(pkts_n - rcvd_pkt, MLX5_VPMD_DESCS_PER_LOOP); 771 /* Not to cross queue end. */ 772 pkts_n = RTE_MIN(pkts_n, q_n - elts_idx); 773 if (!pkts_n) 774 return rcvd_pkt; 775 /* At this point, there shouldn't be any remained packets. */ 776 assert(rxq->rq_pi == rxq->cq_ci); 777 /* 778 * Note that vectors have reverse order - {v3, v2, v1, v0}, because 779 * there's no instruction to count trailing zeros. __builtin_clzl() is 780 * used instead. 781 * 782 * A. copy 4 mbuf pointers from elts ring to returing pkts. 783 * B. load 64B CQE and extract necessary fields 784 * Final 16bytes cqes[] extracted from original 64bytes CQE has the 785 * following structure: 786 * struct { 787 * uint16_t hdr_type_etc; 788 * uint8_t pkt_info; 789 * uint8_t rsvd; 790 * uint16_t byte_cnt; 791 * uint16_t vlan_info; 792 * uint32_t rx_has_res; 793 * uint8_t flow_tag[3]; 794 * uint8_t op_own; 795 * } c; 796 * C. fill in mbuf. 797 * D. get valid CQEs. 798 * E. find compressed CQE. 799 */ 800 for (pos = 0; 801 pos < pkts_n; 802 pos += MLX5_VPMD_DESCS_PER_LOOP) { 803 uint16x4_t op_own; 804 uint16x4_t opcode, owner_mask, invalid_mask; 805 uint16x4_t comp_mask; 806 uint16x4_t mask; 807 uint16x4_t byte_cnt; 808 uint32x4_t ptype_info, flow_tag; 809 uint8_t *p0, *p1, *p2, *p3; 810 uint8_t *e0 = (void *)&elts[pos]->pkt_len; 811 uint8_t *e1 = (void *)&elts[pos + 1]->pkt_len; 812 uint8_t *e2 = (void *)&elts[pos + 2]->pkt_len; 813 uint8_t *e3 = (void *)&elts[pos + 3]->pkt_len; 814 void *elts_p = (void *)&elts[pos]; 815 void *pkts_p = (void *)&pkts[pos]; 816 817 /* A.0 do not cross the end of CQ. */ 818 mask = vcreate_u16(pkts_n - pos < MLX5_VPMD_DESCS_PER_LOOP ? 819 -1UL >> ((pkts_n - pos) * 820 sizeof(uint16_t) * 8) : 0); 821 p0 = (void *)&cq[pos].pkt_info; 822 p1 = p0 + (pkts_n - pos > 1) * sizeof(struct mlx5_cqe); 823 p2 = p1 + (pkts_n - pos > 2) * sizeof(struct mlx5_cqe); 824 p3 = p2 + (pkts_n - pos > 3) * sizeof(struct mlx5_cqe); 825 /* Prefetch next 4 CQEs. */ 826 if (pkts_n - pos >= 2 * MLX5_VPMD_DESCS_PER_LOOP) { 827 unsigned int next = pos + MLX5_VPMD_DESCS_PER_LOOP; 828 rte_prefetch_non_temporal(&cq[next]); 829 rte_prefetch_non_temporal(&cq[next + 1]); 830 rte_prefetch_non_temporal(&cq[next + 2]); 831 rte_prefetch_non_temporal(&cq[next + 3]); 832 } 833 __asm__ volatile ( 834 /* B.1 (CQE 3) load a block having op_own. */ 835 "ld1 {v19.16b}, [%[p3]] \n\t" 836 "sub %[p3], %[p3], #48 \n\t" 837 /* B.2 (CQE 3) load the rest blocks. */ 838 "ld1 {v16.16b - v18.16b}, [%[p3]] \n\t" 839 /* B.3 (CQE 3) extract 16B fields. */ 840 "tbl v23.16b, {v16.16b - v19.16b}, %[cqe_shuf_m].16b \n\t" 841 /* B.4 (CQE 3) adjust CRC length. */ 842 "sub v23.8h, v23.8h, %[crc_adj].8h \n\t" 843 /* B.1 (CQE 2) load a block having op_own. */ 844 "ld1 {v19.16b}, [%[p2]] \n\t" 845 "sub %[p2], %[p2], #48 \n\t" 846 /* C.1 (CQE 3) generate final structure for mbuf. */ 847 "tbl v15.16b, {v23.16b}, %[mb_shuf_m].16b \n\t" 848 /* B.2 (CQE 2) load the rest blocks. */ 849 "ld1 {v16.16b - v18.16b}, [%[p2]] \n\t" 850 /* B.3 (CQE 2) extract 16B fields. */ 851 "tbl v22.16b, {v16.16b - v19.16b}, %[cqe_shuf_m].16b \n\t" 852 /* B.4 (CQE 2) adjust CRC length. */ 853 "sub v22.8h, v22.8h, %[crc_adj].8h \n\t" 854 /* B.1 (CQE 1) load a block having op_own. */ 855 "ld1 {v19.16b}, [%[p1]] \n\t" 856 "sub %[p1], %[p1], #48 \n\t" 857 /* C.1 (CQE 2) generate final structure for mbuf. */ 858 "tbl v14.16b, {v22.16b}, %[mb_shuf_m].16b \n\t" 859 /* B.2 (CQE 1) load the rest blocks. */ 860 "ld1 {v16.16b - v18.16b}, [%[p1]] \n\t" 861 /* B.3 (CQE 1) extract 16B fields. */ 862 "tbl v21.16b, {v16.16b - v19.16b}, %[cqe_shuf_m].16b \n\t" 863 /* B.4 (CQE 1) adjust CRC length. */ 864 "sub v21.8h, v21.8h, %[crc_adj].8h \n\t" 865 /* B.1 (CQE 0) load a block having op_own. */ 866 "ld1 {v19.16b}, [%[p0]] \n\t" 867 "sub %[p0], %[p0], #48 \n\t" 868 /* C.1 (CQE 1) generate final structure for mbuf. */ 869 "tbl v13.16b, {v21.16b}, %[mb_shuf_m].16b \n\t" 870 /* B.2 (CQE 0) load the rest blocks. */ 871 "ld1 {v16.16b - v18.16b}, [%[p0]] \n\t" 872 /* B.3 (CQE 0) extract 16B fields. */ 873 "tbl v20.16b, {v16.16b - v19.16b}, %[cqe_shuf_m].16b \n\t" 874 /* B.4 (CQE 0) adjust CRC length. */ 875 "sub v20.8h, v20.8h, %[crc_adj].8h \n\t" 876 /* A.1 load mbuf pointers. */ 877 "ld1 {v24.2d - v25.2d}, [%[elts_p]] \n\t" 878 /* D.1 extract op_own byte. */ 879 "tbl %[op_own].8b, {v20.16b - v23.16b}, %[owner_shuf_m].8b \n\t" 880 /* C.2 (CQE 3) adjust flow mark. */ 881 "add v15.4s, v15.4s, %[flow_mark_adj].4s \n\t" 882 /* C.3 (CQE 3) fill in mbuf - rx_descriptor_fields1. */ 883 "st1 {v15.2d}, [%[e3]] \n\t" 884 /* C.2 (CQE 2) adjust flow mark. */ 885 "add v14.4s, v14.4s, %[flow_mark_adj].4s \n\t" 886 /* C.3 (CQE 2) fill in mbuf - rx_descriptor_fields1. */ 887 "st1 {v14.2d}, [%[e2]] \n\t" 888 /* C.1 (CQE 0) generate final structure for mbuf. */ 889 "tbl v12.16b, {v20.16b}, %[mb_shuf_m].16b \n\t" 890 /* C.2 (CQE 1) adjust flow mark. */ 891 "add v13.4s, v13.4s, %[flow_mark_adj].4s \n\t" 892 /* C.3 (CQE 1) fill in mbuf - rx_descriptor_fields1. */ 893 "st1 {v13.2d}, [%[e1]] \n\t" 894 #ifdef MLX5_PMD_SOFT_COUNTERS 895 /* Extract byte_cnt. */ 896 "tbl %[byte_cnt].8b, {v20.16b - v23.16b}, %[len_shuf_m].8b \n\t" 897 #endif 898 /* Extract ptype_info. */ 899 "tbl %[ptype_info].16b, {v20.16b - v23.16b}, %[ptype_shuf_m].16b \n\t" 900 /* Extract flow_tag. */ 901 "tbl %[flow_tag].16b, {v20.16b - v23.16b}, %[ftag_shuf_m].16b \n\t" 902 /* A.2 copy mbuf pointers. */ 903 "st1 {v24.2d - v25.2d}, [%[pkts_p]] \n\t" 904 /* C.2 (CQE 0) adjust flow mark. */ 905 "add v12.4s, v12.4s, %[flow_mark_adj].4s \n\t" 906 /* C.3 (CQE 1) fill in mbuf - rx_descriptor_fields1. */ 907 "st1 {v12.2d}, [%[e0]] \n\t" 908 :[op_own]"=&w"(op_own), 909 [byte_cnt]"=&w"(byte_cnt), 910 [ptype_info]"=&w"(ptype_info), 911 [flow_tag]"=&w"(flow_tag) 912 :[p3]"r"(p3 + 48), [p2]"r"(p2 + 48), 913 [p1]"r"(p1 + 48), [p0]"r"(p0 + 48), 914 [e3]"r"(e3), [e2]"r"(e2), [e1]"r"(e1), [e0]"r"(e0), 915 [elts_p]"r"(elts_p), 916 [pkts_p]"r"(pkts_p), 917 [cqe_shuf_m]"w"(cqe_shuf_m), 918 [mb_shuf_m]"w"(mb_shuf_m), 919 [owner_shuf_m]"w"(owner_shuf_m), 920 [len_shuf_m]"w"(len_shuf_m), 921 [ptype_shuf_m]"w"(ptype_shuf_m), 922 [ftag_shuf_m]"w"(ftag_shuf_m), 923 [crc_adj]"w"(crc_adj), 924 [flow_mark_adj]"w"(flow_mark_adj) 925 :"memory", 926 "v12", "v13", "v14", "v15", 927 "v16", "v17", "v18", "v19", 928 "v20", "v21", "v22", "v23", 929 "v24", "v25"); 930 /* D.2 flip owner bit to mark CQEs from last round. */ 931 owner_mask = vand_u16(op_own, owner_check); 932 owner_mask = vceq_u16(owner_mask, ownership); 933 /* D.3 get mask for invalidated CQEs. */ 934 opcode = vand_u16(op_own, opcode_check); 935 invalid_mask = vceq_u16(opcode_check, opcode); 936 /* E.1 find compressed CQE format. */ 937 comp_mask = vand_u16(op_own, format_check); 938 comp_mask = vceq_u16(comp_mask, format_check); 939 /* D.4 mask out beyond boundary. */ 940 invalid_mask = vorr_u16(invalid_mask, mask); 941 /* D.5 merge invalid_mask with invalid owner. */ 942 invalid_mask = vorr_u16(invalid_mask, owner_mask); 943 /* E.2 mask out invalid entries. */ 944 comp_mask = vbic_u16(comp_mask, invalid_mask); 945 /* E.3 get the first compressed CQE. */ 946 comp_idx = __builtin_clzl(vget_lane_u64(vreinterpret_u64_u16( 947 comp_mask), 0)) / 948 (sizeof(uint16_t) * 8); 949 /* D.6 mask out entries after the compressed CQE. */ 950 mask = vcreate_u16(comp_idx < MLX5_VPMD_DESCS_PER_LOOP ? 951 -1UL >> (comp_idx * sizeof(uint16_t) * 8) : 952 0); 953 invalid_mask = vorr_u16(invalid_mask, mask); 954 /* D.7 count non-compressed valid CQEs. */ 955 n = __builtin_clzl(vget_lane_u64(vreinterpret_u64_u16( 956 invalid_mask), 0)) / (sizeof(uint16_t) * 8); 957 nocmp_n += n; 958 /* D.2 get the final invalid mask. */ 959 mask = vcreate_u16(n < MLX5_VPMD_DESCS_PER_LOOP ? 960 -1UL >> (n * sizeof(uint16_t) * 8) : 0); 961 invalid_mask = vorr_u16(invalid_mask, mask); 962 /* D.3 check error in opcode. */ 963 opcode = vceq_u16(resp_err_check, opcode); 964 opcode = vbic_u16(opcode, invalid_mask); 965 /* D.4 mark if any error is set */ 966 rxq->pending_err |= 967 !!vget_lane_u64(vreinterpret_u64_u16(opcode), 0); 968 /* C.4 fill in mbuf - rearm_data and packet_type. */ 969 rxq_cq_to_ptype_oflags_v(rxq, ptype_info, flow_tag, 970 opcode, &elts[pos]); 971 if (rxq->hw_timestamp) { 972 elts[pos]->timestamp = 973 rte_be_to_cpu_64( 974 container_of(p0, struct mlx5_cqe, 975 pkt_info)->timestamp); 976 elts[pos + 1]->timestamp = 977 rte_be_to_cpu_64( 978 container_of(p1, struct mlx5_cqe, 979 pkt_info)->timestamp); 980 elts[pos + 2]->timestamp = 981 rte_be_to_cpu_64( 982 container_of(p2, struct mlx5_cqe, 983 pkt_info)->timestamp); 984 elts[pos + 3]->timestamp = 985 rte_be_to_cpu_64( 986 container_of(p3, struct mlx5_cqe, 987 pkt_info)->timestamp); 988 } 989 #ifdef MLX5_PMD_SOFT_COUNTERS 990 /* Add up received bytes count. */ 991 byte_cnt = vbic_u16(byte_cnt, invalid_mask); 992 rcvd_byte += vget_lane_u64(vpaddl_u32(vpaddl_u16(byte_cnt)), 0); 993 #endif 994 /* 995 * Break the loop unless more valid CQE is expected, or if 996 * there's a compressed CQE. 997 */ 998 if (n != MLX5_VPMD_DESCS_PER_LOOP) 999 break; 1000 } 1001 /* If no new CQE seen, return without updating cq_db. */ 1002 if (unlikely(!nocmp_n && comp_idx == MLX5_VPMD_DESCS_PER_LOOP)) 1003 return rcvd_pkt; 1004 /* Update the consumer indexes for non-compressed CQEs. */ 1005 assert(nocmp_n <= pkts_n); 1006 rxq->cq_ci += nocmp_n; 1007 rxq->rq_pi += nocmp_n; 1008 rcvd_pkt += nocmp_n; 1009 #ifdef MLX5_PMD_SOFT_COUNTERS 1010 rxq->stats.ipackets += nocmp_n; 1011 rxq->stats.ibytes += rcvd_byte; 1012 #endif 1013 /* Decompress the last CQE if compressed. */ 1014 if (comp_idx < MLX5_VPMD_DESCS_PER_LOOP && comp_idx == n) { 1015 assert(comp_idx == (nocmp_n % MLX5_VPMD_DESCS_PER_LOOP)); 1016 rxq_cq_decompress_v(rxq, &cq[nocmp_n], &elts[nocmp_n]); 1017 /* Return more packets if needed. */ 1018 if (nocmp_n < pkts_n) { 1019 uint16_t n = rxq->cq_ci - rxq->rq_pi; 1020 1021 n = RTE_MIN(n, pkts_n - nocmp_n); 1022 rxq_copy_mbuf_v(rxq, &pkts[nocmp_n], n); 1023 rxq->rq_pi += n; 1024 rcvd_pkt += n; 1025 } 1026 } 1027 rte_compiler_barrier(); 1028 *rxq->cq_db = rte_cpu_to_be_32(rxq->cq_ci); 1029 return rcvd_pkt; 1030 } 1031 1032 #endif /* RTE_PMD_MLX5_RXTX_VEC_NEON_H_ */ 1033