1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2017 6WIND S.A. 3 * Copyright 2017 Mellanox Technologies, Ltd 4 */ 5 6 #ifndef RTE_PMD_MLX5_RXTX_VEC_NEON_H_ 7 #define RTE_PMD_MLX5_RXTX_VEC_NEON_H_ 8 9 #include <stdint.h> 10 #include <string.h> 11 #include <stdlib.h> 12 #include <arm_neon.h> 13 14 #include <rte_mbuf.h> 15 #include <rte_mempool.h> 16 #include <rte_prefetch.h> 17 18 #include <mlx5_prm.h> 19 20 #include "mlx5_defs.h" 21 #include "mlx5.h" 22 #include "mlx5_utils.h" 23 #include "mlx5_rxtx.h" 24 #include "mlx5_rxtx_vec.h" 25 #include "mlx5_autoconf.h" 26 27 #pragma GCC diagnostic ignored "-Wcast-qual" 28 29 /** 30 * Store free buffers to RX SW ring. 31 * 32 * @param rxq 33 * Pointer to RX queue structure. 34 * @param pkts 35 * Pointer to array of packets to be stored. 36 * @param pkts_n 37 * Number of packets to be stored. 38 */ 39 static inline void 40 rxq_copy_mbuf_v(struct mlx5_rxq_data *rxq, struct rte_mbuf **pkts, uint16_t n) 41 { 42 const uint16_t q_mask = (1 << rxq->elts_n) - 1; 43 struct rte_mbuf **elts = &(*rxq->elts)[rxq->rq_pi & q_mask]; 44 unsigned int pos; 45 uint16_t p = n & -2; 46 47 for (pos = 0; pos < p; pos += 2) { 48 uint64x2_t mbp; 49 50 mbp = vld1q_u64((void *)&elts[pos]); 51 vst1q_u64((void *)&pkts[pos], mbp); 52 } 53 if (n & 1) 54 pkts[pos] = elts[pos]; 55 } 56 57 /** 58 * Decompress a compressed completion and fill in mbufs in RX SW ring with data 59 * extracted from the title completion descriptor. 60 * 61 * @param rxq 62 * Pointer to RX queue structure. 63 * @param cq 64 * Pointer to completion array having a compressed completion at first. 65 * @param elts 66 * Pointer to SW ring to be filled. The first mbuf has to be pre-built from 67 * the title completion descriptor to be copied to the rest of mbufs. 68 * 69 * @return 70 * Number of mini-CQEs successfully decompressed. 71 */ 72 static inline uint16_t 73 rxq_cq_decompress_v(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cq, 74 struct rte_mbuf **elts) 75 { 76 volatile struct mlx5_mini_cqe8 *mcq = (void *)&(cq + 1)->pkt_info; 77 struct rte_mbuf *t_pkt = elts[0]; /* Title packet is pre-built. */ 78 unsigned int pos; 79 unsigned int i; 80 unsigned int inv = 0; 81 /* Mask to shuffle from extracted mini CQE to mbuf. */ 82 const uint8x16_t mcqe_shuf_m1 = { 83 -1, -1, -1, -1, /* skip packet_type */ 84 7, 6, -1, -1, /* pkt_len, bswap16 */ 85 7, 6, /* data_len, bswap16 */ 86 -1, -1, /* skip vlan_tci */ 87 3, 2, 1, 0 /* hash.rss, bswap32 */ 88 }; 89 const uint8x16_t mcqe_shuf_m2 = { 90 -1, -1, -1, -1, /* skip packet_type */ 91 15, 14, -1, -1, /* pkt_len, bswap16 */ 92 15, 14, /* data_len, bswap16 */ 93 -1, -1, /* skip vlan_tci */ 94 11, 10, 9, 8 /* hash.rss, bswap32 */ 95 }; 96 /* Restore the compressed count. Must be 16 bits. */ 97 const uint16_t mcqe_n = t_pkt->data_len + 98 (rxq->crc_present * RTE_ETHER_CRC_LEN); 99 const uint64x2_t rearm = 100 vld1q_u64((void *)&t_pkt->rearm_data); 101 const uint32x4_t rxdf_mask = { 102 0xffffffff, /* packet_type */ 103 0, /* skip pkt_len */ 104 0xffff0000, /* vlan_tci, skip data_len */ 105 0, /* skip hash.rss */ 106 }; 107 const uint8x16_t rxdf = 108 vandq_u8(vld1q_u8((void *)&t_pkt->rx_descriptor_fields1), 109 vreinterpretq_u8_u32(rxdf_mask)); 110 const uint16x8_t crc_adj = { 111 0, 0, 112 rxq->crc_present * RTE_ETHER_CRC_LEN, 0, 113 rxq->crc_present * RTE_ETHER_CRC_LEN, 0, 114 0, 0 115 }; 116 const uint32_t flow_tag = t_pkt->hash.fdir.hi; 117 #ifdef MLX5_PMD_SOFT_COUNTERS 118 uint32_t rcvd_byte = 0; 119 #endif 120 /* Mask to shuffle byte_cnt to add up stats. Do bswap16 for all. */ 121 const uint8x8_t len_shuf_m = { 122 7, 6, /* 1st mCQE */ 123 15, 14, /* 2nd mCQE */ 124 23, 22, /* 3rd mCQE */ 125 31, 30 /* 4th mCQE */ 126 }; 127 128 /* 129 * A. load mCQEs into a 128bit register. 130 * B. store rearm data to mbuf. 131 * C. combine data from mCQEs with rx_descriptor_fields1. 132 * D. store rx_descriptor_fields1. 133 * E. store flow tag (rte_flow mark). 134 */ 135 for (pos = 0; pos < mcqe_n; ) { 136 uint8_t *p = (void *)&mcq[pos % 8]; 137 uint8_t *e0 = (void *)&elts[pos]->rearm_data; 138 uint8_t *e1 = (void *)&elts[pos + 1]->rearm_data; 139 uint8_t *e2 = (void *)&elts[pos + 2]->rearm_data; 140 uint8_t *e3 = (void *)&elts[pos + 3]->rearm_data; 141 uint16x4_t byte_cnt; 142 #ifdef MLX5_PMD_SOFT_COUNTERS 143 uint16x4_t invalid_mask = 144 vcreate_u16(mcqe_n - pos < MLX5_VPMD_DESCS_PER_LOOP ? 145 -1UL << ((mcqe_n - pos) * 146 sizeof(uint16_t) * 8) : 0); 147 #endif 148 149 for (i = 0; i < MLX5_VPMD_DESCS_PER_LOOP; ++i) 150 if (likely(pos + i < mcqe_n)) 151 rte_prefetch0((void *)(cq + pos + i)); 152 __asm__ volatile ( 153 /* A.1 load mCQEs into a 128bit register. */ 154 "ld1 {v16.16b - v17.16b}, [%[mcq]] \n\t" 155 /* B.1 store rearm data to mbuf. */ 156 "st1 {%[rearm].2d}, [%[e0]] \n\t" 157 "add %[e0], %[e0], #16 \n\t" 158 "st1 {%[rearm].2d}, [%[e1]] \n\t" 159 "add %[e1], %[e1], #16 \n\t" 160 /* C.1 combine data from mCQEs with rx_descriptor_fields1. */ 161 "tbl v18.16b, {v16.16b}, %[mcqe_shuf_m1].16b \n\t" 162 "tbl v19.16b, {v16.16b}, %[mcqe_shuf_m2].16b \n\t" 163 "sub v18.8h, v18.8h, %[crc_adj].8h \n\t" 164 "sub v19.8h, v19.8h, %[crc_adj].8h \n\t" 165 "orr v18.16b, v18.16b, %[rxdf].16b \n\t" 166 "orr v19.16b, v19.16b, %[rxdf].16b \n\t" 167 /* D.1 store rx_descriptor_fields1. */ 168 "st1 {v18.2d}, [%[e0]] \n\t" 169 "st1 {v19.2d}, [%[e1]] \n\t" 170 /* B.1 store rearm data to mbuf. */ 171 "st1 {%[rearm].2d}, [%[e2]] \n\t" 172 "add %[e2], %[e2], #16 \n\t" 173 "st1 {%[rearm].2d}, [%[e3]] \n\t" 174 "add %[e3], %[e3], #16 \n\t" 175 /* C.1 combine data from mCQEs with rx_descriptor_fields1. */ 176 "tbl v18.16b, {v17.16b}, %[mcqe_shuf_m1].16b \n\t" 177 "tbl v19.16b, {v17.16b}, %[mcqe_shuf_m2].16b \n\t" 178 "sub v18.8h, v18.8h, %[crc_adj].8h \n\t" 179 "sub v19.8h, v19.8h, %[crc_adj].8h \n\t" 180 "orr v18.16b, v18.16b, %[rxdf].16b \n\t" 181 "orr v19.16b, v19.16b, %[rxdf].16b \n\t" 182 /* D.1 store rx_descriptor_fields1. */ 183 "st1 {v18.2d}, [%[e2]] \n\t" 184 "st1 {v19.2d}, [%[e3]] \n\t" 185 #ifdef MLX5_PMD_SOFT_COUNTERS 186 "tbl %[byte_cnt].8b, {v16.16b - v17.16b}, %[len_shuf_m].8b \n\t" 187 #endif 188 :[byte_cnt]"=&w"(byte_cnt) 189 :[mcq]"r"(p), 190 [rxdf]"w"(rxdf), 191 [rearm]"w"(rearm), 192 [e3]"r"(e3), [e2]"r"(e2), [e1]"r"(e1), [e0]"r"(e0), 193 [mcqe_shuf_m1]"w"(mcqe_shuf_m1), 194 [mcqe_shuf_m2]"w"(mcqe_shuf_m2), 195 [crc_adj]"w"(crc_adj), 196 [len_shuf_m]"w"(len_shuf_m) 197 :"memory", "v16", "v17", "v18", "v19"); 198 #ifdef MLX5_PMD_SOFT_COUNTERS 199 byte_cnt = vbic_u16(byte_cnt, invalid_mask); 200 rcvd_byte += vget_lane_u64(vpaddl_u32(vpaddl_u16(byte_cnt)), 0); 201 #endif 202 if (rxq->mark) { 203 /* E.1 store flow tag (rte_flow mark). */ 204 elts[pos]->hash.fdir.hi = flow_tag; 205 elts[pos + 1]->hash.fdir.hi = flow_tag; 206 elts[pos + 2]->hash.fdir.hi = flow_tag; 207 elts[pos + 3]->hash.fdir.hi = flow_tag; 208 } 209 if (rxq->dynf_meta) { 210 int32_t offs = rxq->flow_meta_offset; 211 const uint32_t meta = 212 *RTE_MBUF_DYNFIELD(t_pkt, offs, uint32_t *); 213 214 /* Check if title packet has valid metadata. */ 215 if (meta) { 216 MLX5_ASSERT(t_pkt->ol_flags & 217 rxq->flow_meta_mask); 218 *RTE_MBUF_DYNFIELD(elts[pos], offs, 219 uint32_t *) = meta; 220 *RTE_MBUF_DYNFIELD(elts[pos + 1], offs, 221 uint32_t *) = meta; 222 *RTE_MBUF_DYNFIELD(elts[pos + 2], offs, 223 uint32_t *) = meta; 224 *RTE_MBUF_DYNFIELD(elts[pos + 3], offs, 225 uint32_t *) = meta; 226 } 227 } 228 pos += MLX5_VPMD_DESCS_PER_LOOP; 229 /* Move to next CQE and invalidate consumed CQEs. */ 230 if (!(pos & 0x7) && pos < mcqe_n) { 231 if (pos + 8 < mcqe_n) 232 rte_prefetch0((void *)(cq + pos + 8)); 233 mcq = (void *)&(cq + pos)->pkt_info; 234 for (i = 0; i < 8; ++i) 235 cq[inv++].op_own = MLX5_CQE_INVALIDATE; 236 } 237 } 238 /* Invalidate the rest of CQEs. */ 239 for (; inv < mcqe_n; ++inv) 240 cq[inv].op_own = MLX5_CQE_INVALIDATE; 241 #ifdef MLX5_PMD_SOFT_COUNTERS 242 rxq->stats.ipackets += mcqe_n; 243 rxq->stats.ibytes += rcvd_byte; 244 #endif 245 rxq->cq_ci += mcqe_n; 246 return mcqe_n; 247 } 248 249 /** 250 * Calculate packet type and offload flag for mbuf and store it. 251 * 252 * @param rxq 253 * Pointer to RX queue structure. 254 * @param ptype_info 255 * Array of four 4bytes packet type info extracted from the original 256 * completion descriptor. 257 * @param flow_tag 258 * Array of four 4bytes flow ID extracted from the original completion 259 * descriptor. 260 * @param op_err 261 * Opcode vector having responder error status. Each field is 4B. 262 * @param pkts 263 * Pointer to array of packets to be filled. 264 */ 265 static inline void 266 rxq_cq_to_ptype_oflags_v(struct mlx5_rxq_data *rxq, 267 uint32x4_t ptype_info, uint32x4_t flow_tag, 268 uint16x4_t op_err, struct rte_mbuf **pkts) 269 { 270 uint16x4_t ptype; 271 uint32x4_t pinfo, cv_flags; 272 uint32x4_t ol_flags = 273 vdupq_n_u32(rxq->rss_hash * PKT_RX_RSS_HASH | 274 rxq->hw_timestamp * PKT_RX_TIMESTAMP); 275 const uint32x4_t ptype_ol_mask = { 0x106, 0x106, 0x106, 0x106 }; 276 const uint8x16_t cv_flag_sel = { 277 0, 278 (uint8_t)(PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED), 279 (uint8_t)(PKT_RX_IP_CKSUM_GOOD >> 1), 280 0, 281 (uint8_t)(PKT_RX_L4_CKSUM_GOOD >> 1), 282 0, 283 (uint8_t)((PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD) >> 1), 284 0, 0, 0, 0, 0, 0, 0, 0, 0 285 }; 286 const uint32x4_t cv_mask = 287 vdupq_n_u32(PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD | 288 PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED); 289 const uint64x2_t mbuf_init = vld1q_u64 290 ((const uint64_t *)&rxq->mbuf_initializer); 291 uint64x2_t rearm0, rearm1, rearm2, rearm3; 292 uint8_t pt_idx0, pt_idx1, pt_idx2, pt_idx3; 293 294 if (rxq->mark) { 295 const uint32x4_t ft_def = vdupq_n_u32(MLX5_FLOW_MARK_DEFAULT); 296 const uint32x4_t fdir_flags = vdupq_n_u32(PKT_RX_FDIR); 297 uint32x4_t fdir_id_flags = vdupq_n_u32(PKT_RX_FDIR_ID); 298 uint32x4_t invalid_mask; 299 300 /* Check if flow tag is non-zero then set PKT_RX_FDIR. */ 301 invalid_mask = vceqzq_u32(flow_tag); 302 ol_flags = vorrq_u32(ol_flags, 303 vbicq_u32(fdir_flags, invalid_mask)); 304 /* Mask out invalid entries. */ 305 fdir_id_flags = vbicq_u32(fdir_id_flags, invalid_mask); 306 /* Check if flow tag MLX5_FLOW_MARK_DEFAULT. */ 307 ol_flags = vorrq_u32(ol_flags, 308 vbicq_u32(fdir_id_flags, 309 vceqq_u32(flow_tag, ft_def))); 310 } 311 /* 312 * ptype_info has the following: 313 * bit[1] = l3_ok 314 * bit[2] = l4_ok 315 * bit[8] = cv 316 * bit[11:10] = l3_hdr_type 317 * bit[14:12] = l4_hdr_type 318 * bit[15] = ip_frag 319 * bit[16] = tunneled 320 * bit[17] = outer_l3_type 321 */ 322 ptype = vshrn_n_u32(ptype_info, 10); 323 /* Errored packets will have RTE_PTYPE_ALL_MASK. */ 324 ptype = vorr_u16(ptype, op_err); 325 pt_idx0 = vget_lane_u8(vreinterpret_u8_u16(ptype), 6); 326 pt_idx1 = vget_lane_u8(vreinterpret_u8_u16(ptype), 4); 327 pt_idx2 = vget_lane_u8(vreinterpret_u8_u16(ptype), 2); 328 pt_idx3 = vget_lane_u8(vreinterpret_u8_u16(ptype), 0); 329 pkts[0]->packet_type = mlx5_ptype_table[pt_idx0] | 330 !!(pt_idx0 & (1 << 6)) * rxq->tunnel; 331 pkts[1]->packet_type = mlx5_ptype_table[pt_idx1] | 332 !!(pt_idx1 & (1 << 6)) * rxq->tunnel; 333 pkts[2]->packet_type = mlx5_ptype_table[pt_idx2] | 334 !!(pt_idx2 & (1 << 6)) * rxq->tunnel; 335 pkts[3]->packet_type = mlx5_ptype_table[pt_idx3] | 336 !!(pt_idx3 & (1 << 6)) * rxq->tunnel; 337 /* Fill flags for checksum and VLAN. */ 338 pinfo = vandq_u32(ptype_info, ptype_ol_mask); 339 pinfo = vreinterpretq_u32_u8( 340 vqtbl1q_u8(cv_flag_sel, vreinterpretq_u8_u32(pinfo))); 341 /* Locate checksum flags at byte[2:1] and merge with VLAN flags. */ 342 cv_flags = vshlq_n_u32(pinfo, 9); 343 cv_flags = vorrq_u32(pinfo, cv_flags); 344 /* Move back flags to start from byte[0]. */ 345 cv_flags = vshrq_n_u32(cv_flags, 8); 346 /* Mask out garbage bits. */ 347 cv_flags = vandq_u32(cv_flags, cv_mask); 348 /* Merge to ol_flags. */ 349 ol_flags = vorrq_u32(ol_flags, cv_flags); 350 /* Merge mbuf_init and ol_flags, and store. */ 351 rearm0 = vreinterpretq_u64_u32(vsetq_lane_u32 352 (vgetq_lane_u32(ol_flags, 3), 353 vreinterpretq_u32_u64(mbuf_init), 2)); 354 rearm1 = vreinterpretq_u64_u32(vsetq_lane_u32 355 (vgetq_lane_u32(ol_flags, 2), 356 vreinterpretq_u32_u64(mbuf_init), 2)); 357 rearm2 = vreinterpretq_u64_u32(vsetq_lane_u32 358 (vgetq_lane_u32(ol_flags, 1), 359 vreinterpretq_u32_u64(mbuf_init), 2)); 360 rearm3 = vreinterpretq_u64_u32(vsetq_lane_u32 361 (vgetq_lane_u32(ol_flags, 0), 362 vreinterpretq_u32_u64(mbuf_init), 2)); 363 364 vst1q_u64((void *)&pkts[0]->rearm_data, rearm0); 365 vst1q_u64((void *)&pkts[1]->rearm_data, rearm1); 366 vst1q_u64((void *)&pkts[2]->rearm_data, rearm2); 367 vst1q_u64((void *)&pkts[3]->rearm_data, rearm3); 368 } 369 370 /** 371 * Receive burst of packets. An errored completion also consumes a mbuf, but the 372 * packet_type is set to be RTE_PTYPE_ALL_MASK. Marked mbufs should be freed 373 * before returning to application. 374 * 375 * @param rxq 376 * Pointer to RX queue structure. 377 * @param[out] pkts 378 * Array to store received packets. 379 * @param pkts_n 380 * Maximum number of packets in array. 381 * @param[out] err 382 * Pointer to a flag. Set non-zero value if pkts array has at least one error 383 * packet to handle. 384 * @param[out] no_cq 385 * Pointer to a boolean. Set true if no new CQE seen. 386 * 387 * @return 388 * Number of packets received including errors (<= pkts_n). 389 */ 390 static inline uint16_t 391 rxq_burst_v(struct mlx5_rxq_data *rxq, struct rte_mbuf **pkts, uint16_t pkts_n, 392 uint64_t *err, bool *no_cq) 393 { 394 const uint16_t q_n = 1 << rxq->cqe_n; 395 const uint16_t q_mask = q_n - 1; 396 volatile struct mlx5_cqe *cq; 397 struct rte_mbuf **elts; 398 unsigned int pos; 399 uint64_t n; 400 uint16_t repl_n; 401 uint64_t comp_idx = MLX5_VPMD_DESCS_PER_LOOP; 402 uint16_t nocmp_n = 0; 403 uint16_t rcvd_pkt = 0; 404 unsigned int cq_idx = rxq->cq_ci & q_mask; 405 unsigned int elts_idx; 406 const uint16x4_t ownership = vdup_n_u16(!(rxq->cq_ci & (q_mask + 1))); 407 const uint16x4_t owner_check = vcreate_u16(0x0001000100010001); 408 const uint16x4_t opcode_check = vcreate_u16(0x00f000f000f000f0); 409 const uint16x4_t format_check = vcreate_u16(0x000c000c000c000c); 410 const uint16x4_t resp_err_check = vcreate_u16(0x00e000e000e000e0); 411 #ifdef MLX5_PMD_SOFT_COUNTERS 412 uint32_t rcvd_byte = 0; 413 #endif 414 /* Mask to generate 16B length vector. */ 415 const uint8x8_t len_shuf_m = { 416 52, 53, /* 4th CQE */ 417 36, 37, /* 3rd CQE */ 418 20, 21, /* 2nd CQE */ 419 4, 5 /* 1st CQE */ 420 }; 421 /* Mask to extract 16B data from a 64B CQE. */ 422 const uint8x16_t cqe_shuf_m = { 423 28, 29, /* hdr_type_etc */ 424 0, /* pkt_info */ 425 -1, /* null */ 426 47, 46, /* byte_cnt, bswap16 */ 427 31, 30, /* vlan_info, bswap16 */ 428 15, 14, 13, 12, /* rx_hash_res, bswap32 */ 429 57, 58, 59, /* flow_tag */ 430 63 /* op_own */ 431 }; 432 /* Mask to generate 16B data for mbuf. */ 433 const uint8x16_t mb_shuf_m = { 434 4, 5, -1, -1, /* pkt_len */ 435 4, 5, /* data_len */ 436 6, 7, /* vlan_tci */ 437 8, 9, 10, 11, /* hash.rss */ 438 12, 13, 14, -1 /* hash.fdir.hi */ 439 }; 440 /* Mask to generate 16B owner vector. */ 441 const uint8x8_t owner_shuf_m = { 442 63, -1, /* 4th CQE */ 443 47, -1, /* 3rd CQE */ 444 31, -1, /* 2nd CQE */ 445 15, -1 /* 1st CQE */ 446 }; 447 /* Mask to generate a vector having packet_type/ol_flags. */ 448 const uint8x16_t ptype_shuf_m = { 449 48, 49, 50, -1, /* 4th CQE */ 450 32, 33, 34, -1, /* 3rd CQE */ 451 16, 17, 18, -1, /* 2nd CQE */ 452 0, 1, 2, -1 /* 1st CQE */ 453 }; 454 /* Mask to generate a vector having flow tags. */ 455 const uint8x16_t ftag_shuf_m = { 456 60, 61, 62, -1, /* 4th CQE */ 457 44, 45, 46, -1, /* 3rd CQE */ 458 28, 29, 30, -1, /* 2nd CQE */ 459 12, 13, 14, -1 /* 1st CQE */ 460 }; 461 const uint16x8_t crc_adj = { 462 0, 0, rxq->crc_present * RTE_ETHER_CRC_LEN, 0, 0, 0, 0, 0 463 }; 464 const uint32x4_t flow_mark_adj = { 0, 0, 0, rxq->mark * (-1) }; 465 466 MLX5_ASSERT(rxq->sges_n == 0); 467 MLX5_ASSERT(rxq->cqe_n == rxq->elts_n); 468 cq = &(*rxq->cqes)[cq_idx]; 469 rte_prefetch_non_temporal(cq); 470 rte_prefetch_non_temporal(cq + 1); 471 rte_prefetch_non_temporal(cq + 2); 472 rte_prefetch_non_temporal(cq + 3); 473 pkts_n = RTE_MIN(pkts_n, MLX5_VPMD_RX_MAX_BURST); 474 repl_n = q_n - (rxq->rq_ci - rxq->rq_pi); 475 if (repl_n >= rxq->rq_repl_thresh) 476 mlx5_rx_replenish_bulk_mbuf(rxq, repl_n); 477 /* See if there're unreturned mbufs from compressed CQE. */ 478 rcvd_pkt = rxq->decompressed; 479 if (rcvd_pkt > 0) { 480 rcvd_pkt = RTE_MIN(rcvd_pkt, pkts_n); 481 rxq_copy_mbuf_v(rxq, pkts, rcvd_pkt); 482 rxq->rq_pi += rcvd_pkt; 483 pkts += rcvd_pkt; 484 rxq->decompressed -= rcvd_pkt; 485 } 486 elts_idx = rxq->rq_pi & q_mask; 487 elts = &(*rxq->elts)[elts_idx]; 488 /* Not to overflow pkts array. */ 489 pkts_n = RTE_ALIGN_FLOOR(pkts_n - rcvd_pkt, MLX5_VPMD_DESCS_PER_LOOP); 490 /* Not to cross queue end. */ 491 pkts_n = RTE_MIN(pkts_n, q_n - elts_idx); 492 pkts_n = RTE_MIN(pkts_n, q_n - cq_idx); 493 if (!pkts_n) { 494 *no_cq = !rcvd_pkt; 495 return rcvd_pkt; 496 } 497 /* At this point, there shouldn't be any remained packets. */ 498 MLX5_ASSERT(rxq->decompressed == 0); 499 /* 500 * Note that vectors have reverse order - {v3, v2, v1, v0}, because 501 * there's no instruction to count trailing zeros. __builtin_clzl() is 502 * used instead. 503 * 504 * A. copy 4 mbuf pointers from elts ring to returing pkts. 505 * B. load 64B CQE and extract necessary fields 506 * Final 16bytes cqes[] extracted from original 64bytes CQE has the 507 * following structure: 508 * struct { 509 * uint16_t hdr_type_etc; 510 * uint8_t pkt_info; 511 * uint8_t rsvd; 512 * uint16_t byte_cnt; 513 * uint16_t vlan_info; 514 * uint32_t rx_has_res; 515 * uint8_t flow_tag[3]; 516 * uint8_t op_own; 517 * } c; 518 * C. fill in mbuf. 519 * D. get valid CQEs. 520 * E. find compressed CQE. 521 */ 522 for (pos = 0; 523 pos < pkts_n; 524 pos += MLX5_VPMD_DESCS_PER_LOOP) { 525 uint16x4_t op_own; 526 uint16x4_t opcode, owner_mask, invalid_mask; 527 uint16x4_t comp_mask; 528 uint16x4_t mask; 529 uint16x4_t byte_cnt; 530 uint32x4_t ptype_info, flow_tag; 531 register uint64x2_t c0, c1, c2, c3; 532 uint8_t *p0, *p1, *p2, *p3; 533 uint8_t *e0 = (void *)&elts[pos]->pkt_len; 534 uint8_t *e1 = (void *)&elts[pos + 1]->pkt_len; 535 uint8_t *e2 = (void *)&elts[pos + 2]->pkt_len; 536 uint8_t *e3 = (void *)&elts[pos + 3]->pkt_len; 537 void *elts_p = (void *)&elts[pos]; 538 void *pkts_p = (void *)&pkts[pos]; 539 540 /* A.0 do not cross the end of CQ. */ 541 mask = vcreate_u16(pkts_n - pos < MLX5_VPMD_DESCS_PER_LOOP ? 542 -1UL >> ((pkts_n - pos) * 543 sizeof(uint16_t) * 8) : 0); 544 p0 = (void *)&cq[pos].pkt_info; 545 p1 = p0 + (pkts_n - pos > 1) * sizeof(struct mlx5_cqe); 546 p2 = p1 + (pkts_n - pos > 2) * sizeof(struct mlx5_cqe); 547 p3 = p2 + (pkts_n - pos > 3) * sizeof(struct mlx5_cqe); 548 /* B.0 (CQE 3) load a block having op_own. */ 549 c3 = vld1q_u64((uint64_t *)(p3 + 48)); 550 /* B.0 (CQE 2) load a block having op_own. */ 551 c2 = vld1q_u64((uint64_t *)(p2 + 48)); 552 /* B.0 (CQE 1) load a block having op_own. */ 553 c1 = vld1q_u64((uint64_t *)(p1 + 48)); 554 /* B.0 (CQE 0) load a block having op_own. */ 555 c0 = vld1q_u64((uint64_t *)(p0 + 48)); 556 /* Synchronize for loading the rest of blocks. */ 557 rte_cio_rmb(); 558 /* Prefetch next 4 CQEs. */ 559 if (pkts_n - pos >= 2 * MLX5_VPMD_DESCS_PER_LOOP) { 560 unsigned int next = pos + MLX5_VPMD_DESCS_PER_LOOP; 561 rte_prefetch_non_temporal(&cq[next]); 562 rte_prefetch_non_temporal(&cq[next + 1]); 563 rte_prefetch_non_temporal(&cq[next + 2]); 564 rte_prefetch_non_temporal(&cq[next + 3]); 565 } 566 __asm__ volatile ( 567 /* B.1 (CQE 3) load the rest of blocks. */ 568 "ld1 {v16.16b - v18.16b}, [%[p3]] \n\t" 569 /* B.2 (CQE 3) move the block having op_own. */ 570 "mov v19.16b, %[c3].16b \n\t" 571 /* B.3 (CQE 3) extract 16B fields. */ 572 "tbl v23.16b, {v16.16b - v19.16b}, %[cqe_shuf_m].16b \n\t" 573 /* B.1 (CQE 2) load the rest of blocks. */ 574 "ld1 {v16.16b - v18.16b}, [%[p2]] \n\t" 575 /* B.4 (CQE 3) adjust CRC length. */ 576 "sub v23.8h, v23.8h, %[crc_adj].8h \n\t" 577 /* C.1 (CQE 3) generate final structure for mbuf. */ 578 "tbl v15.16b, {v23.16b}, %[mb_shuf_m].16b \n\t" 579 /* B.2 (CQE 2) move the block having op_own. */ 580 "mov v19.16b, %[c2].16b \n\t" 581 /* B.3 (CQE 2) extract 16B fields. */ 582 "tbl v22.16b, {v16.16b - v19.16b}, %[cqe_shuf_m].16b \n\t" 583 /* B.1 (CQE 1) load the rest of blocks. */ 584 "ld1 {v16.16b - v18.16b}, [%[p1]] \n\t" 585 /* B.4 (CQE 2) adjust CRC length. */ 586 "sub v22.8h, v22.8h, %[crc_adj].8h \n\t" 587 /* C.1 (CQE 2) generate final structure for mbuf. */ 588 "tbl v14.16b, {v22.16b}, %[mb_shuf_m].16b \n\t" 589 /* B.2 (CQE 1) move the block having op_own. */ 590 "mov v19.16b, %[c1].16b \n\t" 591 /* B.3 (CQE 1) extract 16B fields. */ 592 "tbl v21.16b, {v16.16b - v19.16b}, %[cqe_shuf_m].16b \n\t" 593 /* B.1 (CQE 0) load the rest of blocks. */ 594 "ld1 {v16.16b - v18.16b}, [%[p0]] \n\t" 595 /* B.4 (CQE 1) adjust CRC length. */ 596 "sub v21.8h, v21.8h, %[crc_adj].8h \n\t" 597 /* C.1 (CQE 1) generate final structure for mbuf. */ 598 "tbl v13.16b, {v21.16b}, %[mb_shuf_m].16b \n\t" 599 /* B.2 (CQE 0) move the block having op_own. */ 600 "mov v19.16b, %[c0].16b \n\t" 601 /* A.1 load mbuf pointers. */ 602 "ld1 {v24.2d - v25.2d}, [%[elts_p]] \n\t" 603 /* B.3 (CQE 0) extract 16B fields. */ 604 "tbl v20.16b, {v16.16b - v19.16b}, %[cqe_shuf_m].16b \n\t" 605 /* B.4 (CQE 0) adjust CRC length. */ 606 "sub v20.8h, v20.8h, %[crc_adj].8h \n\t" 607 /* D.1 extract op_own byte. */ 608 "tbl %[op_own].8b, {v20.16b - v23.16b}, %[owner_shuf_m].8b \n\t" 609 /* C.2 (CQE 3) adjust flow mark. */ 610 "add v15.4s, v15.4s, %[flow_mark_adj].4s \n\t" 611 /* C.3 (CQE 3) fill in mbuf - rx_descriptor_fields1. */ 612 "st1 {v15.2d}, [%[e3]] \n\t" 613 /* C.2 (CQE 2) adjust flow mark. */ 614 "add v14.4s, v14.4s, %[flow_mark_adj].4s \n\t" 615 /* C.3 (CQE 2) fill in mbuf - rx_descriptor_fields1. */ 616 "st1 {v14.2d}, [%[e2]] \n\t" 617 /* C.1 (CQE 0) generate final structure for mbuf. */ 618 "tbl v12.16b, {v20.16b}, %[mb_shuf_m].16b \n\t" 619 /* C.2 (CQE 1) adjust flow mark. */ 620 "add v13.4s, v13.4s, %[flow_mark_adj].4s \n\t" 621 /* C.3 (CQE 1) fill in mbuf - rx_descriptor_fields1. */ 622 "st1 {v13.2d}, [%[e1]] \n\t" 623 #ifdef MLX5_PMD_SOFT_COUNTERS 624 /* Extract byte_cnt. */ 625 "tbl %[byte_cnt].8b, {v20.16b - v23.16b}, %[len_shuf_m].8b \n\t" 626 #endif 627 /* Extract ptype_info. */ 628 "tbl %[ptype_info].16b, {v20.16b - v23.16b}, %[ptype_shuf_m].16b \n\t" 629 /* Extract flow_tag. */ 630 "tbl %[flow_tag].16b, {v20.16b - v23.16b}, %[ftag_shuf_m].16b \n\t" 631 /* A.2 copy mbuf pointers. */ 632 "st1 {v24.2d - v25.2d}, [%[pkts_p]] \n\t" 633 /* C.2 (CQE 0) adjust flow mark. */ 634 "add v12.4s, v12.4s, %[flow_mark_adj].4s \n\t" 635 /* C.3 (CQE 1) fill in mbuf - rx_descriptor_fields1. */ 636 "st1 {v12.2d}, [%[e0]] \n\t" 637 :[op_own]"=&w"(op_own), 638 [byte_cnt]"=&w"(byte_cnt), 639 [ptype_info]"=&w"(ptype_info), 640 [flow_tag]"=&w"(flow_tag) 641 :[p3]"r"(p3), [p2]"r"(p2), [p1]"r"(p1), [p0]"r"(p0), 642 [e3]"r"(e3), [e2]"r"(e2), [e1]"r"(e1), [e0]"r"(e0), 643 [c3]"w"(c3), [c2]"w"(c2), [c1]"w"(c1), [c0]"w"(c0), 644 [elts_p]"r"(elts_p), 645 [pkts_p]"r"(pkts_p), 646 [cqe_shuf_m]"w"(cqe_shuf_m), 647 [mb_shuf_m]"w"(mb_shuf_m), 648 [owner_shuf_m]"w"(owner_shuf_m), 649 [len_shuf_m]"w"(len_shuf_m), 650 [ptype_shuf_m]"w"(ptype_shuf_m), 651 [ftag_shuf_m]"w"(ftag_shuf_m), 652 [crc_adj]"w"(crc_adj), 653 [flow_mark_adj]"w"(flow_mark_adj) 654 :"memory", 655 "v12", "v13", "v14", "v15", 656 "v16", "v17", "v18", "v19", 657 "v20", "v21", "v22", "v23", 658 "v24", "v25"); 659 /* D.2 flip owner bit to mark CQEs from last round. */ 660 owner_mask = vand_u16(op_own, owner_check); 661 owner_mask = vceq_u16(owner_mask, ownership); 662 /* D.3 get mask for invalidated CQEs. */ 663 opcode = vand_u16(op_own, opcode_check); 664 invalid_mask = vceq_u16(opcode_check, opcode); 665 /* E.1 find compressed CQE format. */ 666 comp_mask = vand_u16(op_own, format_check); 667 comp_mask = vceq_u16(comp_mask, format_check); 668 /* D.4 mask out beyond boundary. */ 669 invalid_mask = vorr_u16(invalid_mask, mask); 670 /* D.5 merge invalid_mask with invalid owner. */ 671 invalid_mask = vorr_u16(invalid_mask, owner_mask); 672 /* E.2 mask out invalid entries. */ 673 comp_mask = vbic_u16(comp_mask, invalid_mask); 674 /* E.3 get the first compressed CQE. */ 675 comp_idx = __builtin_clzl(vget_lane_u64(vreinterpret_u64_u16( 676 comp_mask), 0)) / 677 (sizeof(uint16_t) * 8); 678 /* D.6 mask out entries after the compressed CQE. */ 679 mask = vcreate_u16(comp_idx < MLX5_VPMD_DESCS_PER_LOOP ? 680 -1UL >> (comp_idx * sizeof(uint16_t) * 8) : 681 0); 682 invalid_mask = vorr_u16(invalid_mask, mask); 683 /* D.7 count non-compressed valid CQEs. */ 684 n = __builtin_clzl(vget_lane_u64(vreinterpret_u64_u16( 685 invalid_mask), 0)) / (sizeof(uint16_t) * 8); 686 nocmp_n += n; 687 /* D.2 get the final invalid mask. */ 688 mask = vcreate_u16(n < MLX5_VPMD_DESCS_PER_LOOP ? 689 -1UL >> (n * sizeof(uint16_t) * 8) : 0); 690 invalid_mask = vorr_u16(invalid_mask, mask); 691 /* D.3 check error in opcode. */ 692 opcode = vceq_u16(resp_err_check, opcode); 693 opcode = vbic_u16(opcode, invalid_mask); 694 /* D.4 mark if any error is set */ 695 *err |= vget_lane_u64(vreinterpret_u64_u16(opcode), 0); 696 /* C.4 fill in mbuf - rearm_data and packet_type. */ 697 rxq_cq_to_ptype_oflags_v(rxq, ptype_info, flow_tag, 698 opcode, &elts[pos]); 699 if (rxq->hw_timestamp) { 700 if (rxq->rt_timestamp) { 701 struct mlx5_dev_ctx_shared *sh = rxq->sh; 702 uint64_t ts; 703 704 ts = rte_be_to_cpu_64 705 (container_of(p0, struct mlx5_cqe, 706 pkt_info)->timestamp); 707 elts[pos]->timestamp = 708 mlx5_txpp_convert_rx_ts(sh, ts); 709 ts = rte_be_to_cpu_64 710 (container_of(p1, struct mlx5_cqe, 711 pkt_info)->timestamp); 712 elts[pos + 1]->timestamp = 713 mlx5_txpp_convert_rx_ts(sh, ts); 714 ts = rte_be_to_cpu_64 715 (container_of(p2, struct mlx5_cqe, 716 pkt_info)->timestamp); 717 elts[pos + 2]->timestamp = 718 mlx5_txpp_convert_rx_ts(sh, ts); 719 ts = rte_be_to_cpu_64 720 (container_of(p3, struct mlx5_cqe, 721 pkt_info)->timestamp); 722 elts[pos + 3]->timestamp = 723 mlx5_txpp_convert_rx_ts(sh, ts); 724 } else { 725 elts[pos]->timestamp = rte_be_to_cpu_64 726 (container_of(p0, struct mlx5_cqe, 727 pkt_info)->timestamp); 728 elts[pos + 1]->timestamp = rte_be_to_cpu_64 729 (container_of(p1, struct mlx5_cqe, 730 pkt_info)->timestamp); 731 elts[pos + 2]->timestamp = rte_be_to_cpu_64 732 (container_of(p2, struct mlx5_cqe, 733 pkt_info)->timestamp); 734 elts[pos + 3]->timestamp = rte_be_to_cpu_64 735 (container_of(p3, struct mlx5_cqe, 736 pkt_info)->timestamp); 737 } 738 } 739 if (rxq->dynf_meta) { 740 /* This code is subject for futher optimization. */ 741 int32_t offs = rxq->flow_meta_offset; 742 743 *RTE_MBUF_DYNFIELD(pkts[pos], offs, uint32_t *) = 744 container_of(p0, struct mlx5_cqe, 745 pkt_info)->flow_table_metadata; 746 *RTE_MBUF_DYNFIELD(pkts[pos + 1], offs, uint32_t *) = 747 container_of(p1, struct mlx5_cqe, 748 pkt_info)->flow_table_metadata; 749 *RTE_MBUF_DYNFIELD(pkts[pos + 2], offs, uint32_t *) = 750 container_of(p2, struct mlx5_cqe, 751 pkt_info)->flow_table_metadata; 752 *RTE_MBUF_DYNFIELD(pkts[pos + 3], offs, uint32_t *) = 753 container_of(p3, struct mlx5_cqe, 754 pkt_info)->flow_table_metadata; 755 if (*RTE_MBUF_DYNFIELD(pkts[pos], offs, uint32_t *)) 756 elts[pos]->ol_flags |= rxq->flow_meta_mask; 757 if (*RTE_MBUF_DYNFIELD(pkts[pos + 1], offs, uint32_t *)) 758 elts[pos + 1]->ol_flags |= rxq->flow_meta_mask; 759 if (*RTE_MBUF_DYNFIELD(pkts[pos + 2], offs, uint32_t *)) 760 elts[pos + 2]->ol_flags |= rxq->flow_meta_mask; 761 if (*RTE_MBUF_DYNFIELD(pkts[pos + 3], offs, uint32_t *)) 762 elts[pos + 3]->ol_flags |= rxq->flow_meta_mask; 763 } 764 #ifdef MLX5_PMD_SOFT_COUNTERS 765 /* Add up received bytes count. */ 766 byte_cnt = vbic_u16(byte_cnt, invalid_mask); 767 rcvd_byte += vget_lane_u64(vpaddl_u32(vpaddl_u16(byte_cnt)), 0); 768 #endif 769 /* 770 * Break the loop unless more valid CQE is expected, or if 771 * there's a compressed CQE. 772 */ 773 if (n != MLX5_VPMD_DESCS_PER_LOOP) 774 break; 775 } 776 /* If no new CQE seen, return without updating cq_db. */ 777 if (unlikely(!nocmp_n && comp_idx == MLX5_VPMD_DESCS_PER_LOOP)) { 778 *no_cq = true; 779 return rcvd_pkt; 780 } 781 /* Update the consumer indexes for non-compressed CQEs. */ 782 MLX5_ASSERT(nocmp_n <= pkts_n); 783 rxq->cq_ci += nocmp_n; 784 rxq->rq_pi += nocmp_n; 785 rcvd_pkt += nocmp_n; 786 #ifdef MLX5_PMD_SOFT_COUNTERS 787 rxq->stats.ipackets += nocmp_n; 788 rxq->stats.ibytes += rcvd_byte; 789 #endif 790 /* Decompress the last CQE if compressed. */ 791 if (comp_idx < MLX5_VPMD_DESCS_PER_LOOP && comp_idx == n) { 792 MLX5_ASSERT(comp_idx == (nocmp_n % MLX5_VPMD_DESCS_PER_LOOP)); 793 rxq->decompressed = rxq_cq_decompress_v(rxq, &cq[nocmp_n], 794 &elts[nocmp_n]); 795 /* Return more packets if needed. */ 796 if (nocmp_n < pkts_n) { 797 uint16_t n = rxq->decompressed; 798 799 n = RTE_MIN(n, pkts_n - nocmp_n); 800 rxq_copy_mbuf_v(rxq, &pkts[nocmp_n], n); 801 rxq->rq_pi += n; 802 rcvd_pkt += n; 803 rxq->decompressed -= n; 804 } 805 } 806 rte_cio_wmb(); 807 *rxq->cq_db = rte_cpu_to_be_32(rxq->cq_ci); 808 *no_cq = !rcvd_pkt; 809 return rcvd_pkt; 810 } 811 812 #endif /* RTE_PMD_MLX5_RXTX_VEC_NEON_H_ */ 813