1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2017 6WIND S.A. 3 * Copyright 2017 Mellanox Technologies, Ltd 4 */ 5 6 #ifndef RTE_PMD_MLX5_RXTX_VEC_NEON_H_ 7 #define RTE_PMD_MLX5_RXTX_VEC_NEON_H_ 8 9 #include <stdint.h> 10 #include <string.h> 11 #include <stdlib.h> 12 #include <arm_neon.h> 13 14 #include <rte_mbuf.h> 15 #include <rte_mempool.h> 16 #include <rte_prefetch.h> 17 18 #include <mlx5_prm.h> 19 20 #include "mlx5_defs.h" 21 #include "mlx5.h" 22 #include "mlx5_utils.h" 23 #include "mlx5_rxtx.h" 24 #include "mlx5_rxtx_vec.h" 25 #include "mlx5_autoconf.h" 26 27 #pragma GCC diagnostic ignored "-Wcast-qual" 28 29 /** 30 * Store free buffers to RX SW ring. 31 * 32 * @param elts 33 * Pointer to SW ring to be filled. 34 * @param pkts 35 * Pointer to array of packets to be stored. 36 * @param pkts_n 37 * Number of packets to be stored. 38 */ 39 static inline void 40 rxq_copy_mbuf_v(struct rte_mbuf **elts, struct rte_mbuf **pkts, uint16_t n) 41 { 42 unsigned int pos; 43 uint16_t p = n & -2; 44 45 for (pos = 0; pos < p; pos += 2) { 46 uint64x2_t mbp; 47 48 mbp = vld1q_u64((void *)&elts[pos]); 49 vst1q_u64((void *)&pkts[pos], mbp); 50 } 51 if (n & 1) 52 pkts[pos] = elts[pos]; 53 } 54 55 /** 56 * Decompress a compressed completion and fill in mbufs in RX SW ring with data 57 * extracted from the title completion descriptor. 58 * 59 * @param rxq 60 * Pointer to RX queue structure. 61 * @param cq 62 * Pointer to completion array having a compressed completion at first. 63 * @param elts 64 * Pointer to SW ring to be filled. The first mbuf has to be pre-built from 65 * the title completion descriptor to be copied to the rest of mbufs. 66 * 67 * @return 68 * Number of mini-CQEs successfully decompressed. 69 */ 70 static inline uint16_t 71 rxq_cq_decompress_v(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cq, 72 struct rte_mbuf **elts) 73 { 74 volatile struct mlx5_mini_cqe8 *mcq = (void *)&(cq + 1)->pkt_info; 75 struct rte_mbuf *t_pkt = elts[0]; /* Title packet is pre-built. */ 76 unsigned int pos; 77 unsigned int i; 78 unsigned int inv = 0; 79 /* Mask to shuffle from extracted mini CQE to mbuf. */ 80 const uint8x16_t mcqe_shuf_m1 = { 81 -1, -1, -1, -1, /* skip packet_type */ 82 7, 6, -1, -1, /* pkt_len, bswap16 */ 83 7, 6, /* data_len, bswap16 */ 84 -1, -1, /* skip vlan_tci */ 85 3, 2, 1, 0 /* hash.rss, bswap32 */ 86 }; 87 const uint8x16_t mcqe_shuf_m2 = { 88 -1, -1, -1, -1, /* skip packet_type */ 89 15, 14, -1, -1, /* pkt_len, bswap16 */ 90 15, 14, /* data_len, bswap16 */ 91 -1, -1, /* skip vlan_tci */ 92 11, 10, 9, 8 /* hash.rss, bswap32 */ 93 }; 94 /* Restore the compressed count. Must be 16 bits. */ 95 const uint16_t mcqe_n = t_pkt->data_len + 96 (rxq->crc_present * RTE_ETHER_CRC_LEN); 97 const uint64x2_t rearm = 98 vld1q_u64((void *)&t_pkt->rearm_data); 99 const uint32x4_t rxdf_mask = { 100 0xffffffff, /* packet_type */ 101 0, /* skip pkt_len */ 102 0xffff0000, /* vlan_tci, skip data_len */ 103 0, /* skip hash.rss */ 104 }; 105 const uint8x16_t rxdf = 106 vandq_u8(vld1q_u8((void *)&t_pkt->rx_descriptor_fields1), 107 vreinterpretq_u8_u32(rxdf_mask)); 108 const uint16x8_t crc_adj = { 109 0, 0, 110 rxq->crc_present * RTE_ETHER_CRC_LEN, 0, 111 rxq->crc_present * RTE_ETHER_CRC_LEN, 0, 112 0, 0 113 }; 114 uint32x4_t ol_flags = {0, 0, 0, 0}; 115 uint32x4_t ol_flags_mask = {0, 0, 0, 0}; 116 #ifdef MLX5_PMD_SOFT_COUNTERS 117 uint32_t rcvd_byte = 0; 118 #endif 119 /* Mask to shuffle byte_cnt to add up stats. Do bswap16 for all. */ 120 const uint8x8_t len_shuf_m = { 121 7, 6, /* 1st mCQE */ 122 15, 14, /* 2nd mCQE */ 123 23, 22, /* 3rd mCQE */ 124 31, 30 /* 4th mCQE */ 125 }; 126 127 /* 128 * A. load mCQEs into a 128bit register. 129 * B. store rearm data to mbuf. 130 * C. combine data from mCQEs with rx_descriptor_fields1. 131 * D. store rx_descriptor_fields1. 132 * E. store flow tag (rte_flow mark). 133 */ 134 for (pos = 0; pos < mcqe_n; ) { 135 uint8_t *p = (void *)&mcq[pos % 8]; 136 uint8_t *e0 = (void *)&elts[pos]->rearm_data; 137 uint8_t *e1 = (void *)&elts[pos + 1]->rearm_data; 138 uint8_t *e2 = (void *)&elts[pos + 2]->rearm_data; 139 uint8_t *e3 = (void *)&elts[pos + 3]->rearm_data; 140 uint16x4_t byte_cnt; 141 #ifdef MLX5_PMD_SOFT_COUNTERS 142 uint16x4_t invalid_mask = 143 vcreate_u16(mcqe_n - pos < MLX5_VPMD_DESCS_PER_LOOP ? 144 -1UL << ((mcqe_n - pos) * 145 sizeof(uint16_t) * 8) : 0); 146 #endif 147 148 for (i = 0; i < MLX5_VPMD_DESCS_PER_LOOP; ++i) 149 if (likely(pos + i < mcqe_n)) 150 rte_prefetch0((void *)(cq + pos + i)); 151 __asm__ volatile ( 152 /* A.1 load mCQEs into a 128bit register. */ 153 "ld1 {v16.16b - v17.16b}, [%[mcq]] \n\t" 154 /* B.1 store rearm data to mbuf. */ 155 "st1 {%[rearm].2d}, [%[e0]] \n\t" 156 "add %[e0], %[e0], #16 \n\t" 157 "st1 {%[rearm].2d}, [%[e1]] \n\t" 158 "add %[e1], %[e1], #16 \n\t" 159 /* C.1 combine data from mCQEs with rx_descriptor_fields1. */ 160 "tbl v18.16b, {v16.16b}, %[mcqe_shuf_m1].16b \n\t" 161 "tbl v19.16b, {v16.16b}, %[mcqe_shuf_m2].16b \n\t" 162 "sub v18.8h, v18.8h, %[crc_adj].8h \n\t" 163 "sub v19.8h, v19.8h, %[crc_adj].8h \n\t" 164 "orr v18.16b, v18.16b, %[rxdf].16b \n\t" 165 "orr v19.16b, v19.16b, %[rxdf].16b \n\t" 166 /* D.1 store rx_descriptor_fields1. */ 167 "st1 {v18.2d}, [%[e0]] \n\t" 168 "st1 {v19.2d}, [%[e1]] \n\t" 169 /* B.1 store rearm data to mbuf. */ 170 "st1 {%[rearm].2d}, [%[e2]] \n\t" 171 "add %[e2], %[e2], #16 \n\t" 172 "st1 {%[rearm].2d}, [%[e3]] \n\t" 173 "add %[e3], %[e3], #16 \n\t" 174 /* C.1 combine data from mCQEs with rx_descriptor_fields1. */ 175 "tbl v18.16b, {v17.16b}, %[mcqe_shuf_m1].16b \n\t" 176 "tbl v19.16b, {v17.16b}, %[mcqe_shuf_m2].16b \n\t" 177 "sub v18.8h, v18.8h, %[crc_adj].8h \n\t" 178 "sub v19.8h, v19.8h, %[crc_adj].8h \n\t" 179 "orr v18.16b, v18.16b, %[rxdf].16b \n\t" 180 "orr v19.16b, v19.16b, %[rxdf].16b \n\t" 181 /* D.1 store rx_descriptor_fields1. */ 182 "st1 {v18.2d}, [%[e2]] \n\t" 183 "st1 {v19.2d}, [%[e3]] \n\t" 184 #ifdef MLX5_PMD_SOFT_COUNTERS 185 "tbl %[byte_cnt].8b, {v16.16b - v17.16b}, %[len_shuf_m].8b \n\t" 186 #endif 187 :[byte_cnt]"=&w"(byte_cnt) 188 :[mcq]"r"(p), 189 [rxdf]"w"(rxdf), 190 [rearm]"w"(rearm), 191 [e3]"r"(e3), [e2]"r"(e2), [e1]"r"(e1), [e0]"r"(e0), 192 [mcqe_shuf_m1]"w"(mcqe_shuf_m1), 193 [mcqe_shuf_m2]"w"(mcqe_shuf_m2), 194 [crc_adj]"w"(crc_adj), 195 [len_shuf_m]"w"(len_shuf_m) 196 :"memory", "v16", "v17", "v18", "v19"); 197 #ifdef MLX5_PMD_SOFT_COUNTERS 198 byte_cnt = vbic_u16(byte_cnt, invalid_mask); 199 rcvd_byte += vget_lane_u64(vpaddl_u32(vpaddl_u16(byte_cnt)), 0); 200 #endif 201 if (rxq->mark) { 202 if (rxq->mcqe_format != 203 MLX5_CQE_RESP_FORMAT_FTAG_STRIDX) { 204 const uint32_t flow_tag = t_pkt->hash.fdir.hi; 205 206 /* E.1 store flow tag (rte_flow mark). */ 207 elts[pos]->hash.fdir.hi = flow_tag; 208 elts[pos + 1]->hash.fdir.hi = flow_tag; 209 elts[pos + 2]->hash.fdir.hi = flow_tag; 210 elts[pos + 3]->hash.fdir.hi = flow_tag; 211 } else { 212 const uint32x4_t flow_mark_adj = { 213 -1, -1, -1, -1 }; 214 const uint8x16_t flow_mark_shuf = { 215 28, 24, 25, -1, 216 20, 16, 17, -1, 217 12, 8, 9, -1, 218 4, 0, 1, -1}; 219 /* Extract flow_tag field. */ 220 const uint32x4_t ft_mask = 221 vdupq_n_u32(MLX5_FLOW_MARK_DEFAULT); 222 const uint32x4_t fdir_flags = 223 vdupq_n_u32(PKT_RX_FDIR); 224 const uint32x4_t fdir_all_flags = 225 vdupq_n_u32(PKT_RX_FDIR | 226 PKT_RX_FDIR_ID); 227 uint32x4_t fdir_id_flags = 228 vdupq_n_u32(PKT_RX_FDIR_ID); 229 uint32x4_t invalid_mask, ftag; 230 231 __asm__ volatile 232 /* A.1 load mCQEs into a 128bit register. */ 233 ("ld1 {v16.16b - v17.16b}, [%[mcq]]\n\t" 234 /* Extract flow_tag. */ 235 "tbl %[ftag].16b, {v16.16b - v17.16b}, %[flow_mark_shuf].16b\n\t" 236 : [ftag]"=&w"(ftag) 237 : [mcq]"r"(p), 238 [flow_mark_shuf]"w"(flow_mark_shuf) 239 : "memory", "v16", "v17"); 240 invalid_mask = vceqzq_u32(ftag); 241 ol_flags_mask = vorrq_u32(ol_flags_mask, 242 fdir_all_flags); 243 /* Set PKT_RX_FDIR if flow tag is non-zero. */ 244 ol_flags = vorrq_u32(ol_flags, 245 vbicq_u32(fdir_flags, invalid_mask)); 246 /* Mask out invalid entries. */ 247 fdir_id_flags = vbicq_u32(fdir_id_flags, 248 invalid_mask); 249 /* Check if flow tag MLX5_FLOW_MARK_DEFAULT. */ 250 ol_flags = vorrq_u32(ol_flags, 251 vbicq_u32(fdir_id_flags, 252 vceqq_u32(ftag, ft_mask))); 253 ftag = vaddq_u32(ftag, flow_mark_adj); 254 elts[pos]->hash.fdir.hi = 255 vgetq_lane_u32(ftag, 3); 256 elts[pos + 1]->hash.fdir.hi = 257 vgetq_lane_u32(ftag, 2); 258 elts[pos + 2]->hash.fdir.hi = 259 vgetq_lane_u32(ftag, 1); 260 elts[pos + 3]->hash.fdir.hi = 261 vgetq_lane_u32(ftag, 0); 262 } 263 } 264 if (unlikely(rxq->mcqe_format != 265 MLX5_CQE_RESP_FORMAT_HASH)) { 266 if (rxq->mcqe_format == 267 MLX5_CQE_RESP_FORMAT_L34H_STRIDX) { 268 const uint8_t pkt_info = 269 (cq->pkt_info & 0x3) << 6; 270 const uint8_t pkt_hdr0 = 271 mcq[pos % 8].hdr_type; 272 const uint8_t pkt_hdr1 = 273 mcq[pos % 8 + 1].hdr_type; 274 const uint8_t pkt_hdr2 = 275 mcq[pos % 8 + 2].hdr_type; 276 const uint8_t pkt_hdr3 = 277 mcq[pos % 8 + 3].hdr_type; 278 const uint32x4_t vlan_mask = 279 vdupq_n_u32(PKT_RX_VLAN | 280 PKT_RX_VLAN_STRIPPED); 281 const uint32x4_t cv_mask = 282 vdupq_n_u32(MLX5_CQE_VLAN_STRIPPED); 283 const uint32x4_t pkt_cv = { 284 pkt_hdr0 & 0x1, pkt_hdr1 & 0x1, 285 pkt_hdr2 & 0x1, pkt_hdr3 & 0x1}; 286 287 ol_flags_mask = vorrq_u32(ol_flags_mask, 288 vlan_mask); 289 ol_flags = vorrq_u32(ol_flags, 290 vandq_u32(vlan_mask, 291 vceqq_u32(pkt_cv, cv_mask))); 292 elts[pos]->packet_type = 293 mlx5_ptype_table[(pkt_hdr0 >> 2) | 294 pkt_info]; 295 elts[pos + 1]->packet_type = 296 mlx5_ptype_table[(pkt_hdr1 >> 2) | 297 pkt_info]; 298 elts[pos + 2]->packet_type = 299 mlx5_ptype_table[(pkt_hdr2 >> 2) | 300 pkt_info]; 301 elts[pos + 3]->packet_type = 302 mlx5_ptype_table[(pkt_hdr3 >> 2) | 303 pkt_info]; 304 if (rxq->tunnel) { 305 elts[pos]->packet_type |= 306 !!(((pkt_hdr0 >> 2) | 307 pkt_info) & (1 << 6)); 308 elts[pos + 1]->packet_type |= 309 !!(((pkt_hdr1 >> 2) | 310 pkt_info) & (1 << 6)); 311 elts[pos + 2]->packet_type |= 312 !!(((pkt_hdr2 >> 2) | 313 pkt_info) & (1 << 6)); 314 elts[pos + 3]->packet_type |= 315 !!(((pkt_hdr3 >> 2) | 316 pkt_info) & (1 << 6)); 317 } 318 } 319 const uint32x4_t hash_flags = 320 vdupq_n_u32(PKT_RX_RSS_HASH); 321 const uint32x4_t rearm_flags = 322 vdupq_n_u32((uint32_t)t_pkt->ol_flags); 323 324 ol_flags_mask = vorrq_u32(ol_flags_mask, hash_flags); 325 ol_flags = vorrq_u32(ol_flags, 326 vbicq_u32(rearm_flags, ol_flags_mask)); 327 elts[pos]->ol_flags = vgetq_lane_u32(ol_flags, 3); 328 elts[pos + 1]->ol_flags = vgetq_lane_u32(ol_flags, 2); 329 elts[pos + 2]->ol_flags = vgetq_lane_u32(ol_flags, 1); 330 elts[pos + 3]->ol_flags = vgetq_lane_u32(ol_flags, 0); 331 elts[pos]->hash.rss = 0; 332 elts[pos + 1]->hash.rss = 0; 333 elts[pos + 2]->hash.rss = 0; 334 elts[pos + 3]->hash.rss = 0; 335 } 336 if (rxq->dynf_meta) { 337 int32_t offs = rxq->flow_meta_offset; 338 const uint32_t meta = 339 *RTE_MBUF_DYNFIELD(t_pkt, offs, uint32_t *); 340 341 /* Check if title packet has valid metadata. */ 342 if (meta) { 343 MLX5_ASSERT(t_pkt->ol_flags & 344 rxq->flow_meta_mask); 345 *RTE_MBUF_DYNFIELD(elts[pos], offs, 346 uint32_t *) = meta; 347 *RTE_MBUF_DYNFIELD(elts[pos + 1], offs, 348 uint32_t *) = meta; 349 *RTE_MBUF_DYNFIELD(elts[pos + 2], offs, 350 uint32_t *) = meta; 351 *RTE_MBUF_DYNFIELD(elts[pos + 3], offs, 352 uint32_t *) = meta; 353 } 354 } 355 pos += MLX5_VPMD_DESCS_PER_LOOP; 356 /* Move to next CQE and invalidate consumed CQEs. */ 357 if (!(pos & 0x7) && pos < mcqe_n) { 358 if (pos + 8 < mcqe_n) 359 rte_prefetch0((void *)(cq + pos + 8)); 360 mcq = (void *)&(cq + pos)->pkt_info; 361 for (i = 0; i < 8; ++i) 362 cq[inv++].op_own = MLX5_CQE_INVALIDATE; 363 } 364 } 365 /* Invalidate the rest of CQEs. */ 366 for (; inv < mcqe_n; ++inv) 367 cq[inv].op_own = MLX5_CQE_INVALIDATE; 368 #ifdef MLX5_PMD_SOFT_COUNTERS 369 rxq->stats.ipackets += mcqe_n; 370 rxq->stats.ibytes += rcvd_byte; 371 #endif 372 return mcqe_n; 373 } 374 375 /** 376 * Calculate packet type and offload flag for mbuf and store it. 377 * 378 * @param rxq 379 * Pointer to RX queue structure. 380 * @param ptype_info 381 * Array of four 4bytes packet type info extracted from the original 382 * completion descriptor. 383 * @param flow_tag 384 * Array of four 4bytes flow ID extracted from the original completion 385 * descriptor. 386 * @param op_err 387 * Opcode vector having responder error status. Each field is 4B. 388 * @param pkts 389 * Pointer to array of packets to be filled. 390 */ 391 static inline void 392 rxq_cq_to_ptype_oflags_v(struct mlx5_rxq_data *rxq, 393 uint32x4_t ptype_info, uint32x4_t flow_tag, 394 uint16x4_t op_err, struct rte_mbuf **pkts) 395 { 396 uint16x4_t ptype; 397 uint32x4_t pinfo, cv_flags; 398 uint32x4_t ol_flags = 399 vdupq_n_u32(rxq->rss_hash * PKT_RX_RSS_HASH | 400 rxq->hw_timestamp * rxq->timestamp_rx_flag); 401 const uint32x4_t ptype_ol_mask = { 0x106, 0x106, 0x106, 0x106 }; 402 const uint8x16_t cv_flag_sel = { 403 0, 404 (uint8_t)(PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED), 405 (uint8_t)(PKT_RX_IP_CKSUM_GOOD >> 1), 406 0, 407 (uint8_t)(PKT_RX_L4_CKSUM_GOOD >> 1), 408 0, 409 (uint8_t)((PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD) >> 1), 410 0, 0, 0, 0, 0, 0, 0, 0, 0 411 }; 412 const uint32x4_t cv_mask = 413 vdupq_n_u32(PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD | 414 PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED); 415 const uint64x2_t mbuf_init = vld1q_u64 416 ((const uint64_t *)&rxq->mbuf_initializer); 417 uint64x2_t rearm0, rearm1, rearm2, rearm3; 418 uint8_t pt_idx0, pt_idx1, pt_idx2, pt_idx3; 419 420 if (rxq->mark) { 421 const uint32x4_t ft_def = vdupq_n_u32(MLX5_FLOW_MARK_DEFAULT); 422 const uint32x4_t fdir_flags = vdupq_n_u32(PKT_RX_FDIR); 423 uint32x4_t fdir_id_flags = vdupq_n_u32(PKT_RX_FDIR_ID); 424 uint32x4_t invalid_mask; 425 426 /* Check if flow tag is non-zero then set PKT_RX_FDIR. */ 427 invalid_mask = vceqzq_u32(flow_tag); 428 ol_flags = vorrq_u32(ol_flags, 429 vbicq_u32(fdir_flags, invalid_mask)); 430 /* Mask out invalid entries. */ 431 fdir_id_flags = vbicq_u32(fdir_id_flags, invalid_mask); 432 /* Check if flow tag MLX5_FLOW_MARK_DEFAULT. */ 433 ol_flags = vorrq_u32(ol_flags, 434 vbicq_u32(fdir_id_flags, 435 vceqq_u32(flow_tag, ft_def))); 436 } 437 /* 438 * ptype_info has the following: 439 * bit[1] = l3_ok 440 * bit[2] = l4_ok 441 * bit[8] = cv 442 * bit[11:10] = l3_hdr_type 443 * bit[14:12] = l4_hdr_type 444 * bit[15] = ip_frag 445 * bit[16] = tunneled 446 * bit[17] = outer_l3_type 447 */ 448 ptype = vshrn_n_u32(ptype_info, 10); 449 /* Errored packets will have RTE_PTYPE_ALL_MASK. */ 450 ptype = vorr_u16(ptype, op_err); 451 pt_idx0 = vget_lane_u8(vreinterpret_u8_u16(ptype), 6); 452 pt_idx1 = vget_lane_u8(vreinterpret_u8_u16(ptype), 4); 453 pt_idx2 = vget_lane_u8(vreinterpret_u8_u16(ptype), 2); 454 pt_idx3 = vget_lane_u8(vreinterpret_u8_u16(ptype), 0); 455 pkts[0]->packet_type = mlx5_ptype_table[pt_idx0] | 456 !!(pt_idx0 & (1 << 6)) * rxq->tunnel; 457 pkts[1]->packet_type = mlx5_ptype_table[pt_idx1] | 458 !!(pt_idx1 & (1 << 6)) * rxq->tunnel; 459 pkts[2]->packet_type = mlx5_ptype_table[pt_idx2] | 460 !!(pt_idx2 & (1 << 6)) * rxq->tunnel; 461 pkts[3]->packet_type = mlx5_ptype_table[pt_idx3] | 462 !!(pt_idx3 & (1 << 6)) * rxq->tunnel; 463 /* Fill flags for checksum and VLAN. */ 464 pinfo = vandq_u32(ptype_info, ptype_ol_mask); 465 pinfo = vreinterpretq_u32_u8( 466 vqtbl1q_u8(cv_flag_sel, vreinterpretq_u8_u32(pinfo))); 467 /* Locate checksum flags at byte[2:1] and merge with VLAN flags. */ 468 cv_flags = vshlq_n_u32(pinfo, 9); 469 cv_flags = vorrq_u32(pinfo, cv_flags); 470 /* Move back flags to start from byte[0]. */ 471 cv_flags = vshrq_n_u32(cv_flags, 8); 472 /* Mask out garbage bits. */ 473 cv_flags = vandq_u32(cv_flags, cv_mask); 474 /* Merge to ol_flags. */ 475 ol_flags = vorrq_u32(ol_flags, cv_flags); 476 /* Merge mbuf_init and ol_flags, and store. */ 477 rearm0 = vreinterpretq_u64_u32(vsetq_lane_u32 478 (vgetq_lane_u32(ol_flags, 3), 479 vreinterpretq_u32_u64(mbuf_init), 2)); 480 rearm1 = vreinterpretq_u64_u32(vsetq_lane_u32 481 (vgetq_lane_u32(ol_flags, 2), 482 vreinterpretq_u32_u64(mbuf_init), 2)); 483 rearm2 = vreinterpretq_u64_u32(vsetq_lane_u32 484 (vgetq_lane_u32(ol_flags, 1), 485 vreinterpretq_u32_u64(mbuf_init), 2)); 486 rearm3 = vreinterpretq_u64_u32(vsetq_lane_u32 487 (vgetq_lane_u32(ol_flags, 0), 488 vreinterpretq_u32_u64(mbuf_init), 2)); 489 490 vst1q_u64((void *)&pkts[0]->rearm_data, rearm0); 491 vst1q_u64((void *)&pkts[1]->rearm_data, rearm1); 492 vst1q_u64((void *)&pkts[2]->rearm_data, rearm2); 493 vst1q_u64((void *)&pkts[3]->rearm_data, rearm3); 494 } 495 496 /** 497 * Process a non-compressed completion and fill in mbufs in RX SW ring 498 * with data extracted from the title completion descriptor. 499 * 500 * @param rxq 501 * Pointer to RX queue structure. 502 * @param cq 503 * Pointer to completion array having a non-compressed completion at first. 504 * @param elts 505 * Pointer to SW ring to be filled. The first mbuf has to be pre-built from 506 * the title completion descriptor to be copied to the rest of mbufs. 507 * @param[out] pkts 508 * Array to store received packets. 509 * @param pkts_n 510 * Maximum number of packets in array. 511 * @param[out] err 512 * Pointer to a flag. Set non-zero value if pkts array has at least one error 513 * packet to handle. 514 * @param[out] comp 515 * Pointer to a index. Set it to the first compressed completion if any. 516 * 517 * @return 518 * Number of CQEs successfully processed. 519 */ 520 static inline uint16_t 521 rxq_cq_process_v(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cq, 522 struct rte_mbuf **elts, struct rte_mbuf **pkts, 523 uint16_t pkts_n, uint64_t *err, uint64_t *comp) 524 { 525 const uint16_t q_n = 1 << rxq->cqe_n; 526 const uint16_t q_mask = q_n - 1; 527 unsigned int pos; 528 uint64_t n = 0; 529 uint64_t comp_idx = MLX5_VPMD_DESCS_PER_LOOP; 530 uint16_t nocmp_n = 0; 531 const uint16x4_t ownership = vdup_n_u16(!(rxq->cq_ci & (q_mask + 1))); 532 const uint16x4_t owner_check = vcreate_u16(0x0001000100010001); 533 const uint16x4_t opcode_check = vcreate_u16(0x00f000f000f000f0); 534 const uint16x4_t format_check = vcreate_u16(0x000c000c000c000c); 535 const uint16x4_t resp_err_check = vcreate_u16(0x00e000e000e000e0); 536 #ifdef MLX5_PMD_SOFT_COUNTERS 537 uint32_t rcvd_byte = 0; 538 #endif 539 /* Mask to generate 16B length vector. */ 540 const uint8x8_t len_shuf_m = { 541 52, 53, /* 4th CQE */ 542 36, 37, /* 3rd CQE */ 543 20, 21, /* 2nd CQE */ 544 4, 5 /* 1st CQE */ 545 }; 546 /* Mask to extract 16B data from a 64B CQE. */ 547 const uint8x16_t cqe_shuf_m = { 548 28, 29, /* hdr_type_etc */ 549 0, /* pkt_info */ 550 -1, /* null */ 551 47, 46, /* byte_cnt, bswap16 */ 552 31, 30, /* vlan_info, bswap16 */ 553 15, 14, 13, 12, /* rx_hash_res, bswap32 */ 554 57, 58, 59, /* flow_tag */ 555 63 /* op_own */ 556 }; 557 /* Mask to generate 16B data for mbuf. */ 558 const uint8x16_t mb_shuf_m = { 559 4, 5, -1, -1, /* pkt_len */ 560 4, 5, /* data_len */ 561 6, 7, /* vlan_tci */ 562 8, 9, 10, 11, /* hash.rss */ 563 12, 13, 14, -1 /* hash.fdir.hi */ 564 }; 565 /* Mask to generate 16B owner vector. */ 566 const uint8x8_t owner_shuf_m = { 567 63, -1, /* 4th CQE */ 568 47, -1, /* 3rd CQE */ 569 31, -1, /* 2nd CQE */ 570 15, -1 /* 1st CQE */ 571 }; 572 /* Mask to generate a vector having packet_type/ol_flags. */ 573 const uint8x16_t ptype_shuf_m = { 574 48, 49, 50, -1, /* 4th CQE */ 575 32, 33, 34, -1, /* 3rd CQE */ 576 16, 17, 18, -1, /* 2nd CQE */ 577 0, 1, 2, -1 /* 1st CQE */ 578 }; 579 /* Mask to generate a vector having flow tags. */ 580 const uint8x16_t ftag_shuf_m = { 581 60, 61, 62, -1, /* 4th CQE */ 582 44, 45, 46, -1, /* 3rd CQE */ 583 28, 29, 30, -1, /* 2nd CQE */ 584 12, 13, 14, -1 /* 1st CQE */ 585 }; 586 const uint16x8_t crc_adj = { 587 0, 0, rxq->crc_present * RTE_ETHER_CRC_LEN, 0, 0, 0, 0, 0 588 }; 589 const uint32x4_t flow_mark_adj = { 0, 0, 0, rxq->mark * (-1) }; 590 591 /* 592 * Note that vectors have reverse order - {v3, v2, v1, v0}, because 593 * there's no instruction to count trailing zeros. __builtin_clzl() is 594 * used instead. 595 * 596 * A. copy 4 mbuf pointers from elts ring to returing pkts. 597 * B. load 64B CQE and extract necessary fields 598 * Final 16bytes cqes[] extracted from original 64bytes CQE has the 599 * following structure: 600 * struct { 601 * uint16_t hdr_type_etc; 602 * uint8_t pkt_info; 603 * uint8_t rsvd; 604 * uint16_t byte_cnt; 605 * uint16_t vlan_info; 606 * uint32_t rx_has_res; 607 * uint8_t flow_tag[3]; 608 * uint8_t op_own; 609 * } c; 610 * C. fill in mbuf. 611 * D. get valid CQEs. 612 * E. find compressed CQE. 613 */ 614 for (pos = 0; 615 pos < pkts_n; 616 pos += MLX5_VPMD_DESCS_PER_LOOP) { 617 uint16x4_t op_own; 618 uint16x4_t opcode, owner_mask, invalid_mask; 619 uint16x4_t comp_mask; 620 uint16x4_t mask; 621 uint16x4_t byte_cnt; 622 uint32x4_t ptype_info, flow_tag; 623 register uint64x2_t c0, c1, c2, c3; 624 uint8_t *p0, *p1, *p2, *p3; 625 uint8_t *e0 = (void *)&elts[pos]->pkt_len; 626 uint8_t *e1 = (void *)&elts[pos + 1]->pkt_len; 627 uint8_t *e2 = (void *)&elts[pos + 2]->pkt_len; 628 uint8_t *e3 = (void *)&elts[pos + 3]->pkt_len; 629 void *elts_p = (void *)&elts[pos]; 630 void *pkts_p = (void *)&pkts[pos]; 631 632 /* A.0 do not cross the end of CQ. */ 633 mask = vcreate_u16(pkts_n - pos < MLX5_VPMD_DESCS_PER_LOOP ? 634 -1UL >> ((pkts_n - pos) * 635 sizeof(uint16_t) * 8) : 0); 636 p0 = (void *)&cq[pos].pkt_info; 637 p1 = p0 + (pkts_n - pos > 1) * sizeof(struct mlx5_cqe); 638 p2 = p1 + (pkts_n - pos > 2) * sizeof(struct mlx5_cqe); 639 p3 = p2 + (pkts_n - pos > 3) * sizeof(struct mlx5_cqe); 640 /* B.0 (CQE 3) load a block having op_own. */ 641 c3 = vld1q_u64((uint64_t *)(p3 + 48)); 642 /* B.0 (CQE 2) load a block having op_own. */ 643 c2 = vld1q_u64((uint64_t *)(p2 + 48)); 644 /* B.0 (CQE 1) load a block having op_own. */ 645 c1 = vld1q_u64((uint64_t *)(p1 + 48)); 646 /* B.0 (CQE 0) load a block having op_own. */ 647 c0 = vld1q_u64((uint64_t *)(p0 + 48)); 648 /* Synchronize for loading the rest of blocks. */ 649 rte_io_rmb(); 650 /* Prefetch next 4 CQEs. */ 651 if (pkts_n - pos >= 2 * MLX5_VPMD_DESCS_PER_LOOP) { 652 unsigned int next = pos + MLX5_VPMD_DESCS_PER_LOOP; 653 rte_prefetch_non_temporal(&cq[next]); 654 rte_prefetch_non_temporal(&cq[next + 1]); 655 rte_prefetch_non_temporal(&cq[next + 2]); 656 rte_prefetch_non_temporal(&cq[next + 3]); 657 } 658 __asm__ volatile ( 659 /* B.1 (CQE 3) load the rest of blocks. */ 660 "ld1 {v16.16b - v18.16b}, [%[p3]] \n\t" 661 /* B.2 (CQE 3) move the block having op_own. */ 662 "mov v19.16b, %[c3].16b \n\t" 663 /* B.3 (CQE 3) extract 16B fields. */ 664 "tbl v23.16b, {v16.16b - v19.16b}, %[cqe_shuf_m].16b \n\t" 665 /* B.1 (CQE 2) load the rest of blocks. */ 666 "ld1 {v16.16b - v18.16b}, [%[p2]] \n\t" 667 /* B.4 (CQE 3) adjust CRC length. */ 668 "sub v23.8h, v23.8h, %[crc_adj].8h \n\t" 669 /* C.1 (CQE 3) generate final structure for mbuf. */ 670 "tbl v15.16b, {v23.16b}, %[mb_shuf_m].16b \n\t" 671 /* B.2 (CQE 2) move the block having op_own. */ 672 "mov v19.16b, %[c2].16b \n\t" 673 /* B.3 (CQE 2) extract 16B fields. */ 674 "tbl v22.16b, {v16.16b - v19.16b}, %[cqe_shuf_m].16b \n\t" 675 /* B.1 (CQE 1) load the rest of blocks. */ 676 "ld1 {v16.16b - v18.16b}, [%[p1]] \n\t" 677 /* B.4 (CQE 2) adjust CRC length. */ 678 "sub v22.8h, v22.8h, %[crc_adj].8h \n\t" 679 /* C.1 (CQE 2) generate final structure for mbuf. */ 680 "tbl v14.16b, {v22.16b}, %[mb_shuf_m].16b \n\t" 681 /* B.2 (CQE 1) move the block having op_own. */ 682 "mov v19.16b, %[c1].16b \n\t" 683 /* B.3 (CQE 1) extract 16B fields. */ 684 "tbl v21.16b, {v16.16b - v19.16b}, %[cqe_shuf_m].16b \n\t" 685 /* B.1 (CQE 0) load the rest of blocks. */ 686 "ld1 {v16.16b - v18.16b}, [%[p0]] \n\t" 687 /* B.4 (CQE 1) adjust CRC length. */ 688 "sub v21.8h, v21.8h, %[crc_adj].8h \n\t" 689 /* C.1 (CQE 1) generate final structure for mbuf. */ 690 "tbl v13.16b, {v21.16b}, %[mb_shuf_m].16b \n\t" 691 /* B.2 (CQE 0) move the block having op_own. */ 692 "mov v19.16b, %[c0].16b \n\t" 693 /* A.1 load mbuf pointers. */ 694 "ld1 {v24.2d - v25.2d}, [%[elts_p]] \n\t" 695 /* B.3 (CQE 0) extract 16B fields. */ 696 "tbl v20.16b, {v16.16b - v19.16b}, %[cqe_shuf_m].16b \n\t" 697 /* B.4 (CQE 0) adjust CRC length. */ 698 "sub v20.8h, v20.8h, %[crc_adj].8h \n\t" 699 /* D.1 extract op_own byte. */ 700 "tbl %[op_own].8b, {v20.16b - v23.16b}, %[owner_shuf_m].8b \n\t" 701 /* C.2 (CQE 3) adjust flow mark. */ 702 "add v15.4s, v15.4s, %[flow_mark_adj].4s \n\t" 703 /* C.3 (CQE 3) fill in mbuf - rx_descriptor_fields1. */ 704 "st1 {v15.2d}, [%[e3]] \n\t" 705 /* C.2 (CQE 2) adjust flow mark. */ 706 "add v14.4s, v14.4s, %[flow_mark_adj].4s \n\t" 707 /* C.3 (CQE 2) fill in mbuf - rx_descriptor_fields1. */ 708 "st1 {v14.2d}, [%[e2]] \n\t" 709 /* C.1 (CQE 0) generate final structure for mbuf. */ 710 "tbl v12.16b, {v20.16b}, %[mb_shuf_m].16b \n\t" 711 /* C.2 (CQE 1) adjust flow mark. */ 712 "add v13.4s, v13.4s, %[flow_mark_adj].4s \n\t" 713 /* C.3 (CQE 1) fill in mbuf - rx_descriptor_fields1. */ 714 "st1 {v13.2d}, [%[e1]] \n\t" 715 #ifdef MLX5_PMD_SOFT_COUNTERS 716 /* Extract byte_cnt. */ 717 "tbl %[byte_cnt].8b, {v20.16b - v23.16b}, %[len_shuf_m].8b \n\t" 718 #endif 719 /* Extract ptype_info. */ 720 "tbl %[ptype_info].16b, {v20.16b - v23.16b}, %[ptype_shuf_m].16b \n\t" 721 /* Extract flow_tag. */ 722 "tbl %[flow_tag].16b, {v20.16b - v23.16b}, %[ftag_shuf_m].16b \n\t" 723 /* A.2 copy mbuf pointers. */ 724 "st1 {v24.2d - v25.2d}, [%[pkts_p]] \n\t" 725 /* C.2 (CQE 0) adjust flow mark. */ 726 "add v12.4s, v12.4s, %[flow_mark_adj].4s \n\t" 727 /* C.3 (CQE 1) fill in mbuf - rx_descriptor_fields1. */ 728 "st1 {v12.2d}, [%[e0]] \n\t" 729 :[op_own]"=&w"(op_own), 730 [byte_cnt]"=&w"(byte_cnt), 731 [ptype_info]"=&w"(ptype_info), 732 [flow_tag]"=&w"(flow_tag) 733 :[p3]"r"(p3), [p2]"r"(p2), [p1]"r"(p1), [p0]"r"(p0), 734 [e3]"r"(e3), [e2]"r"(e2), [e1]"r"(e1), [e0]"r"(e0), 735 [c3]"w"(c3), [c2]"w"(c2), [c1]"w"(c1), [c0]"w"(c0), 736 [elts_p]"r"(elts_p), 737 [pkts_p]"r"(pkts_p), 738 [cqe_shuf_m]"w"(cqe_shuf_m), 739 [mb_shuf_m]"w"(mb_shuf_m), 740 [owner_shuf_m]"w"(owner_shuf_m), 741 [len_shuf_m]"w"(len_shuf_m), 742 [ptype_shuf_m]"w"(ptype_shuf_m), 743 [ftag_shuf_m]"w"(ftag_shuf_m), 744 [crc_adj]"w"(crc_adj), 745 [flow_mark_adj]"w"(flow_mark_adj) 746 :"memory", 747 "v12", "v13", "v14", "v15", 748 "v16", "v17", "v18", "v19", 749 "v20", "v21", "v22", "v23", 750 "v24", "v25"); 751 /* D.2 flip owner bit to mark CQEs from last round. */ 752 owner_mask = vand_u16(op_own, owner_check); 753 owner_mask = vceq_u16(owner_mask, ownership); 754 /* D.3 get mask for invalidated CQEs. */ 755 opcode = vand_u16(op_own, opcode_check); 756 invalid_mask = vceq_u16(opcode_check, opcode); 757 /* E.1 find compressed CQE format. */ 758 comp_mask = vand_u16(op_own, format_check); 759 comp_mask = vceq_u16(comp_mask, format_check); 760 /* D.4 mask out beyond boundary. */ 761 invalid_mask = vorr_u16(invalid_mask, mask); 762 /* D.5 merge invalid_mask with invalid owner. */ 763 invalid_mask = vorr_u16(invalid_mask, owner_mask); 764 /* E.2 mask out invalid entries. */ 765 comp_mask = vbic_u16(comp_mask, invalid_mask); 766 /* E.3 get the first compressed CQE. */ 767 comp_idx = __builtin_clzl(vget_lane_u64(vreinterpret_u64_u16( 768 comp_mask), 0)) / 769 (sizeof(uint16_t) * 8); 770 /* D.6 mask out entries after the compressed CQE. */ 771 mask = vcreate_u16(comp_idx < MLX5_VPMD_DESCS_PER_LOOP ? 772 -1UL >> (comp_idx * sizeof(uint16_t) * 8) : 773 0); 774 invalid_mask = vorr_u16(invalid_mask, mask); 775 /* D.7 count non-compressed valid CQEs. */ 776 n = __builtin_clzl(vget_lane_u64(vreinterpret_u64_u16( 777 invalid_mask), 0)) / (sizeof(uint16_t) * 8); 778 nocmp_n += n; 779 /* D.2 get the final invalid mask. */ 780 mask = vcreate_u16(n < MLX5_VPMD_DESCS_PER_LOOP ? 781 -1UL >> (n * sizeof(uint16_t) * 8) : 0); 782 invalid_mask = vorr_u16(invalid_mask, mask); 783 /* D.3 check error in opcode. */ 784 opcode = vceq_u16(resp_err_check, opcode); 785 opcode = vbic_u16(opcode, invalid_mask); 786 /* D.4 mark if any error is set */ 787 *err |= vget_lane_u64(vreinterpret_u64_u16(opcode), 0); 788 /* C.4 fill in mbuf - rearm_data and packet_type. */ 789 rxq_cq_to_ptype_oflags_v(rxq, ptype_info, flow_tag, 790 opcode, &elts[pos]); 791 if (rxq->hw_timestamp) { 792 int offset = rxq->timestamp_offset; 793 if (rxq->rt_timestamp) { 794 struct mlx5_dev_ctx_shared *sh = rxq->sh; 795 uint64_t ts; 796 797 ts = rte_be_to_cpu_64 798 (container_of(p0, struct mlx5_cqe, 799 pkt_info)->timestamp); 800 mlx5_timestamp_set(elts[pos], offset, 801 mlx5_txpp_convert_rx_ts(sh, ts)); 802 ts = rte_be_to_cpu_64 803 (container_of(p1, struct mlx5_cqe, 804 pkt_info)->timestamp); 805 mlx5_timestamp_set(elts[pos + 1], offset, 806 mlx5_txpp_convert_rx_ts(sh, ts)); 807 ts = rte_be_to_cpu_64 808 (container_of(p2, struct mlx5_cqe, 809 pkt_info)->timestamp); 810 mlx5_timestamp_set(elts[pos + 2], offset, 811 mlx5_txpp_convert_rx_ts(sh, ts)); 812 ts = rte_be_to_cpu_64 813 (container_of(p3, struct mlx5_cqe, 814 pkt_info)->timestamp); 815 mlx5_timestamp_set(elts[pos + 3], offset, 816 mlx5_txpp_convert_rx_ts(sh, ts)); 817 } else { 818 mlx5_timestamp_set(elts[pos], offset, 819 rte_be_to_cpu_64(container_of(p0, 820 struct mlx5_cqe, pkt_info)->timestamp)); 821 mlx5_timestamp_set(elts[pos + 1], offset, 822 rte_be_to_cpu_64(container_of(p1, 823 struct mlx5_cqe, pkt_info)->timestamp)); 824 mlx5_timestamp_set(elts[pos + 2], offset, 825 rte_be_to_cpu_64(container_of(p2, 826 struct mlx5_cqe, pkt_info)->timestamp)); 827 mlx5_timestamp_set(elts[pos + 3], offset, 828 rte_be_to_cpu_64(container_of(p3, 829 struct mlx5_cqe, pkt_info)->timestamp)); 830 } 831 } 832 if (rxq->dynf_meta) { 833 /* This code is subject for futher optimization. */ 834 int32_t offs = rxq->flow_meta_offset; 835 uint32_t mask = rxq->flow_meta_port_mask; 836 837 *RTE_MBUF_DYNFIELD(pkts[pos], offs, uint32_t *) = 838 container_of(p0, struct mlx5_cqe, 839 pkt_info)->flow_table_metadata & 840 mask; 841 *RTE_MBUF_DYNFIELD(pkts[pos + 1], offs, uint32_t *) = 842 container_of(p1, struct mlx5_cqe, 843 pkt_info)->flow_table_metadata & 844 mask; 845 *RTE_MBUF_DYNFIELD(pkts[pos + 2], offs, uint32_t *) = 846 container_of(p2, struct mlx5_cqe, 847 pkt_info)->flow_table_metadata & 848 mask; 849 *RTE_MBUF_DYNFIELD(pkts[pos + 3], offs, uint32_t *) = 850 container_of(p3, struct mlx5_cqe, 851 pkt_info)->flow_table_metadata & 852 mask; 853 if (*RTE_MBUF_DYNFIELD(pkts[pos], offs, uint32_t *)) 854 elts[pos]->ol_flags |= rxq->flow_meta_mask; 855 if (*RTE_MBUF_DYNFIELD(pkts[pos + 1], offs, uint32_t *)) 856 elts[pos + 1]->ol_flags |= rxq->flow_meta_mask; 857 if (*RTE_MBUF_DYNFIELD(pkts[pos + 2], offs, uint32_t *)) 858 elts[pos + 2]->ol_flags |= rxq->flow_meta_mask; 859 if (*RTE_MBUF_DYNFIELD(pkts[pos + 3], offs, uint32_t *)) 860 elts[pos + 3]->ol_flags |= rxq->flow_meta_mask; 861 } 862 #ifdef MLX5_PMD_SOFT_COUNTERS 863 /* Add up received bytes count. */ 864 byte_cnt = vbic_u16(byte_cnt, invalid_mask); 865 rcvd_byte += vget_lane_u64(vpaddl_u32(vpaddl_u16(byte_cnt)), 0); 866 #endif 867 /* 868 * Break the loop unless more valid CQE is expected, or if 869 * there's a compressed CQE. 870 */ 871 if (n != MLX5_VPMD_DESCS_PER_LOOP) 872 break; 873 } 874 #ifdef MLX5_PMD_SOFT_COUNTERS 875 rxq->stats.ipackets += nocmp_n; 876 rxq->stats.ibytes += rcvd_byte; 877 #endif 878 if (comp_idx == n) 879 *comp = comp_idx; 880 return nocmp_n; 881 } 882 883 #endif /* RTE_PMD_MLX5_RXTX_VEC_NEON_H_ */ 884