1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2017 6WIND S.A. 3 * Copyright 2017 Mellanox Technologies, Ltd 4 */ 5 6 #ifndef RTE_PMD_MLX5_RXTX_VEC_NEON_H_ 7 #define RTE_PMD_MLX5_RXTX_VEC_NEON_H_ 8 9 #include <assert.h> 10 #include <stdint.h> 11 #include <string.h> 12 #include <stdlib.h> 13 #include <arm_neon.h> 14 15 #include <rte_mbuf.h> 16 #include <rte_mempool.h> 17 #include <rte_prefetch.h> 18 19 #include "mlx5.h" 20 #include "mlx5_utils.h" 21 #include "mlx5_rxtx.h" 22 #include "mlx5_rxtx_vec.h" 23 #include "mlx5_autoconf.h" 24 #include "mlx5_defs.h" 25 #include "mlx5_prm.h" 26 27 #pragma GCC diagnostic ignored "-Wcast-qual" 28 29 /** 30 * Fill in buffer descriptors in a multi-packet send descriptor. 31 * 32 * @param txq 33 * Pointer to TX queue structure. 34 * @param dseg 35 * Pointer to buffer descriptor to be written. 36 * @param pkts 37 * Pointer to array of packets to be sent. 38 * @param n 39 * Number of packets to be filled. 40 */ 41 static inline void 42 txq_wr_dseg_v(struct mlx5_txq_data *txq, uint8_t *dseg, 43 struct rte_mbuf **pkts, unsigned int n) 44 { 45 unsigned int pos; 46 uintptr_t addr; 47 const uint8x16_t dseg_shuf_m = { 48 3, 2, 1, 0, /* length, bswap32 */ 49 4, 5, 6, 7, /* lkey */ 50 15, 14, 13, 12, /* addr, bswap64 */ 51 11, 10, 9, 8 52 }; 53 #ifdef MLX5_PMD_SOFT_COUNTERS 54 uint32_t tx_byte = 0; 55 #endif 56 57 for (pos = 0; pos < n; ++pos, dseg += MLX5_WQE_DWORD_SIZE) { 58 uint8x16_t desc; 59 struct rte_mbuf *pkt = pkts[pos]; 60 61 addr = rte_pktmbuf_mtod(pkt, uintptr_t); 62 desc = vreinterpretq_u8_u32((uint32x4_t) { 63 DATA_LEN(pkt), 64 mlx5_tx_mb2mr(txq, pkt), 65 addr, 66 addr >> 32 }); 67 desc = vqtbl1q_u8(desc, dseg_shuf_m); 68 vst1q_u8(dseg, desc); 69 #ifdef MLX5_PMD_SOFT_COUNTERS 70 tx_byte += DATA_LEN(pkt); 71 #endif 72 } 73 #ifdef MLX5_PMD_SOFT_COUNTERS 74 txq->stats.obytes += tx_byte; 75 #endif 76 } 77 78 /** 79 * Send multi-segmented packets until it encounters a single segment packet in 80 * the pkts list. 81 * 82 * @param txq 83 * Pointer to TX queue structure. 84 * @param pkts 85 * Pointer to array of packets to be sent. 86 * @param pkts_n 87 * Number of packets to be sent. 88 * 89 * @return 90 * Number of packets successfully transmitted (<= pkts_n). 91 */ 92 static uint16_t 93 txq_scatter_v(struct mlx5_txq_data *txq, struct rte_mbuf **pkts, 94 uint16_t pkts_n) 95 { 96 uint16_t elts_head = txq->elts_head; 97 const uint16_t elts_n = 1 << txq->elts_n; 98 const uint16_t elts_m = elts_n - 1; 99 const uint16_t wq_n = 1 << txq->wqe_n; 100 const uint16_t wq_mask = wq_n - 1; 101 const unsigned int nb_dword_per_wqebb = 102 MLX5_WQE_SIZE / MLX5_WQE_DWORD_SIZE; 103 const unsigned int nb_dword_in_hdr = 104 sizeof(struct mlx5_wqe) / MLX5_WQE_DWORD_SIZE; 105 unsigned int n; 106 volatile struct mlx5_wqe *wqe = NULL; 107 108 assert(elts_n > pkts_n); 109 mlx5_tx_complete(txq); 110 /* A CQE slot must always be available. */ 111 assert((1u << txq->cqe_n) - (txq->cq_pi - txq->cq_ci)); 112 if (unlikely(!pkts_n)) 113 return 0; 114 for (n = 0; n < pkts_n; ++n) { 115 struct rte_mbuf *buf = pkts[n]; 116 unsigned int segs_n = buf->nb_segs; 117 unsigned int ds = nb_dword_in_hdr; 118 unsigned int len = PKT_LEN(buf); 119 uint16_t wqe_ci = txq->wqe_ci; 120 const uint8x16_t ctrl_shuf_m = { 121 3, 2, 1, 0, /* bswap32 */ 122 7, 6, 5, 4, /* bswap32 */ 123 11, 10, 9, 8, /* bswap32 */ 124 12, 13, 14, 15 125 }; 126 uint8_t cs_flags; 127 uint16_t max_elts; 128 uint16_t max_wqe; 129 uint8x16_t *t_wqe; 130 uint8_t *dseg; 131 uint8x16_t ctrl; 132 133 assert(segs_n); 134 max_elts = elts_n - (elts_head - txq->elts_tail); 135 max_wqe = wq_n - (txq->wqe_ci - txq->wqe_pi); 136 /* 137 * A MPW session consumes 2 WQEs at most to 138 * include MLX5_MPW_DSEG_MAX pointers. 139 */ 140 if (segs_n == 1 || 141 max_elts < segs_n || max_wqe < 2) 142 break; 143 wqe = &((volatile struct mlx5_wqe64 *) 144 txq->wqes)[wqe_ci & wq_mask].hdr; 145 cs_flags = txq_ol_cksum_to_cs(buf); 146 /* Title WQEBB pointer. */ 147 t_wqe = (uint8x16_t *)wqe; 148 dseg = (uint8_t *)(wqe + 1); 149 do { 150 if (!(ds++ % nb_dword_per_wqebb)) { 151 dseg = (uint8_t *) 152 &((volatile struct mlx5_wqe64 *) 153 txq->wqes)[++wqe_ci & wq_mask]; 154 } 155 txq_wr_dseg_v(txq, dseg, &buf, 1); 156 dseg += MLX5_WQE_DWORD_SIZE; 157 (*txq->elts)[elts_head++ & elts_m] = buf; 158 buf = buf->next; 159 } while (--segs_n); 160 ++wqe_ci; 161 /* Fill CTRL in the header. */ 162 ctrl = vreinterpretq_u8_u32((uint32x4_t) { 163 MLX5_OPC_MOD_MPW << 24 | 164 txq->wqe_ci << 8 | MLX5_OPCODE_TSO, 165 txq->qp_num_8s | ds, 0, 0}); 166 ctrl = vqtbl1q_u8(ctrl, ctrl_shuf_m); 167 vst1q_u8((void *)t_wqe, ctrl); 168 /* Fill ESEG in the header. */ 169 vst1q_u16((void *)(t_wqe + 1), 170 (uint16x8_t) { 0, 0, cs_flags, rte_cpu_to_be_16(len), 171 0, 0, 0, 0 }); 172 txq->wqe_ci = wqe_ci; 173 } 174 if (!n) 175 return 0; 176 txq->elts_comp += (uint16_t)(elts_head - txq->elts_head); 177 txq->elts_head = elts_head; 178 if (txq->elts_comp >= MLX5_TX_COMP_THRESH) { 179 wqe->ctrl[2] = rte_cpu_to_be_32(8); 180 wqe->ctrl[3] = txq->elts_head; 181 txq->elts_comp = 0; 182 #ifndef NDEBUG 183 ++txq->cq_pi; 184 #endif 185 } 186 #ifdef MLX5_PMD_SOFT_COUNTERS 187 txq->stats.opackets += n; 188 #endif 189 mlx5_tx_dbrec(txq, wqe); 190 return n; 191 } 192 193 /** 194 * Send burst of packets with Enhanced MPW. If it encounters a multi-seg packet, 195 * it returns to make it processed by txq_scatter_v(). All the packets in 196 * the pkts list should be single segment packets having same offload flags. 197 * This must be checked by txq_count_contig_single_seg() and txq_calc_offload(). 198 * 199 * @param txq 200 * Pointer to TX queue structure. 201 * @param pkts 202 * Pointer to array of packets to be sent. 203 * @param pkts_n 204 * Number of packets to be sent (<= MLX5_VPMD_TX_MAX_BURST). 205 * @param cs_flags 206 * Checksum offload flags to be written in the descriptor. 207 * 208 * @return 209 * Number of packets successfully transmitted (<= pkts_n). 210 */ 211 static inline uint16_t 212 txq_burst_v(struct mlx5_txq_data *txq, struct rte_mbuf **pkts, uint16_t pkts_n, 213 uint8_t cs_flags) 214 { 215 struct rte_mbuf **elts; 216 uint16_t elts_head = txq->elts_head; 217 const uint16_t elts_n = 1 << txq->elts_n; 218 const uint16_t elts_m = elts_n - 1; 219 const unsigned int nb_dword_per_wqebb = 220 MLX5_WQE_SIZE / MLX5_WQE_DWORD_SIZE; 221 const unsigned int nb_dword_in_hdr = 222 sizeof(struct mlx5_wqe) / MLX5_WQE_DWORD_SIZE; 223 unsigned int n = 0; 224 unsigned int pos; 225 uint16_t max_elts; 226 uint16_t max_wqe; 227 uint32_t comp_req = 0; 228 const uint16_t wq_n = 1 << txq->wqe_n; 229 const uint16_t wq_mask = wq_n - 1; 230 uint16_t wq_idx = txq->wqe_ci & wq_mask; 231 volatile struct mlx5_wqe64 *wq = 232 &((volatile struct mlx5_wqe64 *)txq->wqes)[wq_idx]; 233 volatile struct mlx5_wqe *wqe = (volatile struct mlx5_wqe *)wq; 234 const uint8x16_t ctrl_shuf_m = { 235 3, 2, 1, 0, /* bswap32 */ 236 7, 6, 5, 4, /* bswap32 */ 237 11, 10, 9, 8, /* bswap32 */ 238 12, 13, 14, 15 239 }; 240 uint8x16_t *t_wqe; 241 uint8_t *dseg; 242 uint8x16_t ctrl; 243 244 /* Make sure all packets can fit into a single WQE. */ 245 assert(elts_n > pkts_n); 246 mlx5_tx_complete(txq); 247 max_elts = (elts_n - (elts_head - txq->elts_tail)); 248 /* A CQE slot must always be available. */ 249 assert((1u << txq->cqe_n) - (txq->cq_pi - txq->cq_ci)); 250 max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi); 251 pkts_n = RTE_MIN((unsigned int)RTE_MIN(pkts_n, max_wqe), max_elts); 252 if (unlikely(!pkts_n)) 253 return 0; 254 elts = &(*txq->elts)[elts_head & elts_m]; 255 /* Loop for available tailroom first. */ 256 n = RTE_MIN(elts_n - (elts_head & elts_m), pkts_n); 257 for (pos = 0; pos < (n & -2); pos += 2) 258 vst1q_u64((void *)&elts[pos], vld1q_u64((void *)&pkts[pos])); 259 if (n & 1) 260 elts[pos] = pkts[pos]; 261 /* Check if it crosses the end of the queue. */ 262 if (unlikely(n < pkts_n)) { 263 elts = &(*txq->elts)[0]; 264 for (pos = 0; pos < pkts_n - n; ++pos) 265 elts[pos] = pkts[n + pos]; 266 } 267 txq->elts_head += pkts_n; 268 /* Save title WQEBB pointer. */ 269 t_wqe = (uint8x16_t *)wqe; 270 dseg = (uint8_t *)(wqe + 1); 271 /* Calculate the number of entries to the end. */ 272 n = RTE_MIN( 273 (wq_n - wq_idx) * nb_dword_per_wqebb - nb_dword_in_hdr, 274 pkts_n); 275 /* Fill DSEGs. */ 276 txq_wr_dseg_v(txq, dseg, pkts, n); 277 /* Check if it crosses the end of the queue. */ 278 if (n < pkts_n) { 279 dseg = (uint8_t *)txq->wqes; 280 txq_wr_dseg_v(txq, dseg, &pkts[n], pkts_n - n); 281 } 282 if (txq->elts_comp + pkts_n < MLX5_TX_COMP_THRESH) { 283 txq->elts_comp += pkts_n; 284 } else { 285 /* Request a completion. */ 286 txq->elts_comp = 0; 287 #ifndef NDEBUG 288 ++txq->cq_pi; 289 #endif 290 comp_req = 8; 291 } 292 /* Fill CTRL in the header. */ 293 ctrl = vreinterpretq_u8_u32((uint32x4_t) { 294 MLX5_OPC_MOD_ENHANCED_MPSW << 24 | 295 txq->wqe_ci << 8 | MLX5_OPCODE_ENHANCED_MPSW, 296 txq->qp_num_8s | (pkts_n + 2), 297 comp_req, 298 txq->elts_head }); 299 ctrl = vqtbl1q_u8(ctrl, ctrl_shuf_m); 300 vst1q_u8((void *)t_wqe, ctrl); 301 /* Fill ESEG in the header. */ 302 vst1q_u8((void *)(t_wqe + 1), 303 (uint8x16_t) { 0, 0, 0, 0, 304 cs_flags, 0, 0, 0, 305 0, 0, 0, 0, 306 0, 0, 0, 0 }); 307 #ifdef MLX5_PMD_SOFT_COUNTERS 308 txq->stats.opackets += pkts_n; 309 #endif 310 txq->wqe_ci += (nb_dword_in_hdr + pkts_n + (nb_dword_per_wqebb - 1)) / 311 nb_dword_per_wqebb; 312 /* Ring QP doorbell. */ 313 mlx5_tx_dbrec_cond_wmb(txq, wqe, pkts_n < MLX5_VPMD_TX_MAX_BURST); 314 return pkts_n; 315 } 316 317 /** 318 * Store free buffers to RX SW ring. 319 * 320 * @param rxq 321 * Pointer to RX queue structure. 322 * @param pkts 323 * Pointer to array of packets to be stored. 324 * @param pkts_n 325 * Number of packets to be stored. 326 */ 327 static inline void 328 rxq_copy_mbuf_v(struct mlx5_rxq_data *rxq, struct rte_mbuf **pkts, uint16_t n) 329 { 330 const uint16_t q_mask = (1 << rxq->elts_n) - 1; 331 struct rte_mbuf **elts = &(*rxq->elts)[rxq->rq_pi & q_mask]; 332 unsigned int pos; 333 uint16_t p = n & -2; 334 335 for (pos = 0; pos < p; pos += 2) { 336 uint64x2_t mbp; 337 338 mbp = vld1q_u64((void *)&elts[pos]); 339 vst1q_u64((void *)&pkts[pos], mbp); 340 } 341 if (n & 1) 342 pkts[pos] = elts[pos]; 343 } 344 345 /** 346 * Decompress a compressed completion and fill in mbufs in RX SW ring with data 347 * extracted from the title completion descriptor. 348 * 349 * @param rxq 350 * Pointer to RX queue structure. 351 * @param cq 352 * Pointer to completion array having a compressed completion at first. 353 * @param elts 354 * Pointer to SW ring to be filled. The first mbuf has to be pre-built from 355 * the title completion descriptor to be copied to the rest of mbufs. 356 */ 357 static inline void 358 rxq_cq_decompress_v(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cq, 359 struct rte_mbuf **elts) 360 { 361 volatile struct mlx5_mini_cqe8 *mcq = (void *)&(cq + 1)->pkt_info; 362 struct rte_mbuf *t_pkt = elts[0]; /* Title packet is pre-built. */ 363 unsigned int pos; 364 unsigned int i; 365 unsigned int inv = 0; 366 /* Mask to shuffle from extracted mini CQE to mbuf. */ 367 const uint8x16_t mcqe_shuf_m1 = { 368 -1, -1, -1, -1, /* skip packet_type */ 369 7, 6, -1, -1, /* pkt_len, bswap16 */ 370 7, 6, /* data_len, bswap16 */ 371 -1, -1, /* skip vlan_tci */ 372 3, 2, 1, 0 /* hash.rss, bswap32 */ 373 }; 374 const uint8x16_t mcqe_shuf_m2 = { 375 -1, -1, -1, -1, /* skip packet_type */ 376 15, 14, -1, -1, /* pkt_len, bswap16 */ 377 15, 14, /* data_len, bswap16 */ 378 -1, -1, /* skip vlan_tci */ 379 11, 10, 9, 8 /* hash.rss, bswap32 */ 380 }; 381 /* Restore the compressed count. Must be 16 bits. */ 382 const uint16_t mcqe_n = t_pkt->data_len + 383 (rxq->crc_present * ETHER_CRC_LEN); 384 const uint64x2_t rearm = 385 vld1q_u64((void *)&t_pkt->rearm_data); 386 const uint32x4_t rxdf_mask = { 387 0xffffffff, /* packet_type */ 388 0, /* skip pkt_len */ 389 0xffff0000, /* vlan_tci, skip data_len */ 390 0, /* skip hash.rss */ 391 }; 392 const uint8x16_t rxdf = 393 vandq_u8(vld1q_u8((void *)&t_pkt->rx_descriptor_fields1), 394 vreinterpretq_u8_u32(rxdf_mask)); 395 const uint16x8_t crc_adj = { 396 0, 0, 397 rxq->crc_present * ETHER_CRC_LEN, 0, 398 rxq->crc_present * ETHER_CRC_LEN, 0, 399 0, 0 400 }; 401 const uint32_t flow_tag = t_pkt->hash.fdir.hi; 402 #ifdef MLX5_PMD_SOFT_COUNTERS 403 uint32_t rcvd_byte = 0; 404 #endif 405 /* Mask to shuffle byte_cnt to add up stats. Do bswap16 for all. */ 406 const uint8x8_t len_shuf_m = { 407 7, 6, /* 1st mCQE */ 408 15, 14, /* 2nd mCQE */ 409 23, 22, /* 3rd mCQE */ 410 31, 30 /* 4th mCQE */ 411 }; 412 413 /* 414 * A. load mCQEs into a 128bit register. 415 * B. store rearm data to mbuf. 416 * C. combine data from mCQEs with rx_descriptor_fields1. 417 * D. store rx_descriptor_fields1. 418 * E. store flow tag (rte_flow mark). 419 */ 420 for (pos = 0; pos < mcqe_n; ) { 421 uint8_t *p = (void *)&mcq[pos % 8]; 422 uint8_t *e0 = (void *)&elts[pos]->rearm_data; 423 uint8_t *e1 = (void *)&elts[pos + 1]->rearm_data; 424 uint8_t *e2 = (void *)&elts[pos + 2]->rearm_data; 425 uint8_t *e3 = (void *)&elts[pos + 3]->rearm_data; 426 uint16x4_t byte_cnt; 427 #ifdef MLX5_PMD_SOFT_COUNTERS 428 uint16x4_t invalid_mask = 429 vcreate_u16(mcqe_n - pos < MLX5_VPMD_DESCS_PER_LOOP ? 430 -1UL << ((mcqe_n - pos) * 431 sizeof(uint16_t) * 8) : 0); 432 #endif 433 434 if (!(pos & 0x7) && pos + 8 < mcqe_n) 435 rte_prefetch0((void *)(cq + pos + 8)); 436 __asm__ volatile ( 437 /* A.1 load mCQEs into a 128bit register. */ 438 "ld1 {v16.16b - v17.16b}, [%[mcq]] \n\t" 439 /* B.1 store rearm data to mbuf. */ 440 "st1 {%[rearm].2d}, [%[e0]] \n\t" 441 "add %[e0], %[e0], #16 \n\t" 442 "st1 {%[rearm].2d}, [%[e1]] \n\t" 443 "add %[e1], %[e1], #16 \n\t" 444 /* C.1 combine data from mCQEs with rx_descriptor_fields1. */ 445 "tbl v18.16b, {v16.16b}, %[mcqe_shuf_m1].16b \n\t" 446 "tbl v19.16b, {v16.16b}, %[mcqe_shuf_m2].16b \n\t" 447 "sub v18.8h, v18.8h, %[crc_adj].8h \n\t" 448 "sub v19.8h, v19.8h, %[crc_adj].8h \n\t" 449 "orr v18.16b, v18.16b, %[rxdf].16b \n\t" 450 "orr v19.16b, v19.16b, %[rxdf].16b \n\t" 451 /* D.1 store rx_descriptor_fields1. */ 452 "st1 {v18.2d}, [%[e0]] \n\t" 453 "st1 {v19.2d}, [%[e1]] \n\t" 454 /* B.1 store rearm data to mbuf. */ 455 "st1 {%[rearm].2d}, [%[e2]] \n\t" 456 "add %[e2], %[e2], #16 \n\t" 457 "st1 {%[rearm].2d}, [%[e3]] \n\t" 458 "add %[e3], %[e3], #16 \n\t" 459 /* C.1 combine data from mCQEs with rx_descriptor_fields1. */ 460 "tbl v18.16b, {v17.16b}, %[mcqe_shuf_m1].16b \n\t" 461 "tbl v19.16b, {v17.16b}, %[mcqe_shuf_m2].16b \n\t" 462 "sub v18.8h, v18.8h, %[crc_adj].8h \n\t" 463 "sub v19.8h, v19.8h, %[crc_adj].8h \n\t" 464 "orr v18.16b, v18.16b, %[rxdf].16b \n\t" 465 "orr v19.16b, v19.16b, %[rxdf].16b \n\t" 466 /* D.1 store rx_descriptor_fields1. */ 467 "st1 {v18.2d}, [%[e2]] \n\t" 468 "st1 {v19.2d}, [%[e3]] \n\t" 469 #ifdef MLX5_PMD_SOFT_COUNTERS 470 "tbl %[byte_cnt].8b, {v16.16b - v17.16b}, %[len_shuf_m].8b \n\t" 471 #endif 472 :[byte_cnt]"=&w"(byte_cnt) 473 :[mcq]"r"(p), 474 [rxdf]"w"(rxdf), 475 [rearm]"w"(rearm), 476 [e3]"r"(e3), [e2]"r"(e2), [e1]"r"(e1), [e0]"r"(e0), 477 [mcqe_shuf_m1]"w"(mcqe_shuf_m1), 478 [mcqe_shuf_m2]"w"(mcqe_shuf_m2), 479 [crc_adj]"w"(crc_adj), 480 [len_shuf_m]"w"(len_shuf_m) 481 :"memory", "v16", "v17", "v18", "v19"); 482 #ifdef MLX5_PMD_SOFT_COUNTERS 483 byte_cnt = vbic_u16(byte_cnt, invalid_mask); 484 rcvd_byte += vget_lane_u64(vpaddl_u32(vpaddl_u16(byte_cnt)), 0); 485 #endif 486 if (rxq->mark) { 487 /* E.1 store flow tag (rte_flow mark). */ 488 elts[pos]->hash.fdir.hi = flow_tag; 489 elts[pos + 1]->hash.fdir.hi = flow_tag; 490 elts[pos + 2]->hash.fdir.hi = flow_tag; 491 elts[pos + 3]->hash.fdir.hi = flow_tag; 492 } 493 pos += MLX5_VPMD_DESCS_PER_LOOP; 494 /* Move to next CQE and invalidate consumed CQEs. */ 495 if (!(pos & 0x7) && pos < mcqe_n) { 496 mcq = (void *)&(cq + pos)->pkt_info; 497 for (i = 0; i < 8; ++i) 498 cq[inv++].op_own = MLX5_CQE_INVALIDATE; 499 } 500 } 501 /* Invalidate the rest of CQEs. */ 502 for (; inv < mcqe_n; ++inv) 503 cq[inv].op_own = MLX5_CQE_INVALIDATE; 504 #ifdef MLX5_PMD_SOFT_COUNTERS 505 rxq->stats.ipackets += mcqe_n; 506 rxq->stats.ibytes += rcvd_byte; 507 #endif 508 rxq->cq_ci += mcqe_n; 509 } 510 511 /** 512 * Calculate packet type and offload flag for mbuf and store it. 513 * 514 * @param rxq 515 * Pointer to RX queue structure. 516 * @param ptype_info 517 * Array of four 4bytes packet type info extracted from the original 518 * completion descriptor. 519 * @param flow_tag 520 * Array of four 4bytes flow ID extracted from the original completion 521 * descriptor. 522 * @param op_err 523 * Opcode vector having responder error status. Each field is 4B. 524 * @param pkts 525 * Pointer to array of packets to be filled. 526 */ 527 static inline void 528 rxq_cq_to_ptype_oflags_v(struct mlx5_rxq_data *rxq, 529 uint32x4_t ptype_info, uint32x4_t flow_tag, 530 uint16x4_t op_err, struct rte_mbuf **pkts) 531 { 532 uint16x4_t ptype; 533 uint32x4_t pinfo, cv_flags; 534 uint32x4_t ol_flags = 535 vdupq_n_u32(rxq->rss_hash * PKT_RX_RSS_HASH | 536 rxq->hw_timestamp * PKT_RX_TIMESTAMP); 537 const uint32x4_t ptype_ol_mask = { 0x106, 0x106, 0x106, 0x106 }; 538 const uint8x16_t cv_flag_sel = { 539 0, 540 (uint8_t)(PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED), 541 (uint8_t)(PKT_RX_IP_CKSUM_GOOD >> 1), 542 0, 543 (uint8_t)(PKT_RX_L4_CKSUM_GOOD >> 1), 544 0, 545 (uint8_t)((PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD) >> 1), 546 0, 0, 0, 0, 0, 0, 0, 0, 0 547 }; 548 const uint32x4_t cv_mask = 549 vdupq_n_u32(PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD | 550 PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED); 551 const uint64x1_t mbuf_init = vld1_u64(&rxq->mbuf_initializer); 552 const uint64x1_t r32_mask = vcreate_u64(0xffffffff); 553 uint64x2_t rearm0, rearm1, rearm2, rearm3; 554 uint8_t pt_idx0, pt_idx1, pt_idx2, pt_idx3; 555 556 if (rxq->mark) { 557 const uint32x4_t ft_def = vdupq_n_u32(MLX5_FLOW_MARK_DEFAULT); 558 const uint32x4_t fdir_flags = vdupq_n_u32(PKT_RX_FDIR); 559 uint32x4_t fdir_id_flags = vdupq_n_u32(PKT_RX_FDIR_ID); 560 uint32x4_t invalid_mask; 561 562 /* Check if flow tag is non-zero then set PKT_RX_FDIR. */ 563 invalid_mask = vceqzq_u32(flow_tag); 564 ol_flags = vorrq_u32(ol_flags, 565 vbicq_u32(fdir_flags, invalid_mask)); 566 /* Mask out invalid entries. */ 567 fdir_id_flags = vbicq_u32(fdir_id_flags, invalid_mask); 568 /* Check if flow tag MLX5_FLOW_MARK_DEFAULT. */ 569 ol_flags = vorrq_u32(ol_flags, 570 vbicq_u32(fdir_id_flags, 571 vceqq_u32(flow_tag, ft_def))); 572 } 573 /* 574 * ptype_info has the following: 575 * bit[1] = l3_ok 576 * bit[2] = l4_ok 577 * bit[8] = cv 578 * bit[11:10] = l3_hdr_type 579 * bit[14:12] = l4_hdr_type 580 * bit[15] = ip_frag 581 * bit[16] = tunneled 582 * bit[17] = outer_l3_type 583 */ 584 ptype = vshrn_n_u32(ptype_info, 10); 585 /* Errored packets will have RTE_PTYPE_ALL_MASK. */ 586 ptype = vorr_u16(ptype, op_err); 587 pt_idx0 = vget_lane_u8(vreinterpret_u8_u16(ptype), 6); 588 pt_idx1 = vget_lane_u8(vreinterpret_u8_u16(ptype), 4); 589 pt_idx2 = vget_lane_u8(vreinterpret_u8_u16(ptype), 2); 590 pt_idx3 = vget_lane_u8(vreinterpret_u8_u16(ptype), 0); 591 pkts[0]->packet_type = mlx5_ptype_table[pt_idx0] | 592 !!(pt_idx0 & (1 << 6)) * rxq->tunnel; 593 pkts[1]->packet_type = mlx5_ptype_table[pt_idx1] | 594 !!(pt_idx1 & (1 << 6)) * rxq->tunnel; 595 pkts[2]->packet_type = mlx5_ptype_table[pt_idx2] | 596 !!(pt_idx2 & (1 << 6)) * rxq->tunnel; 597 pkts[3]->packet_type = mlx5_ptype_table[pt_idx3] | 598 !!(pt_idx3 & (1 << 6)) * rxq->tunnel; 599 /* Fill flags for checksum and VLAN. */ 600 pinfo = vandq_u32(ptype_info, ptype_ol_mask); 601 pinfo = vreinterpretq_u32_u8( 602 vqtbl1q_u8(cv_flag_sel, vreinterpretq_u8_u32(pinfo))); 603 /* Locate checksum flags at byte[2:1] and merge with VLAN flags. */ 604 cv_flags = vshlq_n_u32(pinfo, 9); 605 cv_flags = vorrq_u32(pinfo, cv_flags); 606 /* Move back flags to start from byte[0]. */ 607 cv_flags = vshrq_n_u32(cv_flags, 8); 608 /* Mask out garbage bits. */ 609 cv_flags = vandq_u32(cv_flags, cv_mask); 610 /* Merge to ol_flags. */ 611 ol_flags = vorrq_u32(ol_flags, cv_flags); 612 /* Merge mbuf_init and ol_flags, and store. */ 613 rearm0 = vcombine_u64(mbuf_init, 614 vshr_n_u64(vget_high_u64(vreinterpretq_u64_u32( 615 ol_flags)), 32)); 616 rearm1 = vcombine_u64(mbuf_init, 617 vand_u64(vget_high_u64(vreinterpretq_u64_u32( 618 ol_flags)), r32_mask)); 619 rearm2 = vcombine_u64(mbuf_init, 620 vshr_n_u64(vget_low_u64(vreinterpretq_u64_u32( 621 ol_flags)), 32)); 622 rearm3 = vcombine_u64(mbuf_init, 623 vand_u64(vget_low_u64(vreinterpretq_u64_u32( 624 ol_flags)), r32_mask)); 625 vst1q_u64((void *)&pkts[0]->rearm_data, rearm0); 626 vst1q_u64((void *)&pkts[1]->rearm_data, rearm1); 627 vst1q_u64((void *)&pkts[2]->rearm_data, rearm2); 628 vst1q_u64((void *)&pkts[3]->rearm_data, rearm3); 629 } 630 631 /** 632 * Receive burst of packets. An errored completion also consumes a mbuf, but the 633 * packet_type is set to be RTE_PTYPE_ALL_MASK. Marked mbufs should be freed 634 * before returning to application. 635 * 636 * @param rxq 637 * Pointer to RX queue structure. 638 * @param[out] pkts 639 * Array to store received packets. 640 * @param pkts_n 641 * Maximum number of packets in array. 642 * @param[out] err 643 * Pointer to a flag. Set non-zero value if pkts array has at least one error 644 * packet to handle. 645 * 646 * @return 647 * Number of packets received including errors (<= pkts_n). 648 */ 649 static inline uint16_t 650 rxq_burst_v(struct mlx5_rxq_data *rxq, struct rte_mbuf **pkts, uint16_t pkts_n, 651 uint64_t *err) 652 { 653 const uint16_t q_n = 1 << rxq->cqe_n; 654 const uint16_t q_mask = q_n - 1; 655 volatile struct mlx5_cqe *cq; 656 struct rte_mbuf **elts; 657 unsigned int pos; 658 uint64_t n; 659 uint16_t repl_n; 660 uint64_t comp_idx = MLX5_VPMD_DESCS_PER_LOOP; 661 uint16_t nocmp_n = 0; 662 uint16_t rcvd_pkt = 0; 663 unsigned int cq_idx = rxq->cq_ci & q_mask; 664 unsigned int elts_idx; 665 const uint16x4_t ownership = vdup_n_u16(!(rxq->cq_ci & (q_mask + 1))); 666 const uint16x4_t owner_check = vcreate_u16(0x0001000100010001); 667 const uint16x4_t opcode_check = vcreate_u16(0x00f000f000f000f0); 668 const uint16x4_t format_check = vcreate_u16(0x000c000c000c000c); 669 const uint16x4_t resp_err_check = vcreate_u16(0x00e000e000e000e0); 670 #ifdef MLX5_PMD_SOFT_COUNTERS 671 uint32_t rcvd_byte = 0; 672 #endif 673 /* Mask to generate 16B length vector. */ 674 const uint8x8_t len_shuf_m = { 675 52, 53, /* 4th CQE */ 676 36, 37, /* 3rd CQE */ 677 20, 21, /* 2nd CQE */ 678 4, 5 /* 1st CQE */ 679 }; 680 /* Mask to extract 16B data from a 64B CQE. */ 681 const uint8x16_t cqe_shuf_m = { 682 28, 29, /* hdr_type_etc */ 683 0, /* pkt_info */ 684 -1, /* null */ 685 47, 46, /* byte_cnt, bswap16 */ 686 31, 30, /* vlan_info, bswap16 */ 687 15, 14, 13, 12, /* rx_hash_res, bswap32 */ 688 57, 58, 59, /* flow_tag */ 689 63 /* op_own */ 690 }; 691 /* Mask to generate 16B data for mbuf. */ 692 const uint8x16_t mb_shuf_m = { 693 4, 5, -1, -1, /* pkt_len */ 694 4, 5, /* data_len */ 695 6, 7, /* vlan_tci */ 696 8, 9, 10, 11, /* hash.rss */ 697 12, 13, 14, -1 /* hash.fdir.hi */ 698 }; 699 /* Mask to generate 16B owner vector. */ 700 const uint8x8_t owner_shuf_m = { 701 63, -1, /* 4th CQE */ 702 47, -1, /* 3rd CQE */ 703 31, -1, /* 2nd CQE */ 704 15, -1 /* 1st CQE */ 705 }; 706 /* Mask to generate a vector having packet_type/ol_flags. */ 707 const uint8x16_t ptype_shuf_m = { 708 48, 49, 50, -1, /* 4th CQE */ 709 32, 33, 34, -1, /* 3rd CQE */ 710 16, 17, 18, -1, /* 2nd CQE */ 711 0, 1, 2, -1 /* 1st CQE */ 712 }; 713 /* Mask to generate a vector having flow tags. */ 714 const uint8x16_t ftag_shuf_m = { 715 60, 61, 62, -1, /* 4th CQE */ 716 44, 45, 46, -1, /* 3rd CQE */ 717 28, 29, 30, -1, /* 2nd CQE */ 718 12, 13, 14, -1 /* 1st CQE */ 719 }; 720 const uint16x8_t crc_adj = { 721 0, 0, rxq->crc_present * ETHER_CRC_LEN, 0, 0, 0, 0, 0 722 }; 723 const uint32x4_t flow_mark_adj = { 0, 0, 0, rxq->mark * (-1) }; 724 725 assert(rxq->sges_n == 0); 726 assert(rxq->cqe_n == rxq->elts_n); 727 cq = &(*rxq->cqes)[cq_idx]; 728 rte_prefetch_non_temporal(cq); 729 rte_prefetch_non_temporal(cq + 1); 730 rte_prefetch_non_temporal(cq + 2); 731 rte_prefetch_non_temporal(cq + 3); 732 pkts_n = RTE_MIN(pkts_n, MLX5_VPMD_RX_MAX_BURST); 733 /* 734 * Order of indexes: 735 * rq_ci >= cq_ci >= rq_pi 736 * Definition of indexes: 737 * rq_ci - cq_ci := # of buffers owned by HW (posted). 738 * cq_ci - rq_pi := # of buffers not returned to app (decompressed). 739 * N - (rq_ci - rq_pi) := # of buffers consumed (to be replenished). 740 */ 741 repl_n = q_n - (rxq->rq_ci - rxq->rq_pi); 742 if (repl_n >= MLX5_VPMD_RXQ_RPLNSH_THRESH) 743 mlx5_rx_replenish_bulk_mbuf(rxq, repl_n); 744 /* See if there're unreturned mbufs from compressed CQE. */ 745 rcvd_pkt = rxq->cq_ci - rxq->rq_pi; 746 if (rcvd_pkt > 0) { 747 rcvd_pkt = RTE_MIN(rcvd_pkt, pkts_n); 748 rxq_copy_mbuf_v(rxq, pkts, rcvd_pkt); 749 rxq->rq_pi += rcvd_pkt; 750 pkts += rcvd_pkt; 751 } 752 elts_idx = rxq->rq_pi & q_mask; 753 elts = &(*rxq->elts)[elts_idx]; 754 /* Not to overflow pkts array. */ 755 pkts_n = RTE_ALIGN_FLOOR(pkts_n - rcvd_pkt, MLX5_VPMD_DESCS_PER_LOOP); 756 /* Not to cross queue end. */ 757 pkts_n = RTE_MIN(pkts_n, q_n - elts_idx); 758 if (!pkts_n) 759 return rcvd_pkt; 760 /* At this point, there shouldn't be any remained packets. */ 761 assert(rxq->rq_pi == rxq->cq_ci); 762 /* 763 * Note that vectors have reverse order - {v3, v2, v1, v0}, because 764 * there's no instruction to count trailing zeros. __builtin_clzl() is 765 * used instead. 766 * 767 * A. copy 4 mbuf pointers from elts ring to returing pkts. 768 * B. load 64B CQE and extract necessary fields 769 * Final 16bytes cqes[] extracted from original 64bytes CQE has the 770 * following structure: 771 * struct { 772 * uint16_t hdr_type_etc; 773 * uint8_t pkt_info; 774 * uint8_t rsvd; 775 * uint16_t byte_cnt; 776 * uint16_t vlan_info; 777 * uint32_t rx_has_res; 778 * uint8_t flow_tag[3]; 779 * uint8_t op_own; 780 * } c; 781 * C. fill in mbuf. 782 * D. get valid CQEs. 783 * E. find compressed CQE. 784 */ 785 for (pos = 0; 786 pos < pkts_n; 787 pos += MLX5_VPMD_DESCS_PER_LOOP) { 788 uint16x4_t op_own; 789 uint16x4_t opcode, owner_mask, invalid_mask; 790 uint16x4_t comp_mask; 791 uint16x4_t mask; 792 uint16x4_t byte_cnt; 793 uint32x4_t ptype_info, flow_tag; 794 register uint64x2_t c0, c1, c2, c3; 795 uint8_t *p0, *p1, *p2, *p3; 796 uint8_t *e0 = (void *)&elts[pos]->pkt_len; 797 uint8_t *e1 = (void *)&elts[pos + 1]->pkt_len; 798 uint8_t *e2 = (void *)&elts[pos + 2]->pkt_len; 799 uint8_t *e3 = (void *)&elts[pos + 3]->pkt_len; 800 void *elts_p = (void *)&elts[pos]; 801 void *pkts_p = (void *)&pkts[pos]; 802 803 /* A.0 do not cross the end of CQ. */ 804 mask = vcreate_u16(pkts_n - pos < MLX5_VPMD_DESCS_PER_LOOP ? 805 -1UL >> ((pkts_n - pos) * 806 sizeof(uint16_t) * 8) : 0); 807 p0 = (void *)&cq[pos].pkt_info; 808 p1 = p0 + (pkts_n - pos > 1) * sizeof(struct mlx5_cqe); 809 p2 = p1 + (pkts_n - pos > 2) * sizeof(struct mlx5_cqe); 810 p3 = p2 + (pkts_n - pos > 3) * sizeof(struct mlx5_cqe); 811 /* B.0 (CQE 3) load a block having op_own. */ 812 c3 = vld1q_u64((uint64_t *)(p3 + 48)); 813 /* B.0 (CQE 2) load a block having op_own. */ 814 c2 = vld1q_u64((uint64_t *)(p2 + 48)); 815 /* B.0 (CQE 1) load a block having op_own. */ 816 c1 = vld1q_u64((uint64_t *)(p1 + 48)); 817 /* B.0 (CQE 0) load a block having op_own. */ 818 c0 = vld1q_u64((uint64_t *)(p0 + 48)); 819 /* Synchronize for loading the rest of blocks. */ 820 rte_cio_rmb(); 821 /* Prefetch next 4 CQEs. */ 822 if (pkts_n - pos >= 2 * MLX5_VPMD_DESCS_PER_LOOP) { 823 unsigned int next = pos + MLX5_VPMD_DESCS_PER_LOOP; 824 rte_prefetch_non_temporal(&cq[next]); 825 rte_prefetch_non_temporal(&cq[next + 1]); 826 rte_prefetch_non_temporal(&cq[next + 2]); 827 rte_prefetch_non_temporal(&cq[next + 3]); 828 } 829 __asm__ volatile ( 830 /* B.1 (CQE 3) load the rest of blocks. */ 831 "ld1 {v16.16b - v18.16b}, [%[p3]] \n\t" 832 /* B.2 (CQE 3) move the block having op_own. */ 833 "mov v19.16b, %[c3].16b \n\t" 834 /* B.3 (CQE 3) extract 16B fields. */ 835 "tbl v23.16b, {v16.16b - v19.16b}, %[cqe_shuf_m].16b \n\t" 836 /* B.1 (CQE 2) load the rest of blocks. */ 837 "ld1 {v16.16b - v18.16b}, [%[p2]] \n\t" 838 /* B.4 (CQE 3) adjust CRC length. */ 839 "sub v23.8h, v23.8h, %[crc_adj].8h \n\t" 840 /* C.1 (CQE 3) generate final structure for mbuf. */ 841 "tbl v15.16b, {v23.16b}, %[mb_shuf_m].16b \n\t" 842 /* B.2 (CQE 2) move the block having op_own. */ 843 "mov v19.16b, %[c2].16b \n\t" 844 /* B.3 (CQE 2) extract 16B fields. */ 845 "tbl v22.16b, {v16.16b - v19.16b}, %[cqe_shuf_m].16b \n\t" 846 /* B.1 (CQE 1) load the rest of blocks. */ 847 "ld1 {v16.16b - v18.16b}, [%[p1]] \n\t" 848 /* B.4 (CQE 2) adjust CRC length. */ 849 "sub v22.8h, v22.8h, %[crc_adj].8h \n\t" 850 /* C.1 (CQE 2) generate final structure for mbuf. */ 851 "tbl v14.16b, {v22.16b}, %[mb_shuf_m].16b \n\t" 852 /* B.2 (CQE 1) move the block having op_own. */ 853 "mov v19.16b, %[c1].16b \n\t" 854 /* B.3 (CQE 1) extract 16B fields. */ 855 "tbl v21.16b, {v16.16b - v19.16b}, %[cqe_shuf_m].16b \n\t" 856 /* B.1 (CQE 0) load the rest of blocks. */ 857 "ld1 {v16.16b - v18.16b}, [%[p0]] \n\t" 858 /* B.4 (CQE 1) adjust CRC length. */ 859 "sub v21.8h, v21.8h, %[crc_adj].8h \n\t" 860 /* C.1 (CQE 1) generate final structure for mbuf. */ 861 "tbl v13.16b, {v21.16b}, %[mb_shuf_m].16b \n\t" 862 /* B.2 (CQE 0) move the block having op_own. */ 863 "mov v19.16b, %[c0].16b \n\t" 864 /* A.1 load mbuf pointers. */ 865 "ld1 {v24.2d - v25.2d}, [%[elts_p]] \n\t" 866 /* B.3 (CQE 0) extract 16B fields. */ 867 "tbl v20.16b, {v16.16b - v19.16b}, %[cqe_shuf_m].16b \n\t" 868 /* B.4 (CQE 0) adjust CRC length. */ 869 "sub v20.8h, v20.8h, %[crc_adj].8h \n\t" 870 /* D.1 extract op_own byte. */ 871 "tbl %[op_own].8b, {v20.16b - v23.16b}, %[owner_shuf_m].8b \n\t" 872 /* C.2 (CQE 3) adjust flow mark. */ 873 "add v15.4s, v15.4s, %[flow_mark_adj].4s \n\t" 874 /* C.3 (CQE 3) fill in mbuf - rx_descriptor_fields1. */ 875 "st1 {v15.2d}, [%[e3]] \n\t" 876 /* C.2 (CQE 2) adjust flow mark. */ 877 "add v14.4s, v14.4s, %[flow_mark_adj].4s \n\t" 878 /* C.3 (CQE 2) fill in mbuf - rx_descriptor_fields1. */ 879 "st1 {v14.2d}, [%[e2]] \n\t" 880 /* C.1 (CQE 0) generate final structure for mbuf. */ 881 "tbl v12.16b, {v20.16b}, %[mb_shuf_m].16b \n\t" 882 /* C.2 (CQE 1) adjust flow mark. */ 883 "add v13.4s, v13.4s, %[flow_mark_adj].4s \n\t" 884 /* C.3 (CQE 1) fill in mbuf - rx_descriptor_fields1. */ 885 "st1 {v13.2d}, [%[e1]] \n\t" 886 #ifdef MLX5_PMD_SOFT_COUNTERS 887 /* Extract byte_cnt. */ 888 "tbl %[byte_cnt].8b, {v20.16b - v23.16b}, %[len_shuf_m].8b \n\t" 889 #endif 890 /* Extract ptype_info. */ 891 "tbl %[ptype_info].16b, {v20.16b - v23.16b}, %[ptype_shuf_m].16b \n\t" 892 /* Extract flow_tag. */ 893 "tbl %[flow_tag].16b, {v20.16b - v23.16b}, %[ftag_shuf_m].16b \n\t" 894 /* A.2 copy mbuf pointers. */ 895 "st1 {v24.2d - v25.2d}, [%[pkts_p]] \n\t" 896 /* C.2 (CQE 0) adjust flow mark. */ 897 "add v12.4s, v12.4s, %[flow_mark_adj].4s \n\t" 898 /* C.3 (CQE 1) fill in mbuf - rx_descriptor_fields1. */ 899 "st1 {v12.2d}, [%[e0]] \n\t" 900 :[op_own]"=&w"(op_own), 901 [byte_cnt]"=&w"(byte_cnt), 902 [ptype_info]"=&w"(ptype_info), 903 [flow_tag]"=&w"(flow_tag) 904 :[p3]"r"(p3), [p2]"r"(p2), [p1]"r"(p1), [p0]"r"(p0), 905 [e3]"r"(e3), [e2]"r"(e2), [e1]"r"(e1), [e0]"r"(e0), 906 [c3]"w"(c3), [c2]"w"(c2), [c1]"w"(c1), [c0]"w"(c0), 907 [elts_p]"r"(elts_p), 908 [pkts_p]"r"(pkts_p), 909 [cqe_shuf_m]"w"(cqe_shuf_m), 910 [mb_shuf_m]"w"(mb_shuf_m), 911 [owner_shuf_m]"w"(owner_shuf_m), 912 [len_shuf_m]"w"(len_shuf_m), 913 [ptype_shuf_m]"w"(ptype_shuf_m), 914 [ftag_shuf_m]"w"(ftag_shuf_m), 915 [crc_adj]"w"(crc_adj), 916 [flow_mark_adj]"w"(flow_mark_adj) 917 :"memory", 918 "v12", "v13", "v14", "v15", 919 "v16", "v17", "v18", "v19", 920 "v20", "v21", "v22", "v23", 921 "v24", "v25"); 922 /* D.2 flip owner bit to mark CQEs from last round. */ 923 owner_mask = vand_u16(op_own, owner_check); 924 owner_mask = vceq_u16(owner_mask, ownership); 925 /* D.3 get mask for invalidated CQEs. */ 926 opcode = vand_u16(op_own, opcode_check); 927 invalid_mask = vceq_u16(opcode_check, opcode); 928 /* E.1 find compressed CQE format. */ 929 comp_mask = vand_u16(op_own, format_check); 930 comp_mask = vceq_u16(comp_mask, format_check); 931 /* D.4 mask out beyond boundary. */ 932 invalid_mask = vorr_u16(invalid_mask, mask); 933 /* D.5 merge invalid_mask with invalid owner. */ 934 invalid_mask = vorr_u16(invalid_mask, owner_mask); 935 /* E.2 mask out invalid entries. */ 936 comp_mask = vbic_u16(comp_mask, invalid_mask); 937 /* E.3 get the first compressed CQE. */ 938 comp_idx = __builtin_clzl(vget_lane_u64(vreinterpret_u64_u16( 939 comp_mask), 0)) / 940 (sizeof(uint16_t) * 8); 941 /* D.6 mask out entries after the compressed CQE. */ 942 mask = vcreate_u16(comp_idx < MLX5_VPMD_DESCS_PER_LOOP ? 943 -1UL >> (comp_idx * sizeof(uint16_t) * 8) : 944 0); 945 invalid_mask = vorr_u16(invalid_mask, mask); 946 /* D.7 count non-compressed valid CQEs. */ 947 n = __builtin_clzl(vget_lane_u64(vreinterpret_u64_u16( 948 invalid_mask), 0)) / (sizeof(uint16_t) * 8); 949 nocmp_n += n; 950 /* D.2 get the final invalid mask. */ 951 mask = vcreate_u16(n < MLX5_VPMD_DESCS_PER_LOOP ? 952 -1UL >> (n * sizeof(uint16_t) * 8) : 0); 953 invalid_mask = vorr_u16(invalid_mask, mask); 954 /* D.3 check error in opcode. */ 955 opcode = vceq_u16(resp_err_check, opcode); 956 opcode = vbic_u16(opcode, invalid_mask); 957 /* D.4 mark if any error is set */ 958 *err |= vget_lane_u64(vreinterpret_u64_u16(opcode), 0); 959 /* C.4 fill in mbuf - rearm_data and packet_type. */ 960 rxq_cq_to_ptype_oflags_v(rxq, ptype_info, flow_tag, 961 opcode, &elts[pos]); 962 if (rxq->hw_timestamp) { 963 elts[pos]->timestamp = 964 rte_be_to_cpu_64( 965 container_of(p0, struct mlx5_cqe, 966 pkt_info)->timestamp); 967 elts[pos + 1]->timestamp = 968 rte_be_to_cpu_64( 969 container_of(p1, struct mlx5_cqe, 970 pkt_info)->timestamp); 971 elts[pos + 2]->timestamp = 972 rte_be_to_cpu_64( 973 container_of(p2, struct mlx5_cqe, 974 pkt_info)->timestamp); 975 elts[pos + 3]->timestamp = 976 rte_be_to_cpu_64( 977 container_of(p3, struct mlx5_cqe, 978 pkt_info)->timestamp); 979 } 980 #ifdef MLX5_PMD_SOFT_COUNTERS 981 /* Add up received bytes count. */ 982 byte_cnt = vbic_u16(byte_cnt, invalid_mask); 983 rcvd_byte += vget_lane_u64(vpaddl_u32(vpaddl_u16(byte_cnt)), 0); 984 #endif 985 /* 986 * Break the loop unless more valid CQE is expected, or if 987 * there's a compressed CQE. 988 */ 989 if (n != MLX5_VPMD_DESCS_PER_LOOP) 990 break; 991 } 992 /* If no new CQE seen, return without updating cq_db. */ 993 if (unlikely(!nocmp_n && comp_idx == MLX5_VPMD_DESCS_PER_LOOP)) 994 return rcvd_pkt; 995 /* Update the consumer indexes for non-compressed CQEs. */ 996 assert(nocmp_n <= pkts_n); 997 rxq->cq_ci += nocmp_n; 998 rxq->rq_pi += nocmp_n; 999 rcvd_pkt += nocmp_n; 1000 #ifdef MLX5_PMD_SOFT_COUNTERS 1001 rxq->stats.ipackets += nocmp_n; 1002 rxq->stats.ibytes += rcvd_byte; 1003 #endif 1004 /* Decompress the last CQE if compressed. */ 1005 if (comp_idx < MLX5_VPMD_DESCS_PER_LOOP && comp_idx == n) { 1006 assert(comp_idx == (nocmp_n % MLX5_VPMD_DESCS_PER_LOOP)); 1007 rxq_cq_decompress_v(rxq, &cq[nocmp_n], &elts[nocmp_n]); 1008 /* Return more packets if needed. */ 1009 if (nocmp_n < pkts_n) { 1010 uint16_t n = rxq->cq_ci - rxq->rq_pi; 1011 1012 n = RTE_MIN(n, pkts_n - nocmp_n); 1013 rxq_copy_mbuf_v(rxq, &pkts[nocmp_n], n); 1014 rxq->rq_pi += n; 1015 rcvd_pkt += n; 1016 } 1017 } 1018 rte_compiler_barrier(); 1019 *rxq->cq_db = rte_cpu_to_be_32(rxq->cq_ci); 1020 return rcvd_pkt; 1021 } 1022 1023 #endif /* RTE_PMD_MLX5_RXTX_VEC_NEON_H_ */ 1024