1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2017 6WIND S.A. 3 * Copyright 2017 Mellanox Technologies, Ltd 4 */ 5 6 #ifndef RTE_PMD_MLX5_RXTX_VEC_NEON_H_ 7 #define RTE_PMD_MLX5_RXTX_VEC_NEON_H_ 8 9 #include <stdint.h> 10 #include <string.h> 11 #include <stdlib.h> 12 #include <arm_neon.h> 13 14 #include <rte_bitops.h> 15 #include <rte_mbuf.h> 16 #include <rte_mempool.h> 17 #include <rte_prefetch.h> 18 19 #include <mlx5_prm.h> 20 21 #include "mlx5_defs.h" 22 #include "mlx5.h" 23 #include "mlx5_utils.h" 24 #include "mlx5_rxtx.h" 25 #include "mlx5_rxtx_vec.h" 26 #include "mlx5_autoconf.h" 27 28 #pragma GCC diagnostic ignored "-Wcast-qual" 29 30 /** 31 * Store free buffers to RX SW ring. 32 * 33 * @param elts 34 * Pointer to SW ring to be filled. 35 * @param pkts 36 * Pointer to array of packets to be stored. 37 * @param pkts_n 38 * Number of packets to be stored. 39 */ 40 static inline void 41 rxq_copy_mbuf_v(struct rte_mbuf **elts, struct rte_mbuf **pkts, uint16_t n) 42 { 43 unsigned int pos; 44 uint16_t p = n & -2; 45 46 for (pos = 0; pos < p; pos += 2) { 47 uint64x2_t mbp; 48 49 mbp = vld1q_u64((void *)&elts[pos]); 50 vst1q_u64((void *)&pkts[pos], mbp); 51 } 52 if (n & 1) 53 pkts[pos] = elts[pos]; 54 } 55 56 /** 57 * Decompress a compressed completion and fill in mbufs in RX SW ring with data 58 * extracted from the title completion descriptor. 59 * 60 * @param rxq 61 * Pointer to RX queue structure. 62 * @param cq 63 * Pointer to completion array having a compressed completion at first. 64 * @param elts 65 * Pointer to SW ring to be filled. The first mbuf has to be pre-built from 66 * the title completion descriptor to be copied to the rest of mbufs. 67 * @param keep 68 * Keep unzipping if the next CQE is the miniCQE array. 69 * 70 * @return 71 * Number of mini-CQEs successfully decompressed. 72 */ 73 static inline uint16_t 74 rxq_cq_decompress_v(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cq, 75 struct rte_mbuf **elts, bool keep) 76 { 77 volatile struct mlx5_mini_cqe8 *mcq = 78 (void *)&(cq + !rxq->cqe_comp_layout)->pkt_info; 79 /* Title packet is pre-built. */ 80 struct rte_mbuf *t_pkt = rxq->cqe_comp_layout ? &rxq->title_pkt : elts[0]; 81 unsigned int pos; 82 unsigned int i; 83 unsigned int inv = 0; 84 /* Mask to shuffle from extracted mini CQE to mbuf. */ 85 const uint8x16_t mcqe_shuf_m1 = { 86 -1, -1, -1, -1, /* skip packet_type */ 87 7, 6, -1, -1, /* pkt_len, bswap16 */ 88 7, 6, /* data_len, bswap16 */ 89 -1, -1, /* skip vlan_tci */ 90 3, 2, 1, 0 /* hash.rss, bswap32 */ 91 }; 92 const uint8x16_t mcqe_shuf_m2 = { 93 -1, -1, -1, -1, /* skip packet_type */ 94 15, 14, -1, -1, /* pkt_len, bswap16 */ 95 15, 14, /* data_len, bswap16 */ 96 -1, -1, /* skip vlan_tci */ 97 11, 10, 9, 8 /* hash.rss, bswap32 */ 98 }; 99 /* Restore the compressed count. Must be 16 bits. */ 100 uint16_t mcqe_n = (rxq->cqe_comp_layout) ? 101 (MLX5_CQE_NUM_MINIS(cq->op_own) + 1) : 102 t_pkt->data_len + (rxq->crc_present * RTE_ETHER_CRC_LEN); 103 uint16_t pkts_n = mcqe_n; 104 const uint64x2_t rearm = 105 vld1q_u64((void *)&t_pkt->rearm_data); 106 const uint32x4_t rxdf_mask = { 107 0xffffffff, /* packet_type */ 108 0, /* skip pkt_len */ 109 0xffff0000, /* vlan_tci, skip data_len */ 110 0, /* skip hash.rss */ 111 }; 112 const uint8x16_t rxdf = 113 vandq_u8(vld1q_u8((void *)&t_pkt->rx_descriptor_fields1), 114 vreinterpretq_u8_u32(rxdf_mask)); 115 const uint16x8_t crc_adj = { 116 0, 0, 117 rxq->crc_present * RTE_ETHER_CRC_LEN, 0, 118 rxq->crc_present * RTE_ETHER_CRC_LEN, 0, 119 0, 0 120 }; 121 uint32x4_t ol_flags = {0, 0, 0, 0}; 122 uint32x4_t ol_flags_mask = {0, 0, 0, 0}; 123 #ifdef MLX5_PMD_SOFT_COUNTERS 124 uint32_t rcvd_byte = 0; 125 #endif 126 /* Mask to shuffle byte_cnt to add up stats. Do bswap16 for all. */ 127 const uint8x8_t len_shuf_m = { 128 7, 6, /* 1st mCQE */ 129 15, 14, /* 2nd mCQE */ 130 23, 22, /* 3rd mCQE */ 131 31, 30 /* 4th mCQE */ 132 }; 133 134 /* 135 * A. load mCQEs into a 128bit register. 136 * B. store rearm data to mbuf. 137 * C. combine data from mCQEs with rx_descriptor_fields1. 138 * D. store rx_descriptor_fields1. 139 * E. store flow tag (rte_flow mark). 140 */ 141 cycle: 142 if (rxq->cqe_comp_layout) 143 rte_prefetch0((void *)(cq + mcqe_n)); 144 for (pos = 0; pos < mcqe_n; ) { 145 uint8_t *p = (void *)&mcq[pos % 8]; 146 uint8_t *e0 = (void *)&elts[pos]->rearm_data; 147 uint8_t *e1 = (void *)&elts[pos + 1]->rearm_data; 148 uint8_t *e2 = (void *)&elts[pos + 2]->rearm_data; 149 uint8_t *e3 = (void *)&elts[pos + 3]->rearm_data; 150 uint16x4_t byte_cnt; 151 #ifdef MLX5_PMD_SOFT_COUNTERS 152 uint16x4_t invalid_mask = 153 vcreate_u16(mcqe_n - pos < MLX5_VPMD_DESCS_PER_LOOP ? 154 -1UL << ((mcqe_n - pos) * 155 sizeof(uint16_t) * 8) : 0); 156 #endif 157 158 if (!rxq->cqe_comp_layout) 159 for (i = 0; i < MLX5_VPMD_DESCS_PER_LOOP; ++i) 160 if (likely(pos + i < mcqe_n)) 161 rte_prefetch0((void *)(cq + pos + i)); 162 __asm__ volatile ( 163 /* A.1 load mCQEs into a 128bit register. */ 164 "ld1 {v16.16b - v17.16b}, [%[mcq]] \n\t" 165 /* B.1 store rearm data to mbuf. */ 166 "st1 {%[rearm].2d}, [%[e0]] \n\t" 167 "add %[e0], %[e0], #16 \n\t" 168 "st1 {%[rearm].2d}, [%[e1]] \n\t" 169 "add %[e1], %[e1], #16 \n\t" 170 /* C.1 combine data from mCQEs with rx_descriptor_fields1. */ 171 "tbl v18.16b, {v16.16b}, %[mcqe_shuf_m1].16b \n\t" 172 "tbl v19.16b, {v16.16b}, %[mcqe_shuf_m2].16b \n\t" 173 "sub v18.8h, v18.8h, %[crc_adj].8h \n\t" 174 "sub v19.8h, v19.8h, %[crc_adj].8h \n\t" 175 "orr v18.16b, v18.16b, %[rxdf].16b \n\t" 176 "orr v19.16b, v19.16b, %[rxdf].16b \n\t" 177 /* D.1 store rx_descriptor_fields1. */ 178 "st1 {v18.2d}, [%[e0]] \n\t" 179 "st1 {v19.2d}, [%[e1]] \n\t" 180 /* B.1 store rearm data to mbuf. */ 181 "st1 {%[rearm].2d}, [%[e2]] \n\t" 182 "add %[e2], %[e2], #16 \n\t" 183 "st1 {%[rearm].2d}, [%[e3]] \n\t" 184 "add %[e3], %[e3], #16 \n\t" 185 /* C.1 combine data from mCQEs with rx_descriptor_fields1. */ 186 "tbl v18.16b, {v17.16b}, %[mcqe_shuf_m1].16b \n\t" 187 "tbl v19.16b, {v17.16b}, %[mcqe_shuf_m2].16b \n\t" 188 "sub v18.8h, v18.8h, %[crc_adj].8h \n\t" 189 "sub v19.8h, v19.8h, %[crc_adj].8h \n\t" 190 "orr v18.16b, v18.16b, %[rxdf].16b \n\t" 191 "orr v19.16b, v19.16b, %[rxdf].16b \n\t" 192 /* D.1 store rx_descriptor_fields1. */ 193 "st1 {v18.2d}, [%[e2]] \n\t" 194 "st1 {v19.2d}, [%[e3]] \n\t" 195 #ifdef MLX5_PMD_SOFT_COUNTERS 196 "tbl %[byte_cnt].8b, {v16.16b - v17.16b}, %[len_shuf_m].8b \n\t" 197 #endif 198 :[byte_cnt]"=&w"(byte_cnt) 199 :[mcq]"r"(p), 200 [rxdf]"w"(rxdf), 201 [rearm]"w"(rearm), 202 [e3]"r"(e3), [e2]"r"(e2), [e1]"r"(e1), [e0]"r"(e0), 203 [mcqe_shuf_m1]"w"(mcqe_shuf_m1), 204 [mcqe_shuf_m2]"w"(mcqe_shuf_m2), 205 [crc_adj]"w"(crc_adj), 206 [len_shuf_m]"w"(len_shuf_m) 207 :"memory", "v16", "v17", "v18", "v19"); 208 #ifdef MLX5_PMD_SOFT_COUNTERS 209 byte_cnt = vbic_u16(byte_cnt, invalid_mask); 210 rcvd_byte += vget_lane_u64(vpaddl_u32(vpaddl_u16(byte_cnt)), 0); 211 #endif 212 if (rxq->mark) { 213 if (rxq->mcqe_format != 214 MLX5_CQE_RESP_FORMAT_FTAG_STRIDX) { 215 const uint32_t flow_tag = t_pkt->hash.fdir.hi; 216 217 /* E.1 store flow tag (rte_flow mark). */ 218 elts[pos]->hash.fdir.hi = flow_tag; 219 elts[pos + 1]->hash.fdir.hi = flow_tag; 220 elts[pos + 2]->hash.fdir.hi = flow_tag; 221 elts[pos + 3]->hash.fdir.hi = flow_tag; 222 } else { 223 const uint32x4_t flow_mark_adj = { 224 -1, -1, -1, -1 }; 225 const uint8x16_t flow_mark_shuf = { 226 28, 24, 25, -1, 227 20, 16, 17, -1, 228 12, 8, 9, -1, 229 4, 0, 1, -1}; 230 /* Extract flow_tag field. */ 231 const uint32x4_t ft_mask = 232 vdupq_n_u32(MLX5_FLOW_MARK_DEFAULT); 233 const uint32x4_t fdir_flags = 234 vdupq_n_u32(RTE_MBUF_F_RX_FDIR); 235 const uint32x4_t fdir_all_flags = 236 vdupq_n_u32(RTE_MBUF_F_RX_FDIR | 237 rxq->mark_flag); 238 uint32x4_t fdir_id_flags = 239 vdupq_n_u32(rxq->mark_flag); 240 uint32x4_t invalid_mask, ftag; 241 242 __asm__ volatile 243 /* A.1 load mCQEs into a 128bit register. */ 244 ("ld1 {v16.16b - v17.16b}, [%[mcq]]\n\t" 245 /* Extract flow_tag. */ 246 "tbl %[ftag].16b, {v16.16b - v17.16b}, %[flow_mark_shuf].16b\n\t" 247 : [ftag]"=&w"(ftag) 248 : [mcq]"r"(p), 249 [flow_mark_shuf]"w"(flow_mark_shuf) 250 : "memory", "v16", "v17"); 251 invalid_mask = vceqzq_u32(ftag); 252 ol_flags_mask = vorrq_u32(ol_flags_mask, 253 fdir_all_flags); 254 /* Set RTE_MBUF_F_RX_FDIR if flow tag is non-zero. */ 255 ol_flags = vorrq_u32(ol_flags, 256 vbicq_u32(fdir_flags, invalid_mask)); 257 /* Mask out invalid entries. */ 258 fdir_id_flags = vbicq_u32(fdir_id_flags, 259 invalid_mask); 260 /* Check if flow tag MLX5_FLOW_MARK_DEFAULT. */ 261 ol_flags = vorrq_u32(ol_flags, 262 vbicq_u32(fdir_id_flags, 263 vceqq_u32(ftag, ft_mask))); 264 ftag = vaddq_u32(ftag, flow_mark_adj); 265 elts[pos]->hash.fdir.hi = 266 vgetq_lane_u32(ftag, 3); 267 elts[pos + 1]->hash.fdir.hi = 268 vgetq_lane_u32(ftag, 2); 269 elts[pos + 2]->hash.fdir.hi = 270 vgetq_lane_u32(ftag, 1); 271 elts[pos + 3]->hash.fdir.hi = 272 vgetq_lane_u32(ftag, 0); 273 } 274 } 275 if (unlikely(rxq->mcqe_format != 276 MLX5_CQE_RESP_FORMAT_HASH)) { 277 if (rxq->mcqe_format == 278 MLX5_CQE_RESP_FORMAT_L34H_STRIDX) { 279 const uint8_t pkt_info = 280 (cq->pkt_info & 0x3) << 6; 281 const uint8_t pkt_hdr0 = 282 mcq[pos % 8].hdr_type; 283 const uint8_t pkt_hdr1 = 284 mcq[pos % 8 + 1].hdr_type; 285 const uint8_t pkt_hdr2 = 286 mcq[pos % 8 + 2].hdr_type; 287 const uint8_t pkt_hdr3 = 288 mcq[pos % 8 + 3].hdr_type; 289 const uint32x4_t vlan_mask = 290 vdupq_n_u32(RTE_MBUF_F_RX_VLAN | 291 RTE_MBUF_F_RX_VLAN_STRIPPED); 292 const uint32x4_t cv_mask = 293 vdupq_n_u32(MLX5_CQE_VLAN_STRIPPED); 294 const uint32x4_t pkt_cv = { 295 pkt_hdr0 & 0x1, pkt_hdr1 & 0x1, 296 pkt_hdr2 & 0x1, pkt_hdr3 & 0x1}; 297 298 ol_flags_mask = vorrq_u32(ol_flags_mask, 299 vlan_mask); 300 ol_flags = vorrq_u32(ol_flags, 301 vandq_u32(vlan_mask, 302 vceqq_u32(pkt_cv, cv_mask))); 303 elts[pos]->packet_type = 304 mlx5_ptype_table[(pkt_hdr0 >> 2) | 305 pkt_info]; 306 elts[pos + 1]->packet_type = 307 mlx5_ptype_table[(pkt_hdr1 >> 2) | 308 pkt_info]; 309 elts[pos + 2]->packet_type = 310 mlx5_ptype_table[(pkt_hdr2 >> 2) | 311 pkt_info]; 312 elts[pos + 3]->packet_type = 313 mlx5_ptype_table[(pkt_hdr3 >> 2) | 314 pkt_info]; 315 if (rxq->tunnel) { 316 elts[pos]->packet_type |= 317 !!(((pkt_hdr0 >> 2) | 318 pkt_info) & (1 << 6)); 319 elts[pos + 1]->packet_type |= 320 !!(((pkt_hdr1 >> 2) | 321 pkt_info) & (1 << 6)); 322 elts[pos + 2]->packet_type |= 323 !!(((pkt_hdr2 >> 2) | 324 pkt_info) & (1 << 6)); 325 elts[pos + 3]->packet_type |= 326 !!(((pkt_hdr3 >> 2) | 327 pkt_info) & (1 << 6)); 328 } 329 } 330 const uint32x4_t hash_flags = 331 vdupq_n_u32(RTE_MBUF_F_RX_RSS_HASH); 332 const uint32x4_t rearm_flags = 333 vdupq_n_u32((uint32_t)t_pkt->ol_flags); 334 335 ol_flags_mask = vorrq_u32(ol_flags_mask, hash_flags); 336 ol_flags = vorrq_u32(ol_flags, 337 vbicq_u32(rearm_flags, ol_flags_mask)); 338 elts[pos]->ol_flags = vgetq_lane_u32(ol_flags, 3); 339 elts[pos + 1]->ol_flags = vgetq_lane_u32(ol_flags, 2); 340 elts[pos + 2]->ol_flags = vgetq_lane_u32(ol_flags, 1); 341 elts[pos + 3]->ol_flags = vgetq_lane_u32(ol_flags, 0); 342 elts[pos]->hash.rss = 0; 343 elts[pos + 1]->hash.rss = 0; 344 elts[pos + 2]->hash.rss = 0; 345 elts[pos + 3]->hash.rss = 0; 346 } 347 if (rxq->dynf_meta) { 348 int32_t offs = rxq->flow_meta_offset; 349 const uint32_t meta = 350 *RTE_MBUF_DYNFIELD(t_pkt, offs, uint32_t *); 351 352 /* Check if title packet has valid metadata. */ 353 if (meta) { 354 MLX5_ASSERT(t_pkt->ol_flags & 355 rxq->flow_meta_mask); 356 *RTE_MBUF_DYNFIELD(elts[pos], offs, 357 uint32_t *) = meta; 358 *RTE_MBUF_DYNFIELD(elts[pos + 1], offs, 359 uint32_t *) = meta; 360 *RTE_MBUF_DYNFIELD(elts[pos + 2], offs, 361 uint32_t *) = meta; 362 *RTE_MBUF_DYNFIELD(elts[pos + 3], offs, 363 uint32_t *) = meta; 364 } 365 } 366 pos += MLX5_VPMD_DESCS_PER_LOOP; 367 /* Move to next CQE and invalidate consumed CQEs. */ 368 if (!rxq->cqe_comp_layout) { 369 if (!(pos & 0x7) && pos < mcqe_n) { 370 if (pos + 8 < mcqe_n) 371 rte_prefetch0((void *)(cq + pos + 8)); 372 mcq = (void *)&(cq + pos)->pkt_info; 373 for (i = 0; i < 8; ++i) 374 cq[inv++].op_own = MLX5_CQE_INVALIDATE; 375 } 376 } 377 } 378 if (rxq->cqe_comp_layout && keep) { 379 int ret; 380 /* Keep unzipping if the next CQE is the miniCQE array. */ 381 cq = &cq[mcqe_n]; 382 ret = check_cqe_iteration(cq, rxq->cqe_n, rxq->cq_ci + pkts_n); 383 if (ret == MLX5_CQE_STATUS_SW_OWN && 384 MLX5_CQE_FORMAT(cq->op_own) == MLX5_COMPRESSED) { 385 pos = 0; 386 elts = &elts[mcqe_n]; 387 mcq = (void *)cq; 388 mcqe_n = MLX5_CQE_NUM_MINIS(cq->op_own) + 1; 389 pkts_n += mcqe_n; 390 goto cycle; 391 } 392 } else { 393 /* Invalidate the rest of CQEs. */ 394 for (; inv < pkts_n; ++inv) 395 cq[inv].op_own = MLX5_CQE_INVALIDATE; 396 } 397 #ifdef MLX5_PMD_SOFT_COUNTERS 398 rxq->stats.ipackets += pkts_n; 399 rxq->stats.ibytes += rcvd_byte; 400 #endif 401 return pkts_n; 402 } 403 404 /** 405 * Calculate packet type and offload flag for mbuf and store it. 406 * 407 * @param rxq 408 * Pointer to RX queue structure. 409 * @param ptype_info 410 * Array of four 4bytes packet type info extracted from the original 411 * completion descriptor. 412 * @param flow_tag 413 * Array of four 4bytes flow ID extracted from the original completion 414 * descriptor. 415 * @param op_err 416 * Opcode vector having responder error status. Each field is 4B. 417 * @param pkts 418 * Pointer to array of packets to be filled. 419 */ 420 static inline void 421 rxq_cq_to_ptype_oflags_v(struct mlx5_rxq_data *rxq, 422 uint32x4_t ptype_info, uint32x4_t flow_tag, 423 uint16x4_t op_err, struct rte_mbuf **pkts) 424 { 425 uint16x4_t ptype; 426 uint32x4_t pinfo, cv_flags; 427 uint32x4_t ol_flags = 428 vdupq_n_u32(rxq->rss_hash * RTE_MBUF_F_RX_RSS_HASH | 429 rxq->hw_timestamp * rxq->timestamp_rx_flag); 430 const uint32x4_t ptype_ol_mask = { 0x106, 0x106, 0x106, 0x106 }; 431 const uint8x16_t cv_flag_sel = { 432 0, 433 (uint8_t)(RTE_MBUF_F_RX_VLAN | RTE_MBUF_F_RX_VLAN_STRIPPED), 434 (uint8_t)(RTE_MBUF_F_RX_IP_CKSUM_GOOD >> 1), 435 0, 436 (uint8_t)(RTE_MBUF_F_RX_L4_CKSUM_GOOD >> 1), 437 0, 438 (uint8_t)((RTE_MBUF_F_RX_IP_CKSUM_GOOD | RTE_MBUF_F_RX_L4_CKSUM_GOOD) >> 1), 439 0, 0, 0, 0, 0, 0, 0, 0, 0 440 }; 441 const uint32x4_t cv_mask = 442 vdupq_n_u32(RTE_MBUF_F_RX_IP_CKSUM_GOOD | RTE_MBUF_F_RX_L4_CKSUM_GOOD | 443 RTE_MBUF_F_RX_VLAN | RTE_MBUF_F_RX_VLAN_STRIPPED); 444 const uint64x2_t mbuf_init = vld1q_u64 445 ((const uint64_t *)&rxq->mbuf_initializer); 446 uint64x2_t rearm0, rearm1, rearm2, rearm3; 447 uint8_t pt_idx0, pt_idx1, pt_idx2, pt_idx3; 448 449 if (rxq->mark) { 450 const uint32x4_t ft_def = vdupq_n_u32(MLX5_FLOW_MARK_DEFAULT); 451 const uint32x4_t fdir_flags = vdupq_n_u32(RTE_MBUF_F_RX_FDIR); 452 uint32x4_t fdir_id_flags = vdupq_n_u32(rxq->mark_flag); 453 uint32x4_t invalid_mask; 454 455 /* Check if flow tag is non-zero then set RTE_MBUF_F_RX_FDIR. */ 456 invalid_mask = vceqzq_u32(flow_tag); 457 ol_flags = vorrq_u32(ol_flags, 458 vbicq_u32(fdir_flags, invalid_mask)); 459 /* Mask out invalid entries. */ 460 fdir_id_flags = vbicq_u32(fdir_id_flags, invalid_mask); 461 /* Check if flow tag MLX5_FLOW_MARK_DEFAULT. */ 462 ol_flags = vorrq_u32(ol_flags, 463 vbicq_u32(fdir_id_flags, 464 vceqq_u32(flow_tag, ft_def))); 465 } 466 /* 467 * ptype_info has the following: 468 * bit[1] = l3_ok 469 * bit[2] = l4_ok 470 * bit[8] = cv 471 * bit[11:10] = l3_hdr_type 472 * bit[14:12] = l4_hdr_type 473 * bit[15] = ip_frag 474 * bit[16] = tunneled 475 * bit[17] = outer_l3_type 476 */ 477 ptype = vshrn_n_u32(ptype_info, 10); 478 /* Errored packets will have RTE_PTYPE_ALL_MASK. */ 479 ptype = vorr_u16(ptype, op_err); 480 pt_idx0 = vget_lane_u8(vreinterpret_u8_u16(ptype), 6); 481 pt_idx1 = vget_lane_u8(vreinterpret_u8_u16(ptype), 4); 482 pt_idx2 = vget_lane_u8(vreinterpret_u8_u16(ptype), 2); 483 pt_idx3 = vget_lane_u8(vreinterpret_u8_u16(ptype), 0); 484 pkts[0]->packet_type = mlx5_ptype_table[pt_idx0] | 485 !!(pt_idx0 & (1 << 6)) * rxq->tunnel; 486 pkts[1]->packet_type = mlx5_ptype_table[pt_idx1] | 487 !!(pt_idx1 & (1 << 6)) * rxq->tunnel; 488 pkts[2]->packet_type = mlx5_ptype_table[pt_idx2] | 489 !!(pt_idx2 & (1 << 6)) * rxq->tunnel; 490 pkts[3]->packet_type = mlx5_ptype_table[pt_idx3] | 491 !!(pt_idx3 & (1 << 6)) * rxq->tunnel; 492 /* Fill flags for checksum and VLAN. */ 493 pinfo = vandq_u32(ptype_info, ptype_ol_mask); 494 pinfo = vreinterpretq_u32_u8( 495 vqtbl1q_u8(cv_flag_sel, vreinterpretq_u8_u32(pinfo))); 496 /* Locate checksum flags at byte[2:1] and merge with VLAN flags. */ 497 cv_flags = vshlq_n_u32(pinfo, 9); 498 cv_flags = vorrq_u32(pinfo, cv_flags); 499 /* Move back flags to start from byte[0]. */ 500 cv_flags = vshrq_n_u32(cv_flags, 8); 501 /* Mask out garbage bits. */ 502 cv_flags = vandq_u32(cv_flags, cv_mask); 503 /* Merge to ol_flags. */ 504 ol_flags = vorrq_u32(ol_flags, cv_flags); 505 /* Merge mbuf_init and ol_flags, and store. */ 506 rearm0 = vreinterpretq_u64_u32(vsetq_lane_u32 507 (vgetq_lane_u32(ol_flags, 3), 508 vreinterpretq_u32_u64(mbuf_init), 2)); 509 rearm1 = vreinterpretq_u64_u32(vsetq_lane_u32 510 (vgetq_lane_u32(ol_flags, 2), 511 vreinterpretq_u32_u64(mbuf_init), 2)); 512 rearm2 = vreinterpretq_u64_u32(vsetq_lane_u32 513 (vgetq_lane_u32(ol_flags, 1), 514 vreinterpretq_u32_u64(mbuf_init), 2)); 515 rearm3 = vreinterpretq_u64_u32(vsetq_lane_u32 516 (vgetq_lane_u32(ol_flags, 0), 517 vreinterpretq_u32_u64(mbuf_init), 2)); 518 519 vst1q_u64((void *)&pkts[0]->rearm_data, rearm0); 520 vst1q_u64((void *)&pkts[1]->rearm_data, rearm1); 521 vst1q_u64((void *)&pkts[2]->rearm_data, rearm2); 522 vst1q_u64((void *)&pkts[3]->rearm_data, rearm3); 523 } 524 525 /** 526 * Process a non-compressed completion and fill in mbufs in RX SW ring 527 * with data extracted from the title completion descriptor. 528 * 529 * @param rxq 530 * Pointer to RX queue structure. 531 * @param cq 532 * Pointer to completion array having a non-compressed completion at first. 533 * @param elts 534 * Pointer to SW ring to be filled. The first mbuf has to be pre-built from 535 * the title completion descriptor to be copied to the rest of mbufs. 536 * @param[out] pkts 537 * Array to store received packets. 538 * @param pkts_n 539 * Maximum number of packets in array. 540 * @param[out] err 541 * Pointer to a flag. Set non-zero value if pkts array has at least one error 542 * packet to handle. 543 * @param[out] comp 544 * Pointer to a index. Set it to the first compressed completion if any. 545 * 546 * @return 547 * Number of CQEs successfully processed. 548 */ 549 static inline uint16_t 550 rxq_cq_process_v(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cq, 551 struct rte_mbuf **elts, struct rte_mbuf **pkts, 552 uint16_t pkts_n, uint64_t *err, uint64_t *comp) 553 { 554 const uint16_t q_n = 1 << rxq->cqe_n; 555 const uint16_t q_mask = q_n - 1; 556 unsigned int pos, adj; 557 uint64_t n = 0; 558 uint64_t comp_idx = MLX5_VPMD_DESCS_PER_LOOP; 559 uint16_t nocmp_n = 0; 560 const uint16x4_t validity = vdup_n_u16((rxq->cq_ci >> rxq->cqe_n) << 8); 561 const uint16x4_t ownership = vdup_n_u16(!(rxq->cq_ci & (q_mask + 1))); 562 const uint16x4_t vic_check = vcreate_u16(0xff00ff00ff00ff00); 563 const uint16x4_t owner_check = vcreate_u16(0x0001000100010001); 564 const uint16x4_t opcode_check = vcreate_u16(0x00f000f000f000f0); 565 const uint16x4_t format_check = vcreate_u16(0x000c000c000c000c); 566 const uint16x4_t resp_err_check = vcreate_u16(0x00e000e000e000e0); 567 #ifdef MLX5_PMD_SOFT_COUNTERS 568 uint32_t rcvd_byte = 0; 569 #endif 570 /* Mask to generate 16B length vector. */ 571 const uint8x8_t len_shuf_m = { 572 52, 53, /* 4th CQE */ 573 36, 37, /* 3rd CQE */ 574 20, 21, /* 2nd CQE */ 575 4, 5 /* 1st CQE */ 576 }; 577 /* Mask to extract 16B data from a 64B CQE. */ 578 const uint8x16_t cqe_shuf_m = { 579 28, 29, /* hdr_type_etc */ 580 0, /* pkt_info */ 581 62, /* validity_iteration_count */ 582 47, 46, /* byte_cnt, bswap16 */ 583 31, 30, /* vlan_info, bswap16 */ 584 15, 14, 13, 12, /* rx_hash_res, bswap32 */ 585 57, 58, 59, /* flow_tag */ 586 63 /* op_own */ 587 }; 588 /* Mask to generate 16B data for mbuf. */ 589 const uint8x16_t mb_shuf_m = { 590 4, 5, -1, -1, /* pkt_len */ 591 4, 5, /* data_len */ 592 6, 7, /* vlan_tci */ 593 8, 9, 10, 11, /* hash.rss */ 594 12, 13, 14, -1 /* hash.fdir.hi */ 595 }; 596 /* Mask to generate 16B owner vector. */ 597 const uint8x8_t owner_shuf_m = { 598 63, 51, /* 4th CQE */ 599 47, 35, /* 3rd CQE */ 600 31, 19, /* 2nd CQE */ 601 15, 3 /* 1st CQE */ 602 }; 603 /* Mask to generate a vector having packet_type/ol_flags. */ 604 const uint8x16_t ptype_shuf_m = { 605 48, 49, 50, -1, /* 4th CQE */ 606 32, 33, 34, -1, /* 3rd CQE */ 607 16, 17, 18, -1, /* 2nd CQE */ 608 0, 1, 2, -1 /* 1st CQE */ 609 }; 610 /* Mask to generate a vector having flow tags. */ 611 const uint8x16_t ftag_shuf_m = { 612 60, 61, 62, -1, /* 4th CQE */ 613 44, 45, 46, -1, /* 3rd CQE */ 614 28, 29, 30, -1, /* 2nd CQE */ 615 12, 13, 14, -1 /* 1st CQE */ 616 }; 617 const uint16x8_t crc_adj = { 618 0, 0, rxq->crc_present * RTE_ETHER_CRC_LEN, 0, 0, 0, 0, 0 619 }; 620 const uint32x4_t flow_mark_adj = { 0, 0, 0, rxq->mark * (-1) }; 621 622 /* 623 * Note that vectors have reverse order - {v3, v2, v1, v0}, because 624 * there's no instruction to count trailing zeros. rte_clz64() is 625 * used instead. 626 * 627 * A. copy 4 mbuf pointers from elts ring to returning pkts. 628 * B. load 64B CQE and extract necessary fields 629 * Final 16bytes cqes[] extracted from original 64bytes CQE has the 630 * following structure: 631 * struct { 632 * uint16_t hdr_type_etc; 633 * uint8_t pkt_info; 634 * uint8_t validity_iteration_count; 635 * uint16_t byte_cnt; 636 * uint16_t vlan_info; 637 * uint32_t rx_has_res; 638 * uint8_t flow_tag[3]; 639 * uint8_t op_own; 640 * } c; 641 * C. fill in mbuf. 642 * D. get valid CQEs. 643 * E. find compressed CQE. 644 */ 645 for (pos = 0; 646 pos < pkts_n; 647 pos += MLX5_VPMD_DESCS_PER_LOOP) { 648 uint16x4_t op_own; 649 uint16x4_t opcode, owner_mask, invalid_mask; 650 uint16x4_t comp_mask, mini_mask; 651 uint16x4_t mask; 652 uint16x4_t byte_cnt; 653 uint32x4_t ptype_info, flow_tag; 654 register uint64x2_t c0, c1, c2, c3; 655 uint8_t *p0, *p1, *p2, *p3; 656 uint8_t *e0 = (void *)&elts[pos]->pkt_len; 657 uint8_t *e1 = (void *)&elts[pos + 1]->pkt_len; 658 uint8_t *e2 = (void *)&elts[pos + 2]->pkt_len; 659 uint8_t *e3 = (void *)&elts[pos + 3]->pkt_len; 660 void *elts_p = (void *)&elts[pos]; 661 void *pkts_p = (void *)&pkts[pos]; 662 663 /* A.0 do not cross the end of CQ. */ 664 mask = vcreate_u16(pkts_n - pos < MLX5_VPMD_DESCS_PER_LOOP ? 665 -1UL >> ((pkts_n - pos) * 666 sizeof(uint16_t) * 8) : 0); 667 p0 = (void *)&cq[pos].pkt_info; 668 p1 = p0 + (pkts_n - pos > 1) * sizeof(struct mlx5_cqe); 669 p2 = p1 + (pkts_n - pos > 2) * sizeof(struct mlx5_cqe); 670 p3 = p2 + (pkts_n - pos > 3) * sizeof(struct mlx5_cqe); 671 /* B.0 (CQE 3) load a block having op_own. */ 672 c3 = vld1q_u64((uint64_t *)(p3 + 48)); 673 /* B.0 (CQE 2) load a block having op_own. */ 674 c2 = vld1q_u64((uint64_t *)(p2 + 48)); 675 /* B.0 (CQE 1) load a block having op_own. */ 676 c1 = vld1q_u64((uint64_t *)(p1 + 48)); 677 /* B.0 (CQE 0) load a block having op_own. */ 678 c0 = vld1q_u64((uint64_t *)(p0 + 48)); 679 /* Synchronize for loading the rest of blocks. */ 680 rte_io_rmb(); 681 /* B.0 (CQE 3) reload lower half of the block. */ 682 c3 = vld1q_lane_u64((uint64_t *)(p3 + 48), c3, 0); 683 /* B.0 (CQE 2) reload lower half of the block. */ 684 c2 = vld1q_lane_u64((uint64_t *)(p2 + 48), c2, 0); 685 /* B.0 (CQE 1) reload lower half of the block. */ 686 c1 = vld1q_lane_u64((uint64_t *)(p1 + 48), c1, 0); 687 /* B.0 (CQE 0) reload lower half of the block. */ 688 c0 = vld1q_lane_u64((uint64_t *)(p0 + 48), c0, 0); 689 /* Prefetch next 4 CQEs. */ 690 if (pkts_n - pos >= 2 * MLX5_VPMD_DESCS_PER_LOOP) { 691 unsigned int next = pos + MLX5_VPMD_DESCS_PER_LOOP; 692 rte_prefetch_non_temporal(&cq[next]); 693 rte_prefetch_non_temporal(&cq[next + 1]); 694 rte_prefetch_non_temporal(&cq[next + 2]); 695 rte_prefetch_non_temporal(&cq[next + 3]); 696 } 697 __asm__ volatile ( 698 /* B.1 (CQE 3) load the rest of blocks. */ 699 "ld1 {v16.16b - v18.16b}, [%[p3]] \n\t" 700 /* B.2 (CQE 3) move the block having op_own. */ 701 "mov v19.16b, %[c3].16b \n\t" 702 /* B.3 (CQE 3) extract 16B fields. */ 703 "tbl v23.16b, {v16.16b - v19.16b}, %[cqe_shuf_m].16b \n\t" 704 /* B.1 (CQE 2) load the rest of blocks. */ 705 "ld1 {v16.16b - v18.16b}, [%[p2]] \n\t" 706 /* B.4 (CQE 3) adjust CRC length. */ 707 "sub v23.8h, v23.8h, %[crc_adj].8h \n\t" 708 /* C.1 (CQE 3) generate final structure for mbuf. */ 709 "tbl v15.16b, {v23.16b}, %[mb_shuf_m].16b \n\t" 710 /* B.2 (CQE 2) move the block having op_own. */ 711 "mov v19.16b, %[c2].16b \n\t" 712 /* B.3 (CQE 2) extract 16B fields. */ 713 "tbl v22.16b, {v16.16b - v19.16b}, %[cqe_shuf_m].16b \n\t" 714 /* B.1 (CQE 1) load the rest of blocks. */ 715 "ld1 {v16.16b - v18.16b}, [%[p1]] \n\t" 716 /* B.4 (CQE 2) adjust CRC length. */ 717 "sub v22.8h, v22.8h, %[crc_adj].8h \n\t" 718 /* C.1 (CQE 2) generate final structure for mbuf. */ 719 "tbl v14.16b, {v22.16b}, %[mb_shuf_m].16b \n\t" 720 /* B.2 (CQE 1) move the block having op_own. */ 721 "mov v19.16b, %[c1].16b \n\t" 722 /* B.3 (CQE 1) extract 16B fields. */ 723 "tbl v21.16b, {v16.16b - v19.16b}, %[cqe_shuf_m].16b \n\t" 724 /* B.1 (CQE 0) load the rest of blocks. */ 725 "ld1 {v16.16b - v18.16b}, [%[p0]] \n\t" 726 /* B.4 (CQE 1) adjust CRC length. */ 727 "sub v21.8h, v21.8h, %[crc_adj].8h \n\t" 728 /* C.1 (CQE 1) generate final structure for mbuf. */ 729 "tbl v13.16b, {v21.16b}, %[mb_shuf_m].16b \n\t" 730 /* B.2 (CQE 0) move the block having op_own. */ 731 "mov v19.16b, %[c0].16b \n\t" 732 /* A.1 load mbuf pointers. */ 733 "ld1 {v24.2d - v25.2d}, [%[elts_p]] \n\t" 734 /* B.3 (CQE 0) extract 16B fields. */ 735 "tbl v20.16b, {v16.16b - v19.16b}, %[cqe_shuf_m].16b \n\t" 736 /* B.4 (CQE 0) adjust CRC length. */ 737 "sub v20.8h, v20.8h, %[crc_adj].8h \n\t" 738 /* D.1 extract op_own byte. */ 739 "tbl %[op_own].8b, {v20.16b - v23.16b}, %[owner_shuf_m].8b \n\t" 740 /* C.2 (CQE 3) adjust flow mark. */ 741 "add v15.4s, v15.4s, %[flow_mark_adj].4s \n\t" 742 /* C.3 (CQE 3) fill in mbuf - rx_descriptor_fields1. */ 743 "st1 {v15.2d}, [%[e3]] \n\t" 744 /* C.2 (CQE 2) adjust flow mark. */ 745 "add v14.4s, v14.4s, %[flow_mark_adj].4s \n\t" 746 /* C.3 (CQE 2) fill in mbuf - rx_descriptor_fields1. */ 747 "st1 {v14.2d}, [%[e2]] \n\t" 748 /* C.1 (CQE 0) generate final structure for mbuf. */ 749 "tbl v12.16b, {v20.16b}, %[mb_shuf_m].16b \n\t" 750 /* C.2 (CQE 1) adjust flow mark. */ 751 "add v13.4s, v13.4s, %[flow_mark_adj].4s \n\t" 752 /* C.3 (CQE 1) fill in mbuf - rx_descriptor_fields1. */ 753 "st1 {v13.2d}, [%[e1]] \n\t" 754 #ifdef MLX5_PMD_SOFT_COUNTERS 755 /* Extract byte_cnt. */ 756 "tbl %[byte_cnt].8b, {v20.16b - v23.16b}, %[len_shuf_m].8b \n\t" 757 #endif 758 /* Extract ptype_info. */ 759 "tbl %[ptype_info].16b, {v20.16b - v23.16b}, %[ptype_shuf_m].16b \n\t" 760 /* Extract flow_tag. */ 761 "tbl %[flow_tag].16b, {v20.16b - v23.16b}, %[ftag_shuf_m].16b \n\t" 762 /* A.2 copy mbuf pointers. */ 763 "st1 {v24.2d - v25.2d}, [%[pkts_p]] \n\t" 764 /* C.2 (CQE 0) adjust flow mark. */ 765 "add v12.4s, v12.4s, %[flow_mark_adj].4s \n\t" 766 /* C.3 (CQE 1) fill in mbuf - rx_descriptor_fields1. */ 767 "st1 {v12.2d}, [%[e0]] \n\t" 768 :[op_own]"=&w"(op_own), 769 [byte_cnt]"=&w"(byte_cnt), 770 [ptype_info]"=&w"(ptype_info), 771 [flow_tag]"=&w"(flow_tag) 772 :[p3]"r"(p3), [p2]"r"(p2), [p1]"r"(p1), [p0]"r"(p0), 773 [e3]"r"(e3), [e2]"r"(e2), [e1]"r"(e1), [e0]"r"(e0), 774 [c3]"w"(c3), [c2]"w"(c2), [c1]"w"(c1), [c0]"w"(c0), 775 [elts_p]"r"(elts_p), 776 [pkts_p]"r"(pkts_p), 777 [cqe_shuf_m]"w"(cqe_shuf_m), 778 [mb_shuf_m]"w"(mb_shuf_m), 779 [owner_shuf_m]"w"(owner_shuf_m), 780 [len_shuf_m]"w"(len_shuf_m), 781 [ptype_shuf_m]"w"(ptype_shuf_m), 782 [ftag_shuf_m]"w"(ftag_shuf_m), 783 [crc_adj]"w"(crc_adj), 784 [flow_mark_adj]"w"(flow_mark_adj) 785 :"memory", 786 "v12", "v13", "v14", "v15", 787 "v16", "v17", "v18", "v19", 788 "v20", "v21", "v22", "v23", 789 "v24", "v25"); 790 /* D.2 mask out CQEs belonging to HW. */ 791 if (rxq->cqe_comp_layout) { 792 owner_mask = vand_u16(op_own, vic_check); 793 owner_mask = vceq_u16(owner_mask, validity); 794 owner_mask = vmvn_u16(owner_mask); 795 } else { 796 owner_mask = vand_u16(op_own, owner_check); 797 owner_mask = vceq_u16(owner_mask, ownership); 798 } 799 /* D.3 get mask for invalidated CQEs. */ 800 opcode = vand_u16(op_own, opcode_check); 801 invalid_mask = vceq_u16(opcode_check, opcode); 802 /* E.1 find compressed CQE format. */ 803 comp_mask = vand_u16(op_own, format_check); 804 comp_mask = vceq_u16(comp_mask, format_check); 805 /* D.4 mask out beyond boundary. */ 806 invalid_mask = vorr_u16(invalid_mask, mask); 807 /* D.5 merge invalid_mask with invalid owner. */ 808 invalid_mask = vorr_u16(invalid_mask, owner_mask); 809 /* E.2 mask out invalid entries. */ 810 comp_mask = vbic_u16(comp_mask, invalid_mask); 811 /* E.3 get the first compressed CQE. */ 812 comp_idx = rte_clz64(vget_lane_u64(vreinterpret_u64_u16(comp_mask), 0)) / 813 (sizeof(uint16_t) * 8); 814 invalid_mask = vorr_u16(invalid_mask, comp_mask); 815 /* D.7 count non-compressed valid CQEs. */ 816 n = rte_clz64(vget_lane_u64(vreinterpret_u64_u16(invalid_mask), 0)) / 817 (sizeof(uint16_t) * 8); 818 nocmp_n += n; 819 /* 820 * D.2 mask out entries after the compressed CQE. 821 * get the final invalid mask. 822 */ 823 mask = vcreate_u16(n < MLX5_VPMD_DESCS_PER_LOOP ? 824 -1UL >> (n * sizeof(uint16_t) * 8) : 0); 825 invalid_mask = vorr_u16(invalid_mask, mask); 826 /* D.3 check error in opcode. */ 827 adj = (!rxq->cqe_comp_layout && 828 comp_idx != MLX5_VPMD_DESCS_PER_LOOP && comp_idx == n); 829 mask = vcreate_u16(adj ? 830 -1UL >> ((n + 1) * sizeof(uint16_t) * 8) : -1UL); 831 mini_mask = vand_u16(invalid_mask, mask); 832 opcode = vceq_u16(resp_err_check, opcode); 833 opcode = vbic_u16(opcode, mini_mask); 834 /* D.4 mark if any error is set */ 835 *err |= vget_lane_u64(vreinterpret_u64_u16(opcode), 0); 836 /* C.4 fill in mbuf - rearm_data and packet_type. */ 837 rxq_cq_to_ptype_oflags_v(rxq, ptype_info, flow_tag, 838 opcode, &elts[pos]); 839 if (unlikely(rxq->shared)) { 840 elts[pos]->port = container_of(p0, struct mlx5_cqe, 841 pkt_info)->user_index_low; 842 elts[pos + 1]->port = container_of(p1, struct mlx5_cqe, 843 pkt_info)->user_index_low; 844 elts[pos + 2]->port = container_of(p2, struct mlx5_cqe, 845 pkt_info)->user_index_low; 846 elts[pos + 3]->port = container_of(p3, struct mlx5_cqe, 847 pkt_info)->user_index_low; 848 } 849 if (unlikely(rxq->hw_timestamp)) { 850 int offset = rxq->timestamp_offset; 851 if (rxq->rt_timestamp) { 852 struct mlx5_dev_ctx_shared *sh = rxq->sh; 853 uint64_t ts; 854 855 ts = rte_be_to_cpu_64 856 (container_of(p0, struct mlx5_cqe, 857 pkt_info)->timestamp); 858 mlx5_timestamp_set(elts[pos], offset, 859 mlx5_txpp_convert_rx_ts(sh, ts)); 860 ts = rte_be_to_cpu_64 861 (container_of(p1, struct mlx5_cqe, 862 pkt_info)->timestamp); 863 mlx5_timestamp_set(elts[pos + 1], offset, 864 mlx5_txpp_convert_rx_ts(sh, ts)); 865 ts = rte_be_to_cpu_64 866 (container_of(p2, struct mlx5_cqe, 867 pkt_info)->timestamp); 868 mlx5_timestamp_set(elts[pos + 2], offset, 869 mlx5_txpp_convert_rx_ts(sh, ts)); 870 ts = rte_be_to_cpu_64 871 (container_of(p3, struct mlx5_cqe, 872 pkt_info)->timestamp); 873 mlx5_timestamp_set(elts[pos + 3], offset, 874 mlx5_txpp_convert_rx_ts(sh, ts)); 875 } else { 876 mlx5_timestamp_set(elts[pos], offset, 877 rte_be_to_cpu_64(container_of(p0, 878 struct mlx5_cqe, pkt_info)->timestamp)); 879 mlx5_timestamp_set(elts[pos + 1], offset, 880 rte_be_to_cpu_64(container_of(p1, 881 struct mlx5_cqe, pkt_info)->timestamp)); 882 mlx5_timestamp_set(elts[pos + 2], offset, 883 rte_be_to_cpu_64(container_of(p2, 884 struct mlx5_cqe, pkt_info)->timestamp)); 885 mlx5_timestamp_set(elts[pos + 3], offset, 886 rte_be_to_cpu_64(container_of(p3, 887 struct mlx5_cqe, pkt_info)->timestamp)); 888 } 889 } 890 if (rxq->dynf_meta) { 891 /* This code is subject for further optimization. */ 892 int32_t offs = rxq->flow_meta_offset; 893 uint32_t mask = rxq->flow_meta_port_mask; 894 895 *RTE_MBUF_DYNFIELD(pkts[pos], offs, uint32_t *) = 896 rte_be_to_cpu_32(container_of 897 (p0, struct mlx5_cqe, 898 pkt_info)->flow_table_metadata) & mask; 899 *RTE_MBUF_DYNFIELD(pkts[pos + 1], offs, uint32_t *) = 900 rte_be_to_cpu_32(container_of 901 (p1, struct mlx5_cqe, 902 pkt_info)->flow_table_metadata) & mask; 903 *RTE_MBUF_DYNFIELD(pkts[pos + 2], offs, uint32_t *) = 904 rte_be_to_cpu_32(container_of 905 (p2, struct mlx5_cqe, 906 pkt_info)->flow_table_metadata) & mask; 907 *RTE_MBUF_DYNFIELD(pkts[pos + 3], offs, uint32_t *) = 908 rte_be_to_cpu_32(container_of 909 (p3, struct mlx5_cqe, 910 pkt_info)->flow_table_metadata) & mask; 911 if (*RTE_MBUF_DYNFIELD(pkts[pos], offs, uint32_t *)) 912 elts[pos]->ol_flags |= rxq->flow_meta_mask; 913 if (*RTE_MBUF_DYNFIELD(pkts[pos + 1], offs, uint32_t *)) 914 elts[pos + 1]->ol_flags |= rxq->flow_meta_mask; 915 if (*RTE_MBUF_DYNFIELD(pkts[pos + 2], offs, uint32_t *)) 916 elts[pos + 2]->ol_flags |= rxq->flow_meta_mask; 917 if (*RTE_MBUF_DYNFIELD(pkts[pos + 3], offs, uint32_t *)) 918 elts[pos + 3]->ol_flags |= rxq->flow_meta_mask; 919 } 920 #ifdef MLX5_PMD_SOFT_COUNTERS 921 /* Add up received bytes count. */ 922 byte_cnt = vbic_u16(byte_cnt, invalid_mask); 923 rcvd_byte += vget_lane_u64(vpaddl_u32(vpaddl_u16(byte_cnt)), 0); 924 #endif 925 /* 926 * Break the loop unless more valid CQE is expected, or if 927 * there's a compressed CQE. 928 */ 929 if (n != MLX5_VPMD_DESCS_PER_LOOP) 930 break; 931 } 932 #ifdef MLX5_PMD_SOFT_COUNTERS 933 rxq->stats.ipackets += nocmp_n; 934 rxq->stats.ibytes += rcvd_byte; 935 #endif 936 if (comp_idx == n) 937 *comp = comp_idx; 938 return nocmp_n; 939 } 940 941 #endif /* RTE_PMD_MLX5_RXTX_VEC_NEON_H_ */ 942