1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2017 6WIND S.A. 3 * Copyright 2017 Mellanox Technologies, Ltd 4 */ 5 6 #ifndef RTE_PMD_MLX5_RXTX_VEC_H_ 7 #define RTE_PMD_MLX5_RXTX_VEC_H_ 8 9 #include <rte_common.h> 10 #include <rte_mbuf.h> 11 12 #include "mlx5_autoconf.h" 13 #include "mlx5_prm.h" 14 15 /* HW checksum offload capabilities of vectorized Tx. */ 16 #define MLX5_VEC_TX_CKSUM_OFFLOAD_CAP \ 17 (DEV_TX_OFFLOAD_IPV4_CKSUM | \ 18 DEV_TX_OFFLOAD_UDP_CKSUM | \ 19 DEV_TX_OFFLOAD_TCP_CKSUM | \ 20 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM) 21 22 /* 23 * Compile time sanity check for vectorized functions. 24 */ 25 26 #define S_ASSERT_RTE_MBUF(s) \ 27 static_assert(s, "A field of struct rte_mbuf is changed") 28 #define S_ASSERT_MLX5_CQE(s) \ 29 static_assert(s, "A field of struct mlx5_cqe is changed") 30 31 /* rxq_cq_decompress_v() */ 32 S_ASSERT_RTE_MBUF(offsetof(struct rte_mbuf, pkt_len) == 33 offsetof(struct rte_mbuf, rx_descriptor_fields1) + 4); 34 S_ASSERT_RTE_MBUF(offsetof(struct rte_mbuf, data_len) == 35 offsetof(struct rte_mbuf, rx_descriptor_fields1) + 8); 36 S_ASSERT_RTE_MBUF(offsetof(struct rte_mbuf, hash) == 37 offsetof(struct rte_mbuf, rx_descriptor_fields1) + 12); 38 39 /* rxq_cq_to_ptype_oflags_v() */ 40 S_ASSERT_RTE_MBUF(offsetof(struct rte_mbuf, ol_flags) == 41 offsetof(struct rte_mbuf, rearm_data) + 8); 42 S_ASSERT_RTE_MBUF(offsetof(struct rte_mbuf, rearm_data) == 43 RTE_ALIGN(offsetof(struct rte_mbuf, rearm_data), 16)); 44 45 /* rxq_burst_v() */ 46 S_ASSERT_RTE_MBUF(offsetof(struct rte_mbuf, pkt_len) == 47 offsetof(struct rte_mbuf, rx_descriptor_fields1) + 4); 48 S_ASSERT_RTE_MBUF(offsetof(struct rte_mbuf, data_len) == 49 offsetof(struct rte_mbuf, rx_descriptor_fields1) + 8); 50 #if (RTE_CACHE_LINE_SIZE == 128) 51 S_ASSERT_MLX5_CQE(offsetof(struct mlx5_cqe, pkt_info) == 64); 52 #else 53 S_ASSERT_MLX5_CQE(offsetof(struct mlx5_cqe, pkt_info) == 0); 54 #endif 55 S_ASSERT_MLX5_CQE(offsetof(struct mlx5_cqe, rx_hash_res) == 56 offsetof(struct mlx5_cqe, pkt_info) + 12); 57 S_ASSERT_MLX5_CQE(offsetof(struct mlx5_cqe, rsvd1) + 11 == 58 offsetof(struct mlx5_cqe, hdr_type_etc)); 59 S_ASSERT_MLX5_CQE(offsetof(struct mlx5_cqe, vlan_info) == 60 offsetof(struct mlx5_cqe, hdr_type_etc) + 2); 61 S_ASSERT_MLX5_CQE(offsetof(struct mlx5_cqe, lro_num_seg) + 12 == 62 offsetof(struct mlx5_cqe, byte_cnt)); 63 S_ASSERT_MLX5_CQE(offsetof(struct mlx5_cqe, sop_drop_qpn) == 64 RTE_ALIGN(offsetof(struct mlx5_cqe, sop_drop_qpn), 8)); 65 S_ASSERT_MLX5_CQE(offsetof(struct mlx5_cqe, op_own) == 66 offsetof(struct mlx5_cqe, sop_drop_qpn) + 7); 67 68 /** 69 * Replenish buffers for RX in bulk. 70 * 71 * @param rxq 72 * Pointer to RX queue structure. 73 * @param n 74 * Number of buffers to be replenished. 75 */ 76 static inline void 77 mlx5_rx_replenish_bulk_mbuf(struct mlx5_rxq_data *rxq, uint16_t n) 78 { 79 const uint16_t q_n = 1 << rxq->elts_n; 80 const uint16_t q_mask = q_n - 1; 81 uint16_t elts_idx = rxq->rq_ci & q_mask; 82 struct rte_mbuf **elts = &(*rxq->elts)[elts_idx]; 83 volatile struct mlx5_wqe_data_seg *wq = 84 &((volatile struct mlx5_wqe_data_seg *)rxq->wqes)[elts_idx]; 85 unsigned int i; 86 87 assert(n >= MLX5_VPMD_RXQ_RPLNSH_THRESH(q_n)); 88 assert(n <= (uint16_t)(q_n - (rxq->rq_ci - rxq->rq_pi))); 89 assert(MLX5_VPMD_RXQ_RPLNSH_THRESH(q_n) > MLX5_VPMD_DESCS_PER_LOOP); 90 /* Not to cross queue end. */ 91 n = RTE_MIN(n - MLX5_VPMD_DESCS_PER_LOOP, q_n - elts_idx); 92 if (rte_mempool_get_bulk(rxq->mp, (void *)elts, n) < 0) { 93 rxq->stats.rx_nombuf += n; 94 return; 95 } 96 for (i = 0; i < n; ++i) { 97 void *buf_addr; 98 99 /* 100 * Load the virtual address for Rx WQE. non-x86 processors 101 * (mostly RISC such as ARM and Power) are more vulnerable to 102 * load stall. For x86, reducing the number of instructions 103 * seems to matter most. 104 */ 105 #ifdef RTE_ARCH_X86_64 106 buf_addr = elts[i]->buf_addr; 107 assert(buf_addr == rte_mbuf_buf_addr(elts[i], rxq->mp)); 108 #else 109 buf_addr = rte_mbuf_buf_addr(elts[i], rxq->mp); 110 assert(buf_addr == elts[i]->buf_addr); 111 #endif 112 wq[i].addr = rte_cpu_to_be_64((uintptr_t)buf_addr + 113 RTE_PKTMBUF_HEADROOM); 114 /* If there's only one MR, no need to replace LKey in WQE. */ 115 if (unlikely(mlx5_mr_btree_len(&rxq->mr_ctrl.cache_bh) > 1)) 116 wq[i].lkey = mlx5_rx_mb2mr(rxq, elts[i]); 117 } 118 rxq->rq_ci += n; 119 /* Prevent overflowing into consumed mbufs. */ 120 elts_idx = rxq->rq_ci & q_mask; 121 for (i = 0; i < MLX5_VPMD_DESCS_PER_LOOP; ++i) 122 (*rxq->elts)[elts_idx + i] = &rxq->fake_mbuf; 123 rte_cio_wmb(); 124 *rxq->rq_db = rte_cpu_to_be_32(rxq->rq_ci); 125 } 126 127 #endif /* RTE_PMD_MLX5_RXTX_VEC_H_ */ 128