1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2016 6WIND S.A. 3 * Copyright 2016 Mellanox Technologies, Ltd 4 */ 5 6 #include <stdalign.h> 7 #include <stdint.h> 8 #include <string.h> 9 #include <stdbool.h> 10 #include <sys/queue.h> 11 12 #include <rte_common.h> 13 #include <rte_ether.h> 14 #include <ethdev_driver.h> 15 #include <rte_eal_paging.h> 16 #include <rte_flow.h> 17 #include <rte_cycles.h> 18 #include <rte_flow_driver.h> 19 #include <rte_malloc.h> 20 #include <rte_ip.h> 21 22 #include <mlx5_glue.h> 23 #include <mlx5_devx_cmds.h> 24 #include <mlx5_prm.h> 25 #include <mlx5_malloc.h> 26 27 #include "mlx5_defs.h" 28 #include "mlx5.h" 29 #include "mlx5_flow.h" 30 #include "mlx5_flow_os.h" 31 #include "mlx5_rx.h" 32 #include "mlx5_tx.h" 33 #include "mlx5_common_os.h" 34 #include "rte_pmd_mlx5.h" 35 36 /* 37 * Shared array for quick translation between port_id and vport mask/values 38 * used for HWS rules. 39 */ 40 struct flow_hw_port_info mlx5_flow_hw_port_infos[RTE_MAX_ETHPORTS]; 41 42 /* 43 * A global structure to save the available REG_C_x for tags usage. 44 * The Meter color REG (ASO) and the last available one will be reserved 45 * for PMD internal usage. 46 * Since there is no "port" concept in the driver, it is assumed that the 47 * available tags set will be the minimum intersection. 48 * 3 - in FDB mode / 5 - in legacy mode 49 */ 50 uint32_t mlx5_flow_hw_avl_tags_init_cnt; 51 enum modify_reg mlx5_flow_hw_avl_tags[MLX5_FLOW_HW_TAGS_MAX] = {REG_NON}; 52 enum modify_reg mlx5_flow_hw_aso_tag; 53 54 struct tunnel_default_miss_ctx { 55 uint16_t *queue; 56 __extension__ 57 union { 58 struct rte_flow_action_rss action_rss; 59 struct rte_flow_action_queue miss_queue; 60 struct rte_flow_action_jump miss_jump; 61 uint8_t raw[0]; 62 }; 63 }; 64 65 static int 66 flow_tunnel_add_default_miss(struct rte_eth_dev *dev, 67 struct rte_flow *flow, 68 const struct rte_flow_attr *attr, 69 const struct rte_flow_action *app_actions, 70 uint32_t flow_idx, 71 const struct mlx5_flow_tunnel *tunnel, 72 struct tunnel_default_miss_ctx *ctx, 73 struct rte_flow_error *error); 74 static struct mlx5_flow_tunnel * 75 mlx5_find_tunnel_id(struct rte_eth_dev *dev, uint32_t id); 76 static void 77 mlx5_flow_tunnel_free(struct rte_eth_dev *dev, struct mlx5_flow_tunnel *tunnel); 78 static uint32_t 79 tunnel_flow_group_to_flow_table(struct rte_eth_dev *dev, 80 const struct mlx5_flow_tunnel *tunnel, 81 uint32_t group, uint32_t *table, 82 struct rte_flow_error *error); 83 84 /** Device flow drivers. */ 85 extern const struct mlx5_flow_driver_ops mlx5_flow_verbs_drv_ops; 86 87 const struct mlx5_flow_driver_ops mlx5_flow_null_drv_ops; 88 89 const struct mlx5_flow_driver_ops *flow_drv_ops[] = { 90 [MLX5_FLOW_TYPE_MIN] = &mlx5_flow_null_drv_ops, 91 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H) 92 [MLX5_FLOW_TYPE_DV] = &mlx5_flow_dv_drv_ops, 93 #endif 94 #ifdef HAVE_MLX5_HWS_SUPPORT 95 [MLX5_FLOW_TYPE_HW] = &mlx5_flow_hw_drv_ops, 96 #endif 97 [MLX5_FLOW_TYPE_VERBS] = &mlx5_flow_verbs_drv_ops, 98 [MLX5_FLOW_TYPE_MAX] = &mlx5_flow_null_drv_ops 99 }; 100 101 /** Helper macro to build input graph for mlx5_flow_expand_rss(). */ 102 #define MLX5_FLOW_EXPAND_RSS_NEXT(...) \ 103 (const int []){ \ 104 __VA_ARGS__, 0, \ 105 } 106 107 /** Node object of input graph for mlx5_flow_expand_rss(). */ 108 struct mlx5_flow_expand_node { 109 const int *const next; 110 /**< 111 * List of next node indexes. Index 0 is interpreted as a terminator. 112 */ 113 const enum rte_flow_item_type type; 114 /**< Pattern item type of current node. */ 115 uint64_t rss_types; 116 /**< 117 * RSS types bit-field associated with this node 118 * (see RTE_ETH_RSS_* definitions). 119 */ 120 uint64_t node_flags; 121 /**< 122 * Bit-fields that define how the node is used in the expansion. 123 * (see MLX5_EXPANSION_NODE_* definitions). 124 */ 125 }; 126 127 /** Keep same format with mlx5_flow_expand_rss to share the buffer for expansion. */ 128 struct mlx5_flow_expand_sqn { 129 uint32_t entries; /** Number of entries */ 130 struct { 131 struct rte_flow_item *pattern; /**< Expanded pattern array. */ 132 uint32_t priority; /**< Priority offset for each expansion. */ 133 } entry[]; 134 }; 135 136 /* Optional expand field. The expansion alg will not go deeper. */ 137 #define MLX5_EXPANSION_NODE_OPTIONAL (UINT64_C(1) << 0) 138 139 /* The node is not added implicitly as expansion to the flow pattern. 140 * If the node type does not match the flow pattern item type, the 141 * expansion alg will go deeper to its next items. 142 * In the current implementation, the list of next nodes indexes can 143 * have up to one node with this flag set and it has to be the last 144 * node index (before the list terminator). 145 */ 146 #define MLX5_EXPANSION_NODE_EXPLICIT (UINT64_C(1) << 1) 147 148 /** Object returned by mlx5_flow_expand_rss(). */ 149 struct mlx5_flow_expand_rss { 150 uint32_t entries; 151 /**< Number of entries @p patterns and @p priorities. */ 152 struct { 153 struct rte_flow_item *pattern; /**< Expanded pattern array. */ 154 uint32_t priority; /**< Priority offset for each expansion. */ 155 } entry[]; 156 }; 157 158 static void 159 mlx5_dbg__print_pattern(const struct rte_flow_item *item); 160 161 static const struct mlx5_flow_expand_node * 162 mlx5_flow_expand_rss_adjust_node(const struct rte_flow_item *pattern, 163 unsigned int item_idx, 164 const struct mlx5_flow_expand_node graph[], 165 const struct mlx5_flow_expand_node *node); 166 167 static bool 168 mlx5_flow_is_rss_expandable_item(const struct rte_flow_item *item) 169 { 170 switch (item->type) { 171 case RTE_FLOW_ITEM_TYPE_ETH: 172 case RTE_FLOW_ITEM_TYPE_VLAN: 173 case RTE_FLOW_ITEM_TYPE_IPV4: 174 case RTE_FLOW_ITEM_TYPE_IPV6: 175 case RTE_FLOW_ITEM_TYPE_UDP: 176 case RTE_FLOW_ITEM_TYPE_TCP: 177 case RTE_FLOW_ITEM_TYPE_ESP: 178 case RTE_FLOW_ITEM_TYPE_ICMP: 179 case RTE_FLOW_ITEM_TYPE_ICMP6: 180 case RTE_FLOW_ITEM_TYPE_VXLAN: 181 case RTE_FLOW_ITEM_TYPE_NVGRE: 182 case RTE_FLOW_ITEM_TYPE_GRE: 183 case RTE_FLOW_ITEM_TYPE_GENEVE: 184 case RTE_FLOW_ITEM_TYPE_MPLS: 185 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE: 186 case RTE_FLOW_ITEM_TYPE_GRE_KEY: 187 case RTE_FLOW_ITEM_TYPE_IPV6_FRAG_EXT: 188 case RTE_FLOW_ITEM_TYPE_GTP: 189 return true; 190 default: 191 break; 192 } 193 return false; 194 } 195 196 /** 197 * Network Service Header (NSH) and its next protocol values 198 * are described in RFC-8393. 199 */ 200 static enum rte_flow_item_type 201 mlx5_nsh_proto_to_item_type(uint8_t proto_spec, uint8_t proto_mask) 202 { 203 enum rte_flow_item_type type; 204 205 switch (proto_mask & proto_spec) { 206 case 0: 207 type = RTE_FLOW_ITEM_TYPE_VOID; 208 break; 209 case RTE_VXLAN_GPE_TYPE_IPV4: 210 type = RTE_FLOW_ITEM_TYPE_IPV4; 211 break; 212 case RTE_VXLAN_GPE_TYPE_IPV6: 213 type = RTE_VXLAN_GPE_TYPE_IPV6; 214 break; 215 case RTE_VXLAN_GPE_TYPE_ETH: 216 type = RTE_FLOW_ITEM_TYPE_ETH; 217 break; 218 default: 219 type = RTE_FLOW_ITEM_TYPE_END; 220 } 221 return type; 222 } 223 224 static enum rte_flow_item_type 225 mlx5_inet_proto_to_item_type(uint8_t proto_spec, uint8_t proto_mask) 226 { 227 enum rte_flow_item_type type; 228 229 switch (proto_mask & proto_spec) { 230 case 0: 231 type = RTE_FLOW_ITEM_TYPE_VOID; 232 break; 233 case IPPROTO_UDP: 234 type = RTE_FLOW_ITEM_TYPE_UDP; 235 break; 236 case IPPROTO_TCP: 237 type = RTE_FLOW_ITEM_TYPE_TCP; 238 break; 239 case IPPROTO_IPIP: 240 type = RTE_FLOW_ITEM_TYPE_IPV4; 241 break; 242 case IPPROTO_IPV6: 243 type = RTE_FLOW_ITEM_TYPE_IPV6; 244 break; 245 case IPPROTO_ESP: 246 type = RTE_FLOW_ITEM_TYPE_ESP; 247 break; 248 default: 249 type = RTE_FLOW_ITEM_TYPE_END; 250 } 251 return type; 252 } 253 254 static enum rte_flow_item_type 255 mlx5_ethertype_to_item_type(rte_be16_t type_spec, 256 rte_be16_t type_mask, bool is_tunnel) 257 { 258 enum rte_flow_item_type type; 259 260 switch (rte_be_to_cpu_16(type_spec & type_mask)) { 261 case 0: 262 type = RTE_FLOW_ITEM_TYPE_VOID; 263 break; 264 case RTE_ETHER_TYPE_TEB: 265 type = is_tunnel ? 266 RTE_FLOW_ITEM_TYPE_ETH : RTE_FLOW_ITEM_TYPE_END; 267 break; 268 case RTE_ETHER_TYPE_VLAN: 269 type = !is_tunnel ? 270 RTE_FLOW_ITEM_TYPE_VLAN : RTE_FLOW_ITEM_TYPE_END; 271 break; 272 case RTE_ETHER_TYPE_IPV4: 273 type = RTE_FLOW_ITEM_TYPE_IPV4; 274 break; 275 case RTE_ETHER_TYPE_IPV6: 276 type = RTE_FLOW_ITEM_TYPE_IPV6; 277 break; 278 default: 279 type = RTE_FLOW_ITEM_TYPE_END; 280 } 281 return type; 282 } 283 284 static enum rte_flow_item_type 285 mlx5_flow_expand_rss_item_complete(const struct rte_flow_item *item) 286 { 287 #define MLX5_XSET_ITEM_MASK_SPEC(type, fld) \ 288 do { \ 289 const void *m = item->mask; \ 290 const void *s = item->spec; \ 291 mask = m ? \ 292 ((const struct rte_flow_item_##type *)m)->fld : \ 293 rte_flow_item_##type##_mask.fld; \ 294 spec = ((const struct rte_flow_item_##type *)s)->fld; \ 295 } while (0) 296 297 enum rte_flow_item_type ret; 298 uint16_t spec, mask; 299 300 if (item == NULL || item->spec == NULL) 301 return RTE_FLOW_ITEM_TYPE_VOID; 302 switch (item->type) { 303 case RTE_FLOW_ITEM_TYPE_ETH: 304 MLX5_XSET_ITEM_MASK_SPEC(eth, hdr.ether_type); 305 if (!mask) 306 return RTE_FLOW_ITEM_TYPE_VOID; 307 ret = mlx5_ethertype_to_item_type(spec, mask, false); 308 break; 309 case RTE_FLOW_ITEM_TYPE_VLAN: 310 MLX5_XSET_ITEM_MASK_SPEC(vlan, hdr.eth_proto); 311 if (!mask) 312 return RTE_FLOW_ITEM_TYPE_VOID; 313 ret = mlx5_ethertype_to_item_type(spec, mask, false); 314 break; 315 case RTE_FLOW_ITEM_TYPE_IPV4: 316 MLX5_XSET_ITEM_MASK_SPEC(ipv4, hdr.next_proto_id); 317 if (!mask) 318 return RTE_FLOW_ITEM_TYPE_VOID; 319 ret = mlx5_inet_proto_to_item_type(spec, mask); 320 break; 321 case RTE_FLOW_ITEM_TYPE_IPV6: 322 MLX5_XSET_ITEM_MASK_SPEC(ipv6, hdr.proto); 323 if (!mask) 324 return RTE_FLOW_ITEM_TYPE_VOID; 325 ret = mlx5_inet_proto_to_item_type(spec, mask); 326 break; 327 case RTE_FLOW_ITEM_TYPE_GENEVE: 328 MLX5_XSET_ITEM_MASK_SPEC(geneve, protocol); 329 ret = mlx5_ethertype_to_item_type(spec, mask, true); 330 break; 331 case RTE_FLOW_ITEM_TYPE_GRE: 332 MLX5_XSET_ITEM_MASK_SPEC(gre, protocol); 333 ret = mlx5_ethertype_to_item_type(spec, mask, true); 334 break; 335 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE: 336 MLX5_XSET_ITEM_MASK_SPEC(vxlan_gpe, hdr.proto); 337 ret = mlx5_nsh_proto_to_item_type(spec, mask); 338 break; 339 default: 340 ret = RTE_FLOW_ITEM_TYPE_VOID; 341 break; 342 } 343 return ret; 344 #undef MLX5_XSET_ITEM_MASK_SPEC 345 } 346 347 static const int * 348 mlx5_flow_expand_rss_skip_explicit(const struct mlx5_flow_expand_node graph[], 349 const int *next_node) 350 { 351 const struct mlx5_flow_expand_node *node = NULL; 352 const int *next = next_node; 353 354 while (next && *next) { 355 /* 356 * Skip the nodes with the MLX5_EXPANSION_NODE_EXPLICIT 357 * flag set, because they were not found in the flow pattern. 358 */ 359 node = &graph[*next]; 360 if (!(node->node_flags & MLX5_EXPANSION_NODE_EXPLICIT)) 361 break; 362 next = node->next; 363 } 364 return next; 365 } 366 367 #define MLX5_RSS_EXP_ELT_N 16 368 369 /** 370 * Expand RSS flows into several possible flows according to the RSS hash 371 * fields requested and the driver capabilities. 372 * 373 * @param[out] buf 374 * Buffer to store the result expansion. 375 * @param[in] size 376 * Buffer size in bytes. If 0, @p buf can be NULL. 377 * @param[in] pattern 378 * User flow pattern. 379 * @param[in] types 380 * RSS types to expand (see RTE_ETH_RSS_* definitions). 381 * @param[in] graph 382 * Input graph to expand @p pattern according to @p types. 383 * @param[in] graph_root_index 384 * Index of root node in @p graph, typically 0. 385 * 386 * @return 387 * A positive value representing the size of @p buf in bytes regardless of 388 * @p size on success, a negative errno value otherwise and rte_errno is 389 * set, the following errors are defined: 390 * 391 * -E2BIG: graph-depth @p graph is too deep. 392 * -EINVAL: @p size has not enough space for expanded pattern. 393 */ 394 static int 395 mlx5_flow_expand_rss(struct mlx5_flow_expand_rss *buf, size_t size, 396 const struct rte_flow_item *pattern, uint64_t types, 397 const struct mlx5_flow_expand_node graph[], 398 int graph_root_index) 399 { 400 const struct rte_flow_item *item; 401 const struct mlx5_flow_expand_node *node = &graph[graph_root_index]; 402 const int *next_node; 403 const int *stack[MLX5_RSS_EXP_ELT_N]; 404 int stack_pos = 0; 405 struct rte_flow_item flow_items[MLX5_RSS_EXP_ELT_N]; 406 unsigned int i, item_idx, last_expand_item_idx = 0; 407 size_t lsize; 408 size_t user_pattern_size = 0; 409 void *addr = NULL; 410 const struct mlx5_flow_expand_node *next = NULL; 411 struct rte_flow_item missed_item; 412 int missed = 0; 413 int elt = 0; 414 const struct rte_flow_item *last_expand_item = NULL; 415 416 memset(&missed_item, 0, sizeof(missed_item)); 417 lsize = offsetof(struct mlx5_flow_expand_rss, entry) + 418 MLX5_RSS_EXP_ELT_N * sizeof(buf->entry[0]); 419 if (lsize > size) 420 return -EINVAL; 421 buf->entry[0].priority = 0; 422 buf->entry[0].pattern = (void *)&buf->entry[MLX5_RSS_EXP_ELT_N]; 423 buf->entries = 0; 424 addr = buf->entry[0].pattern; 425 for (item = pattern, item_idx = 0; 426 item->type != RTE_FLOW_ITEM_TYPE_END; 427 item++, item_idx++) { 428 if (!mlx5_flow_is_rss_expandable_item(item)) { 429 user_pattern_size += sizeof(*item); 430 continue; 431 } 432 last_expand_item = item; 433 last_expand_item_idx = item_idx; 434 i = 0; 435 while (node->next && node->next[i]) { 436 next = &graph[node->next[i]]; 437 if (next->type == item->type) 438 break; 439 if (next->node_flags & MLX5_EXPANSION_NODE_EXPLICIT) { 440 node = next; 441 i = 0; 442 } else { 443 ++i; 444 } 445 } 446 if (next) 447 node = next; 448 user_pattern_size += sizeof(*item); 449 } 450 user_pattern_size += sizeof(*item); /* Handle END item. */ 451 lsize += user_pattern_size; 452 if (lsize > size) 453 return -EINVAL; 454 /* Copy the user pattern in the first entry of the buffer. */ 455 rte_memcpy(addr, pattern, user_pattern_size); 456 addr = (void *)(((uintptr_t)addr) + user_pattern_size); 457 buf->entries = 1; 458 /* Start expanding. */ 459 memset(flow_items, 0, sizeof(flow_items)); 460 user_pattern_size -= sizeof(*item); 461 /* 462 * Check if the last valid item has spec set, need complete pattern, 463 * and the pattern can be used for expansion. 464 */ 465 missed_item.type = mlx5_flow_expand_rss_item_complete(last_expand_item); 466 if (missed_item.type == RTE_FLOW_ITEM_TYPE_END) { 467 /* Item type END indicates expansion is not required. */ 468 return lsize; 469 } 470 if (missed_item.type != RTE_FLOW_ITEM_TYPE_VOID) { 471 next = NULL; 472 missed = 1; 473 i = 0; 474 while (node->next && node->next[i]) { 475 next = &graph[node->next[i]]; 476 if (next->type == missed_item.type) { 477 flow_items[0].type = missed_item.type; 478 flow_items[1].type = RTE_FLOW_ITEM_TYPE_END; 479 break; 480 } 481 if (next->node_flags & MLX5_EXPANSION_NODE_EXPLICIT) { 482 node = next; 483 i = 0; 484 } else { 485 ++i; 486 } 487 next = NULL; 488 } 489 } 490 if (next && missed) { 491 elt = 2; /* missed item + item end. */ 492 node = next; 493 lsize += elt * sizeof(*item) + user_pattern_size; 494 if (lsize > size) 495 return -EINVAL; 496 if (node->rss_types & types) { 497 buf->entry[buf->entries].priority = 1; 498 buf->entry[buf->entries].pattern = addr; 499 buf->entries++; 500 rte_memcpy(addr, buf->entry[0].pattern, 501 user_pattern_size); 502 addr = (void *)(((uintptr_t)addr) + user_pattern_size); 503 rte_memcpy(addr, flow_items, elt * sizeof(*item)); 504 addr = (void *)(((uintptr_t)addr) + 505 elt * sizeof(*item)); 506 } 507 } else if (last_expand_item != NULL) { 508 node = mlx5_flow_expand_rss_adjust_node(pattern, 509 last_expand_item_idx, graph, node); 510 } 511 memset(flow_items, 0, sizeof(flow_items)); 512 next_node = mlx5_flow_expand_rss_skip_explicit(graph, 513 node->next); 514 stack[stack_pos] = next_node; 515 node = next_node ? &graph[*next_node] : NULL; 516 while (node) { 517 flow_items[stack_pos].type = node->type; 518 if (node->rss_types & types) { 519 size_t n; 520 /* 521 * compute the number of items to copy from the 522 * expansion and copy it. 523 * When the stack_pos is 0, there are 1 element in it, 524 * plus the addition END item. 525 */ 526 elt = stack_pos + 2; 527 flow_items[stack_pos + 1].type = RTE_FLOW_ITEM_TYPE_END; 528 lsize += elt * sizeof(*item) + user_pattern_size; 529 if (lsize > size) 530 return -EINVAL; 531 n = elt * sizeof(*item); 532 buf->entry[buf->entries].priority = 533 stack_pos + 1 + missed; 534 buf->entry[buf->entries].pattern = addr; 535 buf->entries++; 536 rte_memcpy(addr, buf->entry[0].pattern, 537 user_pattern_size); 538 addr = (void *)(((uintptr_t)addr) + 539 user_pattern_size); 540 rte_memcpy(addr, &missed_item, 541 missed * sizeof(*item)); 542 addr = (void *)(((uintptr_t)addr) + 543 missed * sizeof(*item)); 544 rte_memcpy(addr, flow_items, n); 545 addr = (void *)(((uintptr_t)addr) + n); 546 } 547 /* Go deeper. */ 548 if (!(node->node_flags & MLX5_EXPANSION_NODE_OPTIONAL) && 549 node->next) { 550 next_node = mlx5_flow_expand_rss_skip_explicit(graph, 551 node->next); 552 if (stack_pos++ == MLX5_RSS_EXP_ELT_N) { 553 rte_errno = E2BIG; 554 return -rte_errno; 555 } 556 stack[stack_pos] = next_node; 557 } else if (*(next_node + 1)) { 558 /* Follow up with the next possibility. */ 559 next_node = mlx5_flow_expand_rss_skip_explicit(graph, 560 ++next_node); 561 } else if (!stack_pos) { 562 /* 563 * Completing the traverse over the different paths. 564 * The next_node is advanced to the terminator. 565 */ 566 ++next_node; 567 } else { 568 /* Move to the next path. */ 569 while (stack_pos) { 570 next_node = stack[--stack_pos]; 571 next_node++; 572 if (*next_node) 573 break; 574 } 575 next_node = mlx5_flow_expand_rss_skip_explicit(graph, 576 next_node); 577 stack[stack_pos] = next_node; 578 } 579 node = next_node && *next_node ? &graph[*next_node] : NULL; 580 }; 581 return lsize; 582 } 583 584 /** 585 * Expand SQN flows into several possible flows according to the Tx queue 586 * number 587 * 588 * @param[in] buf 589 * Buffer to store the result expansion. 590 * @param[in] size 591 * Buffer size in bytes. If 0, @p buf can be NULL. 592 * @param[in] pattern 593 * User flow pattern. 594 * @param[in] sq_specs 595 * Buffer to store sq spec. 596 * 597 * @return 598 * 0 for success and negative value for failure 599 * 600 */ 601 static int 602 mlx5_flow_expand_sqn(struct mlx5_flow_expand_sqn *buf, size_t size, 603 const struct rte_flow_item *pattern, 604 struct mlx5_rte_flow_item_sq *sq_specs) 605 { 606 const struct rte_flow_item *item; 607 bool port_representor = false; 608 size_t user_pattern_size = 0; 609 struct rte_eth_dev *dev; 610 struct mlx5_priv *priv; 611 void *addr = NULL; 612 uint16_t port_id; 613 size_t lsize; 614 int elt = 2; 615 uint16_t i; 616 617 buf->entries = 0; 618 for (item = pattern; item->type != RTE_FLOW_ITEM_TYPE_END; item++) { 619 if (item->type == RTE_FLOW_ITEM_TYPE_PORT_REPRESENTOR) { 620 const struct rte_flow_item_ethdev *pid_v = item->spec; 621 622 if (!pid_v) 623 return 0; 624 port_id = pid_v->port_id; 625 port_representor = true; 626 } 627 user_pattern_size += sizeof(*item); 628 } 629 if (!port_representor) 630 return 0; 631 dev = &rte_eth_devices[port_id]; 632 priv = dev->data->dev_private; 633 buf->entry[0].pattern = (void *)&buf->entry[priv->txqs_n]; 634 lsize = offsetof(struct mlx5_flow_expand_sqn, entry) + 635 sizeof(buf->entry[0]) * priv->txqs_n; 636 if (lsize + (user_pattern_size + sizeof(struct rte_flow_item) * elt) * priv->txqs_n > size) 637 return -EINVAL; 638 addr = buf->entry[0].pattern; 639 for (i = 0; i != priv->txqs_n; ++i) { 640 struct rte_flow_item pattern_add[] = { 641 { 642 .type = (enum rte_flow_item_type) 643 MLX5_RTE_FLOW_ITEM_TYPE_SQ, 644 .spec = &sq_specs[i], 645 }, 646 { 647 .type = RTE_FLOW_ITEM_TYPE_END, 648 }, 649 }; 650 struct mlx5_txq_ctrl *txq = mlx5_txq_get(dev, i); 651 652 if (txq == NULL) 653 return -EINVAL; 654 buf->entry[i].pattern = addr; 655 sq_specs[i].queue = mlx5_txq_get_sqn(txq); 656 mlx5_txq_release(dev, i); 657 rte_memcpy(addr, pattern, user_pattern_size); 658 addr = (void *)(((uintptr_t)addr) + user_pattern_size); 659 rte_memcpy(addr, pattern_add, sizeof(struct rte_flow_item) * elt); 660 addr = (void *)(((uintptr_t)addr) + sizeof(struct rte_flow_item) * elt); 661 buf->entries++; 662 } 663 return 0; 664 } 665 666 enum mlx5_expansion { 667 MLX5_EXPANSION_ROOT, 668 MLX5_EXPANSION_ROOT_OUTER, 669 MLX5_EXPANSION_OUTER_ETH, 670 MLX5_EXPANSION_OUTER_VLAN, 671 MLX5_EXPANSION_OUTER_IPV4, 672 MLX5_EXPANSION_OUTER_IPV4_UDP, 673 MLX5_EXPANSION_OUTER_IPV4_TCP, 674 MLX5_EXPANSION_OUTER_IPV4_ESP, 675 MLX5_EXPANSION_OUTER_IPV4_ICMP, 676 MLX5_EXPANSION_OUTER_IPV6, 677 MLX5_EXPANSION_OUTER_IPV6_UDP, 678 MLX5_EXPANSION_OUTER_IPV6_TCP, 679 MLX5_EXPANSION_OUTER_IPV6_ESP, 680 MLX5_EXPANSION_OUTER_IPV6_ICMP6, 681 MLX5_EXPANSION_VXLAN, 682 MLX5_EXPANSION_STD_VXLAN, 683 MLX5_EXPANSION_L3_VXLAN, 684 MLX5_EXPANSION_VXLAN_GPE, 685 MLX5_EXPANSION_GRE, 686 MLX5_EXPANSION_NVGRE, 687 MLX5_EXPANSION_GRE_KEY, 688 MLX5_EXPANSION_MPLS, 689 MLX5_EXPANSION_ETH, 690 MLX5_EXPANSION_VLAN, 691 MLX5_EXPANSION_IPV4, 692 MLX5_EXPANSION_IPV4_UDP, 693 MLX5_EXPANSION_IPV4_TCP, 694 MLX5_EXPANSION_IPV4_ESP, 695 MLX5_EXPANSION_IPV4_ICMP, 696 MLX5_EXPANSION_IPV6, 697 MLX5_EXPANSION_IPV6_UDP, 698 MLX5_EXPANSION_IPV6_TCP, 699 MLX5_EXPANSION_IPV6_ESP, 700 MLX5_EXPANSION_IPV6_ICMP6, 701 MLX5_EXPANSION_IPV6_FRAG_EXT, 702 MLX5_EXPANSION_GTP, 703 MLX5_EXPANSION_GENEVE, 704 }; 705 706 /** Supported expansion of items. */ 707 static const struct mlx5_flow_expand_node mlx5_support_expansion[] = { 708 [MLX5_EXPANSION_ROOT] = { 709 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_ETH, 710 MLX5_EXPANSION_IPV4, 711 MLX5_EXPANSION_IPV6), 712 .type = RTE_FLOW_ITEM_TYPE_END, 713 }, 714 [MLX5_EXPANSION_ROOT_OUTER] = { 715 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_OUTER_ETH, 716 MLX5_EXPANSION_OUTER_IPV4, 717 MLX5_EXPANSION_OUTER_IPV6), 718 .type = RTE_FLOW_ITEM_TYPE_END, 719 }, 720 [MLX5_EXPANSION_OUTER_ETH] = { 721 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_OUTER_VLAN), 722 .type = RTE_FLOW_ITEM_TYPE_ETH, 723 .rss_types = 0, 724 }, 725 [MLX5_EXPANSION_OUTER_VLAN] = { 726 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_OUTER_IPV4, 727 MLX5_EXPANSION_OUTER_IPV6), 728 .type = RTE_FLOW_ITEM_TYPE_VLAN, 729 .node_flags = MLX5_EXPANSION_NODE_EXPLICIT, 730 }, 731 [MLX5_EXPANSION_OUTER_IPV4] = { 732 .next = MLX5_FLOW_EXPAND_RSS_NEXT 733 (MLX5_EXPANSION_OUTER_IPV4_UDP, 734 MLX5_EXPANSION_OUTER_IPV4_TCP, 735 MLX5_EXPANSION_OUTER_IPV4_ESP, 736 MLX5_EXPANSION_OUTER_IPV4_ICMP, 737 MLX5_EXPANSION_GRE, 738 MLX5_EXPANSION_NVGRE, 739 MLX5_EXPANSION_IPV4, 740 MLX5_EXPANSION_IPV6), 741 .type = RTE_FLOW_ITEM_TYPE_IPV4, 742 .rss_types = RTE_ETH_RSS_IPV4 | RTE_ETH_RSS_FRAG_IPV4 | 743 RTE_ETH_RSS_NONFRAG_IPV4_OTHER, 744 }, 745 [MLX5_EXPANSION_OUTER_IPV4_UDP] = { 746 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_VXLAN, 747 MLX5_EXPANSION_VXLAN_GPE, 748 MLX5_EXPANSION_MPLS, 749 MLX5_EXPANSION_GENEVE, 750 MLX5_EXPANSION_GTP), 751 .type = RTE_FLOW_ITEM_TYPE_UDP, 752 .rss_types = RTE_ETH_RSS_NONFRAG_IPV4_UDP, 753 }, 754 [MLX5_EXPANSION_OUTER_IPV4_TCP] = { 755 .type = RTE_FLOW_ITEM_TYPE_TCP, 756 .rss_types = RTE_ETH_RSS_NONFRAG_IPV4_TCP, 757 }, 758 [MLX5_EXPANSION_OUTER_IPV4_ESP] = { 759 .type = RTE_FLOW_ITEM_TYPE_ESP, 760 .rss_types = RTE_ETH_RSS_ESP, 761 }, 762 [MLX5_EXPANSION_OUTER_IPV4_ICMP] = { 763 .type = RTE_FLOW_ITEM_TYPE_ICMP, 764 }, 765 [MLX5_EXPANSION_OUTER_IPV6] = { 766 .next = MLX5_FLOW_EXPAND_RSS_NEXT 767 (MLX5_EXPANSION_OUTER_IPV6_UDP, 768 MLX5_EXPANSION_OUTER_IPV6_TCP, 769 MLX5_EXPANSION_OUTER_IPV6_ESP, 770 MLX5_EXPANSION_OUTER_IPV6_ICMP6, 771 MLX5_EXPANSION_IPV4, 772 MLX5_EXPANSION_IPV6, 773 MLX5_EXPANSION_GRE, 774 MLX5_EXPANSION_NVGRE), 775 .type = RTE_FLOW_ITEM_TYPE_IPV6, 776 .rss_types = RTE_ETH_RSS_IPV6 | RTE_ETH_RSS_FRAG_IPV6 | 777 RTE_ETH_RSS_NONFRAG_IPV6_OTHER, 778 }, 779 [MLX5_EXPANSION_OUTER_IPV6_UDP] = { 780 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_VXLAN, 781 MLX5_EXPANSION_VXLAN_GPE, 782 MLX5_EXPANSION_MPLS, 783 MLX5_EXPANSION_GENEVE, 784 MLX5_EXPANSION_GTP), 785 .type = RTE_FLOW_ITEM_TYPE_UDP, 786 .rss_types = RTE_ETH_RSS_NONFRAG_IPV6_UDP, 787 }, 788 [MLX5_EXPANSION_OUTER_IPV6_TCP] = { 789 .type = RTE_FLOW_ITEM_TYPE_TCP, 790 .rss_types = RTE_ETH_RSS_NONFRAG_IPV6_TCP, 791 }, 792 [MLX5_EXPANSION_OUTER_IPV6_ESP] = { 793 .type = RTE_FLOW_ITEM_TYPE_ESP, 794 .rss_types = RTE_ETH_RSS_ESP, 795 }, 796 [MLX5_EXPANSION_OUTER_IPV6_ICMP6] = { 797 .type = RTE_FLOW_ITEM_TYPE_ICMP6, 798 }, 799 [MLX5_EXPANSION_VXLAN] = { 800 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_ETH, 801 MLX5_EXPANSION_IPV4, 802 MLX5_EXPANSION_IPV6), 803 .type = RTE_FLOW_ITEM_TYPE_VXLAN, 804 }, 805 [MLX5_EXPANSION_STD_VXLAN] = { 806 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_ETH), 807 .type = RTE_FLOW_ITEM_TYPE_VXLAN, 808 }, 809 [MLX5_EXPANSION_L3_VXLAN] = { 810 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_IPV4, 811 MLX5_EXPANSION_IPV6), 812 .type = RTE_FLOW_ITEM_TYPE_VXLAN, 813 }, 814 [MLX5_EXPANSION_VXLAN_GPE] = { 815 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_ETH, 816 MLX5_EXPANSION_IPV4, 817 MLX5_EXPANSION_IPV6), 818 .type = RTE_FLOW_ITEM_TYPE_VXLAN_GPE, 819 }, 820 [MLX5_EXPANSION_GRE] = { 821 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_ETH, 822 MLX5_EXPANSION_IPV4, 823 MLX5_EXPANSION_IPV6, 824 MLX5_EXPANSION_GRE_KEY, 825 MLX5_EXPANSION_MPLS), 826 .type = RTE_FLOW_ITEM_TYPE_GRE, 827 }, 828 [MLX5_EXPANSION_GRE_KEY] = { 829 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_IPV4, 830 MLX5_EXPANSION_IPV6, 831 MLX5_EXPANSION_MPLS), 832 .type = RTE_FLOW_ITEM_TYPE_GRE_KEY, 833 .node_flags = MLX5_EXPANSION_NODE_OPTIONAL, 834 }, 835 [MLX5_EXPANSION_NVGRE] = { 836 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_ETH), 837 .type = RTE_FLOW_ITEM_TYPE_NVGRE, 838 }, 839 [MLX5_EXPANSION_MPLS] = { 840 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_IPV4, 841 MLX5_EXPANSION_IPV6, 842 MLX5_EXPANSION_ETH), 843 .type = RTE_FLOW_ITEM_TYPE_MPLS, 844 .node_flags = MLX5_EXPANSION_NODE_OPTIONAL, 845 }, 846 [MLX5_EXPANSION_ETH] = { 847 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_VLAN), 848 .type = RTE_FLOW_ITEM_TYPE_ETH, 849 }, 850 [MLX5_EXPANSION_VLAN] = { 851 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_IPV4, 852 MLX5_EXPANSION_IPV6), 853 .type = RTE_FLOW_ITEM_TYPE_VLAN, 854 .node_flags = MLX5_EXPANSION_NODE_EXPLICIT, 855 }, 856 [MLX5_EXPANSION_IPV4] = { 857 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_IPV4_UDP, 858 MLX5_EXPANSION_IPV4_TCP, 859 MLX5_EXPANSION_IPV4_ESP, 860 MLX5_EXPANSION_IPV4_ICMP), 861 .type = RTE_FLOW_ITEM_TYPE_IPV4, 862 .rss_types = RTE_ETH_RSS_IPV4 | RTE_ETH_RSS_FRAG_IPV4 | 863 RTE_ETH_RSS_NONFRAG_IPV4_OTHER, 864 }, 865 [MLX5_EXPANSION_IPV4_UDP] = { 866 .type = RTE_FLOW_ITEM_TYPE_UDP, 867 .rss_types = RTE_ETH_RSS_NONFRAG_IPV4_UDP, 868 }, 869 [MLX5_EXPANSION_IPV4_TCP] = { 870 .type = RTE_FLOW_ITEM_TYPE_TCP, 871 .rss_types = RTE_ETH_RSS_NONFRAG_IPV4_TCP, 872 }, 873 [MLX5_EXPANSION_IPV4_ESP] = { 874 .type = RTE_FLOW_ITEM_TYPE_ESP, 875 .rss_types = RTE_ETH_RSS_ESP, 876 }, 877 [MLX5_EXPANSION_IPV4_ICMP] = { 878 .type = RTE_FLOW_ITEM_TYPE_ICMP, 879 }, 880 [MLX5_EXPANSION_IPV6] = { 881 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_IPV6_UDP, 882 MLX5_EXPANSION_IPV6_TCP, 883 MLX5_EXPANSION_IPV6_ESP, 884 MLX5_EXPANSION_IPV6_ICMP6, 885 MLX5_EXPANSION_IPV6_FRAG_EXT), 886 .type = RTE_FLOW_ITEM_TYPE_IPV6, 887 .rss_types = RTE_ETH_RSS_IPV6 | RTE_ETH_RSS_FRAG_IPV6 | 888 RTE_ETH_RSS_NONFRAG_IPV6_OTHER, 889 }, 890 [MLX5_EXPANSION_IPV6_UDP] = { 891 .type = RTE_FLOW_ITEM_TYPE_UDP, 892 .rss_types = RTE_ETH_RSS_NONFRAG_IPV6_UDP, 893 }, 894 [MLX5_EXPANSION_IPV6_TCP] = { 895 .type = RTE_FLOW_ITEM_TYPE_TCP, 896 .rss_types = RTE_ETH_RSS_NONFRAG_IPV6_TCP, 897 }, 898 [MLX5_EXPANSION_IPV6_ESP] = { 899 .type = RTE_FLOW_ITEM_TYPE_ESP, 900 .rss_types = RTE_ETH_RSS_ESP, 901 }, 902 [MLX5_EXPANSION_IPV6_FRAG_EXT] = { 903 .type = RTE_FLOW_ITEM_TYPE_IPV6_FRAG_EXT, 904 }, 905 [MLX5_EXPANSION_IPV6_ICMP6] = { 906 .type = RTE_FLOW_ITEM_TYPE_ICMP6, 907 }, 908 [MLX5_EXPANSION_GTP] = { 909 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_IPV4, 910 MLX5_EXPANSION_IPV6), 911 .type = RTE_FLOW_ITEM_TYPE_GTP, 912 }, 913 [MLX5_EXPANSION_GENEVE] = { 914 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_ETH, 915 MLX5_EXPANSION_IPV4, 916 MLX5_EXPANSION_IPV6), 917 .type = RTE_FLOW_ITEM_TYPE_GENEVE, 918 }, 919 }; 920 921 static struct rte_flow_action_handle * 922 mlx5_action_handle_create(struct rte_eth_dev *dev, 923 const struct rte_flow_indir_action_conf *conf, 924 const struct rte_flow_action *action, 925 struct rte_flow_error *error); 926 static int mlx5_action_handle_destroy 927 (struct rte_eth_dev *dev, 928 struct rte_flow_action_handle *handle, 929 struct rte_flow_error *error); 930 static int mlx5_action_handle_update 931 (struct rte_eth_dev *dev, 932 struct rte_flow_action_handle *handle, 933 const void *update, 934 struct rte_flow_error *error); 935 static int mlx5_action_handle_query 936 (struct rte_eth_dev *dev, 937 const struct rte_flow_action_handle *handle, 938 void *data, 939 struct rte_flow_error *error); 940 static int 941 mlx5_flow_tunnel_decap_set(struct rte_eth_dev *dev, 942 struct rte_flow_tunnel *app_tunnel, 943 struct rte_flow_action **actions, 944 uint32_t *num_of_actions, 945 struct rte_flow_error *error); 946 static int 947 mlx5_flow_tunnel_match(struct rte_eth_dev *dev, 948 struct rte_flow_tunnel *app_tunnel, 949 struct rte_flow_item **items, 950 uint32_t *num_of_items, 951 struct rte_flow_error *error); 952 static int 953 mlx5_flow_tunnel_item_release(struct rte_eth_dev *dev, 954 struct rte_flow_item *pmd_items, 955 uint32_t num_items, struct rte_flow_error *err); 956 static int 957 mlx5_flow_tunnel_action_release(struct rte_eth_dev *dev, 958 struct rte_flow_action *pmd_actions, 959 uint32_t num_actions, 960 struct rte_flow_error *err); 961 static int 962 mlx5_flow_tunnel_get_restore_info(struct rte_eth_dev *dev, 963 struct rte_mbuf *m, 964 struct rte_flow_restore_info *info, 965 struct rte_flow_error *err); 966 static struct rte_flow_item_flex_handle * 967 mlx5_flow_flex_item_create(struct rte_eth_dev *dev, 968 const struct rte_flow_item_flex_conf *conf, 969 struct rte_flow_error *error); 970 static int 971 mlx5_flow_flex_item_release(struct rte_eth_dev *dev, 972 const struct rte_flow_item_flex_handle *handle, 973 struct rte_flow_error *error); 974 static int 975 mlx5_flow_info_get(struct rte_eth_dev *dev, 976 struct rte_flow_port_info *port_info, 977 struct rte_flow_queue_info *queue_info, 978 struct rte_flow_error *error); 979 static int 980 mlx5_flow_port_configure(struct rte_eth_dev *dev, 981 const struct rte_flow_port_attr *port_attr, 982 uint16_t nb_queue, 983 const struct rte_flow_queue_attr *queue_attr[], 984 struct rte_flow_error *err); 985 986 static struct rte_flow_pattern_template * 987 mlx5_flow_pattern_template_create(struct rte_eth_dev *dev, 988 const struct rte_flow_pattern_template_attr *attr, 989 const struct rte_flow_item items[], 990 struct rte_flow_error *error); 991 992 static int 993 mlx5_flow_pattern_template_destroy(struct rte_eth_dev *dev, 994 struct rte_flow_pattern_template *template, 995 struct rte_flow_error *error); 996 static struct rte_flow_actions_template * 997 mlx5_flow_actions_template_create(struct rte_eth_dev *dev, 998 const struct rte_flow_actions_template_attr *attr, 999 const struct rte_flow_action actions[], 1000 const struct rte_flow_action masks[], 1001 struct rte_flow_error *error); 1002 static int 1003 mlx5_flow_actions_template_destroy(struct rte_eth_dev *dev, 1004 struct rte_flow_actions_template *template, 1005 struct rte_flow_error *error); 1006 1007 static struct rte_flow_template_table * 1008 mlx5_flow_table_create(struct rte_eth_dev *dev, 1009 const struct rte_flow_template_table_attr *attr, 1010 struct rte_flow_pattern_template *item_templates[], 1011 uint8_t nb_item_templates, 1012 struct rte_flow_actions_template *action_templates[], 1013 uint8_t nb_action_templates, 1014 struct rte_flow_error *error); 1015 static int 1016 mlx5_flow_table_destroy(struct rte_eth_dev *dev, 1017 struct rte_flow_template_table *table, 1018 struct rte_flow_error *error); 1019 static struct rte_flow * 1020 mlx5_flow_async_flow_create(struct rte_eth_dev *dev, 1021 uint32_t queue, 1022 const struct rte_flow_op_attr *attr, 1023 struct rte_flow_template_table *table, 1024 const struct rte_flow_item items[], 1025 uint8_t pattern_template_index, 1026 const struct rte_flow_action actions[], 1027 uint8_t action_template_index, 1028 void *user_data, 1029 struct rte_flow_error *error); 1030 static int 1031 mlx5_flow_async_flow_destroy(struct rte_eth_dev *dev, 1032 uint32_t queue, 1033 const struct rte_flow_op_attr *attr, 1034 struct rte_flow *flow, 1035 void *user_data, 1036 struct rte_flow_error *error); 1037 static int 1038 mlx5_flow_pull(struct rte_eth_dev *dev, 1039 uint32_t queue, 1040 struct rte_flow_op_result res[], 1041 uint16_t n_res, 1042 struct rte_flow_error *error); 1043 static int 1044 mlx5_flow_push(struct rte_eth_dev *dev, 1045 uint32_t queue, 1046 struct rte_flow_error *error); 1047 1048 static struct rte_flow_action_handle * 1049 mlx5_flow_async_action_handle_create(struct rte_eth_dev *dev, uint32_t queue, 1050 const struct rte_flow_op_attr *attr, 1051 const struct rte_flow_indir_action_conf *conf, 1052 const struct rte_flow_action *action, 1053 void *user_data, 1054 struct rte_flow_error *error); 1055 1056 static int 1057 mlx5_flow_async_action_handle_update(struct rte_eth_dev *dev, uint32_t queue, 1058 const struct rte_flow_op_attr *attr, 1059 struct rte_flow_action_handle *handle, 1060 const void *update, 1061 void *user_data, 1062 struct rte_flow_error *error); 1063 1064 static int 1065 mlx5_flow_async_action_handle_destroy(struct rte_eth_dev *dev, uint32_t queue, 1066 const struct rte_flow_op_attr *attr, 1067 struct rte_flow_action_handle *handle, 1068 void *user_data, 1069 struct rte_flow_error *error); 1070 1071 static int 1072 mlx5_flow_async_action_handle_query(struct rte_eth_dev *dev, uint32_t queue, 1073 const struct rte_flow_op_attr *attr, 1074 const struct rte_flow_action_handle *handle, 1075 void *data, 1076 void *user_data, 1077 struct rte_flow_error *error); 1078 1079 static const struct rte_flow_ops mlx5_flow_ops = { 1080 .validate = mlx5_flow_validate, 1081 .create = mlx5_flow_create, 1082 .destroy = mlx5_flow_destroy, 1083 .flush = mlx5_flow_flush, 1084 .isolate = mlx5_flow_isolate, 1085 .query = mlx5_flow_query, 1086 .dev_dump = mlx5_flow_dev_dump, 1087 .get_q_aged_flows = mlx5_flow_get_q_aged_flows, 1088 .get_aged_flows = mlx5_flow_get_aged_flows, 1089 .action_handle_create = mlx5_action_handle_create, 1090 .action_handle_destroy = mlx5_action_handle_destroy, 1091 .action_handle_update = mlx5_action_handle_update, 1092 .action_handle_query = mlx5_action_handle_query, 1093 .tunnel_decap_set = mlx5_flow_tunnel_decap_set, 1094 .tunnel_match = mlx5_flow_tunnel_match, 1095 .tunnel_action_decap_release = mlx5_flow_tunnel_action_release, 1096 .tunnel_item_release = mlx5_flow_tunnel_item_release, 1097 .get_restore_info = mlx5_flow_tunnel_get_restore_info, 1098 .flex_item_create = mlx5_flow_flex_item_create, 1099 .flex_item_release = mlx5_flow_flex_item_release, 1100 .info_get = mlx5_flow_info_get, 1101 .pick_transfer_proxy = mlx5_flow_pick_transfer_proxy, 1102 .configure = mlx5_flow_port_configure, 1103 .pattern_template_create = mlx5_flow_pattern_template_create, 1104 .pattern_template_destroy = mlx5_flow_pattern_template_destroy, 1105 .actions_template_create = mlx5_flow_actions_template_create, 1106 .actions_template_destroy = mlx5_flow_actions_template_destroy, 1107 .template_table_create = mlx5_flow_table_create, 1108 .template_table_destroy = mlx5_flow_table_destroy, 1109 .async_create = mlx5_flow_async_flow_create, 1110 .async_destroy = mlx5_flow_async_flow_destroy, 1111 .pull = mlx5_flow_pull, 1112 .push = mlx5_flow_push, 1113 .async_action_handle_create = mlx5_flow_async_action_handle_create, 1114 .async_action_handle_update = mlx5_flow_async_action_handle_update, 1115 .async_action_handle_query = mlx5_flow_async_action_handle_query, 1116 .async_action_handle_destroy = mlx5_flow_async_action_handle_destroy, 1117 }; 1118 1119 /* Tunnel information. */ 1120 struct mlx5_flow_tunnel_info { 1121 uint64_t tunnel; /**< Tunnel bit (see MLX5_FLOW_*). */ 1122 uint32_t ptype; /**< Tunnel Ptype (see RTE_PTYPE_*). */ 1123 }; 1124 1125 static struct mlx5_flow_tunnel_info tunnels_info[] = { 1126 { 1127 .tunnel = MLX5_FLOW_LAYER_VXLAN, 1128 .ptype = RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_L4_UDP, 1129 }, 1130 { 1131 .tunnel = MLX5_FLOW_LAYER_GENEVE, 1132 .ptype = RTE_PTYPE_TUNNEL_GENEVE | RTE_PTYPE_L4_UDP, 1133 }, 1134 { 1135 .tunnel = MLX5_FLOW_LAYER_VXLAN_GPE, 1136 .ptype = RTE_PTYPE_TUNNEL_VXLAN_GPE | RTE_PTYPE_L4_UDP, 1137 }, 1138 { 1139 .tunnel = MLX5_FLOW_LAYER_GRE, 1140 .ptype = RTE_PTYPE_TUNNEL_GRE, 1141 }, 1142 { 1143 .tunnel = MLX5_FLOW_LAYER_MPLS | MLX5_FLOW_LAYER_OUTER_L4_UDP, 1144 .ptype = RTE_PTYPE_TUNNEL_MPLS_IN_UDP | RTE_PTYPE_L4_UDP, 1145 }, 1146 { 1147 .tunnel = MLX5_FLOW_LAYER_MPLS, 1148 .ptype = RTE_PTYPE_TUNNEL_MPLS_IN_GRE, 1149 }, 1150 { 1151 .tunnel = MLX5_FLOW_LAYER_NVGRE, 1152 .ptype = RTE_PTYPE_TUNNEL_NVGRE, 1153 }, 1154 { 1155 .tunnel = MLX5_FLOW_LAYER_IPIP, 1156 .ptype = RTE_PTYPE_TUNNEL_IP, 1157 }, 1158 { 1159 .tunnel = MLX5_FLOW_LAYER_IPV6_ENCAP, 1160 .ptype = RTE_PTYPE_TUNNEL_IP, 1161 }, 1162 { 1163 .tunnel = MLX5_FLOW_LAYER_GTP, 1164 .ptype = RTE_PTYPE_TUNNEL_GTPU, 1165 }, 1166 }; 1167 1168 1169 1170 /** 1171 * Translate tag ID to register. 1172 * 1173 * @param[in] dev 1174 * Pointer to the Ethernet device structure. 1175 * @param[in] feature 1176 * The feature that request the register. 1177 * @param[in] id 1178 * The request register ID. 1179 * @param[out] error 1180 * Error description in case of any. 1181 * 1182 * @return 1183 * The request register on success, a negative errno 1184 * value otherwise and rte_errno is set. 1185 */ 1186 int 1187 mlx5_flow_get_reg_id(struct rte_eth_dev *dev, 1188 enum mlx5_feature_name feature, 1189 uint32_t id, 1190 struct rte_flow_error *error) 1191 { 1192 struct mlx5_priv *priv = dev->data->dev_private; 1193 struct mlx5_sh_config *config = &priv->sh->config; 1194 enum modify_reg start_reg; 1195 bool skip_mtr_reg = false; 1196 1197 switch (feature) { 1198 case MLX5_HAIRPIN_RX: 1199 return REG_B; 1200 case MLX5_HAIRPIN_TX: 1201 return REG_A; 1202 case MLX5_METADATA_RX: 1203 switch (config->dv_xmeta_en) { 1204 case MLX5_XMETA_MODE_LEGACY: 1205 return REG_B; 1206 case MLX5_XMETA_MODE_META16: 1207 return REG_C_0; 1208 case MLX5_XMETA_MODE_META32: 1209 return REG_C_1; 1210 case MLX5_XMETA_MODE_META32_HWS: 1211 return REG_C_1; 1212 } 1213 break; 1214 case MLX5_METADATA_TX: 1215 if (config->dv_flow_en == 2 && config->dv_xmeta_en == MLX5_XMETA_MODE_META32_HWS) { 1216 return REG_C_1; 1217 } else { 1218 return REG_A; 1219 } 1220 case MLX5_METADATA_FDB: 1221 switch (config->dv_xmeta_en) { 1222 case MLX5_XMETA_MODE_LEGACY: 1223 return REG_NON; 1224 case MLX5_XMETA_MODE_META16: 1225 return REG_C_0; 1226 case MLX5_XMETA_MODE_META32: 1227 return REG_C_1; 1228 case MLX5_XMETA_MODE_META32_HWS: 1229 return REG_C_1; 1230 } 1231 break; 1232 case MLX5_FLOW_MARK: 1233 switch (config->dv_xmeta_en) { 1234 case MLX5_XMETA_MODE_LEGACY: 1235 case MLX5_XMETA_MODE_META32_HWS: 1236 return REG_NON; 1237 case MLX5_XMETA_MODE_META16: 1238 return REG_C_1; 1239 case MLX5_XMETA_MODE_META32: 1240 return REG_C_0; 1241 } 1242 break; 1243 case MLX5_MTR_ID: 1244 /* 1245 * If meter color and meter id share one register, flow match 1246 * should use the meter color register for match. 1247 */ 1248 if (priv->mtr_reg_share) 1249 return priv->mtr_color_reg; 1250 else 1251 return priv->mtr_color_reg != REG_C_2 ? REG_C_2 : 1252 REG_C_3; 1253 case MLX5_MTR_COLOR: 1254 case MLX5_ASO_FLOW_HIT: 1255 case MLX5_ASO_CONNTRACK: 1256 case MLX5_SAMPLE_ID: 1257 /* All features use the same REG_C. */ 1258 MLX5_ASSERT(priv->mtr_color_reg != REG_NON); 1259 return priv->mtr_color_reg; 1260 case MLX5_COPY_MARK: 1261 /* 1262 * Metadata COPY_MARK register using is in meter suffix sub 1263 * flow while with meter. It's safe to share the same register. 1264 */ 1265 return priv->mtr_color_reg != REG_C_2 ? REG_C_2 : REG_C_3; 1266 case MLX5_APP_TAG: 1267 /* 1268 * If meter is enable, it will engage the register for color 1269 * match and flow match. If meter color match is not using the 1270 * REG_C_2, need to skip the REG_C_x be used by meter color 1271 * match. 1272 * If meter is disable, free to use all available registers. 1273 */ 1274 start_reg = priv->mtr_color_reg != REG_C_2 ? REG_C_2 : 1275 (priv->mtr_reg_share ? REG_C_3 : REG_C_4); 1276 skip_mtr_reg = !!(priv->mtr_en && start_reg == REG_C_2); 1277 if (id > (uint32_t)(REG_C_7 - start_reg)) 1278 return rte_flow_error_set(error, EINVAL, 1279 RTE_FLOW_ERROR_TYPE_ITEM, 1280 NULL, "invalid tag id"); 1281 if (priv->sh->flow_mreg_c[id + start_reg - REG_C_0] == REG_NON) 1282 return rte_flow_error_set(error, ENOTSUP, 1283 RTE_FLOW_ERROR_TYPE_ITEM, 1284 NULL, "unsupported tag id"); 1285 /* 1286 * This case means meter is using the REG_C_x great than 2. 1287 * Take care not to conflict with meter color REG_C_x. 1288 * If the available index REG_C_y >= REG_C_x, skip the 1289 * color register. 1290 */ 1291 if (skip_mtr_reg && priv->sh->flow_mreg_c 1292 [id + start_reg - REG_C_0] >= priv->mtr_color_reg) { 1293 if (id >= (uint32_t)(REG_C_7 - start_reg)) 1294 return rte_flow_error_set(error, EINVAL, 1295 RTE_FLOW_ERROR_TYPE_ITEM, 1296 NULL, "invalid tag id"); 1297 if (priv->sh->flow_mreg_c 1298 [id + 1 + start_reg - REG_C_0] != REG_NON) 1299 return priv->sh->flow_mreg_c 1300 [id + 1 + start_reg - REG_C_0]; 1301 return rte_flow_error_set(error, ENOTSUP, 1302 RTE_FLOW_ERROR_TYPE_ITEM, 1303 NULL, "unsupported tag id"); 1304 } 1305 return priv->sh->flow_mreg_c[id + start_reg - REG_C_0]; 1306 } 1307 MLX5_ASSERT(false); 1308 return rte_flow_error_set(error, EINVAL, 1309 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, 1310 NULL, "invalid feature name"); 1311 } 1312 1313 /** 1314 * Check extensive flow metadata register support. 1315 * 1316 * @param dev 1317 * Pointer to rte_eth_dev structure. 1318 * 1319 * @return 1320 * True if device supports extensive flow metadata register, otherwise false. 1321 */ 1322 bool 1323 mlx5_flow_ext_mreg_supported(struct rte_eth_dev *dev) 1324 { 1325 struct mlx5_priv *priv = dev->data->dev_private; 1326 1327 /* 1328 * Having available reg_c can be regarded inclusively as supporting 1329 * extensive flow metadata register, which could mean, 1330 * - metadata register copy action by modify header. 1331 * - 16 modify header actions is supported. 1332 * - reg_c's are preserved across different domain (FDB and NIC) on 1333 * packet loopback by flow lookup miss. 1334 */ 1335 return priv->sh->flow_mreg_c[2] != REG_NON; 1336 } 1337 1338 /** 1339 * Get the lowest priority. 1340 * 1341 * @param[in] dev 1342 * Pointer to the Ethernet device structure. 1343 * @param[in] attributes 1344 * Pointer to device flow rule attributes. 1345 * 1346 * @return 1347 * The value of lowest priority of flow. 1348 */ 1349 uint32_t 1350 mlx5_get_lowest_priority(struct rte_eth_dev *dev, 1351 const struct rte_flow_attr *attr) 1352 { 1353 struct mlx5_priv *priv = dev->data->dev_private; 1354 1355 if (!attr->group && !(attr->transfer && priv->fdb_def_rule)) 1356 return priv->sh->flow_max_priority - 2; 1357 return MLX5_NON_ROOT_FLOW_MAX_PRIO - 1; 1358 } 1359 1360 /** 1361 * Calculate matcher priority of the flow. 1362 * 1363 * @param[in] dev 1364 * Pointer to the Ethernet device structure. 1365 * @param[in] attr 1366 * Pointer to device flow rule attributes. 1367 * @param[in] subpriority 1368 * The priority based on the items. 1369 * @param[in] external 1370 * Flow is user flow. 1371 * @return 1372 * The matcher priority of the flow. 1373 */ 1374 uint16_t 1375 mlx5_get_matcher_priority(struct rte_eth_dev *dev, 1376 const struct rte_flow_attr *attr, 1377 uint32_t subpriority, bool external) 1378 { 1379 uint16_t priority = (uint16_t)attr->priority; 1380 struct mlx5_priv *priv = dev->data->dev_private; 1381 1382 /* NIC root rules */ 1383 if (!attr->group && !attr->transfer) { 1384 if (attr->priority == MLX5_FLOW_LOWEST_PRIO_INDICATOR) 1385 priority = priv->sh->flow_max_priority - 1; 1386 return mlx5_os_flow_adjust_priority(dev, priority, subpriority); 1387 /* FDB root rules */ 1388 } else if (attr->transfer && (!external || !priv->fdb_def_rule) && 1389 attr->group == 0 && 1390 attr->priority == MLX5_FLOW_LOWEST_PRIO_INDICATOR) { 1391 return (priv->sh->flow_max_priority - 1) * 3; 1392 } 1393 if (attr->priority == MLX5_FLOW_LOWEST_PRIO_INDICATOR) 1394 priority = MLX5_NON_ROOT_FLOW_MAX_PRIO; 1395 return priority * 3 + subpriority; 1396 } 1397 1398 /** 1399 * Verify the @p item specifications (spec, last, mask) are compatible with the 1400 * NIC capabilities. 1401 * 1402 * @param[in] item 1403 * Item specification. 1404 * @param[in] mask 1405 * @p item->mask or flow default bit-masks. 1406 * @param[in] nic_mask 1407 * Bit-masks covering supported fields by the NIC to compare with user mask. 1408 * @param[in] size 1409 * Bit-masks size in bytes. 1410 * @param[in] range_accepted 1411 * True if range of values is accepted for specific fields, false otherwise. 1412 * @param[out] error 1413 * Pointer to error structure. 1414 * 1415 * @return 1416 * 0 on success, a negative errno value otherwise and rte_errno is set. 1417 */ 1418 int 1419 mlx5_flow_item_acceptable(const struct rte_flow_item *item, 1420 const uint8_t *mask, 1421 const uint8_t *nic_mask, 1422 unsigned int size, 1423 bool range_accepted, 1424 struct rte_flow_error *error) 1425 { 1426 unsigned int i; 1427 1428 MLX5_ASSERT(nic_mask); 1429 for (i = 0; i < size; ++i) 1430 if ((nic_mask[i] | mask[i]) != nic_mask[i]) 1431 return rte_flow_error_set(error, ENOTSUP, 1432 RTE_FLOW_ERROR_TYPE_ITEM, 1433 item, 1434 "mask enables non supported" 1435 " bits"); 1436 if (!item->spec && (item->mask || item->last)) 1437 return rte_flow_error_set(error, EINVAL, 1438 RTE_FLOW_ERROR_TYPE_ITEM, item, 1439 "mask/last without a spec is not" 1440 " supported"); 1441 if (item->spec && item->last && !range_accepted) { 1442 uint8_t spec[size]; 1443 uint8_t last[size]; 1444 unsigned int i; 1445 int ret; 1446 1447 for (i = 0; i < size; ++i) { 1448 spec[i] = ((const uint8_t *)item->spec)[i] & mask[i]; 1449 last[i] = ((const uint8_t *)item->last)[i] & mask[i]; 1450 } 1451 ret = memcmp(spec, last, size); 1452 if (ret != 0) 1453 return rte_flow_error_set(error, EINVAL, 1454 RTE_FLOW_ERROR_TYPE_ITEM, 1455 item, 1456 "range is not valid"); 1457 } 1458 return 0; 1459 } 1460 1461 /** 1462 * Adjust the hash fields according to the @p flow information. 1463 * 1464 * @param[in] dev_flow. 1465 * Pointer to the mlx5_flow. 1466 * @param[in] tunnel 1467 * 1 when the hash field is for a tunnel item. 1468 * @param[in] layer_types 1469 * RTE_ETH_RSS_* types. 1470 * @param[in] hash_fields 1471 * Item hash fields. 1472 * 1473 * @return 1474 * The hash fields that should be used. 1475 */ 1476 uint64_t 1477 mlx5_flow_hashfields_adjust(struct mlx5_flow_rss_desc *rss_desc, 1478 int tunnel __rte_unused, uint64_t layer_types, 1479 uint64_t hash_fields) 1480 { 1481 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT 1482 int rss_request_inner = rss_desc->level >= 2; 1483 1484 /* Check RSS hash level for tunnel. */ 1485 if (tunnel && rss_request_inner) 1486 hash_fields |= IBV_RX_HASH_INNER; 1487 else if (tunnel || rss_request_inner) 1488 return 0; 1489 #endif 1490 /* Check if requested layer matches RSS hash fields. */ 1491 if (!(rss_desc->types & layer_types)) 1492 return 0; 1493 return hash_fields; 1494 } 1495 1496 /** 1497 * Lookup and set the ptype in the data Rx part. A single Ptype can be used, 1498 * if several tunnel rules are used on this queue, the tunnel ptype will be 1499 * cleared. 1500 * 1501 * @param rxq_ctrl 1502 * Rx queue to update. 1503 */ 1504 static void 1505 flow_rxq_tunnel_ptype_update(struct mlx5_rxq_ctrl *rxq_ctrl) 1506 { 1507 unsigned int i; 1508 uint32_t tunnel_ptype = 0; 1509 1510 /* Look up for the ptype to use. */ 1511 for (i = 0; i != MLX5_FLOW_TUNNEL; ++i) { 1512 if (!rxq_ctrl->flow_tunnels_n[i]) 1513 continue; 1514 if (!tunnel_ptype) { 1515 tunnel_ptype = tunnels_info[i].ptype; 1516 } else { 1517 tunnel_ptype = 0; 1518 break; 1519 } 1520 } 1521 rxq_ctrl->rxq.tunnel = tunnel_ptype; 1522 } 1523 1524 /** 1525 * Set the Rx queue flags (Mark/Flag and Tunnel Ptypes) according to the device 1526 * flow. 1527 * 1528 * @param[in] dev 1529 * Pointer to the Ethernet device structure. 1530 * @param[in] dev_handle 1531 * Pointer to device flow handle structure. 1532 */ 1533 void 1534 flow_drv_rxq_flags_set(struct rte_eth_dev *dev, 1535 struct mlx5_flow_handle *dev_handle) 1536 { 1537 struct mlx5_priv *priv = dev->data->dev_private; 1538 const int tunnel = !!(dev_handle->layers & MLX5_FLOW_LAYER_TUNNEL); 1539 struct mlx5_ind_table_obj *ind_tbl = NULL; 1540 unsigned int i; 1541 1542 if (dev_handle->fate_action == MLX5_FLOW_FATE_QUEUE) { 1543 struct mlx5_hrxq *hrxq; 1544 1545 hrxq = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_HRXQ], 1546 dev_handle->rix_hrxq); 1547 if (hrxq) 1548 ind_tbl = hrxq->ind_table; 1549 } else if (dev_handle->fate_action == MLX5_FLOW_FATE_SHARED_RSS) { 1550 struct mlx5_shared_action_rss *shared_rss; 1551 1552 shared_rss = mlx5_ipool_get 1553 (priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], 1554 dev_handle->rix_srss); 1555 if (shared_rss) 1556 ind_tbl = shared_rss->ind_tbl; 1557 } 1558 if (!ind_tbl) 1559 return; 1560 for (i = 0; i != ind_tbl->queues_n; ++i) { 1561 int idx = ind_tbl->queues[i]; 1562 struct mlx5_rxq_ctrl *rxq_ctrl; 1563 1564 if (mlx5_is_external_rxq(dev, idx)) 1565 continue; 1566 rxq_ctrl = mlx5_rxq_ctrl_get(dev, idx); 1567 MLX5_ASSERT(rxq_ctrl != NULL); 1568 if (rxq_ctrl == NULL) 1569 continue; 1570 /* 1571 * To support metadata register copy on Tx loopback, 1572 * this must be always enabled (metadata may arive 1573 * from other port - not from local flows only. 1574 */ 1575 if (tunnel) { 1576 unsigned int j; 1577 1578 /* Increase the counter matching the flow. */ 1579 for (j = 0; j != MLX5_FLOW_TUNNEL; ++j) { 1580 if ((tunnels_info[j].tunnel & 1581 dev_handle->layers) == 1582 tunnels_info[j].tunnel) { 1583 rxq_ctrl->flow_tunnels_n[j]++; 1584 break; 1585 } 1586 } 1587 flow_rxq_tunnel_ptype_update(rxq_ctrl); 1588 } 1589 } 1590 } 1591 1592 static void 1593 flow_rxq_mark_flag_set(struct rte_eth_dev *dev) 1594 { 1595 struct mlx5_priv *priv = dev->data->dev_private; 1596 struct mlx5_rxq_ctrl *rxq_ctrl; 1597 uint16_t port_id; 1598 1599 if (priv->sh->shared_mark_enabled) 1600 return; 1601 if (priv->master || priv->representor) { 1602 MLX5_ETH_FOREACH_DEV(port_id, dev->device) { 1603 struct mlx5_priv *opriv = 1604 rte_eth_devices[port_id].data->dev_private; 1605 1606 if (!opriv || 1607 opriv->sh != priv->sh || 1608 opriv->domain_id != priv->domain_id || 1609 opriv->mark_enabled) 1610 continue; 1611 LIST_FOREACH(rxq_ctrl, &opriv->rxqsctrl, next) { 1612 rxq_ctrl->rxq.mark = 1; 1613 } 1614 opriv->mark_enabled = 1; 1615 } 1616 } else { 1617 LIST_FOREACH(rxq_ctrl, &priv->rxqsctrl, next) { 1618 rxq_ctrl->rxq.mark = 1; 1619 } 1620 priv->mark_enabled = 1; 1621 } 1622 priv->sh->shared_mark_enabled = 1; 1623 } 1624 1625 /** 1626 * Set the Rx queue flags (Mark/Flag and Tunnel Ptypes) for a flow 1627 * 1628 * @param[in] dev 1629 * Pointer to the Ethernet device structure. 1630 * @param[in] flow 1631 * Pointer to flow structure. 1632 */ 1633 static void 1634 flow_rxq_flags_set(struct rte_eth_dev *dev, struct rte_flow *flow) 1635 { 1636 struct mlx5_priv *priv = dev->data->dev_private; 1637 uint32_t handle_idx; 1638 struct mlx5_flow_handle *dev_handle; 1639 struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace(); 1640 1641 MLX5_ASSERT(wks); 1642 if (wks->mark) 1643 flow_rxq_mark_flag_set(dev); 1644 SILIST_FOREACH(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW], flow->dev_handles, 1645 handle_idx, dev_handle, next) 1646 flow_drv_rxq_flags_set(dev, dev_handle); 1647 } 1648 1649 /** 1650 * Clear the Rx queue flags (Mark/Flag and Tunnel Ptype) associated with the 1651 * device flow if no other flow uses it with the same kind of request. 1652 * 1653 * @param dev 1654 * Pointer to Ethernet device. 1655 * @param[in] dev_handle 1656 * Pointer to the device flow handle structure. 1657 */ 1658 static void 1659 flow_drv_rxq_flags_trim(struct rte_eth_dev *dev, 1660 struct mlx5_flow_handle *dev_handle) 1661 { 1662 struct mlx5_priv *priv = dev->data->dev_private; 1663 const int tunnel = !!(dev_handle->layers & MLX5_FLOW_LAYER_TUNNEL); 1664 struct mlx5_ind_table_obj *ind_tbl = NULL; 1665 unsigned int i; 1666 1667 if (dev_handle->fate_action == MLX5_FLOW_FATE_QUEUE) { 1668 struct mlx5_hrxq *hrxq; 1669 1670 hrxq = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_HRXQ], 1671 dev_handle->rix_hrxq); 1672 if (hrxq) 1673 ind_tbl = hrxq->ind_table; 1674 } else if (dev_handle->fate_action == MLX5_FLOW_FATE_SHARED_RSS) { 1675 struct mlx5_shared_action_rss *shared_rss; 1676 1677 shared_rss = mlx5_ipool_get 1678 (priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], 1679 dev_handle->rix_srss); 1680 if (shared_rss) 1681 ind_tbl = shared_rss->ind_tbl; 1682 } 1683 if (!ind_tbl) 1684 return; 1685 MLX5_ASSERT(dev->data->dev_started); 1686 for (i = 0; i != ind_tbl->queues_n; ++i) { 1687 int idx = ind_tbl->queues[i]; 1688 struct mlx5_rxq_ctrl *rxq_ctrl; 1689 1690 if (mlx5_is_external_rxq(dev, idx)) 1691 continue; 1692 rxq_ctrl = mlx5_rxq_ctrl_get(dev, idx); 1693 MLX5_ASSERT(rxq_ctrl != NULL); 1694 if (rxq_ctrl == NULL) 1695 continue; 1696 if (tunnel) { 1697 unsigned int j; 1698 1699 /* Decrease the counter matching the flow. */ 1700 for (j = 0; j != MLX5_FLOW_TUNNEL; ++j) { 1701 if ((tunnels_info[j].tunnel & 1702 dev_handle->layers) == 1703 tunnels_info[j].tunnel) { 1704 rxq_ctrl->flow_tunnels_n[j]--; 1705 break; 1706 } 1707 } 1708 flow_rxq_tunnel_ptype_update(rxq_ctrl); 1709 } 1710 } 1711 } 1712 1713 /** 1714 * Clear the Rx queue flags (Mark/Flag and Tunnel Ptype) associated with the 1715 * @p flow if no other flow uses it with the same kind of request. 1716 * 1717 * @param dev 1718 * Pointer to Ethernet device. 1719 * @param[in] flow 1720 * Pointer to the flow. 1721 */ 1722 static void 1723 flow_rxq_flags_trim(struct rte_eth_dev *dev, struct rte_flow *flow) 1724 { 1725 struct mlx5_priv *priv = dev->data->dev_private; 1726 uint32_t handle_idx; 1727 struct mlx5_flow_handle *dev_handle; 1728 1729 SILIST_FOREACH(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW], flow->dev_handles, 1730 handle_idx, dev_handle, next) 1731 flow_drv_rxq_flags_trim(dev, dev_handle); 1732 } 1733 1734 /** 1735 * Clear the Mark/Flag and Tunnel ptype information in all Rx queues. 1736 * 1737 * @param dev 1738 * Pointer to Ethernet device. 1739 */ 1740 static void 1741 flow_rxq_flags_clear(struct rte_eth_dev *dev) 1742 { 1743 struct mlx5_priv *priv = dev->data->dev_private; 1744 unsigned int i; 1745 1746 for (i = 0; i != priv->rxqs_n; ++i) { 1747 struct mlx5_rxq_priv *rxq = mlx5_rxq_get(dev, i); 1748 unsigned int j; 1749 1750 if (rxq == NULL || rxq->ctrl == NULL) 1751 continue; 1752 rxq->ctrl->rxq.mark = 0; 1753 for (j = 0; j != MLX5_FLOW_TUNNEL; ++j) 1754 rxq->ctrl->flow_tunnels_n[j] = 0; 1755 rxq->ctrl->rxq.tunnel = 0; 1756 } 1757 priv->mark_enabled = 0; 1758 priv->sh->shared_mark_enabled = 0; 1759 } 1760 1761 /** 1762 * Set the Rx queue dynamic metadata (mask and offset) for a flow 1763 * 1764 * @param[in] dev 1765 * Pointer to the Ethernet device structure. 1766 */ 1767 void 1768 mlx5_flow_rxq_dynf_metadata_set(struct rte_eth_dev *dev) 1769 { 1770 struct mlx5_priv *priv = dev->data->dev_private; 1771 unsigned int i; 1772 1773 for (i = 0; i != priv->rxqs_n; ++i) { 1774 struct mlx5_rxq_priv *rxq = mlx5_rxq_get(dev, i); 1775 struct mlx5_rxq_data *data; 1776 1777 if (rxq == NULL || rxq->ctrl == NULL) 1778 continue; 1779 data = &rxq->ctrl->rxq; 1780 if (!rte_flow_dynf_metadata_avail()) { 1781 data->dynf_meta = 0; 1782 data->flow_meta_mask = 0; 1783 data->flow_meta_offset = -1; 1784 data->flow_meta_port_mask = 0; 1785 } else { 1786 data->dynf_meta = 1; 1787 data->flow_meta_mask = rte_flow_dynf_metadata_mask; 1788 data->flow_meta_offset = rte_flow_dynf_metadata_offs; 1789 data->flow_meta_port_mask = priv->sh->dv_meta_mask; 1790 } 1791 } 1792 } 1793 1794 /* 1795 * return a pointer to the desired action in the list of actions. 1796 * 1797 * @param[in] actions 1798 * The list of actions to search the action in. 1799 * @param[in] action 1800 * The action to find. 1801 * 1802 * @return 1803 * Pointer to the action in the list, if found. NULL otherwise. 1804 */ 1805 const struct rte_flow_action * 1806 mlx5_flow_find_action(const struct rte_flow_action *actions, 1807 enum rte_flow_action_type action) 1808 { 1809 if (actions == NULL) 1810 return NULL; 1811 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) 1812 if (actions->type == action) 1813 return actions; 1814 return NULL; 1815 } 1816 1817 /* 1818 * Validate the flag action. 1819 * 1820 * @param[in] action_flags 1821 * Bit-fields that holds the actions detected until now. 1822 * @param[in] attr 1823 * Attributes of flow that includes this action. 1824 * @param[out] error 1825 * Pointer to error structure. 1826 * 1827 * @return 1828 * 0 on success, a negative errno value otherwise and rte_errno is set. 1829 */ 1830 int 1831 mlx5_flow_validate_action_flag(uint64_t action_flags, 1832 const struct rte_flow_attr *attr, 1833 struct rte_flow_error *error) 1834 { 1835 if (action_flags & MLX5_FLOW_ACTION_MARK) 1836 return rte_flow_error_set(error, EINVAL, 1837 RTE_FLOW_ERROR_TYPE_ACTION, NULL, 1838 "can't mark and flag in same flow"); 1839 if (action_flags & MLX5_FLOW_ACTION_FLAG) 1840 return rte_flow_error_set(error, EINVAL, 1841 RTE_FLOW_ERROR_TYPE_ACTION, NULL, 1842 "can't have 2 flag" 1843 " actions in same flow"); 1844 if (attr->egress) 1845 return rte_flow_error_set(error, ENOTSUP, 1846 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, NULL, 1847 "flag action not supported for " 1848 "egress"); 1849 return 0; 1850 } 1851 1852 /* 1853 * Validate the mark action. 1854 * 1855 * @param[in] action 1856 * Pointer to the queue action. 1857 * @param[in] action_flags 1858 * Bit-fields that holds the actions detected until now. 1859 * @param[in] attr 1860 * Attributes of flow that includes this action. 1861 * @param[out] error 1862 * Pointer to error structure. 1863 * 1864 * @return 1865 * 0 on success, a negative errno value otherwise and rte_errno is set. 1866 */ 1867 int 1868 mlx5_flow_validate_action_mark(const struct rte_flow_action *action, 1869 uint64_t action_flags, 1870 const struct rte_flow_attr *attr, 1871 struct rte_flow_error *error) 1872 { 1873 const struct rte_flow_action_mark *mark = action->conf; 1874 1875 if (!mark) 1876 return rte_flow_error_set(error, EINVAL, 1877 RTE_FLOW_ERROR_TYPE_ACTION, 1878 action, 1879 "configuration cannot be null"); 1880 if (mark->id >= MLX5_FLOW_MARK_MAX) 1881 return rte_flow_error_set(error, EINVAL, 1882 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 1883 &mark->id, 1884 "mark id must in 0 <= id < " 1885 RTE_STR(MLX5_FLOW_MARK_MAX)); 1886 if (action_flags & MLX5_FLOW_ACTION_FLAG) 1887 return rte_flow_error_set(error, EINVAL, 1888 RTE_FLOW_ERROR_TYPE_ACTION, NULL, 1889 "can't flag and mark in same flow"); 1890 if (action_flags & MLX5_FLOW_ACTION_MARK) 1891 return rte_flow_error_set(error, EINVAL, 1892 RTE_FLOW_ERROR_TYPE_ACTION, NULL, 1893 "can't have 2 mark actions in same" 1894 " flow"); 1895 if (attr->egress) 1896 return rte_flow_error_set(error, ENOTSUP, 1897 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, NULL, 1898 "mark action not supported for " 1899 "egress"); 1900 return 0; 1901 } 1902 1903 /* 1904 * Validate the drop action. 1905 * 1906 * @param[in] action_flags 1907 * Bit-fields that holds the actions detected until now. 1908 * @param[in] attr 1909 * Attributes of flow that includes this action. 1910 * @param[out] error 1911 * Pointer to error structure. 1912 * 1913 * @return 1914 * 0 on success, a negative errno value otherwise and rte_errno is set. 1915 */ 1916 int 1917 mlx5_flow_validate_action_drop(uint64_t action_flags __rte_unused, 1918 const struct rte_flow_attr *attr, 1919 struct rte_flow_error *error) 1920 { 1921 if (attr->egress) 1922 return rte_flow_error_set(error, ENOTSUP, 1923 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, NULL, 1924 "drop action not supported for " 1925 "egress"); 1926 return 0; 1927 } 1928 1929 /* 1930 * Validate the queue action. 1931 * 1932 * @param[in] action 1933 * Pointer to the queue action. 1934 * @param[in] action_flags 1935 * Bit-fields that holds the actions detected until now. 1936 * @param[in] dev 1937 * Pointer to the Ethernet device structure. 1938 * @param[in] attr 1939 * Attributes of flow that includes this action. 1940 * @param[out] error 1941 * Pointer to error structure. 1942 * 1943 * @return 1944 * 0 on success, a negative errno value otherwise and rte_errno is set. 1945 */ 1946 int 1947 mlx5_flow_validate_action_queue(const struct rte_flow_action *action, 1948 uint64_t action_flags, 1949 struct rte_eth_dev *dev, 1950 const struct rte_flow_attr *attr, 1951 struct rte_flow_error *error) 1952 { 1953 struct mlx5_priv *priv = dev->data->dev_private; 1954 const struct rte_flow_action_queue *queue = action->conf; 1955 1956 if (action_flags & MLX5_FLOW_FATE_ACTIONS) 1957 return rte_flow_error_set(error, EINVAL, 1958 RTE_FLOW_ERROR_TYPE_ACTION, NULL, 1959 "can't have 2 fate actions in" 1960 " same flow"); 1961 if (attr->egress) 1962 return rte_flow_error_set(error, ENOTSUP, 1963 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, NULL, 1964 "queue action not supported for egress."); 1965 if (mlx5_is_external_rxq(dev, queue->index)) 1966 return 0; 1967 if (!priv->rxqs_n) 1968 return rte_flow_error_set(error, EINVAL, 1969 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 1970 NULL, "No Rx queues configured"); 1971 if (queue->index >= priv->rxqs_n) 1972 return rte_flow_error_set(error, EINVAL, 1973 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 1974 &queue->index, 1975 "queue index out of range"); 1976 if (mlx5_rxq_get(dev, queue->index) == NULL) 1977 return rte_flow_error_set(error, EINVAL, 1978 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 1979 &queue->index, 1980 "queue is not configured"); 1981 return 0; 1982 } 1983 1984 /** 1985 * Validate queue numbers for device RSS. 1986 * 1987 * @param[in] dev 1988 * Configured device. 1989 * @param[in] queues 1990 * Array of queue numbers. 1991 * @param[in] queues_n 1992 * Size of the @p queues array. 1993 * @param[out] error 1994 * On error, filled with a textual error description. 1995 * @param[out] queue_idx 1996 * On error, filled with an offending queue index in @p queues array. 1997 * 1998 * @return 1999 * 0 on success, a negative errno code on error. 2000 */ 2001 static int 2002 mlx5_validate_rss_queues(struct rte_eth_dev *dev, 2003 const uint16_t *queues, uint32_t queues_n, 2004 const char **error, uint32_t *queue_idx) 2005 { 2006 const struct mlx5_priv *priv = dev->data->dev_private; 2007 bool is_hairpin = false; 2008 bool is_ext_rss = false; 2009 uint32_t i; 2010 2011 for (i = 0; i != queues_n; ++i) { 2012 struct mlx5_rxq_ctrl *rxq_ctrl; 2013 2014 if (mlx5_is_external_rxq(dev, queues[0])) { 2015 is_ext_rss = true; 2016 continue; 2017 } 2018 if (is_ext_rss) { 2019 *error = "Combining external and regular RSS queues is not supported"; 2020 *queue_idx = i; 2021 return -ENOTSUP; 2022 } 2023 if (queues[i] >= priv->rxqs_n) { 2024 *error = "queue index out of range"; 2025 *queue_idx = i; 2026 return -EINVAL; 2027 } 2028 rxq_ctrl = mlx5_rxq_ctrl_get(dev, queues[i]); 2029 if (rxq_ctrl == NULL) { 2030 *error = "queue is not configured"; 2031 *queue_idx = i; 2032 return -EINVAL; 2033 } 2034 if (i == 0 && rxq_ctrl->is_hairpin) 2035 is_hairpin = true; 2036 if (is_hairpin != rxq_ctrl->is_hairpin) { 2037 *error = "combining hairpin and regular RSS queues is not supported"; 2038 *queue_idx = i; 2039 return -ENOTSUP; 2040 } 2041 } 2042 return 0; 2043 } 2044 2045 /* 2046 * Validate the rss action. 2047 * 2048 * @param[in] dev 2049 * Pointer to the Ethernet device structure. 2050 * @param[in] action 2051 * Pointer to the queue action. 2052 * @param[out] error 2053 * Pointer to error structure. 2054 * 2055 * @return 2056 * 0 on success, a negative errno value otherwise and rte_errno is set. 2057 */ 2058 int 2059 mlx5_validate_action_rss(struct rte_eth_dev *dev, 2060 const struct rte_flow_action *action, 2061 struct rte_flow_error *error) 2062 { 2063 struct mlx5_priv *priv = dev->data->dev_private; 2064 const struct rte_flow_action_rss *rss = action->conf; 2065 int ret; 2066 const char *message; 2067 uint32_t queue_idx; 2068 2069 if (rss->func != RTE_ETH_HASH_FUNCTION_DEFAULT && 2070 rss->func != RTE_ETH_HASH_FUNCTION_TOEPLITZ) 2071 return rte_flow_error_set(error, ENOTSUP, 2072 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 2073 &rss->func, 2074 "RSS hash function not supported"); 2075 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT 2076 if (rss->level > 2) 2077 #else 2078 if (rss->level > 1) 2079 #endif 2080 return rte_flow_error_set(error, ENOTSUP, 2081 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 2082 &rss->level, 2083 "tunnel RSS is not supported"); 2084 /* allow RSS key_len 0 in case of NULL (default) RSS key. */ 2085 if (rss->key_len == 0 && rss->key != NULL) 2086 return rte_flow_error_set(error, ENOTSUP, 2087 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 2088 &rss->key_len, 2089 "RSS hash key length 0"); 2090 if (rss->key_len > 0 && rss->key_len < MLX5_RSS_HASH_KEY_LEN) 2091 return rte_flow_error_set(error, ENOTSUP, 2092 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 2093 &rss->key_len, 2094 "RSS hash key too small"); 2095 if (rss->key_len > MLX5_RSS_HASH_KEY_LEN) 2096 return rte_flow_error_set(error, ENOTSUP, 2097 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 2098 &rss->key_len, 2099 "RSS hash key too large"); 2100 if (rss->queue_num > priv->sh->dev_cap.ind_table_max_size) 2101 return rte_flow_error_set(error, ENOTSUP, 2102 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 2103 &rss->queue_num, 2104 "number of queues too large"); 2105 if (rss->types & MLX5_RSS_HF_MASK) 2106 return rte_flow_error_set(error, ENOTSUP, 2107 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 2108 &rss->types, 2109 "some RSS protocols are not" 2110 " supported"); 2111 if ((rss->types & (RTE_ETH_RSS_L3_SRC_ONLY | RTE_ETH_RSS_L3_DST_ONLY)) && 2112 !(rss->types & RTE_ETH_RSS_IP)) 2113 return rte_flow_error_set(error, EINVAL, 2114 RTE_FLOW_ERROR_TYPE_ACTION_CONF, NULL, 2115 "L3 partial RSS requested but L3 RSS" 2116 " type not specified"); 2117 if ((rss->types & (RTE_ETH_RSS_L4_SRC_ONLY | RTE_ETH_RSS_L4_DST_ONLY)) && 2118 !(rss->types & (RTE_ETH_RSS_UDP | RTE_ETH_RSS_TCP))) 2119 return rte_flow_error_set(error, EINVAL, 2120 RTE_FLOW_ERROR_TYPE_ACTION_CONF, NULL, 2121 "L4 partial RSS requested but L4 RSS" 2122 " type not specified"); 2123 if (!priv->rxqs_n && priv->ext_rxqs == NULL) 2124 return rte_flow_error_set(error, EINVAL, 2125 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 2126 NULL, "No Rx queues configured"); 2127 if (!rss->queue_num) 2128 return rte_flow_error_set(error, EINVAL, 2129 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 2130 NULL, "No queues configured"); 2131 ret = mlx5_validate_rss_queues(dev, rss->queue, rss->queue_num, 2132 &message, &queue_idx); 2133 if (ret != 0) { 2134 return rte_flow_error_set(error, -ret, 2135 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 2136 &rss->queue[queue_idx], message); 2137 } 2138 return 0; 2139 } 2140 2141 /* 2142 * Validate the rss action. 2143 * 2144 * @param[in] action 2145 * Pointer to the queue action. 2146 * @param[in] action_flags 2147 * Bit-fields that holds the actions detected until now. 2148 * @param[in] dev 2149 * Pointer to the Ethernet device structure. 2150 * @param[in] attr 2151 * Attributes of flow that includes this action. 2152 * @param[in] item_flags 2153 * Items that were detected. 2154 * @param[out] error 2155 * Pointer to error structure. 2156 * 2157 * @return 2158 * 0 on success, a negative errno value otherwise and rte_errno is set. 2159 */ 2160 int 2161 mlx5_flow_validate_action_rss(const struct rte_flow_action *action, 2162 uint64_t action_flags, 2163 struct rte_eth_dev *dev, 2164 const struct rte_flow_attr *attr, 2165 uint64_t item_flags, 2166 struct rte_flow_error *error) 2167 { 2168 const struct rte_flow_action_rss *rss = action->conf; 2169 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL); 2170 int ret; 2171 2172 if (action_flags & MLX5_FLOW_FATE_ACTIONS) 2173 return rte_flow_error_set(error, EINVAL, 2174 RTE_FLOW_ERROR_TYPE_ACTION, NULL, 2175 "can't have 2 fate actions" 2176 " in same flow"); 2177 ret = mlx5_validate_action_rss(dev, action, error); 2178 if (ret) 2179 return ret; 2180 if (attr->egress) 2181 return rte_flow_error_set(error, ENOTSUP, 2182 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, NULL, 2183 "rss action not supported for " 2184 "egress"); 2185 if (rss->level > 1 && !tunnel) 2186 return rte_flow_error_set(error, EINVAL, 2187 RTE_FLOW_ERROR_TYPE_ACTION_CONF, NULL, 2188 "inner RSS is not supported for " 2189 "non-tunnel flows"); 2190 if ((item_flags & MLX5_FLOW_LAYER_ECPRI) && 2191 !(item_flags & MLX5_FLOW_LAYER_INNER_L4_UDP)) { 2192 return rte_flow_error_set(error, EINVAL, 2193 RTE_FLOW_ERROR_TYPE_ACTION_CONF, NULL, 2194 "RSS on eCPRI is not supported now"); 2195 } 2196 if ((item_flags & MLX5_FLOW_LAYER_MPLS) && 2197 !(item_flags & 2198 (MLX5_FLOW_LAYER_INNER_L2 | MLX5_FLOW_LAYER_INNER_L3)) && 2199 rss->level > 1) 2200 return rte_flow_error_set(error, EINVAL, 2201 RTE_FLOW_ERROR_TYPE_ITEM, NULL, 2202 "MPLS inner RSS needs to specify inner L2/L3 items after MPLS in pattern"); 2203 return 0; 2204 } 2205 2206 /* 2207 * Validate the default miss action. 2208 * 2209 * @param[in] action_flags 2210 * Bit-fields that holds the actions detected until now. 2211 * @param[out] error 2212 * Pointer to error structure. 2213 * 2214 * @return 2215 * 0 on success, a negative errno value otherwise and rte_errno is set. 2216 */ 2217 int 2218 mlx5_flow_validate_action_default_miss(uint64_t action_flags, 2219 const struct rte_flow_attr *attr, 2220 struct rte_flow_error *error) 2221 { 2222 if (action_flags & MLX5_FLOW_FATE_ACTIONS) 2223 return rte_flow_error_set(error, EINVAL, 2224 RTE_FLOW_ERROR_TYPE_ACTION, NULL, 2225 "can't have 2 fate actions in" 2226 " same flow"); 2227 if (attr->egress) 2228 return rte_flow_error_set(error, ENOTSUP, 2229 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, NULL, 2230 "default miss action not supported " 2231 "for egress"); 2232 if (attr->group) 2233 return rte_flow_error_set(error, ENOTSUP, 2234 RTE_FLOW_ERROR_TYPE_ATTR_GROUP, NULL, 2235 "only group 0 is supported"); 2236 if (attr->transfer) 2237 return rte_flow_error_set(error, ENOTSUP, 2238 RTE_FLOW_ERROR_TYPE_ATTR_TRANSFER, 2239 NULL, "transfer is not supported"); 2240 return 0; 2241 } 2242 2243 /* 2244 * Validate the count action. 2245 * 2246 * @param[in] dev 2247 * Pointer to the Ethernet device structure. 2248 * @param[in] attr 2249 * Attributes of flow that includes this action. 2250 * @param[out] error 2251 * Pointer to error structure. 2252 * 2253 * @return 2254 * 0 on success, a negative errno value otherwise and rte_errno is set. 2255 */ 2256 int 2257 mlx5_flow_validate_action_count(struct rte_eth_dev *dev __rte_unused, 2258 const struct rte_flow_attr *attr, 2259 struct rte_flow_error *error) 2260 { 2261 if (attr->egress) 2262 return rte_flow_error_set(error, ENOTSUP, 2263 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, NULL, 2264 "count action not supported for " 2265 "egress"); 2266 return 0; 2267 } 2268 2269 /* 2270 * Validate the ASO CT action. 2271 * 2272 * @param[in] dev 2273 * Pointer to the Ethernet device structure. 2274 * @param[in] conntrack 2275 * Pointer to the CT action profile. 2276 * @param[out] error 2277 * Pointer to error structure. 2278 * 2279 * @return 2280 * 0 on success, a negative errno value otherwise and rte_errno is set. 2281 */ 2282 int 2283 mlx5_validate_action_ct(struct rte_eth_dev *dev, 2284 const struct rte_flow_action_conntrack *conntrack, 2285 struct rte_flow_error *error) 2286 { 2287 RTE_SET_USED(dev); 2288 2289 if (conntrack->state > RTE_FLOW_CONNTRACK_STATE_TIME_WAIT) 2290 return rte_flow_error_set(error, EINVAL, 2291 RTE_FLOW_ERROR_TYPE_ACTION, NULL, 2292 "Invalid CT state"); 2293 if (conntrack->last_index > RTE_FLOW_CONNTRACK_FLAG_RST) 2294 return rte_flow_error_set(error, EINVAL, 2295 RTE_FLOW_ERROR_TYPE_ACTION, NULL, 2296 "Invalid last TCP packet flag"); 2297 return 0; 2298 } 2299 2300 /** 2301 * Validate ICMP6 item. 2302 * 2303 * @param[in] item 2304 * Item specification. 2305 * @param[in] item_flags 2306 * Bit-fields that holds the items detected until now. 2307 * @param[in] ext_vlan_sup 2308 * Whether extended VLAN features are supported or not. 2309 * @param[out] error 2310 * Pointer to error structure. 2311 * 2312 * @return 2313 * 0 on success, a negative errno value otherwise and rte_errno is set. 2314 */ 2315 int 2316 mlx5_flow_validate_item_icmp6(const struct rte_flow_item *item, 2317 uint64_t item_flags, 2318 uint8_t target_protocol, 2319 struct rte_flow_error *error) 2320 { 2321 const struct rte_flow_item_icmp6 *mask = item->mask; 2322 const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL); 2323 const uint64_t l3m = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 : 2324 MLX5_FLOW_LAYER_OUTER_L3_IPV6; 2325 const uint64_t l4m = tunnel ? MLX5_FLOW_LAYER_INNER_L4 : 2326 MLX5_FLOW_LAYER_OUTER_L4; 2327 int ret; 2328 2329 if (target_protocol != 0xFF && target_protocol != IPPROTO_ICMPV6) 2330 return rte_flow_error_set(error, EINVAL, 2331 RTE_FLOW_ERROR_TYPE_ITEM, item, 2332 "protocol filtering not compatible" 2333 " with ICMP6 layer"); 2334 if (!(item_flags & l3m)) 2335 return rte_flow_error_set(error, EINVAL, 2336 RTE_FLOW_ERROR_TYPE_ITEM, item, 2337 "IPv6 is mandatory to filter on" 2338 " ICMP6"); 2339 if (item_flags & l4m) 2340 return rte_flow_error_set(error, EINVAL, 2341 RTE_FLOW_ERROR_TYPE_ITEM, item, 2342 "multiple L4 layers not supported"); 2343 if (!mask) 2344 mask = &rte_flow_item_icmp6_mask; 2345 ret = mlx5_flow_item_acceptable 2346 (item, (const uint8_t *)mask, 2347 (const uint8_t *)&rte_flow_item_icmp6_mask, 2348 sizeof(struct rte_flow_item_icmp6), 2349 MLX5_ITEM_RANGE_NOT_ACCEPTED, error); 2350 if (ret < 0) 2351 return ret; 2352 return 0; 2353 } 2354 2355 /** 2356 * Validate ICMP6 echo request/reply item. 2357 * 2358 * @param[in] item 2359 * Item specification. 2360 * @param[in] item_flags 2361 * Bit-fields that holds the items detected until now. 2362 * @param[in] ext_vlan_sup 2363 * Whether extended VLAN features are supported or not. 2364 * @param[out] error 2365 * Pointer to error structure. 2366 * 2367 * @return 2368 * 0 on success, a negative errno value otherwise and rte_errno is set. 2369 */ 2370 int 2371 mlx5_flow_validate_item_icmp6_echo(const struct rte_flow_item *item, 2372 uint64_t item_flags, 2373 uint8_t target_protocol, 2374 struct rte_flow_error *error) 2375 { 2376 const struct rte_flow_item_icmp6_echo *mask = item->mask; 2377 const struct rte_flow_item_icmp6_echo nic_mask = { 2378 .hdr.base.type = 0xff, 2379 .hdr.base.code = 0xff, 2380 .hdr.identifier = RTE_BE16(0xffff), 2381 .hdr.sequence = RTE_BE16(0xffff), 2382 }; 2383 const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL); 2384 const uint64_t l3m = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 : 2385 MLX5_FLOW_LAYER_OUTER_L3_IPV6; 2386 const uint64_t l4m = tunnel ? MLX5_FLOW_LAYER_INNER_L4 : 2387 MLX5_FLOW_LAYER_OUTER_L4; 2388 int ret; 2389 2390 if (target_protocol != 0xFF && target_protocol != IPPROTO_ICMPV6) 2391 return rte_flow_error_set(error, EINVAL, 2392 RTE_FLOW_ERROR_TYPE_ITEM, item, 2393 "protocol filtering not compatible" 2394 " with ICMP6 layer"); 2395 if (!(item_flags & l3m)) 2396 return rte_flow_error_set(error, EINVAL, 2397 RTE_FLOW_ERROR_TYPE_ITEM, item, 2398 "IPv6 is mandatory to filter on" 2399 " ICMP6"); 2400 if (item_flags & l4m) 2401 return rte_flow_error_set(error, EINVAL, 2402 RTE_FLOW_ERROR_TYPE_ITEM, item, 2403 "multiple L4 layers not supported"); 2404 if (!mask) 2405 mask = &nic_mask; 2406 ret = mlx5_flow_item_acceptable 2407 (item, (const uint8_t *)mask, 2408 (const uint8_t *)&nic_mask, 2409 sizeof(struct rte_flow_item_icmp6_echo), 2410 MLX5_ITEM_RANGE_NOT_ACCEPTED, error); 2411 if (ret < 0) 2412 return ret; 2413 return 0; 2414 } 2415 2416 /** 2417 * Validate ICMP item. 2418 * 2419 * @param[in] item 2420 * Item specification. 2421 * @param[in] item_flags 2422 * Bit-fields that holds the items detected until now. 2423 * @param[out] error 2424 * Pointer to error structure. 2425 * 2426 * @return 2427 * 0 on success, a negative errno value otherwise and rte_errno is set. 2428 */ 2429 int 2430 mlx5_flow_validate_item_icmp(const struct rte_flow_item *item, 2431 uint64_t item_flags, 2432 uint8_t target_protocol, 2433 struct rte_flow_error *error) 2434 { 2435 const struct rte_flow_item_icmp *mask = item->mask; 2436 const struct rte_flow_item_icmp nic_mask = { 2437 .hdr.icmp_type = 0xff, 2438 .hdr.icmp_code = 0xff, 2439 .hdr.icmp_ident = RTE_BE16(0xffff), 2440 .hdr.icmp_seq_nb = RTE_BE16(0xffff), 2441 }; 2442 const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL); 2443 const uint64_t l3m = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 : 2444 MLX5_FLOW_LAYER_OUTER_L3_IPV4; 2445 const uint64_t l4m = tunnel ? MLX5_FLOW_LAYER_INNER_L4 : 2446 MLX5_FLOW_LAYER_OUTER_L4; 2447 int ret; 2448 2449 if (target_protocol != 0xFF && target_protocol != IPPROTO_ICMP) 2450 return rte_flow_error_set(error, EINVAL, 2451 RTE_FLOW_ERROR_TYPE_ITEM, item, 2452 "protocol filtering not compatible" 2453 " with ICMP layer"); 2454 if (!(item_flags & l3m)) 2455 return rte_flow_error_set(error, EINVAL, 2456 RTE_FLOW_ERROR_TYPE_ITEM, item, 2457 "IPv4 is mandatory to filter" 2458 " on ICMP"); 2459 if (item_flags & l4m) 2460 return rte_flow_error_set(error, EINVAL, 2461 RTE_FLOW_ERROR_TYPE_ITEM, item, 2462 "multiple L4 layers not supported"); 2463 if (!mask) 2464 mask = &nic_mask; 2465 ret = mlx5_flow_item_acceptable 2466 (item, (const uint8_t *)mask, 2467 (const uint8_t *)&nic_mask, 2468 sizeof(struct rte_flow_item_icmp), 2469 MLX5_ITEM_RANGE_NOT_ACCEPTED, error); 2470 if (ret < 0) 2471 return ret; 2472 return 0; 2473 } 2474 2475 /** 2476 * Validate Ethernet item. 2477 * 2478 * @param[in] item 2479 * Item specification. 2480 * @param[in] item_flags 2481 * Bit-fields that holds the items detected until now. 2482 * @param[out] error 2483 * Pointer to error structure. 2484 * 2485 * @return 2486 * 0 on success, a negative errno value otherwise and rte_errno is set. 2487 */ 2488 int 2489 mlx5_flow_validate_item_eth(const struct rte_flow_item *item, 2490 uint64_t item_flags, bool ext_vlan_sup, 2491 struct rte_flow_error *error) 2492 { 2493 const struct rte_flow_item_eth *mask = item->mask; 2494 const struct rte_flow_item_eth nic_mask = { 2495 .hdr.dst_addr.addr_bytes = "\xff\xff\xff\xff\xff\xff", 2496 .hdr.src_addr.addr_bytes = "\xff\xff\xff\xff\xff\xff", 2497 .hdr.ether_type = RTE_BE16(0xffff), 2498 .has_vlan = ext_vlan_sup ? 1 : 0, 2499 }; 2500 int ret; 2501 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL); 2502 const uint64_t ethm = tunnel ? MLX5_FLOW_LAYER_INNER_L2 : 2503 MLX5_FLOW_LAYER_OUTER_L2; 2504 2505 if (item_flags & ethm) 2506 return rte_flow_error_set(error, ENOTSUP, 2507 RTE_FLOW_ERROR_TYPE_ITEM, item, 2508 "multiple L2 layers not supported"); 2509 if ((!tunnel && (item_flags & MLX5_FLOW_LAYER_OUTER_L3)) || 2510 (tunnel && (item_flags & MLX5_FLOW_LAYER_INNER_L3))) 2511 return rte_flow_error_set(error, EINVAL, 2512 RTE_FLOW_ERROR_TYPE_ITEM, item, 2513 "L2 layer should not follow " 2514 "L3 layers"); 2515 if ((!tunnel && (item_flags & MLX5_FLOW_LAYER_OUTER_VLAN)) || 2516 (tunnel && (item_flags & MLX5_FLOW_LAYER_INNER_VLAN))) 2517 return rte_flow_error_set(error, EINVAL, 2518 RTE_FLOW_ERROR_TYPE_ITEM, item, 2519 "L2 layer should not follow VLAN"); 2520 if (item_flags & MLX5_FLOW_LAYER_GTP) 2521 return rte_flow_error_set(error, EINVAL, 2522 RTE_FLOW_ERROR_TYPE_ITEM, item, 2523 "L2 layer should not follow GTP"); 2524 if (!mask) 2525 mask = &rte_flow_item_eth_mask; 2526 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask, 2527 (const uint8_t *)&nic_mask, 2528 sizeof(struct rte_flow_item_eth), 2529 MLX5_ITEM_RANGE_NOT_ACCEPTED, error); 2530 return ret; 2531 } 2532 2533 /** 2534 * Validate VLAN item. 2535 * 2536 * @param[in] item 2537 * Item specification. 2538 * @param[in] item_flags 2539 * Bit-fields that holds the items detected until now. 2540 * @param[in] dev 2541 * Ethernet device flow is being created on. 2542 * @param[out] error 2543 * Pointer to error structure. 2544 * 2545 * @return 2546 * 0 on success, a negative errno value otherwise and rte_errno is set. 2547 */ 2548 int 2549 mlx5_flow_validate_item_vlan(const struct rte_flow_item *item, 2550 uint64_t item_flags, 2551 struct rte_eth_dev *dev, 2552 struct rte_flow_error *error) 2553 { 2554 const struct rte_flow_item_vlan *spec = item->spec; 2555 const struct rte_flow_item_vlan *mask = item->mask; 2556 const struct rte_flow_item_vlan nic_mask = { 2557 .hdr.vlan_tci = RTE_BE16(UINT16_MAX), 2558 .hdr.eth_proto = RTE_BE16(UINT16_MAX), 2559 }; 2560 uint16_t vlan_tag = 0; 2561 const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL); 2562 int ret; 2563 const uint64_t l34m = tunnel ? (MLX5_FLOW_LAYER_INNER_L3 | 2564 MLX5_FLOW_LAYER_INNER_L4) : 2565 (MLX5_FLOW_LAYER_OUTER_L3 | 2566 MLX5_FLOW_LAYER_OUTER_L4); 2567 const uint64_t vlanm = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN : 2568 MLX5_FLOW_LAYER_OUTER_VLAN; 2569 2570 if (item_flags & vlanm) 2571 return rte_flow_error_set(error, EINVAL, 2572 RTE_FLOW_ERROR_TYPE_ITEM, item, 2573 "multiple VLAN layers not supported"); 2574 else if ((item_flags & l34m) != 0) 2575 return rte_flow_error_set(error, EINVAL, 2576 RTE_FLOW_ERROR_TYPE_ITEM, item, 2577 "VLAN cannot follow L3/L4 layer"); 2578 if (!mask) 2579 mask = &rte_flow_item_vlan_mask; 2580 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask, 2581 (const uint8_t *)&nic_mask, 2582 sizeof(struct rte_flow_item_vlan), 2583 MLX5_ITEM_RANGE_NOT_ACCEPTED, error); 2584 if (ret) 2585 return ret; 2586 if (!tunnel && mask->hdr.vlan_tci != RTE_BE16(0x0fff)) { 2587 struct mlx5_priv *priv = dev->data->dev_private; 2588 2589 if (priv->vmwa_context) { 2590 /* 2591 * Non-NULL context means we have a virtual machine 2592 * and SR-IOV enabled, we have to create VLAN interface 2593 * to make hypervisor to setup E-Switch vport 2594 * context correctly. We avoid creating the multiple 2595 * VLAN interfaces, so we cannot support VLAN tag mask. 2596 */ 2597 return rte_flow_error_set(error, EINVAL, 2598 RTE_FLOW_ERROR_TYPE_ITEM, 2599 item, 2600 "VLAN tag mask is not" 2601 " supported in virtual" 2602 " environment"); 2603 } 2604 } 2605 if (spec) { 2606 vlan_tag = spec->hdr.vlan_tci; 2607 vlan_tag &= mask->hdr.vlan_tci; 2608 } 2609 /* 2610 * From verbs perspective an empty VLAN is equivalent 2611 * to a packet without VLAN layer. 2612 */ 2613 if (!vlan_tag) 2614 return rte_flow_error_set(error, EINVAL, 2615 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, 2616 item->spec, 2617 "VLAN cannot be empty"); 2618 return 0; 2619 } 2620 2621 /** 2622 * Validate IPV4 item. 2623 * 2624 * @param[in] item 2625 * Item specification. 2626 * @param[in] item_flags 2627 * Bit-fields that holds the items detected until now. 2628 * @param[in] last_item 2629 * Previous validated item in the pattern items. 2630 * @param[in] ether_type 2631 * Type in the ethernet layer header (including dot1q). 2632 * @param[in] acc_mask 2633 * Acceptable mask, if NULL default internal default mask 2634 * will be used to check whether item fields are supported. 2635 * @param[in] range_accepted 2636 * True if range of values is accepted for specific fields, false otherwise. 2637 * @param[out] error 2638 * Pointer to error structure. 2639 * 2640 * @return 2641 * 0 on success, a negative errno value otherwise and rte_errno is set. 2642 */ 2643 int 2644 mlx5_flow_validate_item_ipv4(const struct rte_flow_item *item, 2645 uint64_t item_flags, 2646 uint64_t last_item, 2647 uint16_t ether_type, 2648 const struct rte_flow_item_ipv4 *acc_mask, 2649 bool range_accepted, 2650 struct rte_flow_error *error) 2651 { 2652 const struct rte_flow_item_ipv4 *mask = item->mask; 2653 const struct rte_flow_item_ipv4 *spec = item->spec; 2654 const struct rte_flow_item_ipv4 nic_mask = { 2655 .hdr = { 2656 .src_addr = RTE_BE32(0xffffffff), 2657 .dst_addr = RTE_BE32(0xffffffff), 2658 .type_of_service = 0xff, 2659 .next_proto_id = 0xff, 2660 }, 2661 }; 2662 const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL); 2663 const uint64_t l3m = tunnel ? MLX5_FLOW_LAYER_INNER_L3 : 2664 MLX5_FLOW_LAYER_OUTER_L3; 2665 const uint64_t l4m = tunnel ? MLX5_FLOW_LAYER_INNER_L4 : 2666 MLX5_FLOW_LAYER_OUTER_L4; 2667 int ret; 2668 uint8_t next_proto = 0xFF; 2669 const uint64_t l2_vlan = (MLX5_FLOW_LAYER_L2 | 2670 MLX5_FLOW_LAYER_OUTER_VLAN | 2671 MLX5_FLOW_LAYER_INNER_VLAN); 2672 2673 if ((last_item & l2_vlan) && ether_type && 2674 ether_type != RTE_ETHER_TYPE_IPV4) 2675 return rte_flow_error_set(error, EINVAL, 2676 RTE_FLOW_ERROR_TYPE_ITEM, item, 2677 "IPv4 cannot follow L2/VLAN layer " 2678 "which ether type is not IPv4"); 2679 if (item_flags & MLX5_FLOW_LAYER_IPIP) { 2680 if (mask && spec) 2681 next_proto = mask->hdr.next_proto_id & 2682 spec->hdr.next_proto_id; 2683 if (next_proto == IPPROTO_IPIP || next_proto == IPPROTO_IPV6) 2684 return rte_flow_error_set(error, EINVAL, 2685 RTE_FLOW_ERROR_TYPE_ITEM, 2686 item, 2687 "multiple tunnel " 2688 "not supported"); 2689 } 2690 if (item_flags & MLX5_FLOW_LAYER_IPV6_ENCAP) 2691 return rte_flow_error_set(error, EINVAL, 2692 RTE_FLOW_ERROR_TYPE_ITEM, item, 2693 "wrong tunnel type - IPv6 specified " 2694 "but IPv4 item provided"); 2695 if (item_flags & l3m) 2696 return rte_flow_error_set(error, ENOTSUP, 2697 RTE_FLOW_ERROR_TYPE_ITEM, item, 2698 "multiple L3 layers not supported"); 2699 else if (item_flags & l4m) 2700 return rte_flow_error_set(error, EINVAL, 2701 RTE_FLOW_ERROR_TYPE_ITEM, item, 2702 "L3 cannot follow an L4 layer."); 2703 else if ((item_flags & MLX5_FLOW_LAYER_NVGRE) && 2704 !(item_flags & MLX5_FLOW_LAYER_INNER_L2)) 2705 return rte_flow_error_set(error, EINVAL, 2706 RTE_FLOW_ERROR_TYPE_ITEM, item, 2707 "L3 cannot follow an NVGRE layer."); 2708 if (!mask) 2709 mask = &rte_flow_item_ipv4_mask; 2710 else if (mask->hdr.next_proto_id != 0 && 2711 mask->hdr.next_proto_id != 0xff) 2712 return rte_flow_error_set(error, EINVAL, 2713 RTE_FLOW_ERROR_TYPE_ITEM_MASK, mask, 2714 "partial mask is not supported" 2715 " for protocol"); 2716 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask, 2717 acc_mask ? (const uint8_t *)acc_mask 2718 : (const uint8_t *)&nic_mask, 2719 sizeof(struct rte_flow_item_ipv4), 2720 range_accepted, error); 2721 if (ret < 0) 2722 return ret; 2723 return 0; 2724 } 2725 2726 /** 2727 * Validate IPV6 item. 2728 * 2729 * @param[in] item 2730 * Item specification. 2731 * @param[in] item_flags 2732 * Bit-fields that holds the items detected until now. 2733 * @param[in] last_item 2734 * Previous validated item in the pattern items. 2735 * @param[in] ether_type 2736 * Type in the ethernet layer header (including dot1q). 2737 * @param[in] acc_mask 2738 * Acceptable mask, if NULL default internal default mask 2739 * will be used to check whether item fields are supported. 2740 * @param[out] error 2741 * Pointer to error structure. 2742 * 2743 * @return 2744 * 0 on success, a negative errno value otherwise and rte_errno is set. 2745 */ 2746 int 2747 mlx5_flow_validate_item_ipv6(const struct rte_flow_item *item, 2748 uint64_t item_flags, 2749 uint64_t last_item, 2750 uint16_t ether_type, 2751 const struct rte_flow_item_ipv6 *acc_mask, 2752 struct rte_flow_error *error) 2753 { 2754 const struct rte_flow_item_ipv6 *mask = item->mask; 2755 const struct rte_flow_item_ipv6 *spec = item->spec; 2756 const struct rte_flow_item_ipv6 nic_mask = { 2757 .hdr = { 2758 .src_addr = 2759 "\xff\xff\xff\xff\xff\xff\xff\xff" 2760 "\xff\xff\xff\xff\xff\xff\xff\xff", 2761 .dst_addr = 2762 "\xff\xff\xff\xff\xff\xff\xff\xff" 2763 "\xff\xff\xff\xff\xff\xff\xff\xff", 2764 .vtc_flow = RTE_BE32(0xffffffff), 2765 .proto = 0xff, 2766 }, 2767 }; 2768 const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL); 2769 const uint64_t l3m = tunnel ? MLX5_FLOW_LAYER_INNER_L3 : 2770 MLX5_FLOW_LAYER_OUTER_L3; 2771 const uint64_t l4m = tunnel ? MLX5_FLOW_LAYER_INNER_L4 : 2772 MLX5_FLOW_LAYER_OUTER_L4; 2773 int ret; 2774 uint8_t next_proto = 0xFF; 2775 const uint64_t l2_vlan = (MLX5_FLOW_LAYER_L2 | 2776 MLX5_FLOW_LAYER_OUTER_VLAN | 2777 MLX5_FLOW_LAYER_INNER_VLAN); 2778 2779 if ((last_item & l2_vlan) && ether_type && 2780 ether_type != RTE_ETHER_TYPE_IPV6) 2781 return rte_flow_error_set(error, EINVAL, 2782 RTE_FLOW_ERROR_TYPE_ITEM, item, 2783 "IPv6 cannot follow L2/VLAN layer " 2784 "which ether type is not IPv6"); 2785 if (mask && mask->hdr.proto == UINT8_MAX && spec) 2786 next_proto = spec->hdr.proto; 2787 if (item_flags & MLX5_FLOW_LAYER_IPIP) { 2788 if (next_proto == IPPROTO_IPIP || next_proto == IPPROTO_IPV6) 2789 return rte_flow_error_set(error, EINVAL, 2790 RTE_FLOW_ERROR_TYPE_ITEM, 2791 item, 2792 "multiple tunnel " 2793 "not supported"); 2794 } 2795 if (next_proto == IPPROTO_HOPOPTS || 2796 next_proto == IPPROTO_ROUTING || 2797 next_proto == IPPROTO_FRAGMENT || 2798 next_proto == IPPROTO_ESP || 2799 next_proto == IPPROTO_AH || 2800 next_proto == IPPROTO_DSTOPTS) 2801 return rte_flow_error_set(error, EINVAL, 2802 RTE_FLOW_ERROR_TYPE_ITEM, item, 2803 "IPv6 proto (next header) should " 2804 "not be set as extension header"); 2805 if (item_flags & MLX5_FLOW_LAYER_IPIP) 2806 return rte_flow_error_set(error, EINVAL, 2807 RTE_FLOW_ERROR_TYPE_ITEM, item, 2808 "wrong tunnel type - IPv4 specified " 2809 "but IPv6 item provided"); 2810 if (item_flags & l3m) 2811 return rte_flow_error_set(error, ENOTSUP, 2812 RTE_FLOW_ERROR_TYPE_ITEM, item, 2813 "multiple L3 layers not supported"); 2814 else if (item_flags & l4m) 2815 return rte_flow_error_set(error, EINVAL, 2816 RTE_FLOW_ERROR_TYPE_ITEM, item, 2817 "L3 cannot follow an L4 layer."); 2818 else if ((item_flags & MLX5_FLOW_LAYER_NVGRE) && 2819 !(item_flags & MLX5_FLOW_LAYER_INNER_L2)) 2820 return rte_flow_error_set(error, EINVAL, 2821 RTE_FLOW_ERROR_TYPE_ITEM, item, 2822 "L3 cannot follow an NVGRE layer."); 2823 if (!mask) 2824 mask = &rte_flow_item_ipv6_mask; 2825 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask, 2826 acc_mask ? (const uint8_t *)acc_mask 2827 : (const uint8_t *)&nic_mask, 2828 sizeof(struct rte_flow_item_ipv6), 2829 MLX5_ITEM_RANGE_NOT_ACCEPTED, error); 2830 if (ret < 0) 2831 return ret; 2832 return 0; 2833 } 2834 2835 /** 2836 * Validate UDP item. 2837 * 2838 * @param[in] item 2839 * Item specification. 2840 * @param[in] item_flags 2841 * Bit-fields that holds the items detected until now. 2842 * @param[in] target_protocol 2843 * The next protocol in the previous item. 2844 * @param[in] flow_mask 2845 * mlx5 flow-specific (DV, verbs, etc.) supported header fields mask. 2846 * @param[out] error 2847 * Pointer to error structure. 2848 * 2849 * @return 2850 * 0 on success, a negative errno value otherwise and rte_errno is set. 2851 */ 2852 int 2853 mlx5_flow_validate_item_udp(const struct rte_flow_item *item, 2854 uint64_t item_flags, 2855 uint8_t target_protocol, 2856 struct rte_flow_error *error) 2857 { 2858 const struct rte_flow_item_udp *mask = item->mask; 2859 const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL); 2860 const uint64_t l3m = tunnel ? MLX5_FLOW_LAYER_INNER_L3 : 2861 MLX5_FLOW_LAYER_OUTER_L3; 2862 const uint64_t l4m = tunnel ? MLX5_FLOW_LAYER_INNER_L4 : 2863 MLX5_FLOW_LAYER_OUTER_L4; 2864 int ret; 2865 2866 if (target_protocol != 0xff && target_protocol != IPPROTO_UDP) 2867 return rte_flow_error_set(error, EINVAL, 2868 RTE_FLOW_ERROR_TYPE_ITEM, item, 2869 "protocol filtering not compatible" 2870 " with UDP layer"); 2871 if (!(item_flags & l3m)) 2872 return rte_flow_error_set(error, EINVAL, 2873 RTE_FLOW_ERROR_TYPE_ITEM, item, 2874 "L3 is mandatory to filter on L4"); 2875 if (item_flags & l4m) 2876 return rte_flow_error_set(error, EINVAL, 2877 RTE_FLOW_ERROR_TYPE_ITEM, item, 2878 "multiple L4 layers not supported"); 2879 if (!mask) 2880 mask = &rte_flow_item_udp_mask; 2881 ret = mlx5_flow_item_acceptable 2882 (item, (const uint8_t *)mask, 2883 (const uint8_t *)&rte_flow_item_udp_mask, 2884 sizeof(struct rte_flow_item_udp), MLX5_ITEM_RANGE_NOT_ACCEPTED, 2885 error); 2886 if (ret < 0) 2887 return ret; 2888 return 0; 2889 } 2890 2891 /** 2892 * Validate TCP item. 2893 * 2894 * @param[in] item 2895 * Item specification. 2896 * @param[in] item_flags 2897 * Bit-fields that holds the items detected until now. 2898 * @param[in] target_protocol 2899 * The next protocol in the previous item. 2900 * @param[out] error 2901 * Pointer to error structure. 2902 * 2903 * @return 2904 * 0 on success, a negative errno value otherwise and rte_errno is set. 2905 */ 2906 int 2907 mlx5_flow_validate_item_tcp(const struct rte_flow_item *item, 2908 uint64_t item_flags, 2909 uint8_t target_protocol, 2910 const struct rte_flow_item_tcp *flow_mask, 2911 struct rte_flow_error *error) 2912 { 2913 const struct rte_flow_item_tcp *mask = item->mask; 2914 const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL); 2915 const uint64_t l3m = tunnel ? MLX5_FLOW_LAYER_INNER_L3 : 2916 MLX5_FLOW_LAYER_OUTER_L3; 2917 const uint64_t l4m = tunnel ? MLX5_FLOW_LAYER_INNER_L4 : 2918 MLX5_FLOW_LAYER_OUTER_L4; 2919 int ret; 2920 2921 MLX5_ASSERT(flow_mask); 2922 if (target_protocol != 0xff && target_protocol != IPPROTO_TCP) 2923 return rte_flow_error_set(error, EINVAL, 2924 RTE_FLOW_ERROR_TYPE_ITEM, item, 2925 "protocol filtering not compatible" 2926 " with TCP layer"); 2927 if (!(item_flags & l3m)) 2928 return rte_flow_error_set(error, EINVAL, 2929 RTE_FLOW_ERROR_TYPE_ITEM, item, 2930 "L3 is mandatory to filter on L4"); 2931 if (item_flags & l4m) 2932 return rte_flow_error_set(error, EINVAL, 2933 RTE_FLOW_ERROR_TYPE_ITEM, item, 2934 "multiple L4 layers not supported"); 2935 if (!mask) 2936 mask = &rte_flow_item_tcp_mask; 2937 ret = mlx5_flow_item_acceptable 2938 (item, (const uint8_t *)mask, 2939 (const uint8_t *)flow_mask, 2940 sizeof(struct rte_flow_item_tcp), MLX5_ITEM_RANGE_NOT_ACCEPTED, 2941 error); 2942 if (ret < 0) 2943 return ret; 2944 return 0; 2945 } 2946 2947 /** 2948 * Validate VXLAN item. 2949 * 2950 * @param[in] dev 2951 * Pointer to the Ethernet device structure. 2952 * @param[in] udp_dport 2953 * UDP destination port 2954 * @param[in] item 2955 * Item specification. 2956 * @param[in] item_flags 2957 * Bit-fields that holds the items detected until now. 2958 * @param root 2959 * Whether action is on root table. 2960 * @param[out] error 2961 * Pointer to error structure. 2962 * 2963 * @return 2964 * 0 on success, a negative errno value otherwise and rte_errno is set. 2965 */ 2966 int 2967 mlx5_flow_validate_item_vxlan(struct rte_eth_dev *dev, 2968 uint16_t udp_dport, 2969 const struct rte_flow_item *item, 2970 uint64_t item_flags, 2971 bool root, 2972 struct rte_flow_error *error) 2973 { 2974 const struct rte_flow_item_vxlan *spec = item->spec; 2975 const struct rte_flow_item_vxlan *mask = item->mask; 2976 int ret; 2977 struct mlx5_priv *priv = dev->data->dev_private; 2978 union vni { 2979 uint32_t vlan_id; 2980 uint8_t vni[4]; 2981 } id = { .vlan_id = 0, }; 2982 const struct rte_flow_item_vxlan nic_mask = { 2983 .hdr.vni = "\xff\xff\xff", 2984 .hdr.rsvd1 = 0xff, 2985 }; 2986 const struct rte_flow_item_vxlan *valid_mask; 2987 2988 if (item_flags & MLX5_FLOW_LAYER_TUNNEL) 2989 return rte_flow_error_set(error, ENOTSUP, 2990 RTE_FLOW_ERROR_TYPE_ITEM, item, 2991 "multiple tunnel layers not" 2992 " supported"); 2993 valid_mask = &rte_flow_item_vxlan_mask; 2994 /* 2995 * Verify only UDPv4 is present as defined in 2996 * https://tools.ietf.org/html/rfc7348 2997 */ 2998 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_UDP)) 2999 return rte_flow_error_set(error, EINVAL, 3000 RTE_FLOW_ERROR_TYPE_ITEM, item, 3001 "no outer UDP layer found"); 3002 if (!mask) 3003 mask = &rte_flow_item_vxlan_mask; 3004 3005 if (priv->sh->steering_format_version != 3006 MLX5_STEERING_LOGIC_FORMAT_CONNECTX_5 || 3007 !udp_dport || udp_dport == MLX5_UDP_PORT_VXLAN) { 3008 /* non-root table */ 3009 if (!root && priv->sh->misc5_cap) 3010 valid_mask = &nic_mask; 3011 /* Group zero in NIC domain */ 3012 if (!root && priv->sh->tunnel_header_0_1) 3013 valid_mask = &nic_mask; 3014 } 3015 ret = mlx5_flow_item_acceptable 3016 (item, (const uint8_t *)mask, 3017 (const uint8_t *)valid_mask, 3018 sizeof(struct rte_flow_item_vxlan), 3019 MLX5_ITEM_RANGE_NOT_ACCEPTED, error); 3020 if (ret < 0) 3021 return ret; 3022 if (spec) { 3023 memcpy(&id.vni[1], spec->hdr.vni, 3); 3024 memcpy(&id.vni[1], mask->hdr.vni, 3); 3025 } 3026 if (!(item_flags & MLX5_FLOW_LAYER_OUTER)) 3027 return rte_flow_error_set(error, ENOTSUP, 3028 RTE_FLOW_ERROR_TYPE_ITEM, item, 3029 "VXLAN tunnel must be fully defined"); 3030 return 0; 3031 } 3032 3033 /** 3034 * Validate VXLAN_GPE item. 3035 * 3036 * @param[in] item 3037 * Item specification. 3038 * @param[in] item_flags 3039 * Bit-fields that holds the items detected until now. 3040 * @param[in] priv 3041 * Pointer to the private data structure. 3042 * @param[in] target_protocol 3043 * The next protocol in the previous item. 3044 * @param[out] error 3045 * Pointer to error structure. 3046 * 3047 * @return 3048 * 0 on success, a negative errno value otherwise and rte_errno is set. 3049 */ 3050 int 3051 mlx5_flow_validate_item_vxlan_gpe(const struct rte_flow_item *item, 3052 uint64_t item_flags, 3053 struct rte_eth_dev *dev, 3054 struct rte_flow_error *error) 3055 { 3056 struct mlx5_priv *priv = dev->data->dev_private; 3057 const struct rte_flow_item_vxlan_gpe *spec = item->spec; 3058 const struct rte_flow_item_vxlan_gpe *mask = item->mask; 3059 int ret; 3060 union vni { 3061 uint32_t vlan_id; 3062 uint8_t vni[4]; 3063 } id = { .vlan_id = 0, }; 3064 3065 if (!priv->sh->config.l3_vxlan_en) 3066 return rte_flow_error_set(error, ENOTSUP, 3067 RTE_FLOW_ERROR_TYPE_ITEM, item, 3068 "L3 VXLAN is not enabled by device" 3069 " parameter and/or not configured in" 3070 " firmware"); 3071 if (item_flags & MLX5_FLOW_LAYER_TUNNEL) 3072 return rte_flow_error_set(error, ENOTSUP, 3073 RTE_FLOW_ERROR_TYPE_ITEM, item, 3074 "multiple tunnel layers not" 3075 " supported"); 3076 /* 3077 * Verify only UDPv4 is present as defined in 3078 * https://tools.ietf.org/html/rfc7348 3079 */ 3080 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_UDP)) 3081 return rte_flow_error_set(error, EINVAL, 3082 RTE_FLOW_ERROR_TYPE_ITEM, item, 3083 "no outer UDP layer found"); 3084 if (!mask) 3085 mask = &rte_flow_item_vxlan_gpe_mask; 3086 ret = mlx5_flow_item_acceptable 3087 (item, (const uint8_t *)mask, 3088 (const uint8_t *)&rte_flow_item_vxlan_gpe_mask, 3089 sizeof(struct rte_flow_item_vxlan_gpe), 3090 MLX5_ITEM_RANGE_NOT_ACCEPTED, error); 3091 if (ret < 0) 3092 return ret; 3093 if (spec) { 3094 if (spec->hdr.proto) 3095 return rte_flow_error_set(error, ENOTSUP, 3096 RTE_FLOW_ERROR_TYPE_ITEM, 3097 item, 3098 "VxLAN-GPE protocol" 3099 " not supported"); 3100 memcpy(&id.vni[1], spec->hdr.vni, 3); 3101 memcpy(&id.vni[1], mask->hdr.vni, 3); 3102 } 3103 if (!(item_flags & MLX5_FLOW_LAYER_OUTER)) 3104 return rte_flow_error_set(error, ENOTSUP, 3105 RTE_FLOW_ERROR_TYPE_ITEM, item, 3106 "VXLAN-GPE tunnel must be fully" 3107 " defined"); 3108 return 0; 3109 } 3110 /** 3111 * Validate GRE Key item. 3112 * 3113 * @param[in] item 3114 * Item specification. 3115 * @param[in] item_flags 3116 * Bit flags to mark detected items. 3117 * @param[in] gre_item 3118 * Pointer to gre_item 3119 * @param[out] error 3120 * Pointer to error structure. 3121 * 3122 * @return 3123 * 0 on success, a negative errno value otherwise and rte_errno is set. 3124 */ 3125 int 3126 mlx5_flow_validate_item_gre_key(const struct rte_flow_item *item, 3127 uint64_t item_flags, 3128 const struct rte_flow_item *gre_item, 3129 struct rte_flow_error *error) 3130 { 3131 const rte_be32_t *mask = item->mask; 3132 int ret = 0; 3133 rte_be32_t gre_key_default_mask = RTE_BE32(UINT32_MAX); 3134 const struct rte_flow_item_gre *gre_spec; 3135 const struct rte_flow_item_gre *gre_mask; 3136 3137 if (item_flags & MLX5_FLOW_LAYER_GRE_KEY) 3138 return rte_flow_error_set(error, ENOTSUP, 3139 RTE_FLOW_ERROR_TYPE_ITEM, item, 3140 "Multiple GRE key not support"); 3141 if (!(item_flags & MLX5_FLOW_LAYER_GRE)) 3142 return rte_flow_error_set(error, ENOTSUP, 3143 RTE_FLOW_ERROR_TYPE_ITEM, item, 3144 "No preceding GRE header"); 3145 if (item_flags & MLX5_FLOW_LAYER_INNER) 3146 return rte_flow_error_set(error, ENOTSUP, 3147 RTE_FLOW_ERROR_TYPE_ITEM, item, 3148 "GRE key following a wrong item"); 3149 gre_mask = gre_item->mask; 3150 if (!gre_mask) 3151 gre_mask = &rte_flow_item_gre_mask; 3152 gre_spec = gre_item->spec; 3153 if (gre_spec && (gre_mask->c_rsvd0_ver & RTE_BE16(0x2000)) && 3154 !(gre_spec->c_rsvd0_ver & RTE_BE16(0x2000))) 3155 return rte_flow_error_set(error, EINVAL, 3156 RTE_FLOW_ERROR_TYPE_ITEM, item, 3157 "Key bit must be on"); 3158 3159 if (!mask) 3160 mask = &gre_key_default_mask; 3161 ret = mlx5_flow_item_acceptable 3162 (item, (const uint8_t *)mask, 3163 (const uint8_t *)&gre_key_default_mask, 3164 sizeof(rte_be32_t), MLX5_ITEM_RANGE_NOT_ACCEPTED, error); 3165 return ret; 3166 } 3167 3168 /** 3169 * Validate GRE optional item. 3170 * 3171 * @param[in] dev 3172 * Pointer to the Ethernet device structure. 3173 * @param[in] item 3174 * Item specification. 3175 * @param[in] item_flags 3176 * Bit flags to mark detected items. 3177 * @param[in] attr 3178 * Flow rule attributes. 3179 * @param[in] gre_item 3180 * Pointer to gre_item 3181 * @param[out] error 3182 * Pointer to error structure. 3183 * 3184 * @return 3185 * 0 on success, a negative errno value otherwise and rte_errno is set. 3186 */ 3187 int 3188 mlx5_flow_validate_item_gre_option(struct rte_eth_dev *dev, 3189 const struct rte_flow_item *item, 3190 uint64_t item_flags, 3191 const struct rte_flow_attr *attr, 3192 const struct rte_flow_item *gre_item, 3193 struct rte_flow_error *error) 3194 { 3195 const struct rte_flow_item_gre *gre_spec = gre_item->spec; 3196 const struct rte_flow_item_gre *gre_mask = gre_item->mask; 3197 const struct rte_flow_item_gre_opt *spec = item->spec; 3198 const struct rte_flow_item_gre_opt *mask = item->mask; 3199 struct mlx5_priv *priv = dev->data->dev_private; 3200 int ret = 0; 3201 struct rte_flow_item_gre_opt nic_mask = { 3202 .checksum_rsvd = { 3203 .checksum = RTE_BE16(UINT16_MAX), 3204 .reserved1 = 0x0, 3205 }, 3206 .key = { 3207 .key = RTE_BE32(UINT32_MAX), 3208 }, 3209 .sequence = { 3210 .sequence = RTE_BE32(UINT32_MAX), 3211 }, 3212 }; 3213 3214 if (!(item_flags & MLX5_FLOW_LAYER_GRE)) 3215 return rte_flow_error_set(error, ENOTSUP, 3216 RTE_FLOW_ERROR_TYPE_ITEM, item, 3217 "No preceding GRE header"); 3218 if (item_flags & MLX5_FLOW_LAYER_INNER) 3219 return rte_flow_error_set(error, ENOTSUP, 3220 RTE_FLOW_ERROR_TYPE_ITEM, item, 3221 "GRE option following a wrong item"); 3222 if (!spec || !mask) 3223 return rte_flow_error_set(error, EINVAL, 3224 RTE_FLOW_ERROR_TYPE_ITEM, item, 3225 "At least one field gre_option(checksum/key/sequence) must be specified"); 3226 if (!gre_mask) 3227 gre_mask = &rte_flow_item_gre_mask; 3228 if (mask->checksum_rsvd.checksum) 3229 if (gre_spec && (gre_mask->c_rsvd0_ver & RTE_BE16(0x8000)) && 3230 !(gre_spec->c_rsvd0_ver & RTE_BE16(0x8000))) 3231 return rte_flow_error_set(error, EINVAL, 3232 RTE_FLOW_ERROR_TYPE_ITEM, 3233 item, 3234 "Checksum bit must be on"); 3235 if (mask->key.key) 3236 if (gre_spec && (gre_mask->c_rsvd0_ver & RTE_BE16(0x2000)) && 3237 !(gre_spec->c_rsvd0_ver & RTE_BE16(0x2000))) 3238 return rte_flow_error_set(error, EINVAL, 3239 RTE_FLOW_ERROR_TYPE_ITEM, 3240 item, "Key bit must be on"); 3241 if (mask->sequence.sequence) 3242 if (gre_spec && (gre_mask->c_rsvd0_ver & RTE_BE16(0x1000)) && 3243 !(gre_spec->c_rsvd0_ver & RTE_BE16(0x1000))) 3244 return rte_flow_error_set(error, EINVAL, 3245 RTE_FLOW_ERROR_TYPE_ITEM, 3246 item, 3247 "Sequence bit must be on"); 3248 if (mask->checksum_rsvd.checksum || mask->sequence.sequence) { 3249 if (priv->sh->steering_format_version == 3250 MLX5_STEERING_LOGIC_FORMAT_CONNECTX_5 || 3251 ((attr->group || (attr->transfer && priv->fdb_def_rule)) && 3252 !priv->sh->misc5_cap) || 3253 (!(priv->sh->tunnel_header_0_1 && 3254 priv->sh->tunnel_header_2_3) && 3255 !attr->group && (!attr->transfer || !priv->fdb_def_rule))) 3256 return rte_flow_error_set(error, EINVAL, 3257 RTE_FLOW_ERROR_TYPE_ITEM, 3258 item, 3259 "Checksum/Sequence not supported"); 3260 } 3261 ret = mlx5_flow_item_acceptable 3262 (item, (const uint8_t *)mask, 3263 (const uint8_t *)&nic_mask, 3264 sizeof(struct rte_flow_item_gre_opt), 3265 MLX5_ITEM_RANGE_NOT_ACCEPTED, error); 3266 return ret; 3267 } 3268 3269 /** 3270 * Validate GRE item. 3271 * 3272 * @param[in] item 3273 * Item specification. 3274 * @param[in] item_flags 3275 * Bit flags to mark detected items. 3276 * @param[in] target_protocol 3277 * The next protocol in the previous item. 3278 * @param[out] error 3279 * Pointer to error structure. 3280 * 3281 * @return 3282 * 0 on success, a negative errno value otherwise and rte_errno is set. 3283 */ 3284 int 3285 mlx5_flow_validate_item_gre(const struct rte_flow_item *item, 3286 uint64_t item_flags, 3287 uint8_t target_protocol, 3288 struct rte_flow_error *error) 3289 { 3290 const struct rte_flow_item_gre *spec __rte_unused = item->spec; 3291 const struct rte_flow_item_gre *mask = item->mask; 3292 int ret; 3293 const struct rte_flow_item_gre nic_mask = { 3294 .c_rsvd0_ver = RTE_BE16(0xB000), 3295 .protocol = RTE_BE16(UINT16_MAX), 3296 }; 3297 3298 if (target_protocol != 0xff && target_protocol != IPPROTO_GRE) 3299 return rte_flow_error_set(error, EINVAL, 3300 RTE_FLOW_ERROR_TYPE_ITEM, item, 3301 "protocol filtering not compatible" 3302 " with this GRE layer"); 3303 if (item_flags & MLX5_FLOW_LAYER_TUNNEL) 3304 return rte_flow_error_set(error, ENOTSUP, 3305 RTE_FLOW_ERROR_TYPE_ITEM, item, 3306 "multiple tunnel layers not" 3307 " supported"); 3308 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L3)) 3309 return rte_flow_error_set(error, ENOTSUP, 3310 RTE_FLOW_ERROR_TYPE_ITEM, item, 3311 "L3 Layer is missing"); 3312 if (!mask) 3313 mask = &rte_flow_item_gre_mask; 3314 ret = mlx5_flow_item_acceptable 3315 (item, (const uint8_t *)mask, 3316 (const uint8_t *)&nic_mask, 3317 sizeof(struct rte_flow_item_gre), MLX5_ITEM_RANGE_NOT_ACCEPTED, 3318 error); 3319 if (ret < 0) 3320 return ret; 3321 #ifndef HAVE_MLX5DV_DR 3322 #ifndef HAVE_IBV_DEVICE_MPLS_SUPPORT 3323 if (spec && (spec->protocol & mask->protocol)) 3324 return rte_flow_error_set(error, ENOTSUP, 3325 RTE_FLOW_ERROR_TYPE_ITEM, item, 3326 "without MPLS support the" 3327 " specification cannot be used for" 3328 " filtering"); 3329 #endif 3330 #endif 3331 return 0; 3332 } 3333 3334 /** 3335 * Validate Geneve item. 3336 * 3337 * @param[in] item 3338 * Item specification. 3339 * @param[in] itemFlags 3340 * Bit-fields that holds the items detected until now. 3341 * @param[in] enPriv 3342 * Pointer to the private data structure. 3343 * @param[out] error 3344 * Pointer to error structure. 3345 * 3346 * @return 3347 * 0 on success, a negative errno value otherwise and rte_errno is set. 3348 */ 3349 3350 int 3351 mlx5_flow_validate_item_geneve(const struct rte_flow_item *item, 3352 uint64_t item_flags, 3353 struct rte_eth_dev *dev, 3354 struct rte_flow_error *error) 3355 { 3356 struct mlx5_priv *priv = dev->data->dev_private; 3357 const struct rte_flow_item_geneve *spec = item->spec; 3358 const struct rte_flow_item_geneve *mask = item->mask; 3359 int ret; 3360 uint16_t gbhdr; 3361 uint8_t opt_len = priv->sh->cdev->config.hca_attr.geneve_max_opt_len ? 3362 MLX5_GENEVE_OPT_LEN_1 : MLX5_GENEVE_OPT_LEN_0; 3363 const struct rte_flow_item_geneve nic_mask = { 3364 .ver_opt_len_o_c_rsvd0 = RTE_BE16(0x3f80), 3365 .vni = "\xff\xff\xff", 3366 .protocol = RTE_BE16(UINT16_MAX), 3367 }; 3368 3369 if (!priv->sh->cdev->config.hca_attr.tunnel_stateless_geneve_rx) 3370 return rte_flow_error_set(error, ENOTSUP, 3371 RTE_FLOW_ERROR_TYPE_ITEM, item, 3372 "L3 Geneve is not enabled by device" 3373 " parameter and/or not configured in" 3374 " firmware"); 3375 if (item_flags & MLX5_FLOW_LAYER_TUNNEL) 3376 return rte_flow_error_set(error, ENOTSUP, 3377 RTE_FLOW_ERROR_TYPE_ITEM, item, 3378 "multiple tunnel layers not" 3379 " supported"); 3380 /* 3381 * Verify only UDPv4 is present as defined in 3382 * https://tools.ietf.org/html/rfc7348 3383 */ 3384 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_UDP)) 3385 return rte_flow_error_set(error, EINVAL, 3386 RTE_FLOW_ERROR_TYPE_ITEM, item, 3387 "no outer UDP layer found"); 3388 if (!mask) 3389 mask = &rte_flow_item_geneve_mask; 3390 ret = mlx5_flow_item_acceptable 3391 (item, (const uint8_t *)mask, 3392 (const uint8_t *)&nic_mask, 3393 sizeof(struct rte_flow_item_geneve), 3394 MLX5_ITEM_RANGE_NOT_ACCEPTED, error); 3395 if (ret) 3396 return ret; 3397 if (spec) { 3398 gbhdr = rte_be_to_cpu_16(spec->ver_opt_len_o_c_rsvd0); 3399 if (MLX5_GENEVE_VER_VAL(gbhdr) || 3400 MLX5_GENEVE_CRITO_VAL(gbhdr) || 3401 MLX5_GENEVE_RSVD_VAL(gbhdr) || spec->rsvd1) 3402 return rte_flow_error_set(error, ENOTSUP, 3403 RTE_FLOW_ERROR_TYPE_ITEM, 3404 item, 3405 "Geneve protocol unsupported" 3406 " fields are being used"); 3407 if (MLX5_GENEVE_OPTLEN_VAL(gbhdr) > opt_len) 3408 return rte_flow_error_set 3409 (error, ENOTSUP, 3410 RTE_FLOW_ERROR_TYPE_ITEM, 3411 item, 3412 "Unsupported Geneve options length"); 3413 } 3414 if (!(item_flags & MLX5_FLOW_LAYER_OUTER)) 3415 return rte_flow_error_set 3416 (error, ENOTSUP, 3417 RTE_FLOW_ERROR_TYPE_ITEM, item, 3418 "Geneve tunnel must be fully defined"); 3419 return 0; 3420 } 3421 3422 /** 3423 * Validate Geneve TLV option item. 3424 * 3425 * @param[in] item 3426 * Item specification. 3427 * @param[in] last_item 3428 * Previous validated item in the pattern items. 3429 * @param[in] geneve_item 3430 * Previous GENEVE item specification. 3431 * @param[in] dev 3432 * Pointer to the rte_eth_dev structure. 3433 * @param[out] error 3434 * Pointer to error structure. 3435 * 3436 * @return 3437 * 0 on success, a negative errno value otherwise and rte_errno is set. 3438 */ 3439 int 3440 mlx5_flow_validate_item_geneve_opt(const struct rte_flow_item *item, 3441 uint64_t last_item, 3442 const struct rte_flow_item *geneve_item, 3443 struct rte_eth_dev *dev, 3444 struct rte_flow_error *error) 3445 { 3446 struct mlx5_priv *priv = dev->data->dev_private; 3447 struct mlx5_dev_ctx_shared *sh = priv->sh; 3448 struct mlx5_geneve_tlv_option_resource *geneve_opt_resource; 3449 struct mlx5_hca_attr *hca_attr = &sh->cdev->config.hca_attr; 3450 uint8_t data_max_supported = 3451 hca_attr->max_geneve_tlv_option_data_len * 4; 3452 const struct rte_flow_item_geneve *geneve_spec; 3453 const struct rte_flow_item_geneve *geneve_mask; 3454 const struct rte_flow_item_geneve_opt *spec = item->spec; 3455 const struct rte_flow_item_geneve_opt *mask = item->mask; 3456 unsigned int i; 3457 unsigned int data_len; 3458 uint8_t tlv_option_len; 3459 uint16_t optlen_m, optlen_v; 3460 const struct rte_flow_item_geneve_opt full_mask = { 3461 .option_class = RTE_BE16(0xffff), 3462 .option_type = 0xff, 3463 .option_len = 0x1f, 3464 }; 3465 3466 if (!mask) 3467 mask = &rte_flow_item_geneve_opt_mask; 3468 if (!spec) 3469 return rte_flow_error_set 3470 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item, 3471 "Geneve TLV opt class/type/length must be specified"); 3472 if ((uint32_t)spec->option_len > MLX5_GENEVE_OPTLEN_MASK) 3473 return rte_flow_error_set 3474 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item, 3475 "Geneve TLV opt length exceeds the limit (31)"); 3476 /* Check if class type and length masks are full. */ 3477 if (full_mask.option_class != mask->option_class || 3478 full_mask.option_type != mask->option_type || 3479 full_mask.option_len != (mask->option_len & full_mask.option_len)) 3480 return rte_flow_error_set 3481 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item, 3482 "Geneve TLV opt class/type/length masks must be full"); 3483 /* Check if length is supported */ 3484 if ((uint32_t)spec->option_len > 3485 hca_attr->max_geneve_tlv_option_data_len) 3486 return rte_flow_error_set 3487 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item, 3488 "Geneve TLV opt length not supported"); 3489 if (hca_attr->max_geneve_tlv_options > 1) 3490 DRV_LOG(DEBUG, 3491 "max_geneve_tlv_options supports more than 1 option"); 3492 /* Check GENEVE item preceding. */ 3493 if (!geneve_item || !(last_item & MLX5_FLOW_LAYER_GENEVE)) 3494 return rte_flow_error_set 3495 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item, 3496 "Geneve opt item must be preceded with Geneve item"); 3497 geneve_spec = geneve_item->spec; 3498 geneve_mask = geneve_item->mask ? geneve_item->mask : 3499 &rte_flow_item_geneve_mask; 3500 /* Check if GENEVE TLV option size doesn't exceed option length */ 3501 if (geneve_spec && (geneve_mask->ver_opt_len_o_c_rsvd0 || 3502 geneve_spec->ver_opt_len_o_c_rsvd0)) { 3503 tlv_option_len = spec->option_len & mask->option_len; 3504 optlen_v = rte_be_to_cpu_16(geneve_spec->ver_opt_len_o_c_rsvd0); 3505 optlen_v = MLX5_GENEVE_OPTLEN_VAL(optlen_v); 3506 optlen_m = rte_be_to_cpu_16(geneve_mask->ver_opt_len_o_c_rsvd0); 3507 optlen_m = MLX5_GENEVE_OPTLEN_VAL(optlen_m); 3508 if ((optlen_v & optlen_m) <= tlv_option_len) 3509 return rte_flow_error_set 3510 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item, 3511 "GENEVE TLV option length exceeds optlen"); 3512 } 3513 /* Check if length is 0 or data is 0. */ 3514 if (spec->data == NULL || spec->option_len == 0) 3515 return rte_flow_error_set 3516 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item, 3517 "Geneve TLV opt with zero data/length not supported"); 3518 /* Check not all data & mask are 0. */ 3519 data_len = spec->option_len * 4; 3520 if (mask->data == NULL) { 3521 for (i = 0; i < data_len; i++) 3522 if (spec->data[i]) 3523 break; 3524 if (i == data_len) 3525 return rte_flow_error_set(error, ENOTSUP, 3526 RTE_FLOW_ERROR_TYPE_ITEM, item, 3527 "Can't match on Geneve option data 0"); 3528 } else { 3529 for (i = 0; i < data_len; i++) 3530 if (spec->data[i] & mask->data[i]) 3531 break; 3532 if (i == data_len) 3533 return rte_flow_error_set(error, ENOTSUP, 3534 RTE_FLOW_ERROR_TYPE_ITEM, item, 3535 "Can't match on Geneve option data and mask 0"); 3536 /* Check data mask supported. */ 3537 for (i = data_max_supported; i < data_len ; i++) 3538 if (mask->data[i]) 3539 return rte_flow_error_set(error, ENOTSUP, 3540 RTE_FLOW_ERROR_TYPE_ITEM, item, 3541 "Data mask is of unsupported size"); 3542 } 3543 /* Check GENEVE option is supported in NIC. */ 3544 if (!hca_attr->geneve_tlv_opt) 3545 return rte_flow_error_set 3546 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item, 3547 "Geneve TLV opt not supported"); 3548 /* Check if we already have geneve option with different type/class. */ 3549 rte_spinlock_lock(&sh->geneve_tlv_opt_sl); 3550 geneve_opt_resource = sh->geneve_tlv_option_resource; 3551 if (geneve_opt_resource != NULL) 3552 if (geneve_opt_resource->option_class != spec->option_class || 3553 geneve_opt_resource->option_type != spec->option_type || 3554 geneve_opt_resource->length != spec->option_len) { 3555 rte_spinlock_unlock(&sh->geneve_tlv_opt_sl); 3556 return rte_flow_error_set(error, ENOTSUP, 3557 RTE_FLOW_ERROR_TYPE_ITEM, item, 3558 "Only one Geneve TLV option supported"); 3559 } 3560 rte_spinlock_unlock(&sh->geneve_tlv_opt_sl); 3561 return 0; 3562 } 3563 3564 /** 3565 * Validate MPLS item. 3566 * 3567 * @param[in] dev 3568 * Pointer to the rte_eth_dev structure. 3569 * @param[in] item 3570 * Item specification. 3571 * @param[in] item_flags 3572 * Bit-fields that holds the items detected until now. 3573 * @param[in] prev_layer 3574 * The protocol layer indicated in previous item. 3575 * @param[out] error 3576 * Pointer to error structure. 3577 * 3578 * @return 3579 * 0 on success, a negative errno value otherwise and rte_errno is set. 3580 */ 3581 int 3582 mlx5_flow_validate_item_mpls(struct rte_eth_dev *dev __rte_unused, 3583 const struct rte_flow_item *item __rte_unused, 3584 uint64_t item_flags __rte_unused, 3585 uint64_t prev_layer __rte_unused, 3586 struct rte_flow_error *error) 3587 { 3588 #ifdef HAVE_IBV_DEVICE_MPLS_SUPPORT 3589 const struct rte_flow_item_mpls *mask = item->mask; 3590 struct mlx5_priv *priv = dev->data->dev_private; 3591 int ret; 3592 3593 if (!priv->sh->dev_cap.mpls_en) 3594 return rte_flow_error_set(error, ENOTSUP, 3595 RTE_FLOW_ERROR_TYPE_ITEM, item, 3596 "MPLS not supported or" 3597 " disabled in firmware" 3598 " configuration."); 3599 /* MPLS over UDP, GRE is allowed */ 3600 if (!(prev_layer & (MLX5_FLOW_LAYER_OUTER_L4_UDP | 3601 MLX5_FLOW_LAYER_GRE | 3602 MLX5_FLOW_LAYER_GRE_KEY))) 3603 return rte_flow_error_set(error, EINVAL, 3604 RTE_FLOW_ERROR_TYPE_ITEM, item, 3605 "protocol filtering not compatible" 3606 " with MPLS layer"); 3607 /* Multi-tunnel isn't allowed but MPLS over GRE is an exception. */ 3608 if ((item_flags & MLX5_FLOW_LAYER_TUNNEL) && 3609 !(item_flags & MLX5_FLOW_LAYER_GRE)) 3610 return rte_flow_error_set(error, ENOTSUP, 3611 RTE_FLOW_ERROR_TYPE_ITEM, item, 3612 "multiple tunnel layers not" 3613 " supported"); 3614 if (!mask) 3615 mask = &rte_flow_item_mpls_mask; 3616 ret = mlx5_flow_item_acceptable 3617 (item, (const uint8_t *)mask, 3618 (const uint8_t *)&rte_flow_item_mpls_mask, 3619 sizeof(struct rte_flow_item_mpls), 3620 MLX5_ITEM_RANGE_NOT_ACCEPTED, error); 3621 if (ret < 0) 3622 return ret; 3623 return 0; 3624 #else 3625 return rte_flow_error_set(error, ENOTSUP, 3626 RTE_FLOW_ERROR_TYPE_ITEM, item, 3627 "MPLS is not supported by Verbs, please" 3628 " update."); 3629 #endif 3630 } 3631 3632 /** 3633 * Validate NVGRE item. 3634 * 3635 * @param[in] item 3636 * Item specification. 3637 * @param[in] item_flags 3638 * Bit flags to mark detected items. 3639 * @param[in] target_protocol 3640 * The next protocol in the previous item. 3641 * @param[out] error 3642 * Pointer to error structure. 3643 * 3644 * @return 3645 * 0 on success, a negative errno value otherwise and rte_errno is set. 3646 */ 3647 int 3648 mlx5_flow_validate_item_nvgre(const struct rte_flow_item *item, 3649 uint64_t item_flags, 3650 uint8_t target_protocol, 3651 struct rte_flow_error *error) 3652 { 3653 const struct rte_flow_item_nvgre *mask = item->mask; 3654 int ret; 3655 3656 if (target_protocol != 0xff && target_protocol != IPPROTO_GRE) 3657 return rte_flow_error_set(error, EINVAL, 3658 RTE_FLOW_ERROR_TYPE_ITEM, item, 3659 "protocol filtering not compatible" 3660 " with this GRE layer"); 3661 if (item_flags & MLX5_FLOW_LAYER_TUNNEL) 3662 return rte_flow_error_set(error, ENOTSUP, 3663 RTE_FLOW_ERROR_TYPE_ITEM, item, 3664 "multiple tunnel layers not" 3665 " supported"); 3666 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L3)) 3667 return rte_flow_error_set(error, ENOTSUP, 3668 RTE_FLOW_ERROR_TYPE_ITEM, item, 3669 "L3 Layer is missing"); 3670 if (!mask) 3671 mask = &rte_flow_item_nvgre_mask; 3672 ret = mlx5_flow_item_acceptable 3673 (item, (const uint8_t *)mask, 3674 (const uint8_t *)&rte_flow_item_nvgre_mask, 3675 sizeof(struct rte_flow_item_nvgre), 3676 MLX5_ITEM_RANGE_NOT_ACCEPTED, error); 3677 if (ret < 0) 3678 return ret; 3679 return 0; 3680 } 3681 3682 /** 3683 * Validate eCPRI item. 3684 * 3685 * @param[in] item 3686 * Item specification. 3687 * @param[in] item_flags 3688 * Bit-fields that holds the items detected until now. 3689 * @param[in] last_item 3690 * Previous validated item in the pattern items. 3691 * @param[in] ether_type 3692 * Type in the ethernet layer header (including dot1q). 3693 * @param[in] acc_mask 3694 * Acceptable mask, if NULL default internal default mask 3695 * will be used to check whether item fields are supported. 3696 * @param[out] error 3697 * Pointer to error structure. 3698 * 3699 * @return 3700 * 0 on success, a negative errno value otherwise and rte_errno is set. 3701 */ 3702 int 3703 mlx5_flow_validate_item_ecpri(const struct rte_flow_item *item, 3704 uint64_t item_flags, 3705 uint64_t last_item, 3706 uint16_t ether_type, 3707 const struct rte_flow_item_ecpri *acc_mask, 3708 struct rte_flow_error *error) 3709 { 3710 const struct rte_flow_item_ecpri *mask = item->mask; 3711 const struct rte_flow_item_ecpri nic_mask = { 3712 .hdr = { 3713 .common = { 3714 .u32 = 3715 RTE_BE32(((const struct rte_ecpri_common_hdr) { 3716 .type = 0xFF, 3717 }).u32), 3718 }, 3719 .dummy[0] = 0xFFFFFFFF, 3720 }, 3721 }; 3722 const uint64_t outer_l2_vlan = (MLX5_FLOW_LAYER_OUTER_L2 | 3723 MLX5_FLOW_LAYER_OUTER_VLAN); 3724 struct rte_flow_item_ecpri mask_lo; 3725 3726 if (!(last_item & outer_l2_vlan) && 3727 last_item != MLX5_FLOW_LAYER_OUTER_L4_UDP) 3728 return rte_flow_error_set(error, EINVAL, 3729 RTE_FLOW_ERROR_TYPE_ITEM, item, 3730 "eCPRI can only follow L2/VLAN layer or UDP layer"); 3731 if ((last_item & outer_l2_vlan) && ether_type && 3732 ether_type != RTE_ETHER_TYPE_ECPRI) 3733 return rte_flow_error_set(error, EINVAL, 3734 RTE_FLOW_ERROR_TYPE_ITEM, item, 3735 "eCPRI cannot follow L2/VLAN layer which ether type is not 0xAEFE"); 3736 if (item_flags & MLX5_FLOW_LAYER_TUNNEL) 3737 return rte_flow_error_set(error, EINVAL, 3738 RTE_FLOW_ERROR_TYPE_ITEM, item, 3739 "eCPRI with tunnel is not supported right now"); 3740 if (item_flags & MLX5_FLOW_LAYER_OUTER_L3) 3741 return rte_flow_error_set(error, ENOTSUP, 3742 RTE_FLOW_ERROR_TYPE_ITEM, item, 3743 "multiple L3 layers not supported"); 3744 else if (item_flags & MLX5_FLOW_LAYER_OUTER_L4_TCP) 3745 return rte_flow_error_set(error, EINVAL, 3746 RTE_FLOW_ERROR_TYPE_ITEM, item, 3747 "eCPRI cannot coexist with a TCP layer"); 3748 /* In specification, eCPRI could be over UDP layer. */ 3749 else if (item_flags & MLX5_FLOW_LAYER_OUTER_L4_UDP) 3750 return rte_flow_error_set(error, EINVAL, 3751 RTE_FLOW_ERROR_TYPE_ITEM, item, 3752 "eCPRI over UDP layer is not yet supported right now"); 3753 /* Mask for type field in common header could be zero. */ 3754 if (!mask) 3755 mask = &rte_flow_item_ecpri_mask; 3756 mask_lo.hdr.common.u32 = rte_be_to_cpu_32(mask->hdr.common.u32); 3757 /* Input mask is in big-endian format. */ 3758 if (mask_lo.hdr.common.type != 0 && mask_lo.hdr.common.type != 0xff) 3759 return rte_flow_error_set(error, EINVAL, 3760 RTE_FLOW_ERROR_TYPE_ITEM_MASK, mask, 3761 "partial mask is not supported for protocol"); 3762 else if (mask_lo.hdr.common.type == 0 && mask->hdr.dummy[0] != 0) 3763 return rte_flow_error_set(error, EINVAL, 3764 RTE_FLOW_ERROR_TYPE_ITEM_MASK, mask, 3765 "message header mask must be after a type mask"); 3766 return mlx5_flow_item_acceptable(item, (const uint8_t *)mask, 3767 acc_mask ? (const uint8_t *)acc_mask 3768 : (const uint8_t *)&nic_mask, 3769 sizeof(struct rte_flow_item_ecpri), 3770 MLX5_ITEM_RANGE_NOT_ACCEPTED, error); 3771 } 3772 3773 static int 3774 flow_null_validate(struct rte_eth_dev *dev __rte_unused, 3775 const struct rte_flow_attr *attr __rte_unused, 3776 const struct rte_flow_item items[] __rte_unused, 3777 const struct rte_flow_action actions[] __rte_unused, 3778 bool external __rte_unused, 3779 int hairpin __rte_unused, 3780 struct rte_flow_error *error) 3781 { 3782 return rte_flow_error_set(error, ENOTSUP, 3783 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, NULL); 3784 } 3785 3786 static struct mlx5_flow * 3787 flow_null_prepare(struct rte_eth_dev *dev __rte_unused, 3788 const struct rte_flow_attr *attr __rte_unused, 3789 const struct rte_flow_item items[] __rte_unused, 3790 const struct rte_flow_action actions[] __rte_unused, 3791 struct rte_flow_error *error) 3792 { 3793 rte_flow_error_set(error, ENOTSUP, 3794 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, NULL); 3795 return NULL; 3796 } 3797 3798 static int 3799 flow_null_translate(struct rte_eth_dev *dev __rte_unused, 3800 struct mlx5_flow *dev_flow __rte_unused, 3801 const struct rte_flow_attr *attr __rte_unused, 3802 const struct rte_flow_item items[] __rte_unused, 3803 const struct rte_flow_action actions[] __rte_unused, 3804 struct rte_flow_error *error) 3805 { 3806 return rte_flow_error_set(error, ENOTSUP, 3807 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, NULL); 3808 } 3809 3810 static int 3811 flow_null_apply(struct rte_eth_dev *dev __rte_unused, 3812 struct rte_flow *flow __rte_unused, 3813 struct rte_flow_error *error) 3814 { 3815 return rte_flow_error_set(error, ENOTSUP, 3816 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, NULL); 3817 } 3818 3819 static void 3820 flow_null_remove(struct rte_eth_dev *dev __rte_unused, 3821 struct rte_flow *flow __rte_unused) 3822 { 3823 } 3824 3825 static void 3826 flow_null_destroy(struct rte_eth_dev *dev __rte_unused, 3827 struct rte_flow *flow __rte_unused) 3828 { 3829 } 3830 3831 static int 3832 flow_null_query(struct rte_eth_dev *dev __rte_unused, 3833 struct rte_flow *flow __rte_unused, 3834 const struct rte_flow_action *actions __rte_unused, 3835 void *data __rte_unused, 3836 struct rte_flow_error *error) 3837 { 3838 return rte_flow_error_set(error, ENOTSUP, 3839 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, NULL); 3840 } 3841 3842 static int 3843 flow_null_sync_domain(struct rte_eth_dev *dev __rte_unused, 3844 uint32_t domains __rte_unused, 3845 uint32_t flags __rte_unused) 3846 { 3847 return 0; 3848 } 3849 3850 /* Void driver to protect from null pointer reference. */ 3851 const struct mlx5_flow_driver_ops mlx5_flow_null_drv_ops = { 3852 .validate = flow_null_validate, 3853 .prepare = flow_null_prepare, 3854 .translate = flow_null_translate, 3855 .apply = flow_null_apply, 3856 .remove = flow_null_remove, 3857 .destroy = flow_null_destroy, 3858 .query = flow_null_query, 3859 .sync_domain = flow_null_sync_domain, 3860 }; 3861 3862 /** 3863 * Select flow driver type according to flow attributes and device 3864 * configuration. 3865 * 3866 * @param[in] dev 3867 * Pointer to the dev structure. 3868 * @param[in] attr 3869 * Pointer to the flow attributes. 3870 * 3871 * @return 3872 * flow driver type, MLX5_FLOW_TYPE_MAX otherwise. 3873 */ 3874 static enum mlx5_flow_drv_type 3875 flow_get_drv_type(struct rte_eth_dev *dev, const struct rte_flow_attr *attr) 3876 { 3877 struct mlx5_priv *priv = dev->data->dev_private; 3878 /* The OS can determine first a specific flow type (DV, VERBS) */ 3879 enum mlx5_flow_drv_type type = mlx5_flow_os_get_type(); 3880 3881 if (type != MLX5_FLOW_TYPE_MAX) 3882 return type; 3883 /* 3884 * Currently when dv_flow_en == 2, only HW steering engine is 3885 * supported. New engines can also be chosen here if ready. 3886 */ 3887 if (priv->sh->config.dv_flow_en == 2) 3888 return MLX5_FLOW_TYPE_HW; 3889 if (!attr) 3890 return MLX5_FLOW_TYPE_MIN; 3891 /* If no OS specific type - continue with DV/VERBS selection */ 3892 if (attr->transfer && priv->sh->config.dv_esw_en) 3893 type = MLX5_FLOW_TYPE_DV; 3894 if (!attr->transfer) 3895 type = priv->sh->config.dv_flow_en ? MLX5_FLOW_TYPE_DV : 3896 MLX5_FLOW_TYPE_VERBS; 3897 return type; 3898 } 3899 3900 #define flow_get_drv_ops(type) flow_drv_ops[type] 3901 3902 /** 3903 * Flow driver validation API. This abstracts calling driver specific functions. 3904 * The type of flow driver is determined according to flow attributes. 3905 * 3906 * @param[in] dev 3907 * Pointer to the dev structure. 3908 * @param[in] attr 3909 * Pointer to the flow attributes. 3910 * @param[in] items 3911 * Pointer to the list of items. 3912 * @param[in] actions 3913 * Pointer to the list of actions. 3914 * @param[in] external 3915 * This flow rule is created by request external to PMD. 3916 * @param[in] hairpin 3917 * Number of hairpin TX actions, 0 means classic flow. 3918 * @param[out] error 3919 * Pointer to the error structure. 3920 * 3921 * @return 3922 * 0 on success, a negative errno value otherwise and rte_errno is set. 3923 */ 3924 static inline int 3925 flow_drv_validate(struct rte_eth_dev *dev, 3926 const struct rte_flow_attr *attr, 3927 const struct rte_flow_item items[], 3928 const struct rte_flow_action actions[], 3929 bool external, int hairpin, struct rte_flow_error *error) 3930 { 3931 const struct mlx5_flow_driver_ops *fops; 3932 enum mlx5_flow_drv_type type = flow_get_drv_type(dev, attr); 3933 3934 fops = flow_get_drv_ops(type); 3935 return fops->validate(dev, attr, items, actions, external, 3936 hairpin, error); 3937 } 3938 3939 /** 3940 * Flow driver preparation API. This abstracts calling driver specific 3941 * functions. Parent flow (rte_flow) should have driver type (drv_type). It 3942 * calculates the size of memory required for device flow, allocates the memory, 3943 * initializes the device flow and returns the pointer. 3944 * 3945 * @note 3946 * This function initializes device flow structure such as dv or verbs in 3947 * struct mlx5_flow. However, it is caller's responsibility to initialize the 3948 * rest. For example, adding returning device flow to flow->dev_flow list and 3949 * setting backward reference to the flow should be done out of this function. 3950 * layers field is not filled either. 3951 * 3952 * @param[in] dev 3953 * Pointer to the dev structure. 3954 * @param[in] attr 3955 * Pointer to the flow attributes. 3956 * @param[in] items 3957 * Pointer to the list of items. 3958 * @param[in] actions 3959 * Pointer to the list of actions. 3960 * @param[in] flow_idx 3961 * This memory pool index to the flow. 3962 * @param[out] error 3963 * Pointer to the error structure. 3964 * 3965 * @return 3966 * Pointer to device flow on success, otherwise NULL and rte_errno is set. 3967 */ 3968 static inline struct mlx5_flow * 3969 flow_drv_prepare(struct rte_eth_dev *dev, 3970 const struct rte_flow *flow, 3971 const struct rte_flow_attr *attr, 3972 const struct rte_flow_item items[], 3973 const struct rte_flow_action actions[], 3974 uint32_t flow_idx, 3975 struct rte_flow_error *error) 3976 { 3977 const struct mlx5_flow_driver_ops *fops; 3978 enum mlx5_flow_drv_type type = flow->drv_type; 3979 struct mlx5_flow *mlx5_flow = NULL; 3980 3981 MLX5_ASSERT(type > MLX5_FLOW_TYPE_MIN && type < MLX5_FLOW_TYPE_MAX); 3982 fops = flow_get_drv_ops(type); 3983 mlx5_flow = fops->prepare(dev, attr, items, actions, error); 3984 if (mlx5_flow) 3985 mlx5_flow->flow_idx = flow_idx; 3986 return mlx5_flow; 3987 } 3988 3989 /** 3990 * Flow driver translation API. This abstracts calling driver specific 3991 * functions. Parent flow (rte_flow) should have driver type (drv_type). It 3992 * translates a generic flow into a driver flow. flow_drv_prepare() must 3993 * precede. 3994 * 3995 * @note 3996 * dev_flow->layers could be filled as a result of parsing during translation 3997 * if needed by flow_drv_apply(). dev_flow->flow->actions can also be filled 3998 * if necessary. As a flow can have multiple dev_flows by RSS flow expansion, 3999 * flow->actions could be overwritten even though all the expanded dev_flows 4000 * have the same actions. 4001 * 4002 * @param[in] dev 4003 * Pointer to the rte dev structure. 4004 * @param[in, out] dev_flow 4005 * Pointer to the mlx5 flow. 4006 * @param[in] attr 4007 * Pointer to the flow attributes. 4008 * @param[in] items 4009 * Pointer to the list of items. 4010 * @param[in] actions 4011 * Pointer to the list of actions. 4012 * @param[out] error 4013 * Pointer to the error structure. 4014 * 4015 * @return 4016 * 0 on success, a negative errno value otherwise and rte_errno is set. 4017 */ 4018 static inline int 4019 flow_drv_translate(struct rte_eth_dev *dev, struct mlx5_flow *dev_flow, 4020 const struct rte_flow_attr *attr, 4021 const struct rte_flow_item items[], 4022 const struct rte_flow_action actions[], 4023 struct rte_flow_error *error) 4024 { 4025 const struct mlx5_flow_driver_ops *fops; 4026 enum mlx5_flow_drv_type type = dev_flow->flow->drv_type; 4027 4028 MLX5_ASSERT(type > MLX5_FLOW_TYPE_MIN && type < MLX5_FLOW_TYPE_MAX); 4029 fops = flow_get_drv_ops(type); 4030 return fops->translate(dev, dev_flow, attr, items, actions, error); 4031 } 4032 4033 /** 4034 * Flow driver apply API. This abstracts calling driver specific functions. 4035 * Parent flow (rte_flow) should have driver type (drv_type). It applies 4036 * translated driver flows on to device. flow_drv_translate() must precede. 4037 * 4038 * @param[in] dev 4039 * Pointer to Ethernet device structure. 4040 * @param[in, out] flow 4041 * Pointer to flow structure. 4042 * @param[out] error 4043 * Pointer to error structure. 4044 * 4045 * @return 4046 * 0 on success, a negative errno value otherwise and rte_errno is set. 4047 */ 4048 static inline int 4049 flow_drv_apply(struct rte_eth_dev *dev, struct rte_flow *flow, 4050 struct rte_flow_error *error) 4051 { 4052 const struct mlx5_flow_driver_ops *fops; 4053 enum mlx5_flow_drv_type type = flow->drv_type; 4054 4055 MLX5_ASSERT(type > MLX5_FLOW_TYPE_MIN && type < MLX5_FLOW_TYPE_MAX); 4056 fops = flow_get_drv_ops(type); 4057 return fops->apply(dev, flow, error); 4058 } 4059 4060 /** 4061 * Flow driver destroy API. This abstracts calling driver specific functions. 4062 * Parent flow (rte_flow) should have driver type (drv_type). It removes a flow 4063 * on device and releases resources of the flow. 4064 * 4065 * @param[in] dev 4066 * Pointer to Ethernet device. 4067 * @param[in, out] flow 4068 * Pointer to flow structure. 4069 */ 4070 static inline void 4071 flow_drv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow) 4072 { 4073 const struct mlx5_flow_driver_ops *fops; 4074 enum mlx5_flow_drv_type type = flow->drv_type; 4075 4076 MLX5_ASSERT(type > MLX5_FLOW_TYPE_MIN && type < MLX5_FLOW_TYPE_MAX); 4077 fops = flow_get_drv_ops(type); 4078 fops->destroy(dev, flow); 4079 } 4080 4081 /** 4082 * Flow driver find RSS policy tbl API. This abstracts calling driver 4083 * specific functions. Parent flow (rte_flow) should have driver 4084 * type (drv_type). It will find the RSS policy table that has the rss_desc. 4085 * 4086 * @param[in] dev 4087 * Pointer to Ethernet device. 4088 * @param[in, out] flow 4089 * Pointer to flow structure. 4090 * @param[in] policy 4091 * Pointer to meter policy table. 4092 * @param[in] rss_desc 4093 * Pointer to rss_desc 4094 */ 4095 static struct mlx5_flow_meter_sub_policy * 4096 flow_drv_meter_sub_policy_rss_prepare(struct rte_eth_dev *dev, 4097 struct rte_flow *flow, 4098 struct mlx5_flow_meter_policy *policy, 4099 struct mlx5_flow_rss_desc *rss_desc[MLX5_MTR_RTE_COLORS]) 4100 { 4101 const struct mlx5_flow_driver_ops *fops; 4102 enum mlx5_flow_drv_type type = flow->drv_type; 4103 4104 MLX5_ASSERT(type > MLX5_FLOW_TYPE_MIN && type < MLX5_FLOW_TYPE_MAX); 4105 fops = flow_get_drv_ops(type); 4106 return fops->meter_sub_policy_rss_prepare(dev, policy, rss_desc); 4107 } 4108 4109 /** 4110 * Flow driver color tag rule API. This abstracts calling driver 4111 * specific functions. Parent flow (rte_flow) should have driver 4112 * type (drv_type). It will create the color tag rules in hierarchy meter. 4113 * 4114 * @param[in] dev 4115 * Pointer to Ethernet device. 4116 * @param[in, out] flow 4117 * Pointer to flow structure. 4118 * @param[in] fm 4119 * Pointer to flow meter structure. 4120 * @param[in] src_port 4121 * The src port this extra rule should use. 4122 * @param[in] item 4123 * The src port id match item. 4124 * @param[out] error 4125 * Pointer to error structure. 4126 */ 4127 static int 4128 flow_drv_mtr_hierarchy_rule_create(struct rte_eth_dev *dev, 4129 struct rte_flow *flow, 4130 struct mlx5_flow_meter_info *fm, 4131 int32_t src_port, 4132 const struct rte_flow_item *item, 4133 struct rte_flow_error *error) 4134 { 4135 const struct mlx5_flow_driver_ops *fops; 4136 enum mlx5_flow_drv_type type = flow->drv_type; 4137 4138 MLX5_ASSERT(type > MLX5_FLOW_TYPE_MIN && type < MLX5_FLOW_TYPE_MAX); 4139 fops = flow_get_drv_ops(type); 4140 return fops->meter_hierarchy_rule_create(dev, fm, 4141 src_port, item, error); 4142 } 4143 4144 /** 4145 * Get RSS action from the action list. 4146 * 4147 * @param[in] dev 4148 * Pointer to Ethernet device. 4149 * @param[in] actions 4150 * Pointer to the list of actions. 4151 * @param[in] flow 4152 * Parent flow structure pointer. 4153 * 4154 * @return 4155 * Pointer to the RSS action if exist, else return NULL. 4156 */ 4157 static const struct rte_flow_action_rss* 4158 flow_get_rss_action(struct rte_eth_dev *dev, 4159 const struct rte_flow_action actions[]) 4160 { 4161 struct mlx5_priv *priv = dev->data->dev_private; 4162 const struct rte_flow_action_rss *rss = NULL; 4163 struct mlx5_meter_policy_action_container *acg; 4164 struct mlx5_meter_policy_action_container *acy; 4165 4166 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) { 4167 switch (actions->type) { 4168 case RTE_FLOW_ACTION_TYPE_RSS: 4169 rss = actions->conf; 4170 break; 4171 case RTE_FLOW_ACTION_TYPE_SAMPLE: 4172 { 4173 const struct rte_flow_action_sample *sample = 4174 actions->conf; 4175 const struct rte_flow_action *act = sample->actions; 4176 for (; act->type != RTE_FLOW_ACTION_TYPE_END; act++) 4177 if (act->type == RTE_FLOW_ACTION_TYPE_RSS) 4178 rss = act->conf; 4179 break; 4180 } 4181 case RTE_FLOW_ACTION_TYPE_METER: 4182 { 4183 uint32_t mtr_idx; 4184 struct mlx5_flow_meter_info *fm; 4185 struct mlx5_flow_meter_policy *policy; 4186 const struct rte_flow_action_meter *mtr = actions->conf; 4187 4188 fm = mlx5_flow_meter_find(priv, mtr->mtr_id, &mtr_idx); 4189 if (fm && !fm->def_policy) { 4190 policy = mlx5_flow_meter_policy_find(dev, 4191 fm->policy_id, NULL); 4192 MLX5_ASSERT(policy); 4193 if (policy->is_hierarchy) { 4194 policy = 4195 mlx5_flow_meter_hierarchy_get_final_policy(dev, 4196 policy); 4197 if (!policy) 4198 return NULL; 4199 } 4200 if (policy->is_rss) { 4201 acg = 4202 &policy->act_cnt[RTE_COLOR_GREEN]; 4203 acy = 4204 &policy->act_cnt[RTE_COLOR_YELLOW]; 4205 if (acg->fate_action == 4206 MLX5_FLOW_FATE_SHARED_RSS) 4207 rss = acg->rss->conf; 4208 else if (acy->fate_action == 4209 MLX5_FLOW_FATE_SHARED_RSS) 4210 rss = acy->rss->conf; 4211 } 4212 } 4213 break; 4214 } 4215 default: 4216 break; 4217 } 4218 } 4219 return rss; 4220 } 4221 4222 /** 4223 * Get ASO age action by index. 4224 * 4225 * @param[in] dev 4226 * Pointer to the Ethernet device structure. 4227 * @param[in] age_idx 4228 * Index to the ASO age action. 4229 * 4230 * @return 4231 * The specified ASO age action. 4232 */ 4233 struct mlx5_aso_age_action* 4234 flow_aso_age_get_by_idx(struct rte_eth_dev *dev, uint32_t age_idx) 4235 { 4236 uint16_t pool_idx = age_idx & UINT16_MAX; 4237 uint16_t offset = (age_idx >> 16) & UINT16_MAX; 4238 struct mlx5_priv *priv = dev->data->dev_private; 4239 struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng; 4240 struct mlx5_aso_age_pool *pool; 4241 4242 rte_rwlock_read_lock(&mng->resize_rwl); 4243 pool = mng->pools[pool_idx]; 4244 rte_rwlock_read_unlock(&mng->resize_rwl); 4245 return &pool->actions[offset - 1]; 4246 } 4247 4248 /* maps indirect action to translated direct in some actions array */ 4249 struct mlx5_translated_action_handle { 4250 struct rte_flow_action_handle *action; /**< Indirect action handle. */ 4251 int index; /**< Index in related array of rte_flow_action. */ 4252 }; 4253 4254 /** 4255 * Translates actions of type RTE_FLOW_ACTION_TYPE_INDIRECT to related 4256 * direct action if translation possible. 4257 * This functionality used to run same execution path for both direct and 4258 * indirect actions on flow create. All necessary preparations for indirect 4259 * action handling should be performed on *handle* actions list returned 4260 * from this call. 4261 * 4262 * @param[in] dev 4263 * Pointer to Ethernet device. 4264 * @param[in] actions 4265 * List of actions to translate. 4266 * @param[out] handle 4267 * List to store translated indirect action object handles. 4268 * @param[in, out] indir_n 4269 * Size of *handle* array. On return should be updated with number of 4270 * indirect actions retrieved from the *actions* list. 4271 * @param[out] translated_actions 4272 * List of actions where all indirect actions were translated to direct 4273 * if possible. NULL if no translation took place. 4274 * @param[out] error 4275 * Pointer to the error structure. 4276 * 4277 * @return 4278 * 0 on success, a negative errno value otherwise and rte_errno is set. 4279 */ 4280 static int 4281 flow_action_handles_translate(struct rte_eth_dev *dev, 4282 const struct rte_flow_action actions[], 4283 struct mlx5_translated_action_handle *handle, 4284 int *indir_n, 4285 struct rte_flow_action **translated_actions, 4286 struct rte_flow_error *error) 4287 { 4288 struct mlx5_priv *priv = dev->data->dev_private; 4289 struct rte_flow_action *translated = NULL; 4290 size_t actions_size; 4291 int n; 4292 int copied_n = 0; 4293 struct mlx5_translated_action_handle *handle_end = NULL; 4294 4295 for (n = 0; actions[n].type != RTE_FLOW_ACTION_TYPE_END; n++) { 4296 if (actions[n].type != RTE_FLOW_ACTION_TYPE_INDIRECT) 4297 continue; 4298 if (copied_n == *indir_n) { 4299 return rte_flow_error_set 4300 (error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION_NUM, 4301 NULL, "too many shared actions"); 4302 } 4303 rte_memcpy(&handle[copied_n].action, &actions[n].conf, 4304 sizeof(actions[n].conf)); 4305 handle[copied_n].index = n; 4306 copied_n++; 4307 } 4308 n++; 4309 *indir_n = copied_n; 4310 if (!copied_n) 4311 return 0; 4312 actions_size = sizeof(struct rte_flow_action) * n; 4313 translated = mlx5_malloc(MLX5_MEM_ZERO, actions_size, 0, SOCKET_ID_ANY); 4314 if (!translated) { 4315 rte_errno = ENOMEM; 4316 return -ENOMEM; 4317 } 4318 memcpy(translated, actions, actions_size); 4319 for (handle_end = handle + copied_n; handle < handle_end; handle++) { 4320 struct mlx5_shared_action_rss *shared_rss; 4321 uint32_t act_idx = (uint32_t)(uintptr_t)handle->action; 4322 uint32_t type = act_idx >> MLX5_INDIRECT_ACTION_TYPE_OFFSET; 4323 uint32_t idx = act_idx & 4324 ((1u << MLX5_INDIRECT_ACTION_TYPE_OFFSET) - 1); 4325 4326 switch (type) { 4327 case MLX5_INDIRECT_ACTION_TYPE_RSS: 4328 shared_rss = mlx5_ipool_get 4329 (priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], idx); 4330 translated[handle->index].type = 4331 RTE_FLOW_ACTION_TYPE_RSS; 4332 translated[handle->index].conf = 4333 &shared_rss->origin; 4334 break; 4335 case MLX5_INDIRECT_ACTION_TYPE_COUNT: 4336 translated[handle->index].type = 4337 (enum rte_flow_action_type) 4338 MLX5_RTE_FLOW_ACTION_TYPE_COUNT; 4339 translated[handle->index].conf = (void *)(uintptr_t)idx; 4340 break; 4341 case MLX5_INDIRECT_ACTION_TYPE_METER_MARK: 4342 translated[handle->index].type = 4343 (enum rte_flow_action_type) 4344 MLX5_RTE_FLOW_ACTION_TYPE_METER_MARK; 4345 translated[handle->index].conf = (void *)(uintptr_t)idx; 4346 break; 4347 case MLX5_INDIRECT_ACTION_TYPE_AGE: 4348 if (priv->sh->flow_hit_aso_en) { 4349 translated[handle->index].type = 4350 (enum rte_flow_action_type) 4351 MLX5_RTE_FLOW_ACTION_TYPE_AGE; 4352 translated[handle->index].conf = 4353 (void *)(uintptr_t)idx; 4354 break; 4355 } 4356 /* Fall-through */ 4357 case MLX5_INDIRECT_ACTION_TYPE_CT: 4358 if (priv->sh->ct_aso_en) { 4359 translated[handle->index].type = 4360 RTE_FLOW_ACTION_TYPE_CONNTRACK; 4361 translated[handle->index].conf = 4362 (void *)(uintptr_t)idx; 4363 break; 4364 } 4365 /* Fall-through */ 4366 default: 4367 mlx5_free(translated); 4368 return rte_flow_error_set 4369 (error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION, 4370 NULL, "invalid indirect action type"); 4371 } 4372 } 4373 *translated_actions = translated; 4374 return 0; 4375 } 4376 4377 /** 4378 * Get Shared RSS action from the action list. 4379 * 4380 * @param[in] dev 4381 * Pointer to Ethernet device. 4382 * @param[in] shared 4383 * Pointer to the list of actions. 4384 * @param[in] shared_n 4385 * Actions list length. 4386 * 4387 * @return 4388 * The MLX5 RSS action ID if exists, otherwise return 0. 4389 */ 4390 static uint32_t 4391 flow_get_shared_rss_action(struct rte_eth_dev *dev, 4392 struct mlx5_translated_action_handle *handle, 4393 int shared_n) 4394 { 4395 struct mlx5_translated_action_handle *handle_end; 4396 struct mlx5_priv *priv = dev->data->dev_private; 4397 struct mlx5_shared_action_rss *shared_rss; 4398 4399 4400 for (handle_end = handle + shared_n; handle < handle_end; handle++) { 4401 uint32_t act_idx = (uint32_t)(uintptr_t)handle->action; 4402 uint32_t type = act_idx >> MLX5_INDIRECT_ACTION_TYPE_OFFSET; 4403 uint32_t idx = act_idx & 4404 ((1u << MLX5_INDIRECT_ACTION_TYPE_OFFSET) - 1); 4405 switch (type) { 4406 case MLX5_INDIRECT_ACTION_TYPE_RSS: 4407 shared_rss = mlx5_ipool_get 4408 (priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], 4409 idx); 4410 __atomic_add_fetch(&shared_rss->refcnt, 1, 4411 __ATOMIC_RELAXED); 4412 return idx; 4413 default: 4414 break; 4415 } 4416 } 4417 return 0; 4418 } 4419 4420 static unsigned int 4421 find_graph_root(uint32_t rss_level) 4422 { 4423 return rss_level < 2 ? MLX5_EXPANSION_ROOT : 4424 MLX5_EXPANSION_ROOT_OUTER; 4425 } 4426 4427 /** 4428 * Get layer flags from the prefix flow. 4429 * 4430 * Some flows may be split to several subflows, the prefix subflow gets the 4431 * match items and the suffix sub flow gets the actions. 4432 * Some actions need the user defined match item flags to get the detail for 4433 * the action. 4434 * This function helps the suffix flow to get the item layer flags from prefix 4435 * subflow. 4436 * 4437 * @param[in] dev_flow 4438 * Pointer the created prefix subflow. 4439 * 4440 * @return 4441 * The layers get from prefix subflow. 4442 */ 4443 static inline uint64_t 4444 flow_get_prefix_layer_flags(struct mlx5_flow *dev_flow) 4445 { 4446 uint64_t layers = 0; 4447 4448 /* 4449 * Layers bits could be localization, but usually the compiler will 4450 * help to do the optimization work for source code. 4451 * If no decap actions, use the layers directly. 4452 */ 4453 if (!(dev_flow->act_flags & MLX5_FLOW_ACTION_DECAP)) 4454 return dev_flow->handle->layers; 4455 /* Convert L3 layers with decap action. */ 4456 if (dev_flow->handle->layers & MLX5_FLOW_LAYER_INNER_L3_IPV4) 4457 layers |= MLX5_FLOW_LAYER_OUTER_L3_IPV4; 4458 else if (dev_flow->handle->layers & MLX5_FLOW_LAYER_INNER_L3_IPV6) 4459 layers |= MLX5_FLOW_LAYER_OUTER_L3_IPV6; 4460 /* Convert L4 layers with decap action. */ 4461 if (dev_flow->handle->layers & MLX5_FLOW_LAYER_INNER_L4_TCP) 4462 layers |= MLX5_FLOW_LAYER_OUTER_L4_TCP; 4463 else if (dev_flow->handle->layers & MLX5_FLOW_LAYER_INNER_L4_UDP) 4464 layers |= MLX5_FLOW_LAYER_OUTER_L4_UDP; 4465 return layers; 4466 } 4467 4468 /** 4469 * Get metadata split action information. 4470 * 4471 * @param[in] actions 4472 * Pointer to the list of actions. 4473 * @param[out] qrss 4474 * Pointer to the return pointer. 4475 * @param[out] qrss_type 4476 * Pointer to the action type to return. RTE_FLOW_ACTION_TYPE_END is returned 4477 * if no QUEUE/RSS is found. 4478 * @param[out] encap_idx 4479 * Pointer to the index of the encap action if exists, otherwise the last 4480 * action index. 4481 * 4482 * @return 4483 * Total number of actions. 4484 */ 4485 static int 4486 flow_parse_metadata_split_actions_info(const struct rte_flow_action actions[], 4487 const struct rte_flow_action **qrss, 4488 int *encap_idx) 4489 { 4490 const struct rte_flow_action_raw_encap *raw_encap; 4491 int actions_n = 0; 4492 int raw_decap_idx = -1; 4493 4494 *encap_idx = -1; 4495 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) { 4496 switch (actions->type) { 4497 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP: 4498 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP: 4499 *encap_idx = actions_n; 4500 break; 4501 case RTE_FLOW_ACTION_TYPE_RAW_DECAP: 4502 raw_decap_idx = actions_n; 4503 break; 4504 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP: 4505 raw_encap = actions->conf; 4506 if (raw_encap->size > MLX5_ENCAPSULATION_DECISION_SIZE) 4507 *encap_idx = raw_decap_idx != -1 ? 4508 raw_decap_idx : actions_n; 4509 break; 4510 case RTE_FLOW_ACTION_TYPE_QUEUE: 4511 case RTE_FLOW_ACTION_TYPE_RSS: 4512 *qrss = actions; 4513 break; 4514 default: 4515 break; 4516 } 4517 actions_n++; 4518 } 4519 if (*encap_idx == -1) 4520 *encap_idx = actions_n; 4521 /* Count RTE_FLOW_ACTION_TYPE_END. */ 4522 return actions_n + 1; 4523 } 4524 4525 /** 4526 * Check if the action will change packet. 4527 * 4528 * @param dev 4529 * Pointer to Ethernet device. 4530 * @param[in] type 4531 * action type. 4532 * 4533 * @return 4534 * true if action will change packet, false otherwise. 4535 */ 4536 static bool flow_check_modify_action_type(struct rte_eth_dev *dev, 4537 enum rte_flow_action_type type) 4538 { 4539 struct mlx5_priv *priv = dev->data->dev_private; 4540 4541 switch (type) { 4542 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC: 4543 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST: 4544 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC: 4545 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST: 4546 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC: 4547 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST: 4548 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC: 4549 case RTE_FLOW_ACTION_TYPE_SET_TP_DST: 4550 case RTE_FLOW_ACTION_TYPE_DEC_TTL: 4551 case RTE_FLOW_ACTION_TYPE_SET_TTL: 4552 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ: 4553 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ: 4554 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK: 4555 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK: 4556 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP: 4557 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP: 4558 case RTE_FLOW_ACTION_TYPE_SET_META: 4559 case RTE_FLOW_ACTION_TYPE_SET_TAG: 4560 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN: 4561 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN: 4562 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID: 4563 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP: 4564 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP: 4565 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP: 4566 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP: 4567 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP: 4568 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP: 4569 case RTE_FLOW_ACTION_TYPE_RAW_DECAP: 4570 case RTE_FLOW_ACTION_TYPE_MODIFY_FIELD: 4571 return true; 4572 case RTE_FLOW_ACTION_TYPE_FLAG: 4573 case RTE_FLOW_ACTION_TYPE_MARK: 4574 if (priv->sh->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY && 4575 priv->sh->config.dv_xmeta_en != MLX5_XMETA_MODE_META32_HWS) 4576 return true; 4577 else 4578 return false; 4579 default: 4580 return false; 4581 } 4582 } 4583 4584 /** 4585 * Check meter action from the action list. 4586 * 4587 * @param dev 4588 * Pointer to Ethernet device. 4589 * @param[in] actions 4590 * Pointer to the list of actions. 4591 * @param[out] has_mtr 4592 * Pointer to the meter exist flag. 4593 * @param[out] has_modify 4594 * Pointer to the flag showing there's packet change action. 4595 * @param[out] meter_id 4596 * Pointer to the meter id. 4597 * 4598 * @return 4599 * Total number of actions. 4600 */ 4601 static int 4602 flow_check_meter_action(struct rte_eth_dev *dev, 4603 const struct rte_flow_action actions[], 4604 bool *has_mtr, bool *has_modify, uint32_t *meter_id) 4605 { 4606 const struct rte_flow_action_meter *mtr = NULL; 4607 int actions_n = 0; 4608 4609 MLX5_ASSERT(has_mtr); 4610 *has_mtr = false; 4611 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) { 4612 switch (actions->type) { 4613 case RTE_FLOW_ACTION_TYPE_METER: 4614 mtr = actions->conf; 4615 *meter_id = mtr->mtr_id; 4616 *has_mtr = true; 4617 break; 4618 default: 4619 break; 4620 } 4621 if (!*has_mtr) 4622 *has_modify |= flow_check_modify_action_type(dev, 4623 actions->type); 4624 actions_n++; 4625 } 4626 /* Count RTE_FLOW_ACTION_TYPE_END. */ 4627 return actions_n + 1; 4628 } 4629 4630 /** 4631 * Check if the flow should be split due to hairpin. 4632 * The reason for the split is that in current HW we can't 4633 * support encap and push-vlan on Rx, so if a flow contains 4634 * these actions we move it to Tx. 4635 * 4636 * @param dev 4637 * Pointer to Ethernet device. 4638 * @param[in] attr 4639 * Flow rule attributes. 4640 * @param[in] actions 4641 * Associated actions (list terminated by the END action). 4642 * 4643 * @return 4644 * > 0 the number of actions and the flow should be split, 4645 * 0 when no split required. 4646 */ 4647 static int 4648 flow_check_hairpin_split(struct rte_eth_dev *dev, 4649 const struct rte_flow_attr *attr, 4650 const struct rte_flow_action actions[]) 4651 { 4652 int queue_action = 0; 4653 int action_n = 0; 4654 int split = 0; 4655 int push_vlan = 0; 4656 const struct rte_flow_action_queue *queue; 4657 const struct rte_flow_action_rss *rss; 4658 const struct rte_flow_action_raw_encap *raw_encap; 4659 const struct rte_eth_hairpin_conf *conf; 4660 4661 if (!attr->ingress) 4662 return 0; 4663 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) { 4664 if (actions->type == RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN) 4665 push_vlan = 1; 4666 switch (actions->type) { 4667 case RTE_FLOW_ACTION_TYPE_QUEUE: 4668 queue = actions->conf; 4669 if (queue == NULL) 4670 return 0; 4671 conf = mlx5_rxq_get_hairpin_conf(dev, queue->index); 4672 if (conf == NULL || conf->tx_explicit != 0) 4673 return 0; 4674 queue_action = 1; 4675 action_n++; 4676 break; 4677 case RTE_FLOW_ACTION_TYPE_RSS: 4678 rss = actions->conf; 4679 if (rss == NULL || rss->queue_num == 0) 4680 return 0; 4681 conf = mlx5_rxq_get_hairpin_conf(dev, rss->queue[0]); 4682 if (conf == NULL || conf->tx_explicit != 0) 4683 return 0; 4684 queue_action = 1; 4685 action_n++; 4686 break; 4687 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP: 4688 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP: 4689 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN: 4690 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP: 4691 split++; 4692 action_n++; 4693 break; 4694 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID: 4695 if (push_vlan) 4696 split++; 4697 action_n++; 4698 break; 4699 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP: 4700 raw_encap = actions->conf; 4701 if (raw_encap->size > MLX5_ENCAPSULATION_DECISION_SIZE) 4702 split++; 4703 action_n++; 4704 break; 4705 default: 4706 action_n++; 4707 break; 4708 } 4709 } 4710 if (split && queue_action) 4711 return action_n; 4712 return 0; 4713 } 4714 4715 /* Declare flow create/destroy prototype in advance. */ 4716 static uint32_t 4717 flow_list_create(struct rte_eth_dev *dev, enum mlx5_flow_type type, 4718 const struct rte_flow_attr *attr, 4719 const struct rte_flow_item items[], 4720 const struct rte_flow_action actions[], 4721 bool external, struct rte_flow_error *error); 4722 4723 static void 4724 flow_list_destroy(struct rte_eth_dev *dev, enum mlx5_flow_type type, 4725 uint32_t flow_idx); 4726 4727 int 4728 flow_dv_mreg_match_cb(void *tool_ctx __rte_unused, 4729 struct mlx5_list_entry *entry, void *cb_ctx) 4730 { 4731 struct mlx5_flow_cb_ctx *ctx = cb_ctx; 4732 struct mlx5_flow_mreg_copy_resource *mcp_res = 4733 container_of(entry, typeof(*mcp_res), hlist_ent); 4734 4735 return mcp_res->mark_id != *(uint32_t *)(ctx->data); 4736 } 4737 4738 struct mlx5_list_entry * 4739 flow_dv_mreg_create_cb(void *tool_ctx, void *cb_ctx) 4740 { 4741 struct rte_eth_dev *dev = tool_ctx; 4742 struct mlx5_priv *priv = dev->data->dev_private; 4743 struct mlx5_flow_cb_ctx *ctx = cb_ctx; 4744 struct mlx5_flow_mreg_copy_resource *mcp_res; 4745 struct rte_flow_error *error = ctx->error; 4746 uint32_t idx = 0; 4747 int ret; 4748 uint32_t mark_id = *(uint32_t *)(ctx->data); 4749 struct rte_flow_attr attr = { 4750 .group = MLX5_FLOW_MREG_CP_TABLE_GROUP, 4751 .ingress = 1, 4752 }; 4753 struct mlx5_rte_flow_item_tag tag_spec = { 4754 .data = mark_id, 4755 }; 4756 struct rte_flow_item items[] = { 4757 [1] = { .type = RTE_FLOW_ITEM_TYPE_END, }, 4758 }; 4759 struct rte_flow_action_mark ftag = { 4760 .id = mark_id, 4761 }; 4762 struct mlx5_flow_action_copy_mreg cp_mreg = { 4763 .dst = REG_B, 4764 .src = REG_NON, 4765 }; 4766 struct rte_flow_action_jump jump = { 4767 .group = MLX5_FLOW_MREG_ACT_TABLE_GROUP, 4768 }; 4769 struct rte_flow_action actions[] = { 4770 [3] = { .type = RTE_FLOW_ACTION_TYPE_END, }, 4771 }; 4772 4773 /* Fill the register fields in the flow. */ 4774 ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error); 4775 if (ret < 0) 4776 return NULL; 4777 tag_spec.id = ret; 4778 ret = mlx5_flow_get_reg_id(dev, MLX5_METADATA_RX, 0, error); 4779 if (ret < 0) 4780 return NULL; 4781 cp_mreg.src = ret; 4782 /* Provide the full width of FLAG specific value. */ 4783 if (mark_id == (priv->sh->dv_regc0_mask & MLX5_FLOW_MARK_DEFAULT)) 4784 tag_spec.data = MLX5_FLOW_MARK_DEFAULT; 4785 /* Build a new flow. */ 4786 if (mark_id != MLX5_DEFAULT_COPY_ID) { 4787 items[0] = (struct rte_flow_item){ 4788 .type = (enum rte_flow_item_type) 4789 MLX5_RTE_FLOW_ITEM_TYPE_TAG, 4790 .spec = &tag_spec, 4791 }; 4792 items[1] = (struct rte_flow_item){ 4793 .type = RTE_FLOW_ITEM_TYPE_END, 4794 }; 4795 actions[0] = (struct rte_flow_action){ 4796 .type = (enum rte_flow_action_type) 4797 MLX5_RTE_FLOW_ACTION_TYPE_MARK, 4798 .conf = &ftag, 4799 }; 4800 actions[1] = (struct rte_flow_action){ 4801 .type = (enum rte_flow_action_type) 4802 MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG, 4803 .conf = &cp_mreg, 4804 }; 4805 actions[2] = (struct rte_flow_action){ 4806 .type = RTE_FLOW_ACTION_TYPE_JUMP, 4807 .conf = &jump, 4808 }; 4809 actions[3] = (struct rte_flow_action){ 4810 .type = RTE_FLOW_ACTION_TYPE_END, 4811 }; 4812 } else { 4813 /* Default rule, wildcard match. */ 4814 attr.priority = MLX5_FLOW_LOWEST_PRIO_INDICATOR; 4815 items[0] = (struct rte_flow_item){ 4816 .type = RTE_FLOW_ITEM_TYPE_END, 4817 }; 4818 actions[0] = (struct rte_flow_action){ 4819 .type = (enum rte_flow_action_type) 4820 MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG, 4821 .conf = &cp_mreg, 4822 }; 4823 actions[1] = (struct rte_flow_action){ 4824 .type = RTE_FLOW_ACTION_TYPE_JUMP, 4825 .conf = &jump, 4826 }; 4827 actions[2] = (struct rte_flow_action){ 4828 .type = RTE_FLOW_ACTION_TYPE_END, 4829 }; 4830 } 4831 /* Build a new entry. */ 4832 mcp_res = mlx5_ipool_zmalloc(priv->sh->ipool[MLX5_IPOOL_MCP], &idx); 4833 if (!mcp_res) { 4834 rte_errno = ENOMEM; 4835 return NULL; 4836 } 4837 mcp_res->idx = idx; 4838 mcp_res->mark_id = mark_id; 4839 /* 4840 * The copy Flows are not included in any list. There 4841 * ones are referenced from other Flows and can not 4842 * be applied, removed, deleted in arbitrary order 4843 * by list traversing. 4844 */ 4845 mcp_res->rix_flow = flow_list_create(dev, MLX5_FLOW_TYPE_MCP, 4846 &attr, items, actions, false, error); 4847 if (!mcp_res->rix_flow) { 4848 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_MCP], idx); 4849 return NULL; 4850 } 4851 return &mcp_res->hlist_ent; 4852 } 4853 4854 struct mlx5_list_entry * 4855 flow_dv_mreg_clone_cb(void *tool_ctx, struct mlx5_list_entry *oentry, 4856 void *cb_ctx __rte_unused) 4857 { 4858 struct rte_eth_dev *dev = tool_ctx; 4859 struct mlx5_priv *priv = dev->data->dev_private; 4860 struct mlx5_flow_mreg_copy_resource *mcp_res; 4861 uint32_t idx = 0; 4862 4863 mcp_res = mlx5_ipool_malloc(priv->sh->ipool[MLX5_IPOOL_MCP], &idx); 4864 if (!mcp_res) { 4865 rte_errno = ENOMEM; 4866 return NULL; 4867 } 4868 memcpy(mcp_res, oentry, sizeof(*mcp_res)); 4869 mcp_res->idx = idx; 4870 return &mcp_res->hlist_ent; 4871 } 4872 4873 void 4874 flow_dv_mreg_clone_free_cb(void *tool_ctx, struct mlx5_list_entry *entry) 4875 { 4876 struct mlx5_flow_mreg_copy_resource *mcp_res = 4877 container_of(entry, typeof(*mcp_res), hlist_ent); 4878 struct rte_eth_dev *dev = tool_ctx; 4879 struct mlx5_priv *priv = dev->data->dev_private; 4880 4881 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_MCP], mcp_res->idx); 4882 } 4883 4884 /** 4885 * Add a flow of copying flow metadata registers in RX_CP_TBL. 4886 * 4887 * As mark_id is unique, if there's already a registered flow for the mark_id, 4888 * return by increasing the reference counter of the resource. Otherwise, create 4889 * the resource (mcp_res) and flow. 4890 * 4891 * Flow looks like, 4892 * - If ingress port is ANY and reg_c[1] is mark_id, 4893 * flow_tag := mark_id, reg_b := reg_c[0] and jump to RX_ACT_TBL. 4894 * 4895 * For default flow (zero mark_id), flow is like, 4896 * - If ingress port is ANY, 4897 * reg_b := reg_c[0] and jump to RX_ACT_TBL. 4898 * 4899 * @param dev 4900 * Pointer to Ethernet device. 4901 * @param mark_id 4902 * ID of MARK action, zero means default flow for META. 4903 * @param[out] error 4904 * Perform verbose error reporting if not NULL. 4905 * 4906 * @return 4907 * Associated resource on success, NULL otherwise and rte_errno is set. 4908 */ 4909 static struct mlx5_flow_mreg_copy_resource * 4910 flow_mreg_add_copy_action(struct rte_eth_dev *dev, uint32_t mark_id, 4911 struct rte_flow_error *error) 4912 { 4913 struct mlx5_priv *priv = dev->data->dev_private; 4914 struct mlx5_list_entry *entry; 4915 struct mlx5_flow_cb_ctx ctx = { 4916 .dev = dev, 4917 .error = error, 4918 .data = &mark_id, 4919 }; 4920 4921 /* Check if already registered. */ 4922 MLX5_ASSERT(priv->mreg_cp_tbl); 4923 entry = mlx5_hlist_register(priv->mreg_cp_tbl, mark_id, &ctx); 4924 if (!entry) 4925 return NULL; 4926 return container_of(entry, struct mlx5_flow_mreg_copy_resource, 4927 hlist_ent); 4928 } 4929 4930 void 4931 flow_dv_mreg_remove_cb(void *tool_ctx, struct mlx5_list_entry *entry) 4932 { 4933 struct mlx5_flow_mreg_copy_resource *mcp_res = 4934 container_of(entry, typeof(*mcp_res), hlist_ent); 4935 struct rte_eth_dev *dev = tool_ctx; 4936 struct mlx5_priv *priv = dev->data->dev_private; 4937 4938 MLX5_ASSERT(mcp_res->rix_flow); 4939 flow_list_destroy(dev, MLX5_FLOW_TYPE_MCP, mcp_res->rix_flow); 4940 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_MCP], mcp_res->idx); 4941 } 4942 4943 /** 4944 * Release flow in RX_CP_TBL. 4945 * 4946 * @param dev 4947 * Pointer to Ethernet device. 4948 * @flow 4949 * Parent flow for wich copying is provided. 4950 */ 4951 static void 4952 flow_mreg_del_copy_action(struct rte_eth_dev *dev, 4953 struct rte_flow *flow) 4954 { 4955 struct mlx5_flow_mreg_copy_resource *mcp_res; 4956 struct mlx5_priv *priv = dev->data->dev_private; 4957 4958 if (!flow->rix_mreg_copy) 4959 return; 4960 mcp_res = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_MCP], 4961 flow->rix_mreg_copy); 4962 if (!mcp_res || !priv->mreg_cp_tbl) 4963 return; 4964 MLX5_ASSERT(mcp_res->rix_flow); 4965 mlx5_hlist_unregister(priv->mreg_cp_tbl, &mcp_res->hlist_ent); 4966 flow->rix_mreg_copy = 0; 4967 } 4968 4969 /** 4970 * Remove the default copy action from RX_CP_TBL. 4971 * 4972 * This functions is called in the mlx5_dev_start(). No thread safe 4973 * is guaranteed. 4974 * 4975 * @param dev 4976 * Pointer to Ethernet device. 4977 */ 4978 static void 4979 flow_mreg_del_default_copy_action(struct rte_eth_dev *dev) 4980 { 4981 struct mlx5_list_entry *entry; 4982 struct mlx5_priv *priv = dev->data->dev_private; 4983 struct mlx5_flow_cb_ctx ctx; 4984 uint32_t mark_id; 4985 4986 /* Check if default flow is registered. */ 4987 if (!priv->mreg_cp_tbl) 4988 return; 4989 mark_id = MLX5_DEFAULT_COPY_ID; 4990 ctx.data = &mark_id; 4991 entry = mlx5_hlist_lookup(priv->mreg_cp_tbl, mark_id, &ctx); 4992 if (!entry) 4993 return; 4994 mlx5_hlist_unregister(priv->mreg_cp_tbl, entry); 4995 } 4996 4997 /** 4998 * Add the default copy action in in RX_CP_TBL. 4999 * 5000 * This functions is called in the mlx5_dev_start(). No thread safe 5001 * is guaranteed. 5002 * 5003 * @param dev 5004 * Pointer to Ethernet device. 5005 * @param[out] error 5006 * Perform verbose error reporting if not NULL. 5007 * 5008 * @return 5009 * 0 for success, negative value otherwise and rte_errno is set. 5010 */ 5011 static int 5012 flow_mreg_add_default_copy_action(struct rte_eth_dev *dev, 5013 struct rte_flow_error *error) 5014 { 5015 struct mlx5_priv *priv = dev->data->dev_private; 5016 struct mlx5_flow_mreg_copy_resource *mcp_res; 5017 struct mlx5_flow_cb_ctx ctx; 5018 uint32_t mark_id; 5019 5020 /* Check whether extensive metadata feature is engaged. */ 5021 if (!priv->sh->config.dv_flow_en || 5022 priv->sh->config.dv_xmeta_en == MLX5_XMETA_MODE_LEGACY || 5023 !mlx5_flow_ext_mreg_supported(dev) || 5024 !priv->sh->dv_regc0_mask) 5025 return 0; 5026 /* 5027 * Add default mreg copy flow may be called multiple time, but 5028 * only be called once in stop. Avoid register it twice. 5029 */ 5030 mark_id = MLX5_DEFAULT_COPY_ID; 5031 ctx.data = &mark_id; 5032 if (mlx5_hlist_lookup(priv->mreg_cp_tbl, mark_id, &ctx)) 5033 return 0; 5034 mcp_res = flow_mreg_add_copy_action(dev, mark_id, error); 5035 if (!mcp_res) 5036 return -rte_errno; 5037 return 0; 5038 } 5039 5040 /** 5041 * Add a flow of copying flow metadata registers in RX_CP_TBL. 5042 * 5043 * All the flow having Q/RSS action should be split by 5044 * flow_mreg_split_qrss_prep() to pass by RX_CP_TBL. A flow in the RX_CP_TBL 5045 * performs the following, 5046 * - CQE->flow_tag := reg_c[1] (MARK) 5047 * - CQE->flow_table_metadata (reg_b) := reg_c[0] (META) 5048 * As CQE's flow_tag is not a register, it can't be simply copied from reg_c[1] 5049 * but there should be a flow per each MARK ID set by MARK action. 5050 * 5051 * For the aforementioned reason, if there's a MARK action in flow's action 5052 * list, a corresponding flow should be added to the RX_CP_TBL in order to copy 5053 * the MARK ID to CQE's flow_tag like, 5054 * - If reg_c[1] is mark_id, 5055 * flow_tag := mark_id, reg_b := reg_c[0] and jump to RX_ACT_TBL. 5056 * 5057 * For SET_META action which stores value in reg_c[0], as the destination is 5058 * also a flow metadata register (reg_b), adding a default flow is enough. Zero 5059 * MARK ID means the default flow. The default flow looks like, 5060 * - For all flow, reg_b := reg_c[0] and jump to RX_ACT_TBL. 5061 * 5062 * @param dev 5063 * Pointer to Ethernet device. 5064 * @param flow 5065 * Pointer to flow structure. 5066 * @param[in] actions 5067 * Pointer to the list of actions. 5068 * @param[out] error 5069 * Perform verbose error reporting if not NULL. 5070 * 5071 * @return 5072 * 0 on success, negative value otherwise and rte_errno is set. 5073 */ 5074 static int 5075 flow_mreg_update_copy_table(struct rte_eth_dev *dev, 5076 struct rte_flow *flow, 5077 const struct rte_flow_action *actions, 5078 struct rte_flow_error *error) 5079 { 5080 struct mlx5_priv *priv = dev->data->dev_private; 5081 struct mlx5_sh_config *config = &priv->sh->config; 5082 struct mlx5_flow_mreg_copy_resource *mcp_res; 5083 const struct rte_flow_action_mark *mark; 5084 5085 /* Check whether extensive metadata feature is engaged. */ 5086 if (!config->dv_flow_en || 5087 config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY || 5088 !mlx5_flow_ext_mreg_supported(dev) || 5089 !priv->sh->dv_regc0_mask) 5090 return 0; 5091 /* Find MARK action. */ 5092 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) { 5093 switch (actions->type) { 5094 case RTE_FLOW_ACTION_TYPE_FLAG: 5095 mcp_res = flow_mreg_add_copy_action 5096 (dev, MLX5_FLOW_MARK_DEFAULT, error); 5097 if (!mcp_res) 5098 return -rte_errno; 5099 flow->rix_mreg_copy = mcp_res->idx; 5100 return 0; 5101 case RTE_FLOW_ACTION_TYPE_MARK: 5102 mark = (const struct rte_flow_action_mark *) 5103 actions->conf; 5104 mcp_res = 5105 flow_mreg_add_copy_action(dev, mark->id, error); 5106 if (!mcp_res) 5107 return -rte_errno; 5108 flow->rix_mreg_copy = mcp_res->idx; 5109 return 0; 5110 default: 5111 break; 5112 } 5113 } 5114 return 0; 5115 } 5116 5117 #define MLX5_MAX_SPLIT_ACTIONS 24 5118 #define MLX5_MAX_SPLIT_ITEMS 24 5119 5120 /** 5121 * Split the hairpin flow. 5122 * Since HW can't support encap and push-vlan on Rx, we move these 5123 * actions to Tx. 5124 * If the count action is after the encap then we also 5125 * move the count action. in this case the count will also measure 5126 * the outer bytes. 5127 * 5128 * @param dev 5129 * Pointer to Ethernet device. 5130 * @param[in] actions 5131 * Associated actions (list terminated by the END action). 5132 * @param[out] actions_rx 5133 * Rx flow actions. 5134 * @param[out] actions_tx 5135 * Tx flow actions.. 5136 * @param[out] pattern_tx 5137 * The pattern items for the Tx flow. 5138 * @param[out] flow_id 5139 * The flow ID connected to this flow. 5140 * 5141 * @return 5142 * 0 on success. 5143 */ 5144 static int 5145 flow_hairpin_split(struct rte_eth_dev *dev, 5146 const struct rte_flow_action actions[], 5147 struct rte_flow_action actions_rx[], 5148 struct rte_flow_action actions_tx[], 5149 struct rte_flow_item pattern_tx[], 5150 uint32_t flow_id) 5151 { 5152 const struct rte_flow_action_raw_encap *raw_encap; 5153 const struct rte_flow_action_raw_decap *raw_decap; 5154 struct mlx5_rte_flow_action_set_tag *set_tag; 5155 struct rte_flow_action *tag_action; 5156 struct mlx5_rte_flow_item_tag *tag_item; 5157 struct rte_flow_item *item; 5158 char *addr; 5159 int push_vlan = 0; 5160 int encap = 0; 5161 5162 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) { 5163 if (actions->type == RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN) 5164 push_vlan = 1; 5165 switch (actions->type) { 5166 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP: 5167 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP: 5168 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN: 5169 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP: 5170 rte_memcpy(actions_tx, actions, 5171 sizeof(struct rte_flow_action)); 5172 actions_tx++; 5173 break; 5174 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID: 5175 if (push_vlan) { 5176 rte_memcpy(actions_tx, actions, 5177 sizeof(struct rte_flow_action)); 5178 actions_tx++; 5179 } else { 5180 rte_memcpy(actions_rx, actions, 5181 sizeof(struct rte_flow_action)); 5182 actions_rx++; 5183 } 5184 break; 5185 case RTE_FLOW_ACTION_TYPE_COUNT: 5186 if (encap) { 5187 rte_memcpy(actions_tx, actions, 5188 sizeof(struct rte_flow_action)); 5189 actions_tx++; 5190 } else { 5191 rte_memcpy(actions_rx, actions, 5192 sizeof(struct rte_flow_action)); 5193 actions_rx++; 5194 } 5195 break; 5196 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP: 5197 raw_encap = actions->conf; 5198 if (raw_encap->size > MLX5_ENCAPSULATION_DECISION_SIZE) { 5199 memcpy(actions_tx, actions, 5200 sizeof(struct rte_flow_action)); 5201 actions_tx++; 5202 encap = 1; 5203 } else { 5204 rte_memcpy(actions_rx, actions, 5205 sizeof(struct rte_flow_action)); 5206 actions_rx++; 5207 } 5208 break; 5209 case RTE_FLOW_ACTION_TYPE_RAW_DECAP: 5210 raw_decap = actions->conf; 5211 if (raw_decap->size < MLX5_ENCAPSULATION_DECISION_SIZE) { 5212 memcpy(actions_tx, actions, 5213 sizeof(struct rte_flow_action)); 5214 actions_tx++; 5215 } else { 5216 rte_memcpy(actions_rx, actions, 5217 sizeof(struct rte_flow_action)); 5218 actions_rx++; 5219 } 5220 break; 5221 default: 5222 rte_memcpy(actions_rx, actions, 5223 sizeof(struct rte_flow_action)); 5224 actions_rx++; 5225 break; 5226 } 5227 } 5228 /* Add set meta action and end action for the Rx flow. */ 5229 tag_action = actions_rx; 5230 tag_action->type = (enum rte_flow_action_type) 5231 MLX5_RTE_FLOW_ACTION_TYPE_TAG; 5232 actions_rx++; 5233 rte_memcpy(actions_rx, actions, sizeof(struct rte_flow_action)); 5234 actions_rx++; 5235 set_tag = (void *)actions_rx; 5236 *set_tag = (struct mlx5_rte_flow_action_set_tag) { 5237 .id = mlx5_flow_get_reg_id(dev, MLX5_HAIRPIN_RX, 0, NULL), 5238 .data = flow_id, 5239 }; 5240 MLX5_ASSERT(set_tag->id > REG_NON); 5241 tag_action->conf = set_tag; 5242 /* Create Tx item list. */ 5243 rte_memcpy(actions_tx, actions, sizeof(struct rte_flow_action)); 5244 addr = (void *)&pattern_tx[2]; 5245 item = pattern_tx; 5246 item->type = (enum rte_flow_item_type) 5247 MLX5_RTE_FLOW_ITEM_TYPE_TAG; 5248 tag_item = (void *)addr; 5249 tag_item->data = flow_id; 5250 tag_item->id = mlx5_flow_get_reg_id(dev, MLX5_HAIRPIN_TX, 0, NULL); 5251 MLX5_ASSERT(set_tag->id > REG_NON); 5252 item->spec = tag_item; 5253 addr += sizeof(struct mlx5_rte_flow_item_tag); 5254 tag_item = (void *)addr; 5255 tag_item->data = UINT32_MAX; 5256 tag_item->id = UINT16_MAX; 5257 item->mask = tag_item; 5258 item->last = NULL; 5259 item++; 5260 item->type = RTE_FLOW_ITEM_TYPE_END; 5261 return 0; 5262 } 5263 5264 /** 5265 * The last stage of splitting chain, just creates the subflow 5266 * without any modification. 5267 * 5268 * @param[in] dev 5269 * Pointer to Ethernet device. 5270 * @param[in] flow 5271 * Parent flow structure pointer. 5272 * @param[in, out] sub_flow 5273 * Pointer to return the created subflow, may be NULL. 5274 * @param[in] attr 5275 * Flow rule attributes. 5276 * @param[in] items 5277 * Pattern specification (list terminated by the END pattern item). 5278 * @param[in] actions 5279 * Associated actions (list terminated by the END action). 5280 * @param[in] flow_split_info 5281 * Pointer to flow split info structure. 5282 * @param[out] error 5283 * Perform verbose error reporting if not NULL. 5284 * @return 5285 * 0 on success, negative value otherwise 5286 */ 5287 static int 5288 flow_create_split_inner(struct rte_eth_dev *dev, 5289 struct rte_flow *flow, 5290 struct mlx5_flow **sub_flow, 5291 const struct rte_flow_attr *attr, 5292 const struct rte_flow_item items[], 5293 const struct rte_flow_action actions[], 5294 struct mlx5_flow_split_info *flow_split_info, 5295 struct rte_flow_error *error) 5296 { 5297 struct mlx5_flow *dev_flow; 5298 struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace(); 5299 5300 dev_flow = flow_drv_prepare(dev, flow, attr, items, actions, 5301 flow_split_info->flow_idx, error); 5302 if (!dev_flow) 5303 return -rte_errno; 5304 dev_flow->flow = flow; 5305 dev_flow->external = flow_split_info->external; 5306 dev_flow->skip_scale = flow_split_info->skip_scale; 5307 /* Subflow object was created, we must include one in the list. */ 5308 SILIST_INSERT(&flow->dev_handles, dev_flow->handle_idx, 5309 dev_flow->handle, next); 5310 /* 5311 * If dev_flow is as one of the suffix flow, some actions in suffix 5312 * flow may need some user defined item layer flags, and pass the 5313 * Metadata rxq mark flag to suffix flow as well. 5314 */ 5315 if (flow_split_info->prefix_layers) 5316 dev_flow->handle->layers = flow_split_info->prefix_layers; 5317 if (flow_split_info->prefix_mark) { 5318 MLX5_ASSERT(wks); 5319 wks->mark = 1; 5320 } 5321 if (sub_flow) 5322 *sub_flow = dev_flow; 5323 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 5324 dev_flow->dv.table_id = flow_split_info->table_id; 5325 #endif 5326 return flow_drv_translate(dev, dev_flow, attr, items, actions, error); 5327 } 5328 5329 /** 5330 * Get the sub policy of a meter. 5331 * 5332 * @param[in] dev 5333 * Pointer to Ethernet device. 5334 * @param[in] flow 5335 * Parent flow structure pointer. 5336 * @param wks 5337 * Pointer to thread flow work space. 5338 * @param[in] attr 5339 * Flow rule attributes. 5340 * @param[in] items 5341 * Pattern specification (list terminated by the END pattern item). 5342 * @param[out] error 5343 * Perform verbose error reporting if not NULL. 5344 * 5345 * @return 5346 * Pointer to the meter sub policy, NULL otherwise and rte_errno is set. 5347 */ 5348 static struct mlx5_flow_meter_sub_policy * 5349 get_meter_sub_policy(struct rte_eth_dev *dev, 5350 struct rte_flow *flow, 5351 struct mlx5_flow_workspace *wks, 5352 const struct rte_flow_attr *attr, 5353 const struct rte_flow_item items[], 5354 struct rte_flow_error *error) 5355 { 5356 struct mlx5_flow_meter_policy *policy; 5357 struct mlx5_flow_meter_policy *final_policy; 5358 struct mlx5_flow_meter_sub_policy *sub_policy = NULL; 5359 5360 policy = wks->policy; 5361 final_policy = policy->is_hierarchy ? wks->final_policy : policy; 5362 if (final_policy->is_rss || final_policy->is_queue) { 5363 struct mlx5_flow_rss_desc rss_desc_v[MLX5_MTR_RTE_COLORS]; 5364 struct mlx5_flow_rss_desc *rss_desc[MLX5_MTR_RTE_COLORS] = {0}; 5365 uint32_t i; 5366 5367 /* 5368 * This is a tmp dev_flow, 5369 * no need to register any matcher for it in translate. 5370 */ 5371 wks->skip_matcher_reg = 1; 5372 for (i = 0; i < MLX5_MTR_RTE_COLORS; i++) { 5373 struct mlx5_flow dev_flow = {0}; 5374 struct mlx5_flow_handle dev_handle = { {0} }; 5375 uint8_t fate = final_policy->act_cnt[i].fate_action; 5376 5377 if (fate == MLX5_FLOW_FATE_SHARED_RSS) { 5378 const struct rte_flow_action_rss *rss_act = 5379 final_policy->act_cnt[i].rss->conf; 5380 struct rte_flow_action rss_actions[2] = { 5381 [0] = { 5382 .type = RTE_FLOW_ACTION_TYPE_RSS, 5383 .conf = rss_act, 5384 }, 5385 [1] = { 5386 .type = RTE_FLOW_ACTION_TYPE_END, 5387 .conf = NULL, 5388 } 5389 }; 5390 5391 dev_flow.handle = &dev_handle; 5392 dev_flow.ingress = attr->ingress; 5393 dev_flow.flow = flow; 5394 dev_flow.external = 0; 5395 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 5396 dev_flow.dv.transfer = attr->transfer; 5397 #endif 5398 /** 5399 * Translate RSS action to get rss hash fields. 5400 */ 5401 if (flow_drv_translate(dev, &dev_flow, attr, 5402 items, rss_actions, error)) 5403 goto exit; 5404 rss_desc_v[i] = wks->rss_desc; 5405 rss_desc_v[i].key_len = MLX5_RSS_HASH_KEY_LEN; 5406 rss_desc_v[i].hash_fields = 5407 dev_flow.hash_fields; 5408 rss_desc_v[i].queue_num = 5409 rss_desc_v[i].hash_fields ? 5410 rss_desc_v[i].queue_num : 1; 5411 rss_desc_v[i].tunnel = 5412 !!(dev_flow.handle->layers & 5413 MLX5_FLOW_LAYER_TUNNEL); 5414 /* Use the RSS queues in the containers. */ 5415 rss_desc_v[i].queue = 5416 (uint16_t *)(uintptr_t)rss_act->queue; 5417 rss_desc[i] = &rss_desc_v[i]; 5418 } else if (fate == MLX5_FLOW_FATE_QUEUE) { 5419 /* This is queue action. */ 5420 rss_desc_v[i] = wks->rss_desc; 5421 rss_desc_v[i].key_len = 0; 5422 rss_desc_v[i].hash_fields = 0; 5423 rss_desc_v[i].queue = 5424 &final_policy->act_cnt[i].queue; 5425 rss_desc_v[i].queue_num = 1; 5426 rss_desc[i] = &rss_desc_v[i]; 5427 } else { 5428 rss_desc[i] = NULL; 5429 } 5430 } 5431 sub_policy = flow_drv_meter_sub_policy_rss_prepare(dev, 5432 flow, policy, rss_desc); 5433 } else { 5434 enum mlx5_meter_domain mtr_domain = 5435 attr->transfer ? MLX5_MTR_DOMAIN_TRANSFER : 5436 (attr->egress ? MLX5_MTR_DOMAIN_EGRESS : 5437 MLX5_MTR_DOMAIN_INGRESS); 5438 sub_policy = policy->sub_policys[mtr_domain][0]; 5439 } 5440 if (!sub_policy) 5441 rte_flow_error_set(error, EINVAL, 5442 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, 5443 "Failed to get meter sub-policy."); 5444 exit: 5445 return sub_policy; 5446 } 5447 5448 /** 5449 * Split the meter flow. 5450 * 5451 * As meter flow will split to three sub flow, other than meter 5452 * action, the other actions make sense to only meter accepts 5453 * the packet. If it need to be dropped, no other additional 5454 * actions should be take. 5455 * 5456 * One kind of special action which decapsulates the L3 tunnel 5457 * header will be in the prefix sub flow, as not to take the 5458 * L3 tunnel header into account. 5459 * 5460 * @param[in] dev 5461 * Pointer to Ethernet device. 5462 * @param[in] flow 5463 * Parent flow structure pointer. 5464 * @param wks 5465 * Pointer to thread flow work space. 5466 * @param[in] attr 5467 * Flow rule attributes. 5468 * @param[in] items 5469 * Pattern specification (list terminated by the END pattern item). 5470 * @param[out] sfx_items 5471 * Suffix flow match items (list terminated by the END pattern item). 5472 * @param[in] actions 5473 * Associated actions (list terminated by the END action). 5474 * @param[out] actions_sfx 5475 * Suffix flow actions. 5476 * @param[out] actions_pre 5477 * Prefix flow actions. 5478 * @param[out] mtr_flow_id 5479 * Pointer to meter flow id. 5480 * @param[out] error 5481 * Perform verbose error reporting if not NULL. 5482 * 5483 * @return 5484 * 0 on success, a negative errno value otherwise and rte_errno is set. 5485 */ 5486 static int 5487 flow_meter_split_prep(struct rte_eth_dev *dev, 5488 struct rte_flow *flow, 5489 struct mlx5_flow_workspace *wks, 5490 const struct rte_flow_attr *attr, 5491 const struct rte_flow_item items[], 5492 struct rte_flow_item sfx_items[], 5493 const struct rte_flow_action actions[], 5494 struct rte_flow_action actions_sfx[], 5495 struct rte_flow_action actions_pre[], 5496 uint32_t *mtr_flow_id, 5497 struct rte_flow_error *error) 5498 { 5499 struct mlx5_priv *priv = dev->data->dev_private; 5500 struct mlx5_flow_meter_info *fm = wks->fm; 5501 struct rte_flow_action *tag_action = NULL; 5502 struct rte_flow_item *tag_item; 5503 struct mlx5_rte_flow_action_set_tag *set_tag; 5504 const struct rte_flow_action_raw_encap *raw_encap; 5505 const struct rte_flow_action_raw_decap *raw_decap; 5506 struct mlx5_rte_flow_item_tag *tag_item_spec; 5507 struct mlx5_rte_flow_item_tag *tag_item_mask; 5508 uint32_t tag_id = 0; 5509 struct rte_flow_item *vlan_item_dst = NULL; 5510 const struct rte_flow_item *vlan_item_src = NULL; 5511 const struct rte_flow_item *orig_items = items; 5512 struct rte_flow_action *hw_mtr_action; 5513 struct rte_flow_action *action_pre_head = NULL; 5514 uint16_t flow_src_port = priv->representor_id; 5515 bool mtr_first; 5516 uint8_t mtr_id_offset = priv->mtr_reg_share ? MLX5_MTR_COLOR_BITS : 0; 5517 uint8_t mtr_reg_bits = priv->mtr_reg_share ? 5518 MLX5_MTR_IDLE_BITS_IN_COLOR_REG : MLX5_REG_BITS; 5519 uint32_t flow_id = 0; 5520 uint32_t flow_id_reversed = 0; 5521 uint8_t flow_id_bits = 0; 5522 bool after_meter = false; 5523 int shift; 5524 5525 /* Prepare the suffix subflow items. */ 5526 tag_item = sfx_items++; 5527 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) { 5528 int item_type = items->type; 5529 5530 switch (item_type) { 5531 case RTE_FLOW_ITEM_TYPE_PORT_ID: 5532 case RTE_FLOW_ITEM_TYPE_REPRESENTED_PORT: 5533 case RTE_FLOW_ITEM_TYPE_PORT_REPRESENTOR: 5534 if (mlx5_flow_get_item_vport_id(dev, items, &flow_src_port, NULL, error)) 5535 return -rte_errno; 5536 if (!fm->def_policy && wks->policy->hierarchy_match_port && 5537 flow_src_port != priv->representor_id) { 5538 if (flow_drv_mtr_hierarchy_rule_create(dev, 5539 flow, fm, 5540 flow_src_port, 5541 items, 5542 error)) 5543 return -rte_errno; 5544 } 5545 memcpy(sfx_items, items, sizeof(*sfx_items)); 5546 sfx_items++; 5547 break; 5548 case RTE_FLOW_ITEM_TYPE_VLAN: 5549 /* Determine if copy vlan item below. */ 5550 vlan_item_src = items; 5551 vlan_item_dst = sfx_items++; 5552 vlan_item_dst->type = RTE_FLOW_ITEM_TYPE_VOID; 5553 break; 5554 default: 5555 break; 5556 } 5557 } 5558 sfx_items->type = RTE_FLOW_ITEM_TYPE_END; 5559 sfx_items++; 5560 mtr_first = priv->sh->meter_aso_en && 5561 (attr->egress || (attr->transfer && flow_src_port != UINT16_MAX)); 5562 /* For ASO meter, meter must be before tag in TX direction. */ 5563 if (mtr_first) { 5564 action_pre_head = actions_pre++; 5565 /* Leave space for tag action. */ 5566 tag_action = actions_pre++; 5567 } 5568 /* Prepare the actions for prefix and suffix flow. */ 5569 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) { 5570 struct rte_flow_action *action_cur = NULL; 5571 5572 switch (actions->type) { 5573 case RTE_FLOW_ACTION_TYPE_METER: 5574 if (mtr_first) { 5575 action_cur = action_pre_head; 5576 } else { 5577 /* Leave space for tag action. */ 5578 tag_action = actions_pre++; 5579 action_cur = actions_pre++; 5580 } 5581 after_meter = true; 5582 break; 5583 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP: 5584 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP: 5585 action_cur = actions_pre++; 5586 break; 5587 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP: 5588 raw_encap = actions->conf; 5589 if (raw_encap->size < MLX5_ENCAPSULATION_DECISION_SIZE) 5590 action_cur = actions_pre++; 5591 break; 5592 case RTE_FLOW_ACTION_TYPE_RAW_DECAP: 5593 raw_decap = actions->conf; 5594 if (raw_decap->size > MLX5_ENCAPSULATION_DECISION_SIZE) 5595 action_cur = actions_pre++; 5596 break; 5597 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN: 5598 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID: 5599 if (vlan_item_dst && vlan_item_src) { 5600 memcpy(vlan_item_dst, vlan_item_src, 5601 sizeof(*vlan_item_dst)); 5602 /* 5603 * Convert to internal match item, it is used 5604 * for vlan push and set vid. 5605 */ 5606 vlan_item_dst->type = (enum rte_flow_item_type) 5607 MLX5_RTE_FLOW_ITEM_TYPE_VLAN; 5608 } 5609 break; 5610 case RTE_FLOW_ACTION_TYPE_COUNT: 5611 if (fm->def_policy) 5612 action_cur = after_meter ? 5613 actions_sfx++ : actions_pre++; 5614 break; 5615 default: 5616 break; 5617 } 5618 if (!action_cur) 5619 action_cur = (fm->def_policy) ? 5620 actions_sfx++ : actions_pre++; 5621 memcpy(action_cur, actions, sizeof(struct rte_flow_action)); 5622 } 5623 /* Add end action to the actions. */ 5624 actions_sfx->type = RTE_FLOW_ACTION_TYPE_END; 5625 if (priv->sh->meter_aso_en) { 5626 /** 5627 * For ASO meter, need to add an extra jump action explicitly, 5628 * to jump from meter to policer table. 5629 */ 5630 struct mlx5_flow_meter_sub_policy *sub_policy; 5631 struct mlx5_flow_tbl_data_entry *tbl_data; 5632 5633 if (!fm->def_policy) { 5634 sub_policy = get_meter_sub_policy(dev, flow, wks, 5635 attr, orig_items, 5636 error); 5637 if (!sub_policy) 5638 return -rte_errno; 5639 } else { 5640 enum mlx5_meter_domain mtr_domain = 5641 attr->transfer ? MLX5_MTR_DOMAIN_TRANSFER : 5642 (attr->egress ? MLX5_MTR_DOMAIN_EGRESS : 5643 MLX5_MTR_DOMAIN_INGRESS); 5644 5645 sub_policy = 5646 &priv->sh->mtrmng->def_policy[mtr_domain]->sub_policy; 5647 } 5648 tbl_data = container_of(sub_policy->tbl_rsc, 5649 struct mlx5_flow_tbl_data_entry, tbl); 5650 hw_mtr_action = actions_pre++; 5651 hw_mtr_action->type = (enum rte_flow_action_type) 5652 MLX5_RTE_FLOW_ACTION_TYPE_JUMP; 5653 hw_mtr_action->conf = tbl_data->jump.action; 5654 } 5655 actions_pre->type = RTE_FLOW_ACTION_TYPE_END; 5656 actions_pre++; 5657 if (!tag_action) 5658 return rte_flow_error_set(error, ENOMEM, 5659 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, 5660 NULL, "No tag action space."); 5661 if (!mtr_flow_id) { 5662 tag_action->type = RTE_FLOW_ACTION_TYPE_VOID; 5663 goto exit; 5664 } 5665 /* Only default-policy Meter creates mtr flow id. */ 5666 if (fm->def_policy) { 5667 mlx5_ipool_malloc(fm->flow_ipool, &tag_id); 5668 if (!tag_id) 5669 return rte_flow_error_set(error, ENOMEM, 5670 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, 5671 "Failed to allocate meter flow id."); 5672 flow_id = tag_id - 1; 5673 flow_id_bits = (!flow_id) ? 1 : 5674 (MLX5_REG_BITS - __builtin_clz(flow_id)); 5675 if ((flow_id_bits + priv->sh->mtrmng->max_mtr_bits) > 5676 mtr_reg_bits) { 5677 mlx5_ipool_free(fm->flow_ipool, tag_id); 5678 return rte_flow_error_set(error, EINVAL, 5679 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, 5680 "Meter flow id exceeds max limit."); 5681 } 5682 if (flow_id_bits > priv->sh->mtrmng->max_mtr_flow_bits) 5683 priv->sh->mtrmng->max_mtr_flow_bits = flow_id_bits; 5684 } 5685 /* Build tag actions and items for meter_id/meter flow_id. */ 5686 set_tag = (struct mlx5_rte_flow_action_set_tag *)actions_pre; 5687 tag_item_spec = (struct mlx5_rte_flow_item_tag *)sfx_items; 5688 tag_item_mask = tag_item_spec + 1; 5689 /* Both flow_id and meter_id share the same register. */ 5690 *set_tag = (struct mlx5_rte_flow_action_set_tag) { 5691 .id = (enum modify_reg)mlx5_flow_get_reg_id(dev, MLX5_MTR_ID, 5692 0, error), 5693 .offset = mtr_id_offset, 5694 .length = mtr_reg_bits, 5695 .data = flow->meter, 5696 }; 5697 /* 5698 * The color Reg bits used by flow_id are growing from 5699 * msb to lsb, so must do bit reverse for flow_id val in RegC. 5700 */ 5701 for (shift = 0; shift < flow_id_bits; shift++) 5702 flow_id_reversed = (flow_id_reversed << 1) | 5703 ((flow_id >> shift) & 0x1); 5704 set_tag->data |= 5705 flow_id_reversed << (mtr_reg_bits - flow_id_bits); 5706 tag_item_spec->id = set_tag->id; 5707 tag_item_spec->data = set_tag->data << mtr_id_offset; 5708 tag_item_mask->data = UINT32_MAX << mtr_id_offset; 5709 tag_action->type = (enum rte_flow_action_type) 5710 MLX5_RTE_FLOW_ACTION_TYPE_TAG; 5711 tag_action->conf = set_tag; 5712 tag_item->type = (enum rte_flow_item_type) 5713 MLX5_RTE_FLOW_ITEM_TYPE_TAG; 5714 tag_item->spec = tag_item_spec; 5715 tag_item->last = NULL; 5716 tag_item->mask = tag_item_mask; 5717 exit: 5718 if (mtr_flow_id) 5719 *mtr_flow_id = tag_id; 5720 return 0; 5721 } 5722 5723 /** 5724 * Split action list having QUEUE/RSS for metadata register copy. 5725 * 5726 * Once Q/RSS action is detected in user's action list, the flow action 5727 * should be split in order to copy metadata registers, which will happen in 5728 * RX_CP_TBL like, 5729 * - CQE->flow_tag := reg_c[1] (MARK) 5730 * - CQE->flow_table_metadata (reg_b) := reg_c[0] (META) 5731 * The Q/RSS action will be performed on RX_ACT_TBL after passing by RX_CP_TBL. 5732 * This is because the last action of each flow must be a terminal action 5733 * (QUEUE, RSS or DROP). 5734 * 5735 * Flow ID must be allocated to identify actions in the RX_ACT_TBL and it is 5736 * stored and kept in the mlx5_flow structure per each sub_flow. 5737 * 5738 * The Q/RSS action is replaced with, 5739 * - SET_TAG, setting the allocated flow ID to reg_c[2]. 5740 * And the following JUMP action is added at the end, 5741 * - JUMP, to RX_CP_TBL. 5742 * 5743 * A flow to perform remained Q/RSS action will be created in RX_ACT_TBL by 5744 * flow_create_split_metadata() routine. The flow will look like, 5745 * - If flow ID matches (reg_c[2]), perform Q/RSS. 5746 * 5747 * @param dev 5748 * Pointer to Ethernet device. 5749 * @param[out] split_actions 5750 * Pointer to store split actions to jump to CP_TBL. 5751 * @param[in] actions 5752 * Pointer to the list of original flow actions. 5753 * @param[in] qrss 5754 * Pointer to the Q/RSS action. 5755 * @param[in] actions_n 5756 * Number of original actions. 5757 * @param[in] mtr_sfx 5758 * Check if it is in meter suffix table. 5759 * @param[out] error 5760 * Perform verbose error reporting if not NULL. 5761 * 5762 * @return 5763 * non-zero unique flow_id on success, otherwise 0 and 5764 * error/rte_error are set. 5765 */ 5766 static uint32_t 5767 flow_mreg_split_qrss_prep(struct rte_eth_dev *dev, 5768 struct rte_flow_action *split_actions, 5769 const struct rte_flow_action *actions, 5770 const struct rte_flow_action *qrss, 5771 int actions_n, int mtr_sfx, 5772 struct rte_flow_error *error) 5773 { 5774 struct mlx5_priv *priv = dev->data->dev_private; 5775 struct mlx5_rte_flow_action_set_tag *set_tag; 5776 struct rte_flow_action_jump *jump; 5777 const int qrss_idx = qrss - actions; 5778 uint32_t flow_id = 0; 5779 int ret = 0; 5780 5781 /* 5782 * Given actions will be split 5783 * - Replace QUEUE/RSS action with SET_TAG to set flow ID. 5784 * - Add jump to mreg CP_TBL. 5785 * As a result, there will be one more action. 5786 */ 5787 memcpy(split_actions, actions, sizeof(*split_actions) * actions_n); 5788 /* Count MLX5_RTE_FLOW_ACTION_TYPE_TAG. */ 5789 ++actions_n; 5790 set_tag = (void *)(split_actions + actions_n); 5791 /* 5792 * If we are not the meter suffix flow, add the tag action. 5793 * Since meter suffix flow already has the tag added. 5794 */ 5795 if (!mtr_sfx) { 5796 /* 5797 * Allocate the new subflow ID. This one is unique within 5798 * device and not shared with representors. Otherwise, 5799 * we would have to resolve multi-thread access synch 5800 * issue. Each flow on the shared device is appended 5801 * with source vport identifier, so the resulting 5802 * flows will be unique in the shared (by master and 5803 * representors) domain even if they have coinciding 5804 * IDs. 5805 */ 5806 mlx5_ipool_malloc(priv->sh->ipool 5807 [MLX5_IPOOL_RSS_EXPANTION_FLOW_ID], &flow_id); 5808 if (!flow_id) 5809 return rte_flow_error_set(error, ENOMEM, 5810 RTE_FLOW_ERROR_TYPE_ACTION, 5811 NULL, "can't allocate id " 5812 "for split Q/RSS subflow"); 5813 /* Internal SET_TAG action to set flow ID. */ 5814 *set_tag = (struct mlx5_rte_flow_action_set_tag){ 5815 .data = flow_id, 5816 }; 5817 ret = mlx5_flow_get_reg_id(dev, MLX5_COPY_MARK, 0, error); 5818 if (ret < 0) 5819 return ret; 5820 set_tag->id = ret; 5821 /* Construct new actions array. */ 5822 /* Replace QUEUE/RSS action. */ 5823 split_actions[qrss_idx] = (struct rte_flow_action){ 5824 .type = (enum rte_flow_action_type) 5825 MLX5_RTE_FLOW_ACTION_TYPE_TAG, 5826 .conf = set_tag, 5827 }; 5828 } else { 5829 /* 5830 * If we are the suffix flow of meter, tag already exist. 5831 * Set the QUEUE/RSS action to void. 5832 */ 5833 split_actions[qrss_idx].type = RTE_FLOW_ACTION_TYPE_VOID; 5834 } 5835 /* JUMP action to jump to mreg copy table (CP_TBL). */ 5836 jump = (void *)(set_tag + 1); 5837 *jump = (struct rte_flow_action_jump){ 5838 .group = MLX5_FLOW_MREG_CP_TABLE_GROUP, 5839 }; 5840 split_actions[actions_n - 2] = (struct rte_flow_action){ 5841 .type = RTE_FLOW_ACTION_TYPE_JUMP, 5842 .conf = jump, 5843 }; 5844 split_actions[actions_n - 1] = (struct rte_flow_action){ 5845 .type = RTE_FLOW_ACTION_TYPE_END, 5846 }; 5847 return flow_id; 5848 } 5849 5850 /** 5851 * Extend the given action list for Tx metadata copy. 5852 * 5853 * Copy the given action list to the ext_actions and add flow metadata register 5854 * copy action in order to copy reg_a set by WQE to reg_c[0]. 5855 * 5856 * @param[out] ext_actions 5857 * Pointer to the extended action list. 5858 * @param[in] actions 5859 * Pointer to the list of actions. 5860 * @param[in] actions_n 5861 * Number of actions in the list. 5862 * @param[out] error 5863 * Perform verbose error reporting if not NULL. 5864 * @param[in] encap_idx 5865 * The encap action index. 5866 * 5867 * @return 5868 * 0 on success, negative value otherwise 5869 */ 5870 static int 5871 flow_mreg_tx_copy_prep(struct rte_eth_dev *dev, 5872 struct rte_flow_action *ext_actions, 5873 const struct rte_flow_action *actions, 5874 int actions_n, struct rte_flow_error *error, 5875 int encap_idx) 5876 { 5877 struct mlx5_flow_action_copy_mreg *cp_mreg = 5878 (struct mlx5_flow_action_copy_mreg *) 5879 (ext_actions + actions_n + 1); 5880 int ret; 5881 5882 ret = mlx5_flow_get_reg_id(dev, MLX5_METADATA_RX, 0, error); 5883 if (ret < 0) 5884 return ret; 5885 cp_mreg->dst = ret; 5886 ret = mlx5_flow_get_reg_id(dev, MLX5_METADATA_TX, 0, error); 5887 if (ret < 0) 5888 return ret; 5889 cp_mreg->src = ret; 5890 if (encap_idx != 0) 5891 memcpy(ext_actions, actions, sizeof(*ext_actions) * encap_idx); 5892 if (encap_idx == actions_n - 1) { 5893 ext_actions[actions_n - 1] = (struct rte_flow_action){ 5894 .type = (enum rte_flow_action_type) 5895 MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG, 5896 .conf = cp_mreg, 5897 }; 5898 ext_actions[actions_n] = (struct rte_flow_action){ 5899 .type = RTE_FLOW_ACTION_TYPE_END, 5900 }; 5901 } else { 5902 ext_actions[encap_idx] = (struct rte_flow_action){ 5903 .type = (enum rte_flow_action_type) 5904 MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG, 5905 .conf = cp_mreg, 5906 }; 5907 memcpy(ext_actions + encap_idx + 1, actions + encap_idx, 5908 sizeof(*ext_actions) * (actions_n - encap_idx)); 5909 } 5910 return 0; 5911 } 5912 5913 /** 5914 * Check the match action from the action list. 5915 * 5916 * @param[in] actions 5917 * Pointer to the list of actions. 5918 * @param[in] attr 5919 * Flow rule attributes. 5920 * @param[in] action 5921 * The action to be check if exist. 5922 * @param[out] match_action_pos 5923 * Pointer to the position of the matched action if exists, otherwise is -1. 5924 * @param[out] qrss_action_pos 5925 * Pointer to the position of the Queue/RSS action if exists, otherwise is -1. 5926 * @param[out] modify_after_mirror 5927 * Pointer to the flag of modify action after FDB mirroring. 5928 * 5929 * @return 5930 * > 0 the total number of actions. 5931 * 0 if not found match action in action list. 5932 */ 5933 static int 5934 flow_check_match_action(const struct rte_flow_action actions[], 5935 const struct rte_flow_attr *attr, 5936 enum rte_flow_action_type action, 5937 int *match_action_pos, int *qrss_action_pos, 5938 int *modify_after_mirror) 5939 { 5940 const struct rte_flow_action_sample *sample; 5941 const struct rte_flow_action_raw_decap *decap; 5942 int actions_n = 0; 5943 uint32_t ratio = 0; 5944 int sub_type = 0; 5945 int flag = 0; 5946 int fdb_mirror = 0; 5947 5948 *match_action_pos = -1; 5949 *qrss_action_pos = -1; 5950 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) { 5951 if (actions->type == action) { 5952 flag = 1; 5953 *match_action_pos = actions_n; 5954 } 5955 switch (actions->type) { 5956 case RTE_FLOW_ACTION_TYPE_QUEUE: 5957 case RTE_FLOW_ACTION_TYPE_RSS: 5958 *qrss_action_pos = actions_n; 5959 break; 5960 case RTE_FLOW_ACTION_TYPE_SAMPLE: 5961 sample = actions->conf; 5962 ratio = sample->ratio; 5963 sub_type = ((const struct rte_flow_action *) 5964 (sample->actions))->type; 5965 if (ratio == 1 && attr->transfer && 5966 sub_type != RTE_FLOW_ACTION_TYPE_END) 5967 fdb_mirror = 1; 5968 break; 5969 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC: 5970 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST: 5971 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC: 5972 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST: 5973 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC: 5974 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST: 5975 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC: 5976 case RTE_FLOW_ACTION_TYPE_SET_TP_DST: 5977 case RTE_FLOW_ACTION_TYPE_DEC_TTL: 5978 case RTE_FLOW_ACTION_TYPE_SET_TTL: 5979 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ: 5980 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ: 5981 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK: 5982 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK: 5983 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP: 5984 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP: 5985 case RTE_FLOW_ACTION_TYPE_FLAG: 5986 case RTE_FLOW_ACTION_TYPE_MARK: 5987 case RTE_FLOW_ACTION_TYPE_SET_META: 5988 case RTE_FLOW_ACTION_TYPE_SET_TAG: 5989 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN: 5990 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN: 5991 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID: 5992 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP: 5993 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP: 5994 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP: 5995 case RTE_FLOW_ACTION_TYPE_MODIFY_FIELD: 5996 case RTE_FLOW_ACTION_TYPE_METER: 5997 if (fdb_mirror) 5998 *modify_after_mirror = 1; 5999 break; 6000 case RTE_FLOW_ACTION_TYPE_RAW_DECAP: 6001 decap = actions->conf; 6002 while ((++actions)->type == RTE_FLOW_ACTION_TYPE_VOID) 6003 ; 6004 actions_n++; 6005 if (actions->type == RTE_FLOW_ACTION_TYPE_RAW_ENCAP) { 6006 const struct rte_flow_action_raw_encap *encap = 6007 actions->conf; 6008 if (decap->size <= 6009 MLX5_ENCAPSULATION_DECISION_SIZE && 6010 encap->size > 6011 MLX5_ENCAPSULATION_DECISION_SIZE) 6012 /* L3 encap. */ 6013 break; 6014 } 6015 if (fdb_mirror) 6016 *modify_after_mirror = 1; 6017 break; 6018 default: 6019 break; 6020 } 6021 actions_n++; 6022 } 6023 if (flag && fdb_mirror && !*modify_after_mirror) { 6024 /* FDB mirroring uses the destination array to implement 6025 * instead of FLOW_SAMPLER object. 6026 */ 6027 if (sub_type != RTE_FLOW_ACTION_TYPE_END) 6028 flag = 0; 6029 } 6030 /* Count RTE_FLOW_ACTION_TYPE_END. */ 6031 return flag ? actions_n + 1 : 0; 6032 } 6033 6034 #define SAMPLE_SUFFIX_ITEM 3 6035 6036 /** 6037 * Split the sample flow. 6038 * 6039 * As sample flow will split to two sub flow, sample flow with 6040 * sample action, the other actions will move to new suffix flow. 6041 * 6042 * Also add unique tag id with tag action in the sample flow, 6043 * the same tag id will be as match in the suffix flow. 6044 * 6045 * @param dev 6046 * Pointer to Ethernet device. 6047 * @param[in] add_tag 6048 * Add extra tag action flag. 6049 * @param[out] sfx_items 6050 * Suffix flow match items (list terminated by the END pattern item). 6051 * @param[in] actions 6052 * Associated actions (list terminated by the END action). 6053 * @param[out] actions_sfx 6054 * Suffix flow actions. 6055 * @param[out] actions_pre 6056 * Prefix flow actions. 6057 * @param[in] actions_n 6058 * The total number of actions. 6059 * @param[in] sample_action_pos 6060 * The sample action position. 6061 * @param[in] qrss_action_pos 6062 * The Queue/RSS action position. 6063 * @param[in] jump_table 6064 * Add extra jump action flag. 6065 * @param[out] error 6066 * Perform verbose error reporting if not NULL. 6067 * 6068 * @return 6069 * 0 on success, or unique flow_id, a negative errno value 6070 * otherwise and rte_errno is set. 6071 */ 6072 static int 6073 flow_sample_split_prep(struct rte_eth_dev *dev, 6074 int add_tag, 6075 const struct rte_flow_item items[], 6076 struct rte_flow_item sfx_items[], 6077 const struct rte_flow_action actions[], 6078 struct rte_flow_action actions_sfx[], 6079 struct rte_flow_action actions_pre[], 6080 int actions_n, 6081 int sample_action_pos, 6082 int qrss_action_pos, 6083 int jump_table, 6084 struct rte_flow_error *error) 6085 { 6086 struct mlx5_priv *priv = dev->data->dev_private; 6087 struct mlx5_rte_flow_action_set_tag *set_tag; 6088 struct mlx5_rte_flow_item_tag *tag_spec; 6089 struct mlx5_rte_flow_item_tag *tag_mask; 6090 struct rte_flow_action_jump *jump_action; 6091 uint32_t tag_id = 0; 6092 int append_index = 0; 6093 int set_tag_idx = -1; 6094 int index; 6095 int ret; 6096 6097 if (sample_action_pos < 0) 6098 return rte_flow_error_set(error, EINVAL, 6099 RTE_FLOW_ERROR_TYPE_ACTION, 6100 NULL, "invalid position of sample " 6101 "action in list"); 6102 /* Prepare the actions for prefix and suffix flow. */ 6103 if (add_tag) { 6104 /* Update the new added tag action index preceding 6105 * the PUSH_VLAN or ENCAP action. 6106 */ 6107 const struct rte_flow_action_raw_encap *raw_encap; 6108 const struct rte_flow_action *action = actions; 6109 int encap_idx; 6110 int action_idx = 0; 6111 int raw_decap_idx = -1; 6112 int push_vlan_idx = -1; 6113 for (; action->type != RTE_FLOW_ACTION_TYPE_END; action++) { 6114 switch (action->type) { 6115 case RTE_FLOW_ACTION_TYPE_RAW_DECAP: 6116 raw_decap_idx = action_idx; 6117 break; 6118 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP: 6119 raw_encap = action->conf; 6120 if (raw_encap->size > 6121 MLX5_ENCAPSULATION_DECISION_SIZE) { 6122 encap_idx = raw_decap_idx != -1 ? 6123 raw_decap_idx : action_idx; 6124 if (encap_idx < sample_action_pos && 6125 push_vlan_idx == -1) 6126 set_tag_idx = encap_idx; 6127 } 6128 break; 6129 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP: 6130 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP: 6131 encap_idx = action_idx; 6132 if (encap_idx < sample_action_pos && 6133 push_vlan_idx == -1) 6134 set_tag_idx = encap_idx; 6135 break; 6136 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN: 6137 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID: 6138 if (action_idx < sample_action_pos && 6139 push_vlan_idx == -1) { 6140 set_tag_idx = action_idx; 6141 push_vlan_idx = action_idx; 6142 } 6143 break; 6144 default: 6145 break; 6146 } 6147 action_idx++; 6148 } 6149 } 6150 /* Prepare the actions for prefix and suffix flow. */ 6151 if (qrss_action_pos >= 0 && qrss_action_pos < sample_action_pos) { 6152 index = qrss_action_pos; 6153 /* Put the preceding the Queue/RSS action into prefix flow. */ 6154 if (index != 0) 6155 memcpy(actions_pre, actions, 6156 sizeof(struct rte_flow_action) * index); 6157 /* Put others preceding the sample action into prefix flow. */ 6158 if (sample_action_pos > index + 1) 6159 memcpy(actions_pre + index, actions + index + 1, 6160 sizeof(struct rte_flow_action) * 6161 (sample_action_pos - index - 1)); 6162 index = sample_action_pos - 1; 6163 /* Put Queue/RSS action into Suffix flow. */ 6164 memcpy(actions_sfx, actions + qrss_action_pos, 6165 sizeof(struct rte_flow_action)); 6166 actions_sfx++; 6167 } else if (add_tag && set_tag_idx >= 0) { 6168 if (set_tag_idx > 0) 6169 memcpy(actions_pre, actions, 6170 sizeof(struct rte_flow_action) * set_tag_idx); 6171 memcpy(actions_pre + set_tag_idx + 1, actions + set_tag_idx, 6172 sizeof(struct rte_flow_action) * 6173 (sample_action_pos - set_tag_idx)); 6174 index = sample_action_pos; 6175 } else { 6176 index = sample_action_pos; 6177 if (index != 0) 6178 memcpy(actions_pre, actions, 6179 sizeof(struct rte_flow_action) * index); 6180 } 6181 /* For CX5, add an extra tag action for NIC-RX and E-Switch ingress. 6182 * For CX6DX and above, metadata registers Cx preserve their value, 6183 * add an extra tag action for NIC-RX and E-Switch Domain. 6184 */ 6185 if (add_tag) { 6186 /* Prepare the prefix tag action. */ 6187 append_index++; 6188 set_tag = (void *)(actions_pre + actions_n + append_index); 6189 ret = mlx5_flow_get_reg_id(dev, MLX5_SAMPLE_ID, 0, error); 6190 /* Trust VF/SF on CX5 not supported meter so that the reserved 6191 * metadata regC is REG_NON, back to use application tag 6192 * index 0. 6193 */ 6194 if (unlikely(ret == REG_NON)) 6195 ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, 0, error); 6196 if (ret < 0) 6197 return ret; 6198 mlx5_ipool_malloc(priv->sh->ipool 6199 [MLX5_IPOOL_RSS_EXPANTION_FLOW_ID], &tag_id); 6200 *set_tag = (struct mlx5_rte_flow_action_set_tag) { 6201 .id = ret, 6202 .data = tag_id, 6203 }; 6204 /* Prepare the suffix subflow items. */ 6205 tag_spec = (void *)(sfx_items + SAMPLE_SUFFIX_ITEM); 6206 tag_spec->data = tag_id; 6207 tag_spec->id = set_tag->id; 6208 tag_mask = tag_spec + 1; 6209 tag_mask->data = UINT32_MAX; 6210 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) { 6211 if (items->type == RTE_FLOW_ITEM_TYPE_PORT_ID || 6212 items->type == RTE_FLOW_ITEM_TYPE_PORT_REPRESENTOR || 6213 items->type == RTE_FLOW_ITEM_TYPE_REPRESENTED_PORT) { 6214 memcpy(sfx_items, items, sizeof(*sfx_items)); 6215 sfx_items++; 6216 break; 6217 } 6218 } 6219 sfx_items[0] = (struct rte_flow_item){ 6220 .type = (enum rte_flow_item_type) 6221 MLX5_RTE_FLOW_ITEM_TYPE_TAG, 6222 .spec = tag_spec, 6223 .last = NULL, 6224 .mask = tag_mask, 6225 }; 6226 sfx_items[1] = (struct rte_flow_item){ 6227 .type = (enum rte_flow_item_type) 6228 RTE_FLOW_ITEM_TYPE_END, 6229 }; 6230 /* Prepare the tag action in prefix subflow. */ 6231 set_tag_idx = (set_tag_idx == -1) ? index : set_tag_idx; 6232 actions_pre[set_tag_idx] = 6233 (struct rte_flow_action){ 6234 .type = (enum rte_flow_action_type) 6235 MLX5_RTE_FLOW_ACTION_TYPE_TAG, 6236 .conf = set_tag, 6237 }; 6238 /* Update next sample position due to add one tag action */ 6239 index += 1; 6240 } 6241 /* Copy the sample action into prefix flow. */ 6242 memcpy(actions_pre + index, actions + sample_action_pos, 6243 sizeof(struct rte_flow_action)); 6244 index += 1; 6245 /* For the modify action after the sample action in E-Switch mirroring, 6246 * Add the extra jump action in prefix subflow and jump into the next 6247 * table, then do the modify action in the new table. 6248 */ 6249 if (jump_table) { 6250 /* Prepare the prefix jump action. */ 6251 append_index++; 6252 jump_action = (void *)(actions_pre + actions_n + append_index); 6253 jump_action->group = jump_table; 6254 actions_pre[index++] = 6255 (struct rte_flow_action){ 6256 .type = (enum rte_flow_action_type) 6257 RTE_FLOW_ACTION_TYPE_JUMP, 6258 .conf = jump_action, 6259 }; 6260 } 6261 actions_pre[index] = (struct rte_flow_action){ 6262 .type = (enum rte_flow_action_type) 6263 RTE_FLOW_ACTION_TYPE_END, 6264 }; 6265 /* Put the actions after sample into Suffix flow. */ 6266 memcpy(actions_sfx, actions + sample_action_pos + 1, 6267 sizeof(struct rte_flow_action) * 6268 (actions_n - sample_action_pos - 1)); 6269 return tag_id; 6270 } 6271 6272 /** 6273 * The splitting for metadata feature. 6274 * 6275 * - Q/RSS action on NIC Rx should be split in order to pass by 6276 * the mreg copy table (RX_CP_TBL) and then it jumps to the 6277 * action table (RX_ACT_TBL) which has the split Q/RSS action. 6278 * 6279 * - All the actions on NIC Tx should have a mreg copy action to 6280 * copy reg_a from WQE to reg_c[0]. 6281 * 6282 * @param dev 6283 * Pointer to Ethernet device. 6284 * @param[in] flow 6285 * Parent flow structure pointer. 6286 * @param[in] attr 6287 * Flow rule attributes. 6288 * @param[in] items 6289 * Pattern specification (list terminated by the END pattern item). 6290 * @param[in] actions 6291 * Associated actions (list terminated by the END action). 6292 * @param[in] flow_split_info 6293 * Pointer to flow split info structure. 6294 * @param[out] error 6295 * Perform verbose error reporting if not NULL. 6296 * @return 6297 * 0 on success, negative value otherwise 6298 */ 6299 static int 6300 flow_create_split_metadata(struct rte_eth_dev *dev, 6301 struct rte_flow *flow, 6302 const struct rte_flow_attr *attr, 6303 const struct rte_flow_item items[], 6304 const struct rte_flow_action actions[], 6305 struct mlx5_flow_split_info *flow_split_info, 6306 struct rte_flow_error *error) 6307 { 6308 struct mlx5_priv *priv = dev->data->dev_private; 6309 struct mlx5_sh_config *config = &priv->sh->config; 6310 const struct rte_flow_action *qrss = NULL; 6311 struct rte_flow_action *ext_actions = NULL; 6312 struct mlx5_flow *dev_flow = NULL; 6313 uint32_t qrss_id = 0; 6314 int mtr_sfx = 0; 6315 size_t act_size; 6316 int actions_n; 6317 int encap_idx; 6318 int ret; 6319 6320 /* Check whether extensive metadata feature is engaged. */ 6321 if (!config->dv_flow_en || 6322 config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY || 6323 !mlx5_flow_ext_mreg_supported(dev)) 6324 return flow_create_split_inner(dev, flow, NULL, attr, items, 6325 actions, flow_split_info, error); 6326 actions_n = flow_parse_metadata_split_actions_info(actions, &qrss, 6327 &encap_idx); 6328 if (qrss) { 6329 /* Exclude hairpin flows from splitting. */ 6330 if (qrss->type == RTE_FLOW_ACTION_TYPE_QUEUE) { 6331 const struct rte_flow_action_queue *queue; 6332 6333 queue = qrss->conf; 6334 if (mlx5_rxq_is_hairpin(dev, queue->index)) 6335 qrss = NULL; 6336 } else if (qrss->type == RTE_FLOW_ACTION_TYPE_RSS) { 6337 const struct rte_flow_action_rss *rss; 6338 6339 rss = qrss->conf; 6340 if (mlx5_rxq_is_hairpin(dev, rss->queue[0])) 6341 qrss = NULL; 6342 } 6343 } 6344 if (qrss) { 6345 /* Check if it is in meter suffix table. */ 6346 mtr_sfx = attr->group == 6347 ((attr->transfer && priv->fdb_def_rule) ? 6348 (MLX5_FLOW_TABLE_LEVEL_METER - 1) : 6349 MLX5_FLOW_TABLE_LEVEL_METER); 6350 /* 6351 * Q/RSS action on NIC Rx should be split in order to pass by 6352 * the mreg copy table (RX_CP_TBL) and then it jumps to the 6353 * action table (RX_ACT_TBL) which has the split Q/RSS action. 6354 */ 6355 act_size = sizeof(struct rte_flow_action) * (actions_n + 1) + 6356 sizeof(struct rte_flow_action_set_tag) + 6357 sizeof(struct rte_flow_action_jump); 6358 ext_actions = mlx5_malloc(MLX5_MEM_ZERO, act_size, 0, 6359 SOCKET_ID_ANY); 6360 if (!ext_actions) 6361 return rte_flow_error_set(error, ENOMEM, 6362 RTE_FLOW_ERROR_TYPE_ACTION, 6363 NULL, "no memory to split " 6364 "metadata flow"); 6365 /* 6366 * Create the new actions list with removed Q/RSS action 6367 * and appended set tag and jump to register copy table 6368 * (RX_CP_TBL). We should preallocate unique tag ID here 6369 * in advance, because it is needed for set tag action. 6370 */ 6371 qrss_id = flow_mreg_split_qrss_prep(dev, ext_actions, actions, 6372 qrss, actions_n, 6373 mtr_sfx, error); 6374 if (!mtr_sfx && !qrss_id) { 6375 ret = -rte_errno; 6376 goto exit; 6377 } 6378 } else if (attr->egress) { 6379 /* 6380 * All the actions on NIC Tx should have a metadata register 6381 * copy action to copy reg_a from WQE to reg_c[meta] 6382 */ 6383 act_size = sizeof(struct rte_flow_action) * (actions_n + 1) + 6384 sizeof(struct mlx5_flow_action_copy_mreg); 6385 ext_actions = mlx5_malloc(MLX5_MEM_ZERO, act_size, 0, 6386 SOCKET_ID_ANY); 6387 if (!ext_actions) 6388 return rte_flow_error_set(error, ENOMEM, 6389 RTE_FLOW_ERROR_TYPE_ACTION, 6390 NULL, "no memory to split " 6391 "metadata flow"); 6392 /* Create the action list appended with copy register. */ 6393 ret = flow_mreg_tx_copy_prep(dev, ext_actions, actions, 6394 actions_n, error, encap_idx); 6395 if (ret < 0) 6396 goto exit; 6397 } 6398 /* Add the unmodified original or prefix subflow. */ 6399 ret = flow_create_split_inner(dev, flow, &dev_flow, attr, 6400 items, ext_actions ? ext_actions : 6401 actions, flow_split_info, error); 6402 if (ret < 0) 6403 goto exit; 6404 MLX5_ASSERT(dev_flow); 6405 if (qrss) { 6406 const struct rte_flow_attr q_attr = { 6407 .group = MLX5_FLOW_MREG_ACT_TABLE_GROUP, 6408 .ingress = 1, 6409 }; 6410 /* Internal PMD action to set register. */ 6411 struct mlx5_rte_flow_item_tag q_tag_spec = { 6412 .data = qrss_id, 6413 .id = REG_NON, 6414 }; 6415 struct rte_flow_item q_items[] = { 6416 { 6417 .type = (enum rte_flow_item_type) 6418 MLX5_RTE_FLOW_ITEM_TYPE_TAG, 6419 .spec = &q_tag_spec, 6420 .last = NULL, 6421 .mask = NULL, 6422 }, 6423 { 6424 .type = RTE_FLOW_ITEM_TYPE_END, 6425 }, 6426 }; 6427 struct rte_flow_action q_actions[] = { 6428 { 6429 .type = qrss->type, 6430 .conf = qrss->conf, 6431 }, 6432 { 6433 .type = RTE_FLOW_ACTION_TYPE_END, 6434 }, 6435 }; 6436 uint64_t layers = flow_get_prefix_layer_flags(dev_flow); 6437 6438 /* 6439 * Configure the tag item only if there is no meter subflow. 6440 * Since tag is already marked in the meter suffix subflow 6441 * we can just use the meter suffix items as is. 6442 */ 6443 if (qrss_id) { 6444 /* Not meter subflow. */ 6445 MLX5_ASSERT(!mtr_sfx); 6446 /* 6447 * Put unique id in prefix flow due to it is destroyed 6448 * after suffix flow and id will be freed after there 6449 * is no actual flows with this id and identifier 6450 * reallocation becomes possible (for example, for 6451 * other flows in other threads). 6452 */ 6453 dev_flow->handle->split_flow_id = qrss_id; 6454 ret = mlx5_flow_get_reg_id(dev, MLX5_COPY_MARK, 0, 6455 error); 6456 if (ret < 0) 6457 goto exit; 6458 q_tag_spec.id = ret; 6459 } 6460 dev_flow = NULL; 6461 /* Add suffix subflow to execute Q/RSS. */ 6462 flow_split_info->prefix_layers = layers; 6463 flow_split_info->prefix_mark = 0; 6464 flow_split_info->table_id = 0; 6465 ret = flow_create_split_inner(dev, flow, &dev_flow, 6466 &q_attr, mtr_sfx ? items : 6467 q_items, q_actions, 6468 flow_split_info, error); 6469 if (ret < 0) 6470 goto exit; 6471 /* qrss ID should be freed if failed. */ 6472 qrss_id = 0; 6473 MLX5_ASSERT(dev_flow); 6474 } 6475 6476 exit: 6477 /* 6478 * We do not destroy the partially created sub_flows in case of error. 6479 * These ones are included into parent flow list and will be destroyed 6480 * by flow_drv_destroy. 6481 */ 6482 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_RSS_EXPANTION_FLOW_ID], 6483 qrss_id); 6484 mlx5_free(ext_actions); 6485 return ret; 6486 } 6487 6488 /** 6489 * Create meter internal drop flow with the original pattern. 6490 * 6491 * @param dev 6492 * Pointer to Ethernet device. 6493 * @param[in] flow 6494 * Parent flow structure pointer. 6495 * @param[in] attr 6496 * Flow rule attributes. 6497 * @param[in] items 6498 * Pattern specification (list terminated by the END pattern item). 6499 * @param[in] flow_split_info 6500 * Pointer to flow split info structure. 6501 * @param[in] fm 6502 * Pointer to flow meter structure. 6503 * @param[out] error 6504 * Perform verbose error reporting if not NULL. 6505 * @return 6506 * 0 on success, negative value otherwise 6507 */ 6508 static uint32_t 6509 flow_meter_create_drop_flow_with_org_pattern(struct rte_eth_dev *dev, 6510 struct rte_flow *flow, 6511 const struct rte_flow_attr *attr, 6512 const struct rte_flow_item items[], 6513 struct mlx5_flow_split_info *flow_split_info, 6514 struct mlx5_flow_meter_info *fm, 6515 struct rte_flow_error *error) 6516 { 6517 struct mlx5_flow *dev_flow = NULL; 6518 struct rte_flow_attr drop_attr = *attr; 6519 struct rte_flow_action drop_actions[3]; 6520 struct mlx5_flow_split_info drop_split_info = *flow_split_info; 6521 6522 MLX5_ASSERT(fm->drop_cnt); 6523 drop_actions[0].type = 6524 (enum rte_flow_action_type)MLX5_RTE_FLOW_ACTION_TYPE_COUNT; 6525 drop_actions[0].conf = (void *)(uintptr_t)fm->drop_cnt; 6526 drop_actions[1].type = RTE_FLOW_ACTION_TYPE_DROP; 6527 drop_actions[1].conf = NULL; 6528 drop_actions[2].type = RTE_FLOW_ACTION_TYPE_END; 6529 drop_actions[2].conf = NULL; 6530 drop_split_info.external = false; 6531 drop_split_info.skip_scale |= 1 << MLX5_SCALE_FLOW_GROUP_BIT; 6532 drop_split_info.table_id = MLX5_MTR_TABLE_ID_DROP; 6533 drop_attr.group = MLX5_FLOW_TABLE_LEVEL_METER; 6534 return flow_create_split_inner(dev, flow, &dev_flow, 6535 &drop_attr, items, drop_actions, 6536 &drop_split_info, error); 6537 } 6538 6539 /** 6540 * The splitting for meter feature. 6541 * 6542 * - The meter flow will be split to two flows as prefix and 6543 * suffix flow. The packets make sense only it pass the prefix 6544 * meter action. 6545 * 6546 * - Reg_C_5 is used for the packet to match betweend prefix and 6547 * suffix flow. 6548 * 6549 * @param dev 6550 * Pointer to Ethernet device. 6551 * @param[in] flow 6552 * Parent flow structure pointer. 6553 * @param[in] attr 6554 * Flow rule attributes. 6555 * @param[in] items 6556 * Pattern specification (list terminated by the END pattern item). 6557 * @param[in] actions 6558 * Associated actions (list terminated by the END action). 6559 * @param[in] flow_split_info 6560 * Pointer to flow split info structure. 6561 * @param[out] error 6562 * Perform verbose error reporting if not NULL. 6563 * @return 6564 * 0 on success, negative value otherwise 6565 */ 6566 static int 6567 flow_create_split_meter(struct rte_eth_dev *dev, 6568 struct rte_flow *flow, 6569 const struct rte_flow_attr *attr, 6570 const struct rte_flow_item items[], 6571 const struct rte_flow_action actions[], 6572 struct mlx5_flow_split_info *flow_split_info, 6573 struct rte_flow_error *error) 6574 { 6575 struct mlx5_priv *priv = dev->data->dev_private; 6576 struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace(); 6577 struct rte_flow_action *sfx_actions = NULL; 6578 struct rte_flow_action *pre_actions = NULL; 6579 struct rte_flow_item *sfx_items = NULL; 6580 struct mlx5_flow *dev_flow = NULL; 6581 struct rte_flow_attr sfx_attr = *attr; 6582 struct mlx5_flow_meter_info *fm = NULL; 6583 uint8_t skip_scale_restore; 6584 bool has_mtr = false; 6585 bool has_modify = false; 6586 bool set_mtr_reg = true; 6587 bool is_mtr_hierarchy = false; 6588 uint32_t meter_id = 0; 6589 uint32_t mtr_idx = 0; 6590 uint32_t mtr_flow_id = 0; 6591 size_t act_size; 6592 size_t item_size; 6593 int actions_n = 0; 6594 int ret = 0; 6595 6596 if (priv->mtr_en) 6597 actions_n = flow_check_meter_action(dev, actions, &has_mtr, 6598 &has_modify, &meter_id); 6599 if (has_mtr) { 6600 if (flow->meter) { 6601 fm = flow_dv_meter_find_by_idx(priv, flow->meter); 6602 if (!fm) 6603 return rte_flow_error_set(error, EINVAL, 6604 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, 6605 NULL, "Meter not found."); 6606 } else { 6607 fm = mlx5_flow_meter_find(priv, meter_id, &mtr_idx); 6608 if (!fm) 6609 return rte_flow_error_set(error, EINVAL, 6610 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, 6611 NULL, "Meter not found."); 6612 ret = mlx5_flow_meter_attach(priv, fm, 6613 &sfx_attr, error); 6614 if (ret) 6615 return -rte_errno; 6616 flow->meter = mtr_idx; 6617 } 6618 MLX5_ASSERT(wks); 6619 wks->fm = fm; 6620 if (!fm->def_policy) { 6621 wks->policy = mlx5_flow_meter_policy_find(dev, 6622 fm->policy_id, 6623 NULL); 6624 MLX5_ASSERT(wks->policy); 6625 if (wks->policy->mark) 6626 wks->mark = 1; 6627 if (wks->policy->is_hierarchy) { 6628 wks->final_policy = 6629 mlx5_flow_meter_hierarchy_get_final_policy(dev, 6630 wks->policy); 6631 if (!wks->final_policy) 6632 return rte_flow_error_set(error, 6633 EINVAL, 6634 RTE_FLOW_ERROR_TYPE_ACTION, NULL, 6635 "Failed to find terminal policy of hierarchy."); 6636 is_mtr_hierarchy = true; 6637 } 6638 } 6639 /* 6640 * If it isn't default-policy Meter, and 6641 * 1. Not meter hierarchy and there's no action in flow to change 6642 * packet (modify/encap/decap etc.), OR 6643 * 2. No drop count needed for this meter. 6644 * Then no need to use regC to save meter id anymore. 6645 */ 6646 if (!fm->def_policy && ((!has_modify && !is_mtr_hierarchy) || !fm->drop_cnt)) 6647 set_mtr_reg = false; 6648 /* Prefix actions: meter, decap, encap, tag, jump, end, cnt. */ 6649 #define METER_PREFIX_ACTION 7 6650 act_size = (sizeof(struct rte_flow_action) * 6651 (actions_n + METER_PREFIX_ACTION)) + 6652 sizeof(struct mlx5_rte_flow_action_set_tag); 6653 /* Suffix items: tag, vlan, port id, end. */ 6654 #define METER_SUFFIX_ITEM 4 6655 item_size = sizeof(struct rte_flow_item) * METER_SUFFIX_ITEM + 6656 sizeof(struct mlx5_rte_flow_item_tag) * 2; 6657 sfx_actions = mlx5_malloc(MLX5_MEM_ZERO, (act_size + item_size), 6658 0, SOCKET_ID_ANY); 6659 if (!sfx_actions) 6660 return rte_flow_error_set(error, ENOMEM, 6661 RTE_FLOW_ERROR_TYPE_ACTION, 6662 NULL, "no memory to split " 6663 "meter flow"); 6664 sfx_items = (struct rte_flow_item *)((char *)sfx_actions + 6665 act_size); 6666 /* There's no suffix flow for meter of non-default policy. */ 6667 if (!fm->def_policy) 6668 pre_actions = sfx_actions + 1; 6669 else 6670 pre_actions = sfx_actions + actions_n; 6671 ret = flow_meter_split_prep(dev, flow, wks, &sfx_attr, 6672 items, sfx_items, actions, 6673 sfx_actions, pre_actions, 6674 (set_mtr_reg ? &mtr_flow_id : NULL), 6675 error); 6676 if (ret) { 6677 ret = -rte_errno; 6678 goto exit; 6679 } 6680 /* Add the prefix subflow. */ 6681 skip_scale_restore = flow_split_info->skip_scale; 6682 flow_split_info->skip_scale |= 6683 1 << MLX5_SCALE_JUMP_FLOW_GROUP_BIT; 6684 ret = flow_create_split_inner(dev, flow, &dev_flow, 6685 attr, items, pre_actions, 6686 flow_split_info, error); 6687 flow_split_info->skip_scale = skip_scale_restore; 6688 if (ret) { 6689 if (mtr_flow_id) 6690 mlx5_ipool_free(fm->flow_ipool, mtr_flow_id); 6691 ret = -rte_errno; 6692 goto exit; 6693 } 6694 if (mtr_flow_id) { 6695 dev_flow->handle->split_flow_id = mtr_flow_id; 6696 dev_flow->handle->is_meter_flow_id = 1; 6697 } 6698 if (!fm->def_policy) { 6699 if (!set_mtr_reg && fm->drop_cnt) 6700 ret = 6701 flow_meter_create_drop_flow_with_org_pattern(dev, flow, 6702 &sfx_attr, items, 6703 flow_split_info, 6704 fm, error); 6705 goto exit; 6706 } 6707 /* Setting the sfx group atrr. */ 6708 sfx_attr.group = sfx_attr.transfer ? 6709 (MLX5_FLOW_TABLE_LEVEL_METER - 1) : 6710 MLX5_FLOW_TABLE_LEVEL_METER; 6711 flow_split_info->prefix_layers = 6712 flow_get_prefix_layer_flags(dev_flow); 6713 flow_split_info->prefix_mark |= wks->mark; 6714 flow_split_info->table_id = MLX5_MTR_TABLE_ID_SUFFIX; 6715 } 6716 /* Add the prefix subflow. */ 6717 ret = flow_create_split_metadata(dev, flow, 6718 &sfx_attr, sfx_items ? 6719 sfx_items : items, 6720 sfx_actions ? sfx_actions : actions, 6721 flow_split_info, error); 6722 exit: 6723 if (sfx_actions) 6724 mlx5_free(sfx_actions); 6725 return ret; 6726 } 6727 6728 /** 6729 * The splitting for sample feature. 6730 * 6731 * Once Sample action is detected in the action list, the flow actions should 6732 * be split into prefix sub flow and suffix sub flow. 6733 * 6734 * The original items remain in the prefix sub flow, all actions preceding the 6735 * sample action and the sample action itself will be copied to the prefix 6736 * sub flow, the actions following the sample action will be copied to the 6737 * suffix sub flow, Queue action always be located in the suffix sub flow. 6738 * 6739 * In order to make the packet from prefix sub flow matches with suffix sub 6740 * flow, an extra tag action be added into prefix sub flow, and the suffix sub 6741 * flow uses tag item with the unique flow id. 6742 * 6743 * @param dev 6744 * Pointer to Ethernet device. 6745 * @param[in] flow 6746 * Parent flow structure pointer. 6747 * @param[in] attr 6748 * Flow rule attributes. 6749 * @param[in] items 6750 * Pattern specification (list terminated by the END pattern item). 6751 * @param[in] actions 6752 * Associated actions (list terminated by the END action). 6753 * @param[in] flow_split_info 6754 * Pointer to flow split info structure. 6755 * @param[out] error 6756 * Perform verbose error reporting if not NULL. 6757 * @return 6758 * 0 on success, negative value otherwise 6759 */ 6760 static int 6761 flow_create_split_sample(struct rte_eth_dev *dev, 6762 struct rte_flow *flow, 6763 const struct rte_flow_attr *attr, 6764 const struct rte_flow_item items[], 6765 const struct rte_flow_action actions[], 6766 struct mlx5_flow_split_info *flow_split_info, 6767 struct rte_flow_error *error) 6768 { 6769 struct mlx5_priv *priv = dev->data->dev_private; 6770 struct rte_flow_action *sfx_actions = NULL; 6771 struct rte_flow_action *pre_actions = NULL; 6772 struct rte_flow_item *sfx_items = NULL; 6773 struct mlx5_flow *dev_flow = NULL; 6774 struct rte_flow_attr sfx_attr = *attr; 6775 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 6776 struct mlx5_flow_dv_sample_resource *sample_res; 6777 struct mlx5_flow_tbl_data_entry *sfx_tbl_data; 6778 struct mlx5_flow_tbl_resource *sfx_tbl; 6779 struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace(); 6780 #endif 6781 size_t act_size; 6782 size_t item_size; 6783 uint32_t fdb_tx = 0; 6784 int32_t tag_id = 0; 6785 int actions_n = 0; 6786 int sample_action_pos; 6787 int qrss_action_pos; 6788 int add_tag = 0; 6789 int modify_after_mirror = 0; 6790 uint16_t jump_table = 0; 6791 const uint32_t next_ft_step = 1; 6792 int ret = 0; 6793 struct mlx5_priv *item_port_priv = NULL; 6794 const struct rte_flow_item *item; 6795 6796 if (priv->sampler_en) 6797 actions_n = flow_check_match_action(actions, attr, 6798 RTE_FLOW_ACTION_TYPE_SAMPLE, 6799 &sample_action_pos, &qrss_action_pos, 6800 &modify_after_mirror); 6801 if (actions_n) { 6802 /* The prefix actions must includes sample, tag, end. */ 6803 act_size = sizeof(struct rte_flow_action) * (actions_n * 2 + 1) 6804 + sizeof(struct mlx5_rte_flow_action_set_tag); 6805 item_size = sizeof(struct rte_flow_item) * SAMPLE_SUFFIX_ITEM + 6806 sizeof(struct mlx5_rte_flow_item_tag) * 2; 6807 sfx_actions = mlx5_malloc(MLX5_MEM_ZERO, (act_size + 6808 item_size), 0, SOCKET_ID_ANY); 6809 if (!sfx_actions) 6810 return rte_flow_error_set(error, ENOMEM, 6811 RTE_FLOW_ERROR_TYPE_ACTION, 6812 NULL, "no memory to split " 6813 "sample flow"); 6814 for (item = items; item->type != RTE_FLOW_ITEM_TYPE_END; item++) { 6815 if (item->type == RTE_FLOW_ITEM_TYPE_PORT_ID) { 6816 const struct rte_flow_item_port_id *spec; 6817 6818 spec = (const struct rte_flow_item_port_id *)item->spec; 6819 if (spec) 6820 item_port_priv = 6821 mlx5_port_to_eswitch_info(spec->id, true); 6822 break; 6823 } else if (item->type == RTE_FLOW_ITEM_TYPE_REPRESENTED_PORT) { 6824 const struct rte_flow_item_ethdev *spec; 6825 6826 spec = (const struct rte_flow_item_ethdev *)item->spec; 6827 if (spec) 6828 item_port_priv = 6829 mlx5_port_to_eswitch_info(spec->port_id, true); 6830 break; 6831 } else if (item->type == RTE_FLOW_ITEM_TYPE_PORT_REPRESENTOR) { 6832 const struct rte_flow_item_ethdev *spec; 6833 6834 spec = (const struct rte_flow_item_ethdev *)item->spec; 6835 if (spec) 6836 item_port_priv = 6837 mlx5_port_to_eswitch_info(spec->port_id, true); 6838 break; 6839 } 6840 } 6841 /* The representor_id is UINT16_MAX for uplink. */ 6842 fdb_tx = (attr->transfer && 6843 flow_source_vport_representor(priv, item_port_priv)); 6844 /* 6845 * When reg_c_preserve is set, metadata registers Cx preserve 6846 * their value even through packet duplication. 6847 */ 6848 add_tag = (!fdb_tx || 6849 priv->sh->cdev->config.hca_attr.reg_c_preserve); 6850 if (add_tag) 6851 sfx_items = (struct rte_flow_item *)((char *)sfx_actions 6852 + act_size); 6853 if (modify_after_mirror) 6854 jump_table = attr->group * MLX5_FLOW_TABLE_FACTOR + 6855 next_ft_step; 6856 pre_actions = sfx_actions + actions_n; 6857 tag_id = flow_sample_split_prep(dev, add_tag, items, sfx_items, 6858 actions, sfx_actions, 6859 pre_actions, actions_n, 6860 sample_action_pos, 6861 qrss_action_pos, jump_table, 6862 error); 6863 if (tag_id < 0 || (add_tag && !tag_id)) { 6864 ret = -rte_errno; 6865 goto exit; 6866 } 6867 if (modify_after_mirror) 6868 flow_split_info->skip_scale = 6869 1 << MLX5_SCALE_JUMP_FLOW_GROUP_BIT; 6870 /* Add the prefix subflow. */ 6871 ret = flow_create_split_inner(dev, flow, &dev_flow, attr, 6872 items, pre_actions, 6873 flow_split_info, error); 6874 if (ret) { 6875 ret = -rte_errno; 6876 goto exit; 6877 } 6878 dev_flow->handle->split_flow_id = tag_id; 6879 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 6880 if (!modify_after_mirror) { 6881 /* Set the sfx group attr. */ 6882 sample_res = (struct mlx5_flow_dv_sample_resource *) 6883 dev_flow->dv.sample_res; 6884 sfx_tbl = (struct mlx5_flow_tbl_resource *) 6885 sample_res->normal_path_tbl; 6886 sfx_tbl_data = container_of(sfx_tbl, 6887 struct mlx5_flow_tbl_data_entry, 6888 tbl); 6889 sfx_attr.group = sfx_attr.transfer ? 6890 (sfx_tbl_data->level - 1) : sfx_tbl_data->level; 6891 } else { 6892 MLX5_ASSERT(attr->transfer); 6893 sfx_attr.group = jump_table; 6894 } 6895 flow_split_info->prefix_layers = 6896 flow_get_prefix_layer_flags(dev_flow); 6897 MLX5_ASSERT(wks); 6898 flow_split_info->prefix_mark |= wks->mark; 6899 /* Suffix group level already be scaled with factor, set 6900 * MLX5_SCALE_FLOW_GROUP_BIT of skip_scale to 1 to avoid scale 6901 * again in translation. 6902 */ 6903 flow_split_info->skip_scale = 1 << MLX5_SCALE_FLOW_GROUP_BIT; 6904 #endif 6905 } 6906 /* Add the suffix subflow. */ 6907 ret = flow_create_split_meter(dev, flow, &sfx_attr, 6908 sfx_items ? sfx_items : items, 6909 sfx_actions ? sfx_actions : actions, 6910 flow_split_info, error); 6911 exit: 6912 if (sfx_actions) 6913 mlx5_free(sfx_actions); 6914 return ret; 6915 } 6916 6917 /** 6918 * Split the flow to subflow set. The splitters might be linked 6919 * in the chain, like this: 6920 * flow_create_split_outer() calls: 6921 * flow_create_split_meter() calls: 6922 * flow_create_split_metadata(meter_subflow_0) calls: 6923 * flow_create_split_inner(metadata_subflow_0) 6924 * flow_create_split_inner(metadata_subflow_1) 6925 * flow_create_split_inner(metadata_subflow_2) 6926 * flow_create_split_metadata(meter_subflow_1) calls: 6927 * flow_create_split_inner(metadata_subflow_0) 6928 * flow_create_split_inner(metadata_subflow_1) 6929 * flow_create_split_inner(metadata_subflow_2) 6930 * 6931 * This provide flexible way to add new levels of flow splitting. 6932 * The all of successfully created subflows are included to the 6933 * parent flow dev_flow list. 6934 * 6935 * @param dev 6936 * Pointer to Ethernet device. 6937 * @param[in] flow 6938 * Parent flow structure pointer. 6939 * @param[in] attr 6940 * Flow rule attributes. 6941 * @param[in] items 6942 * Pattern specification (list terminated by the END pattern item). 6943 * @param[in] actions 6944 * Associated actions (list terminated by the END action). 6945 * @param[in] flow_split_info 6946 * Pointer to flow split info structure. 6947 * @param[out] error 6948 * Perform verbose error reporting if not NULL. 6949 * @return 6950 * 0 on success, negative value otherwise 6951 */ 6952 static int 6953 flow_create_split_outer(struct rte_eth_dev *dev, 6954 struct rte_flow *flow, 6955 const struct rte_flow_attr *attr, 6956 const struct rte_flow_item items[], 6957 const struct rte_flow_action actions[], 6958 struct mlx5_flow_split_info *flow_split_info, 6959 struct rte_flow_error *error) 6960 { 6961 int ret; 6962 6963 ret = flow_create_split_sample(dev, flow, attr, items, 6964 actions, flow_split_info, error); 6965 MLX5_ASSERT(ret <= 0); 6966 return ret; 6967 } 6968 6969 static inline struct mlx5_flow_tunnel * 6970 flow_tunnel_from_rule(const struct mlx5_flow *flow) 6971 { 6972 struct mlx5_flow_tunnel *tunnel; 6973 6974 #pragma GCC diagnostic push 6975 #pragma GCC diagnostic ignored "-Wcast-qual" 6976 tunnel = (typeof(tunnel))flow->tunnel; 6977 #pragma GCC diagnostic pop 6978 6979 return tunnel; 6980 } 6981 6982 /** 6983 * Adjust flow RSS workspace if needed. 6984 * 6985 * @param wks 6986 * Pointer to thread flow work space. 6987 * @param rss_desc 6988 * Pointer to RSS descriptor. 6989 * @param[in] nrssq_num 6990 * New RSS queue number. 6991 * 6992 * @return 6993 * 0 on success, -1 otherwise and rte_errno is set. 6994 */ 6995 static int 6996 flow_rss_workspace_adjust(struct mlx5_flow_workspace *wks, 6997 struct mlx5_flow_rss_desc *rss_desc, 6998 uint32_t nrssq_num) 6999 { 7000 if (likely(nrssq_num <= wks->rssq_num)) 7001 return 0; 7002 rss_desc->queue = realloc(rss_desc->queue, 7003 sizeof(*rss_desc->queue) * RTE_ALIGN(nrssq_num, 2)); 7004 if (!rss_desc->queue) { 7005 rte_errno = ENOMEM; 7006 return -1; 7007 } 7008 wks->rssq_num = RTE_ALIGN(nrssq_num, 2); 7009 return 0; 7010 } 7011 7012 /** 7013 * Create a flow and add it to @p list. 7014 * 7015 * @param dev 7016 * Pointer to Ethernet device. 7017 * @param list 7018 * Pointer to a TAILQ flow list. If this parameter NULL, 7019 * no list insertion occurred, flow is just created, 7020 * this is caller's responsibility to track the 7021 * created flow. 7022 * @param[in] attr 7023 * Flow rule attributes. 7024 * @param[in] items 7025 * Pattern specification (list terminated by the END pattern item). 7026 * @param[in] actions 7027 * Associated actions (list terminated by the END action). 7028 * @param[in] external 7029 * This flow rule is created by request external to PMD. 7030 * @param[out] error 7031 * Perform verbose error reporting if not NULL. 7032 * 7033 * @return 7034 * A flow index on success, 0 otherwise and rte_errno is set. 7035 */ 7036 static uint32_t 7037 flow_list_create(struct rte_eth_dev *dev, enum mlx5_flow_type type, 7038 const struct rte_flow_attr *attr, 7039 const struct rte_flow_item items[], 7040 const struct rte_flow_action original_actions[], 7041 bool external, struct rte_flow_error *error) 7042 { 7043 struct mlx5_priv *priv = dev->data->dev_private; 7044 struct rte_flow *flow = NULL; 7045 struct mlx5_flow *dev_flow; 7046 const struct rte_flow_action_rss *rss = NULL; 7047 struct mlx5_translated_action_handle 7048 indir_actions[MLX5_MAX_INDIRECT_ACTIONS]; 7049 int indir_actions_n = MLX5_MAX_INDIRECT_ACTIONS; 7050 union { 7051 struct mlx5_flow_expand_rss buf; 7052 uint8_t buffer[8192]; 7053 } expand_buffer; 7054 union { 7055 struct rte_flow_action actions[MLX5_MAX_SPLIT_ACTIONS]; 7056 uint8_t buffer[2048]; 7057 } actions_rx; 7058 union { 7059 struct rte_flow_action actions[MLX5_MAX_SPLIT_ACTIONS]; 7060 uint8_t buffer[2048]; 7061 } actions_hairpin_tx; 7062 union { 7063 struct rte_flow_item items[MLX5_MAX_SPLIT_ITEMS]; 7064 uint8_t buffer[2048]; 7065 } items_tx; 7066 struct mlx5_rte_flow_item_sq sq_specs[RTE_MAX_QUEUES_PER_PORT]; 7067 struct mlx5_flow_expand_rss *buf = &expand_buffer.buf; 7068 struct mlx5_flow_rss_desc *rss_desc; 7069 const struct rte_flow_action *p_actions_rx; 7070 uint32_t i; 7071 uint32_t idx = 0; 7072 int hairpin_flow; 7073 struct rte_flow_attr attr_tx = { .priority = 0 }; 7074 const struct rte_flow_action *actions; 7075 struct rte_flow_action *translated_actions = NULL; 7076 struct mlx5_flow_tunnel *tunnel; 7077 struct tunnel_default_miss_ctx default_miss_ctx = { 0, }; 7078 struct mlx5_flow_workspace *wks = mlx5_flow_push_thread_workspace(); 7079 struct mlx5_flow_split_info flow_split_info = { 7080 .external = !!external, 7081 .skip_scale = 0, 7082 .flow_idx = 0, 7083 .prefix_mark = 0, 7084 .prefix_layers = 0, 7085 .table_id = 0 7086 }; 7087 int ret; 7088 7089 MLX5_ASSERT(wks); 7090 rss_desc = &wks->rss_desc; 7091 ret = flow_action_handles_translate(dev, original_actions, 7092 indir_actions, 7093 &indir_actions_n, 7094 &translated_actions, error); 7095 if (ret < 0) { 7096 MLX5_ASSERT(translated_actions == NULL); 7097 return 0; 7098 } 7099 actions = translated_actions ? translated_actions : original_actions; 7100 p_actions_rx = actions; 7101 hairpin_flow = flow_check_hairpin_split(dev, attr, actions); 7102 ret = flow_drv_validate(dev, attr, items, p_actions_rx, 7103 external, hairpin_flow, error); 7104 if (ret < 0) 7105 goto error_before_hairpin_split; 7106 flow = mlx5_ipool_zmalloc(priv->flows[type], &idx); 7107 if (!flow) { 7108 rte_errno = ENOMEM; 7109 goto error_before_hairpin_split; 7110 } 7111 if (hairpin_flow > 0) { 7112 if (hairpin_flow > MLX5_MAX_SPLIT_ACTIONS) { 7113 rte_errno = EINVAL; 7114 goto error_before_hairpin_split; 7115 } 7116 flow_hairpin_split(dev, actions, actions_rx.actions, 7117 actions_hairpin_tx.actions, items_tx.items, 7118 idx); 7119 p_actions_rx = actions_rx.actions; 7120 } 7121 flow_split_info.flow_idx = idx; 7122 flow->drv_type = flow_get_drv_type(dev, attr); 7123 MLX5_ASSERT(flow->drv_type > MLX5_FLOW_TYPE_MIN && 7124 flow->drv_type < MLX5_FLOW_TYPE_MAX); 7125 memset(rss_desc, 0, offsetof(struct mlx5_flow_rss_desc, queue)); 7126 /* RSS Action only works on NIC RX domain */ 7127 if (attr->ingress) 7128 rss = flow_get_rss_action(dev, p_actions_rx); 7129 if (rss) { 7130 if (flow_rss_workspace_adjust(wks, rss_desc, rss->queue_num)) 7131 return 0; 7132 /* 7133 * The following information is required by 7134 * mlx5_flow_hashfields_adjust() in advance. 7135 */ 7136 rss_desc->level = rss->level; 7137 /* RSS type 0 indicates default RSS type (RTE_ETH_RSS_IP). */ 7138 rss_desc->types = !rss->types ? RTE_ETH_RSS_IP : rss->types; 7139 } 7140 flow->dev_handles = 0; 7141 if (rss && rss->types) { 7142 unsigned int graph_root; 7143 7144 graph_root = find_graph_root(rss->level); 7145 ret = mlx5_flow_expand_rss(buf, sizeof(expand_buffer.buffer), 7146 items, rss->types, 7147 mlx5_support_expansion, graph_root); 7148 MLX5_ASSERT(ret > 0 && 7149 (unsigned int)ret < sizeof(expand_buffer.buffer)); 7150 if (rte_log_can_log(mlx5_logtype, RTE_LOG_DEBUG)) { 7151 for (i = 0; i < buf->entries; ++i) 7152 mlx5_dbg__print_pattern(buf->entry[i].pattern); 7153 } 7154 } else { 7155 ret = mlx5_flow_expand_sqn((struct mlx5_flow_expand_sqn *)buf, 7156 sizeof(expand_buffer.buffer), 7157 items, sq_specs); 7158 if (ret) { 7159 rte_flow_error_set(error, ENOMEM, RTE_FLOW_ERROR_TYPE_HANDLE, 7160 NULL, "not enough memory for rte_flow"); 7161 goto error; 7162 } 7163 if (buf->entries == 0) { 7164 buf->entries = 1; 7165 buf->entry[0].pattern = (void *)(uintptr_t)items; 7166 } 7167 } 7168 rss_desc->shared_rss = flow_get_shared_rss_action(dev, indir_actions, 7169 indir_actions_n); 7170 for (i = 0; i < buf->entries; ++i) { 7171 /* Initialize flow split data. */ 7172 flow_split_info.prefix_layers = 0; 7173 flow_split_info.prefix_mark = 0; 7174 flow_split_info.skip_scale = 0; 7175 /* 7176 * The splitter may create multiple dev_flows, 7177 * depending on configuration. In the simplest 7178 * case it just creates unmodified original flow. 7179 */ 7180 ret = flow_create_split_outer(dev, flow, attr, 7181 buf->entry[i].pattern, 7182 p_actions_rx, &flow_split_info, 7183 error); 7184 if (ret < 0) 7185 goto error; 7186 if (is_flow_tunnel_steer_rule(wks->flows[0].tof_type)) { 7187 ret = flow_tunnel_add_default_miss(dev, flow, attr, 7188 p_actions_rx, 7189 idx, 7190 wks->flows[0].tunnel, 7191 &default_miss_ctx, 7192 error); 7193 if (ret < 0) { 7194 mlx5_free(default_miss_ctx.queue); 7195 goto error; 7196 } 7197 } 7198 } 7199 /* Create the tx flow. */ 7200 if (hairpin_flow) { 7201 attr_tx.group = MLX5_HAIRPIN_TX_TABLE; 7202 attr_tx.ingress = 0; 7203 attr_tx.egress = 1; 7204 dev_flow = flow_drv_prepare(dev, flow, &attr_tx, items_tx.items, 7205 actions_hairpin_tx.actions, 7206 idx, error); 7207 if (!dev_flow) 7208 goto error; 7209 dev_flow->flow = flow; 7210 dev_flow->external = 0; 7211 SILIST_INSERT(&flow->dev_handles, dev_flow->handle_idx, 7212 dev_flow->handle, next); 7213 ret = flow_drv_translate(dev, dev_flow, &attr_tx, 7214 items_tx.items, 7215 actions_hairpin_tx.actions, error); 7216 if (ret < 0) 7217 goto error; 7218 } 7219 /* 7220 * Update the metadata register copy table. If extensive 7221 * metadata feature is enabled and registers are supported 7222 * we might create the extra rte_flow for each unique 7223 * MARK/FLAG action ID. 7224 * 7225 * The table is updated for ingress and transfer flows only, because 7226 * the egress Flows belong to the different device and 7227 * copy table should be updated in peer NIC Rx domain. 7228 */ 7229 if ((attr->ingress || attr->transfer) && 7230 (external || attr->group != MLX5_FLOW_MREG_CP_TABLE_GROUP)) { 7231 ret = flow_mreg_update_copy_table(dev, flow, actions, error); 7232 if (ret) 7233 goto error; 7234 } 7235 /* 7236 * If the flow is external (from application) OR device is started, 7237 * OR mreg discover, then apply immediately. 7238 */ 7239 if (external || dev->data->dev_started || 7240 (attr->group == MLX5_FLOW_MREG_CP_TABLE_GROUP && 7241 attr->priority == MLX5_FLOW_LOWEST_PRIO_INDICATOR)) { 7242 ret = flow_drv_apply(dev, flow, error); 7243 if (ret < 0) 7244 goto error; 7245 } 7246 flow->type = type; 7247 flow_rxq_flags_set(dev, flow); 7248 rte_free(translated_actions); 7249 tunnel = flow_tunnel_from_rule(wks->flows); 7250 if (tunnel) { 7251 flow->tunnel = 1; 7252 flow->tunnel_id = tunnel->tunnel_id; 7253 __atomic_add_fetch(&tunnel->refctn, 1, __ATOMIC_RELAXED); 7254 mlx5_free(default_miss_ctx.queue); 7255 } 7256 mlx5_flow_pop_thread_workspace(); 7257 return idx; 7258 error: 7259 MLX5_ASSERT(flow); 7260 ret = rte_errno; /* Save rte_errno before cleanup. */ 7261 flow_mreg_del_copy_action(dev, flow); 7262 flow_drv_destroy(dev, flow); 7263 if (rss_desc->shared_rss) 7264 __atomic_sub_fetch(&((struct mlx5_shared_action_rss *) 7265 mlx5_ipool_get 7266 (priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], 7267 rss_desc->shared_rss))->refcnt, 1, __ATOMIC_RELAXED); 7268 mlx5_ipool_free(priv->flows[type], idx); 7269 rte_errno = ret; /* Restore rte_errno. */ 7270 ret = rte_errno; 7271 rte_errno = ret; 7272 error_before_hairpin_split: 7273 mlx5_flow_pop_thread_workspace(); 7274 rte_free(translated_actions); 7275 return 0; 7276 } 7277 7278 /** 7279 * Create a dedicated flow rule on e-switch table 0 (root table), to direct all 7280 * incoming packets to table 1. 7281 * 7282 * Other flow rules, requested for group n, will be created in 7283 * e-switch table n+1. 7284 * Jump action to e-switch group n will be created to group n+1. 7285 * 7286 * Used when working in switchdev mode, to utilise advantages of table 1 7287 * and above. 7288 * 7289 * @param dev 7290 * Pointer to Ethernet device. 7291 * 7292 * @return 7293 * Pointer to flow on success, NULL otherwise and rte_errno is set. 7294 */ 7295 struct rte_flow * 7296 mlx5_flow_create_esw_table_zero_flow(struct rte_eth_dev *dev) 7297 { 7298 const struct rte_flow_attr attr = { 7299 .group = 0, 7300 .priority = 0, 7301 .ingress = 0, 7302 .egress = 0, 7303 .transfer = 1, 7304 }; 7305 const struct rte_flow_item pattern = { 7306 .type = RTE_FLOW_ITEM_TYPE_END, 7307 }; 7308 struct rte_flow_action_jump jump = { 7309 .group = 1, 7310 }; 7311 const struct rte_flow_action actions[] = { 7312 { 7313 .type = RTE_FLOW_ACTION_TYPE_JUMP, 7314 .conf = &jump, 7315 }, 7316 { 7317 .type = RTE_FLOW_ACTION_TYPE_END, 7318 }, 7319 }; 7320 struct rte_flow_error error; 7321 7322 return (void *)(uintptr_t)flow_list_create(dev, MLX5_FLOW_TYPE_CTL, 7323 &attr, &pattern, 7324 actions, false, &error); 7325 } 7326 7327 /** 7328 * Create a dedicated flow rule on e-switch table 1, matches ESW manager 7329 * and sq number, directs all packets to peer vport. 7330 * 7331 * @param dev 7332 * Pointer to Ethernet device. 7333 * @param sq_num 7334 * SQ number. 7335 * 7336 * @return 7337 * Flow ID on success, 0 otherwise and rte_errno is set. 7338 */ 7339 uint32_t 7340 mlx5_flow_create_devx_sq_miss_flow(struct rte_eth_dev *dev, uint32_t sq_num) 7341 { 7342 struct rte_flow_attr attr = { 7343 .group = 0, 7344 .priority = MLX5_FLOW_LOWEST_PRIO_INDICATOR, 7345 .ingress = 0, 7346 .egress = 0, 7347 .transfer = 1, 7348 }; 7349 struct rte_flow_item_port_id port_spec = { 7350 .id = MLX5_PORT_ESW_MGR, 7351 }; 7352 struct mlx5_rte_flow_item_sq sq_spec = { 7353 .queue = sq_num, 7354 }; 7355 struct rte_flow_item pattern[] = { 7356 { 7357 .type = RTE_FLOW_ITEM_TYPE_PORT_ID, 7358 .spec = &port_spec, 7359 }, 7360 { 7361 .type = (enum rte_flow_item_type) 7362 MLX5_RTE_FLOW_ITEM_TYPE_SQ, 7363 .spec = &sq_spec, 7364 }, 7365 { 7366 .type = RTE_FLOW_ITEM_TYPE_END, 7367 }, 7368 }; 7369 struct rte_flow_action_jump jump = { 7370 .group = 1, 7371 }; 7372 struct rte_flow_action_port_id port = { 7373 .id = dev->data->port_id, 7374 }; 7375 struct rte_flow_action actions[] = { 7376 { 7377 .type = RTE_FLOW_ACTION_TYPE_JUMP, 7378 .conf = &jump, 7379 }, 7380 { 7381 .type = RTE_FLOW_ACTION_TYPE_END, 7382 }, 7383 }; 7384 struct rte_flow_error error; 7385 7386 /* 7387 * Creates group 0, highest priority jump flow. 7388 * Matches txq to bypass kernel packets. 7389 */ 7390 if (flow_list_create(dev, MLX5_FLOW_TYPE_CTL, &attr, pattern, actions, 7391 false, &error) == 0) 7392 return 0; 7393 /* Create group 1, lowest priority redirect flow for txq. */ 7394 attr.group = 1; 7395 actions[0].conf = &port; 7396 actions[0].type = RTE_FLOW_ACTION_TYPE_PORT_ID; 7397 return flow_list_create(dev, MLX5_FLOW_TYPE_CTL, &attr, pattern, 7398 actions, false, &error); 7399 } 7400 7401 /** 7402 * Validate a flow supported by the NIC. 7403 * 7404 * @see rte_flow_validate() 7405 * @see rte_flow_ops 7406 */ 7407 int 7408 mlx5_flow_validate(struct rte_eth_dev *dev, 7409 const struct rte_flow_attr *attr, 7410 const struct rte_flow_item items[], 7411 const struct rte_flow_action original_actions[], 7412 struct rte_flow_error *error) 7413 { 7414 int hairpin_flow; 7415 struct mlx5_translated_action_handle 7416 indir_actions[MLX5_MAX_INDIRECT_ACTIONS]; 7417 int indir_actions_n = MLX5_MAX_INDIRECT_ACTIONS; 7418 const struct rte_flow_action *actions; 7419 struct rte_flow_action *translated_actions = NULL; 7420 int ret = flow_action_handles_translate(dev, original_actions, 7421 indir_actions, 7422 &indir_actions_n, 7423 &translated_actions, error); 7424 7425 if (ret) 7426 return ret; 7427 actions = translated_actions ? translated_actions : original_actions; 7428 hairpin_flow = flow_check_hairpin_split(dev, attr, actions); 7429 ret = flow_drv_validate(dev, attr, items, actions, 7430 true, hairpin_flow, error); 7431 rte_free(translated_actions); 7432 return ret; 7433 } 7434 7435 /** 7436 * Create a flow. 7437 * 7438 * @see rte_flow_create() 7439 * @see rte_flow_ops 7440 */ 7441 struct rte_flow * 7442 mlx5_flow_create(struct rte_eth_dev *dev, 7443 const struct rte_flow_attr *attr, 7444 const struct rte_flow_item items[], 7445 const struct rte_flow_action actions[], 7446 struct rte_flow_error *error) 7447 { 7448 struct mlx5_priv *priv = dev->data->dev_private; 7449 7450 if (priv->sh->config.dv_flow_en == 2) { 7451 rte_flow_error_set(error, ENOTSUP, 7452 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, 7453 NULL, 7454 "Flow non-Q creation not supported"); 7455 return NULL; 7456 } 7457 /* 7458 * If the device is not started yet, it is not allowed to created a 7459 * flow from application. PMD default flows and traffic control flows 7460 * are not affected. 7461 */ 7462 if (unlikely(!dev->data->dev_started)) { 7463 DRV_LOG(DEBUG, "port %u is not started when " 7464 "inserting a flow", dev->data->port_id); 7465 rte_flow_error_set(error, ENODEV, 7466 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, 7467 NULL, 7468 "port not started"); 7469 return NULL; 7470 } 7471 7472 return (void *)(uintptr_t)flow_list_create(dev, MLX5_FLOW_TYPE_GEN, 7473 attr, items, actions, 7474 true, error); 7475 } 7476 7477 /** 7478 * Destroy a flow in a list. 7479 * 7480 * @param dev 7481 * Pointer to Ethernet device. 7482 * @param[in] flow_idx 7483 * Index of flow to destroy. 7484 */ 7485 static void 7486 flow_list_destroy(struct rte_eth_dev *dev, enum mlx5_flow_type type, 7487 uint32_t flow_idx) 7488 { 7489 struct mlx5_priv *priv = dev->data->dev_private; 7490 struct rte_flow *flow = mlx5_ipool_get(priv->flows[type], flow_idx); 7491 7492 if (!flow) 7493 return; 7494 MLX5_ASSERT(flow->type == type); 7495 /* 7496 * Update RX queue flags only if port is started, otherwise it is 7497 * already clean. 7498 */ 7499 if (dev->data->dev_started) 7500 flow_rxq_flags_trim(dev, flow); 7501 flow_drv_destroy(dev, flow); 7502 if (flow->tunnel) { 7503 struct mlx5_flow_tunnel *tunnel; 7504 7505 tunnel = mlx5_find_tunnel_id(dev, flow->tunnel_id); 7506 RTE_VERIFY(tunnel); 7507 if (!__atomic_sub_fetch(&tunnel->refctn, 1, __ATOMIC_RELAXED)) 7508 mlx5_flow_tunnel_free(dev, tunnel); 7509 } 7510 flow_mreg_del_copy_action(dev, flow); 7511 mlx5_ipool_free(priv->flows[type], flow_idx); 7512 } 7513 7514 /** 7515 * Destroy all flows. 7516 * 7517 * @param dev 7518 * Pointer to Ethernet device. 7519 * @param type 7520 * Flow type to be flushed. 7521 * @param active 7522 * If flushing is called actively. 7523 */ 7524 void 7525 mlx5_flow_list_flush(struct rte_eth_dev *dev, enum mlx5_flow_type type, 7526 bool active) 7527 { 7528 struct mlx5_priv *priv = dev->data->dev_private; 7529 uint32_t num_flushed = 0, fidx = 1; 7530 struct rte_flow *flow; 7531 7532 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 7533 if (priv->sh->config.dv_flow_en == 2 && 7534 type == MLX5_FLOW_TYPE_GEN) { 7535 flow_hw_q_flow_flush(dev, NULL); 7536 return; 7537 } 7538 #endif 7539 7540 MLX5_IPOOL_FOREACH(priv->flows[type], fidx, flow) { 7541 flow_list_destroy(dev, type, fidx); 7542 num_flushed++; 7543 } 7544 if (active) { 7545 DRV_LOG(INFO, "port %u: %u flows flushed before stopping", 7546 dev->data->port_id, num_flushed); 7547 } 7548 } 7549 7550 /** 7551 * Stop all default actions for flows. 7552 * 7553 * @param dev 7554 * Pointer to Ethernet device. 7555 */ 7556 void 7557 mlx5_flow_stop_default(struct rte_eth_dev *dev) 7558 { 7559 flow_mreg_del_default_copy_action(dev); 7560 flow_rxq_flags_clear(dev); 7561 } 7562 7563 /** 7564 * Set rxq flag. 7565 * 7566 * @param[in] dev 7567 * Pointer to the rte_eth_dev structure. 7568 * @param[in] enable 7569 * Flag to enable or not. 7570 */ 7571 void 7572 flow_hw_rxq_flag_set(struct rte_eth_dev *dev, bool enable) 7573 { 7574 struct mlx5_priv *priv = dev->data->dev_private; 7575 unsigned int i; 7576 7577 if ((!priv->mark_enabled && !enable) || 7578 (priv->mark_enabled && enable)) 7579 return; 7580 for (i = 0; i < priv->rxqs_n; ++i) { 7581 struct mlx5_rxq_ctrl *rxq_ctrl = mlx5_rxq_ctrl_get(dev, i); 7582 7583 /* With RXQ start/stop feature, RXQ might be stopped. */ 7584 if (!rxq_ctrl) 7585 continue; 7586 rxq_ctrl->rxq.mark = enable; 7587 } 7588 priv->mark_enabled = enable; 7589 } 7590 7591 /** 7592 * Start all default actions for flows. 7593 * 7594 * @param dev 7595 * Pointer to Ethernet device. 7596 * @return 7597 * 0 on success, a negative errno value otherwise and rte_errno is set. 7598 */ 7599 int 7600 mlx5_flow_start_default(struct rte_eth_dev *dev) 7601 { 7602 struct rte_flow_error error; 7603 7604 /* Make sure default copy action (reg_c[0] -> reg_b) is created. */ 7605 return flow_mreg_add_default_copy_action(dev, &error); 7606 } 7607 7608 /** 7609 * Release key of thread specific flow workspace data. 7610 */ 7611 void 7612 flow_release_workspace(void *data) 7613 { 7614 struct mlx5_flow_workspace *wks = data; 7615 struct mlx5_flow_workspace *next; 7616 7617 while (wks) { 7618 next = wks->next; 7619 free(wks->rss_desc.queue); 7620 free(wks); 7621 wks = next; 7622 } 7623 } 7624 7625 /** 7626 * Get thread specific current flow workspace. 7627 * 7628 * @return pointer to thread specific flow workspace data, NULL on error. 7629 */ 7630 struct mlx5_flow_workspace* 7631 mlx5_flow_get_thread_workspace(void) 7632 { 7633 struct mlx5_flow_workspace *data; 7634 7635 data = mlx5_flow_os_get_specific_workspace(); 7636 MLX5_ASSERT(data && data->inuse); 7637 if (!data || !data->inuse) 7638 DRV_LOG(ERR, "flow workspace not initialized."); 7639 return data; 7640 } 7641 7642 /** 7643 * Allocate and init new flow workspace. 7644 * 7645 * @return pointer to flow workspace data, NULL on error. 7646 */ 7647 static struct mlx5_flow_workspace* 7648 flow_alloc_thread_workspace(void) 7649 { 7650 struct mlx5_flow_workspace *data = calloc(1, sizeof(*data)); 7651 7652 if (!data) { 7653 DRV_LOG(ERR, "Failed to allocate flow workspace " 7654 "memory."); 7655 return NULL; 7656 } 7657 data->rss_desc.queue = calloc(1, 7658 sizeof(uint16_t) * MLX5_RSSQ_DEFAULT_NUM); 7659 if (!data->rss_desc.queue) 7660 goto err; 7661 data->rssq_num = MLX5_RSSQ_DEFAULT_NUM; 7662 return data; 7663 err: 7664 free(data->rss_desc.queue); 7665 free(data); 7666 return NULL; 7667 } 7668 7669 /** 7670 * Get new thread specific flow workspace. 7671 * 7672 * If current workspace inuse, create new one and set as current. 7673 * 7674 * @return pointer to thread specific flow workspace data, NULL on error. 7675 */ 7676 struct mlx5_flow_workspace* 7677 mlx5_flow_push_thread_workspace(void) 7678 { 7679 struct mlx5_flow_workspace *curr; 7680 struct mlx5_flow_workspace *data; 7681 7682 curr = mlx5_flow_os_get_specific_workspace(); 7683 if (!curr) { 7684 data = flow_alloc_thread_workspace(); 7685 if (!data) 7686 return NULL; 7687 } else if (!curr->inuse) { 7688 data = curr; 7689 } else if (curr->next) { 7690 data = curr->next; 7691 } else { 7692 data = flow_alloc_thread_workspace(); 7693 if (!data) 7694 return NULL; 7695 curr->next = data; 7696 data->prev = curr; 7697 } 7698 data->inuse = 1; 7699 data->flow_idx = 0; 7700 /* Set as current workspace */ 7701 if (mlx5_flow_os_set_specific_workspace(data)) 7702 DRV_LOG(ERR, "Failed to set flow workspace to thread."); 7703 return data; 7704 } 7705 7706 /** 7707 * Close current thread specific flow workspace. 7708 * 7709 * If previous workspace available, set it as current. 7710 * 7711 * @return pointer to thread specific flow workspace data, NULL on error. 7712 */ 7713 void 7714 mlx5_flow_pop_thread_workspace(void) 7715 { 7716 struct mlx5_flow_workspace *data = mlx5_flow_get_thread_workspace(); 7717 7718 if (!data) 7719 return; 7720 if (!data->inuse) { 7721 DRV_LOG(ERR, "Failed to close unused flow workspace."); 7722 return; 7723 } 7724 data->inuse = 0; 7725 if (!data->prev) 7726 return; 7727 if (mlx5_flow_os_set_specific_workspace(data->prev)) 7728 DRV_LOG(ERR, "Failed to set flow workspace to thread."); 7729 } 7730 7731 /** 7732 * Verify the flow list is empty 7733 * 7734 * @param dev 7735 * Pointer to Ethernet device. 7736 * 7737 * @return the number of flows not released. 7738 */ 7739 int 7740 mlx5_flow_verify(struct rte_eth_dev *dev __rte_unused) 7741 { 7742 struct mlx5_priv *priv = dev->data->dev_private; 7743 struct rte_flow *flow; 7744 uint32_t idx = 0; 7745 int ret = 0, i; 7746 7747 for (i = 0; i < MLX5_FLOW_TYPE_MAXI; i++) { 7748 MLX5_IPOOL_FOREACH(priv->flows[i], idx, flow) { 7749 DRV_LOG(DEBUG, "port %u flow %p still referenced", 7750 dev->data->port_id, (void *)flow); 7751 ret++; 7752 } 7753 } 7754 return ret; 7755 } 7756 7757 /** 7758 * Enable default hairpin egress flow. 7759 * 7760 * @param dev 7761 * Pointer to Ethernet device. 7762 * @param sq_num 7763 * The SQ hw number. 7764 * 7765 * @return 7766 * 0 on success, a negative errno value otherwise and rte_errno is set. 7767 */ 7768 int 7769 mlx5_ctrl_flow_source_queue(struct rte_eth_dev *dev, 7770 uint32_t sq_num) 7771 { 7772 const struct rte_flow_attr attr = { 7773 .egress = 1, 7774 .priority = 0, 7775 }; 7776 struct mlx5_rte_flow_item_sq queue_spec = { 7777 .queue = sq_num, 7778 }; 7779 struct mlx5_rte_flow_item_sq queue_mask = { 7780 .queue = UINT32_MAX, 7781 }; 7782 struct rte_flow_item items[] = { 7783 { 7784 .type = (enum rte_flow_item_type) 7785 MLX5_RTE_FLOW_ITEM_TYPE_SQ, 7786 .spec = &queue_spec, 7787 .last = NULL, 7788 .mask = &queue_mask, 7789 }, 7790 { 7791 .type = RTE_FLOW_ITEM_TYPE_END, 7792 }, 7793 }; 7794 struct rte_flow_action_jump jump = { 7795 .group = MLX5_HAIRPIN_TX_TABLE, 7796 }; 7797 struct rte_flow_action actions[2]; 7798 uint32_t flow_idx; 7799 struct rte_flow_error error; 7800 7801 actions[0].type = RTE_FLOW_ACTION_TYPE_JUMP; 7802 actions[0].conf = &jump; 7803 actions[1].type = RTE_FLOW_ACTION_TYPE_END; 7804 flow_idx = flow_list_create(dev, MLX5_FLOW_TYPE_CTL, 7805 &attr, items, actions, false, &error); 7806 if (!flow_idx) { 7807 DRV_LOG(DEBUG, 7808 "Failed to create ctrl flow: rte_errno(%d)," 7809 " type(%d), message(%s)", 7810 rte_errno, error.type, 7811 error.message ? error.message : " (no stated reason)"); 7812 return -rte_errno; 7813 } 7814 return 0; 7815 } 7816 7817 /** 7818 * Enable a control flow configured from the control plane. 7819 * 7820 * @param dev 7821 * Pointer to Ethernet device. 7822 * @param eth_spec 7823 * An Ethernet flow spec to apply. 7824 * @param eth_mask 7825 * An Ethernet flow mask to apply. 7826 * @param vlan_spec 7827 * A VLAN flow spec to apply. 7828 * @param vlan_mask 7829 * A VLAN flow mask to apply. 7830 * 7831 * @return 7832 * 0 on success, a negative errno value otherwise and rte_errno is set. 7833 */ 7834 int 7835 mlx5_ctrl_flow_vlan(struct rte_eth_dev *dev, 7836 struct rte_flow_item_eth *eth_spec, 7837 struct rte_flow_item_eth *eth_mask, 7838 struct rte_flow_item_vlan *vlan_spec, 7839 struct rte_flow_item_vlan *vlan_mask) 7840 { 7841 struct mlx5_priv *priv = dev->data->dev_private; 7842 const struct rte_flow_attr attr = { 7843 .ingress = 1, 7844 .priority = MLX5_FLOW_LOWEST_PRIO_INDICATOR, 7845 }; 7846 struct rte_flow_item items[] = { 7847 { 7848 .type = RTE_FLOW_ITEM_TYPE_ETH, 7849 .spec = eth_spec, 7850 .last = NULL, 7851 .mask = eth_mask, 7852 }, 7853 { 7854 .type = (vlan_spec) ? RTE_FLOW_ITEM_TYPE_VLAN : 7855 RTE_FLOW_ITEM_TYPE_END, 7856 .spec = vlan_spec, 7857 .last = NULL, 7858 .mask = vlan_mask, 7859 }, 7860 { 7861 .type = RTE_FLOW_ITEM_TYPE_END, 7862 }, 7863 }; 7864 uint16_t queue[priv->reta_idx_n]; 7865 struct rte_flow_action_rss action_rss = { 7866 .func = RTE_ETH_HASH_FUNCTION_DEFAULT, 7867 .level = 0, 7868 .types = priv->rss_conf.rss_hf, 7869 .key_len = priv->rss_conf.rss_key_len, 7870 .queue_num = priv->reta_idx_n, 7871 .key = priv->rss_conf.rss_key, 7872 .queue = queue, 7873 }; 7874 struct rte_flow_action actions[] = { 7875 { 7876 .type = RTE_FLOW_ACTION_TYPE_RSS, 7877 .conf = &action_rss, 7878 }, 7879 { 7880 .type = RTE_FLOW_ACTION_TYPE_END, 7881 }, 7882 }; 7883 uint32_t flow_idx; 7884 struct rte_flow_error error; 7885 unsigned int i; 7886 7887 if (!priv->reta_idx_n || !priv->rxqs_n) { 7888 return 0; 7889 } 7890 if (!(dev->data->dev_conf.rxmode.mq_mode & RTE_ETH_MQ_RX_RSS_FLAG)) 7891 action_rss.types = 0; 7892 for (i = 0; i != priv->reta_idx_n; ++i) 7893 queue[i] = (*priv->reta_idx)[i]; 7894 flow_idx = flow_list_create(dev, MLX5_FLOW_TYPE_CTL, 7895 &attr, items, actions, false, &error); 7896 if (!flow_idx) 7897 return -rte_errno; 7898 return 0; 7899 } 7900 7901 /** 7902 * Enable a flow control configured from the control plane. 7903 * 7904 * @param dev 7905 * Pointer to Ethernet device. 7906 * @param eth_spec 7907 * An Ethernet flow spec to apply. 7908 * @param eth_mask 7909 * An Ethernet flow mask to apply. 7910 * 7911 * @return 7912 * 0 on success, a negative errno value otherwise and rte_errno is set. 7913 */ 7914 int 7915 mlx5_ctrl_flow(struct rte_eth_dev *dev, 7916 struct rte_flow_item_eth *eth_spec, 7917 struct rte_flow_item_eth *eth_mask) 7918 { 7919 return mlx5_ctrl_flow_vlan(dev, eth_spec, eth_mask, NULL, NULL); 7920 } 7921 7922 /** 7923 * Create default miss flow rule matching lacp traffic 7924 * 7925 * @param dev 7926 * Pointer to Ethernet device. 7927 * @param eth_spec 7928 * An Ethernet flow spec to apply. 7929 * 7930 * @return 7931 * 0 on success, a negative errno value otherwise and rte_errno is set. 7932 */ 7933 int 7934 mlx5_flow_lacp_miss(struct rte_eth_dev *dev) 7935 { 7936 /* 7937 * The LACP matching is done by only using ether type since using 7938 * a multicast dst mac causes kernel to give low priority to this flow. 7939 */ 7940 static const struct rte_flow_item_eth lacp_spec = { 7941 .hdr.ether_type = RTE_BE16(0x8809), 7942 }; 7943 static const struct rte_flow_item_eth lacp_mask = { 7944 .hdr.ether_type = 0xffff, 7945 }; 7946 const struct rte_flow_attr attr = { 7947 .ingress = 1, 7948 }; 7949 struct rte_flow_item items[] = { 7950 { 7951 .type = RTE_FLOW_ITEM_TYPE_ETH, 7952 .spec = &lacp_spec, 7953 .mask = &lacp_mask, 7954 }, 7955 { 7956 .type = RTE_FLOW_ITEM_TYPE_END, 7957 }, 7958 }; 7959 struct rte_flow_action actions[] = { 7960 { 7961 .type = (enum rte_flow_action_type) 7962 MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS, 7963 }, 7964 { 7965 .type = RTE_FLOW_ACTION_TYPE_END, 7966 }, 7967 }; 7968 struct rte_flow_error error; 7969 uint32_t flow_idx = flow_list_create(dev, MLX5_FLOW_TYPE_CTL, 7970 &attr, items, actions, 7971 false, &error); 7972 7973 if (!flow_idx) 7974 return -rte_errno; 7975 return 0; 7976 } 7977 7978 /** 7979 * Destroy a flow. 7980 * 7981 * @see rte_flow_destroy() 7982 * @see rte_flow_ops 7983 */ 7984 int 7985 mlx5_flow_destroy(struct rte_eth_dev *dev, 7986 struct rte_flow *flow, 7987 struct rte_flow_error *error __rte_unused) 7988 { 7989 struct mlx5_priv *priv = dev->data->dev_private; 7990 7991 if (priv->sh->config.dv_flow_en == 2) 7992 return rte_flow_error_set(error, ENOTSUP, 7993 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, 7994 NULL, 7995 "Flow non-Q destruction not supported"); 7996 flow_list_destroy(dev, MLX5_FLOW_TYPE_GEN, 7997 (uintptr_t)(void *)flow); 7998 return 0; 7999 } 8000 8001 /** 8002 * Destroy all flows. 8003 * 8004 * @see rte_flow_flush() 8005 * @see rte_flow_ops 8006 */ 8007 int 8008 mlx5_flow_flush(struct rte_eth_dev *dev, 8009 struct rte_flow_error *error __rte_unused) 8010 { 8011 mlx5_flow_list_flush(dev, MLX5_FLOW_TYPE_GEN, false); 8012 return 0; 8013 } 8014 8015 /** 8016 * Isolated mode. 8017 * 8018 * @see rte_flow_isolate() 8019 * @see rte_flow_ops 8020 */ 8021 int 8022 mlx5_flow_isolate(struct rte_eth_dev *dev, 8023 int enable, 8024 struct rte_flow_error *error) 8025 { 8026 struct mlx5_priv *priv = dev->data->dev_private; 8027 8028 if (dev->data->dev_started) { 8029 rte_flow_error_set(error, EBUSY, 8030 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, 8031 NULL, 8032 "port must be stopped first"); 8033 return -rte_errno; 8034 } 8035 priv->isolated = !!enable; 8036 if (enable) 8037 dev->dev_ops = &mlx5_dev_ops_isolate; 8038 else 8039 dev->dev_ops = &mlx5_dev_ops; 8040 8041 dev->rx_descriptor_status = mlx5_rx_descriptor_status; 8042 dev->tx_descriptor_status = mlx5_tx_descriptor_status; 8043 8044 return 0; 8045 } 8046 8047 /** 8048 * Query a flow. 8049 * 8050 * @see rte_flow_query() 8051 * @see rte_flow_ops 8052 */ 8053 static int 8054 flow_drv_query(struct rte_eth_dev *dev, 8055 struct rte_flow *eflow, 8056 const struct rte_flow_action *actions, 8057 void *data, 8058 struct rte_flow_error *error) 8059 { 8060 struct mlx5_priv *priv = dev->data->dev_private; 8061 const struct mlx5_flow_driver_ops *fops; 8062 struct rte_flow *flow = NULL; 8063 enum mlx5_flow_drv_type ftype = MLX5_FLOW_TYPE_MIN; 8064 8065 if (priv->sh->config.dv_flow_en == 2) { 8066 #ifdef HAVE_MLX5_HWS_SUPPORT 8067 flow = eflow; 8068 ftype = MLX5_FLOW_TYPE_HW; 8069 #endif 8070 } else { 8071 flow = (struct rte_flow *)mlx5_ipool_get(priv->flows[MLX5_FLOW_TYPE_GEN], 8072 (uintptr_t)(void *)eflow); 8073 } 8074 if (!flow) { 8075 return rte_flow_error_set(error, ENOENT, 8076 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, 8077 NULL, 8078 "invalid flow handle"); 8079 } 8080 if (ftype == MLX5_FLOW_TYPE_MIN) 8081 ftype = flow->drv_type; 8082 MLX5_ASSERT(ftype > MLX5_FLOW_TYPE_MIN && ftype < MLX5_FLOW_TYPE_MAX); 8083 fops = flow_get_drv_ops(ftype); 8084 8085 return fops->query(dev, flow, actions, data, error); 8086 } 8087 8088 /** 8089 * Query a flow. 8090 * 8091 * @see rte_flow_query() 8092 * @see rte_flow_ops 8093 */ 8094 int 8095 mlx5_flow_query(struct rte_eth_dev *dev, 8096 struct rte_flow *flow, 8097 const struct rte_flow_action *actions, 8098 void *data, 8099 struct rte_flow_error *error) 8100 { 8101 int ret; 8102 8103 ret = flow_drv_query(dev, flow, actions, data, 8104 error); 8105 if (ret < 0) 8106 return ret; 8107 return 0; 8108 } 8109 8110 /** 8111 * Get rte_flow callbacks. 8112 * 8113 * @param dev 8114 * Pointer to Ethernet device structure. 8115 * @param ops 8116 * Pointer to operation-specific structure. 8117 * 8118 * @return 0 8119 */ 8120 int 8121 mlx5_flow_ops_get(struct rte_eth_dev *dev __rte_unused, 8122 const struct rte_flow_ops **ops) 8123 { 8124 *ops = &mlx5_flow_ops; 8125 return 0; 8126 } 8127 8128 /** 8129 * Validate meter policy actions. 8130 * Dispatcher for action type specific validation. 8131 * 8132 * @param[in] dev 8133 * Pointer to the Ethernet device structure. 8134 * @param[in] action 8135 * The meter policy action object to validate. 8136 * @param[in] attr 8137 * Attributes of flow to determine steering domain. 8138 * @param[out] is_rss 8139 * Is RSS or not. 8140 * @param[out] domain_bitmap 8141 * Domain bitmap. 8142 * @param[out] is_def_policy 8143 * Is default policy or not. 8144 * @param[out] error 8145 * Perform verbose error reporting if not NULL. Initialized in case of 8146 * error only. 8147 * 8148 * @return 8149 * 0 on success, otherwise negative errno value. 8150 */ 8151 int 8152 mlx5_flow_validate_mtr_acts(struct rte_eth_dev *dev, 8153 const struct rte_flow_action *actions[RTE_COLORS], 8154 struct rte_flow_attr *attr, 8155 bool *is_rss, 8156 uint8_t *domain_bitmap, 8157 uint8_t *policy_mode, 8158 struct rte_mtr_error *error) 8159 { 8160 const struct mlx5_flow_driver_ops *fops; 8161 8162 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_DV); 8163 return fops->validate_mtr_acts(dev, actions, attr, is_rss, 8164 domain_bitmap, policy_mode, error); 8165 } 8166 8167 /** 8168 * Destroy the meter table set. 8169 * 8170 * @param[in] dev 8171 * Pointer to Ethernet device. 8172 * @param[in] mtr_policy 8173 * Meter policy struct. 8174 */ 8175 void 8176 mlx5_flow_destroy_mtr_acts(struct rte_eth_dev *dev, 8177 struct mlx5_flow_meter_policy *mtr_policy) 8178 { 8179 const struct mlx5_flow_driver_ops *fops; 8180 8181 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_DV); 8182 fops->destroy_mtr_acts(dev, mtr_policy); 8183 } 8184 8185 /** 8186 * Create policy action, lock free, 8187 * (mutex should be acquired by caller). 8188 * Dispatcher for action type specific call. 8189 * 8190 * @param[in] dev 8191 * Pointer to the Ethernet device structure. 8192 * @param[in] mtr_policy 8193 * Meter policy struct. 8194 * @param[in] action 8195 * Action specification used to create meter actions. 8196 * @param[in] attr 8197 * Flow rule attributes. 8198 * @param[out] error 8199 * Perform verbose error reporting if not NULL. Initialized in case of 8200 * error only. 8201 * 8202 * @return 8203 * 0 on success, otherwise negative errno value. 8204 */ 8205 int 8206 mlx5_flow_create_mtr_acts(struct rte_eth_dev *dev, 8207 struct mlx5_flow_meter_policy *mtr_policy, 8208 const struct rte_flow_action *actions[RTE_COLORS], 8209 struct rte_flow_attr *attr, 8210 struct rte_mtr_error *error) 8211 { 8212 const struct mlx5_flow_driver_ops *fops; 8213 8214 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_DV); 8215 return fops->create_mtr_acts(dev, mtr_policy, actions, attr, error); 8216 } 8217 8218 /** 8219 * Create policy rules, lock free, 8220 * (mutex should be acquired by caller). 8221 * Dispatcher for action type specific call. 8222 * 8223 * @param[in] dev 8224 * Pointer to the Ethernet device structure. 8225 * @param[in] mtr_policy 8226 * Meter policy struct. 8227 * 8228 * @return 8229 * 0 on success, -1 otherwise. 8230 */ 8231 int 8232 mlx5_flow_create_policy_rules(struct rte_eth_dev *dev, 8233 struct mlx5_flow_meter_policy *mtr_policy) 8234 { 8235 const struct mlx5_flow_driver_ops *fops; 8236 8237 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_DV); 8238 return fops->create_policy_rules(dev, mtr_policy); 8239 } 8240 8241 /** 8242 * Destroy policy rules, lock free, 8243 * (mutex should be acquired by caller). 8244 * Dispatcher for action type specific call. 8245 * 8246 * @param[in] dev 8247 * Pointer to the Ethernet device structure. 8248 * @param[in] mtr_policy 8249 * Meter policy struct. 8250 */ 8251 void 8252 mlx5_flow_destroy_policy_rules(struct rte_eth_dev *dev, 8253 struct mlx5_flow_meter_policy *mtr_policy) 8254 { 8255 const struct mlx5_flow_driver_ops *fops; 8256 8257 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_DV); 8258 fops->destroy_policy_rules(dev, mtr_policy); 8259 } 8260 8261 /** 8262 * Destroy the default policy table set. 8263 * 8264 * @param[in] dev 8265 * Pointer to Ethernet device. 8266 */ 8267 void 8268 mlx5_flow_destroy_def_policy(struct rte_eth_dev *dev) 8269 { 8270 const struct mlx5_flow_driver_ops *fops; 8271 8272 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_DV); 8273 fops->destroy_def_policy(dev); 8274 } 8275 8276 /** 8277 * Destroy the default policy table set. 8278 * 8279 * @param[in] dev 8280 * Pointer to Ethernet device. 8281 * 8282 * @return 8283 * 0 on success, -1 otherwise. 8284 */ 8285 int 8286 mlx5_flow_create_def_policy(struct rte_eth_dev *dev) 8287 { 8288 const struct mlx5_flow_driver_ops *fops; 8289 8290 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_DV); 8291 return fops->create_def_policy(dev); 8292 } 8293 8294 /** 8295 * Create the needed meter and suffix tables. 8296 * 8297 * @param[in] dev 8298 * Pointer to Ethernet device. 8299 * 8300 * @return 8301 * 0 on success, -1 otherwise. 8302 */ 8303 int 8304 mlx5_flow_create_mtr_tbls(struct rte_eth_dev *dev, 8305 struct mlx5_flow_meter_info *fm, 8306 uint32_t mtr_idx, 8307 uint8_t domain_bitmap) 8308 { 8309 const struct mlx5_flow_driver_ops *fops; 8310 8311 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_DV); 8312 return fops->create_mtr_tbls(dev, fm, mtr_idx, domain_bitmap); 8313 } 8314 8315 /** 8316 * Destroy the meter table set. 8317 * 8318 * @param[in] dev 8319 * Pointer to Ethernet device. 8320 * @param[in] tbl 8321 * Pointer to the meter table set. 8322 */ 8323 void 8324 mlx5_flow_destroy_mtr_tbls(struct rte_eth_dev *dev, 8325 struct mlx5_flow_meter_info *fm) 8326 { 8327 const struct mlx5_flow_driver_ops *fops; 8328 8329 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_DV); 8330 fops->destroy_mtr_tbls(dev, fm); 8331 } 8332 8333 /** 8334 * Destroy the global meter drop table. 8335 * 8336 * @param[in] dev 8337 * Pointer to Ethernet device. 8338 */ 8339 void 8340 mlx5_flow_destroy_mtr_drop_tbls(struct rte_eth_dev *dev) 8341 { 8342 const struct mlx5_flow_driver_ops *fops; 8343 8344 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_DV); 8345 fops->destroy_mtr_drop_tbls(dev); 8346 } 8347 8348 /** 8349 * Destroy the sub policy table with RX queue. 8350 * 8351 * @param[in] dev 8352 * Pointer to Ethernet device. 8353 * @param[in] mtr_policy 8354 * Pointer to meter policy table. 8355 */ 8356 void 8357 mlx5_flow_destroy_sub_policy_with_rxq(struct rte_eth_dev *dev, 8358 struct mlx5_flow_meter_policy *mtr_policy) 8359 { 8360 const struct mlx5_flow_driver_ops *fops; 8361 8362 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_DV); 8363 fops->destroy_sub_policy_with_rxq(dev, mtr_policy); 8364 } 8365 8366 /** 8367 * Allocate the needed aso flow meter id. 8368 * 8369 * @param[in] dev 8370 * Pointer to Ethernet device. 8371 * 8372 * @return 8373 * Index to aso flow meter on success, NULL otherwise. 8374 */ 8375 uint32_t 8376 mlx5_flow_mtr_alloc(struct rte_eth_dev *dev) 8377 { 8378 const struct mlx5_flow_driver_ops *fops; 8379 8380 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_DV); 8381 return fops->create_meter(dev); 8382 } 8383 8384 /** 8385 * Free the aso flow meter id. 8386 * 8387 * @param[in] dev 8388 * Pointer to Ethernet device. 8389 * @param[in] mtr_idx 8390 * Index to aso flow meter to be free. 8391 * 8392 * @return 8393 * 0 on success. 8394 */ 8395 void 8396 mlx5_flow_mtr_free(struct rte_eth_dev *dev, uint32_t mtr_idx) 8397 { 8398 const struct mlx5_flow_driver_ops *fops; 8399 8400 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_DV); 8401 fops->free_meter(dev, mtr_idx); 8402 } 8403 8404 /** 8405 * Allocate a counter. 8406 * 8407 * @param[in] dev 8408 * Pointer to Ethernet device structure. 8409 * 8410 * @return 8411 * Index to allocated counter on success, 0 otherwise. 8412 */ 8413 uint32_t 8414 mlx5_counter_alloc(struct rte_eth_dev *dev) 8415 { 8416 const struct mlx5_flow_driver_ops *fops; 8417 struct rte_flow_attr attr = { .transfer = 0 }; 8418 8419 if (flow_get_drv_type(dev, &attr) == MLX5_FLOW_TYPE_DV) { 8420 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_DV); 8421 return fops->counter_alloc(dev); 8422 } 8423 DRV_LOG(ERR, 8424 "port %u counter allocate is not supported.", 8425 dev->data->port_id); 8426 return 0; 8427 } 8428 8429 /** 8430 * Free a counter. 8431 * 8432 * @param[in] dev 8433 * Pointer to Ethernet device structure. 8434 * @param[in] cnt 8435 * Index to counter to be free. 8436 */ 8437 void 8438 mlx5_counter_free(struct rte_eth_dev *dev, uint32_t cnt) 8439 { 8440 const struct mlx5_flow_driver_ops *fops; 8441 struct rte_flow_attr attr = { .transfer = 0 }; 8442 8443 if (flow_get_drv_type(dev, &attr) == MLX5_FLOW_TYPE_DV) { 8444 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_DV); 8445 fops->counter_free(dev, cnt); 8446 return; 8447 } 8448 DRV_LOG(ERR, 8449 "port %u counter free is not supported.", 8450 dev->data->port_id); 8451 } 8452 8453 /** 8454 * Query counter statistics. 8455 * 8456 * @param[in] dev 8457 * Pointer to Ethernet device structure. 8458 * @param[in] cnt 8459 * Index to counter to query. 8460 * @param[in] clear 8461 * Set to clear counter statistics. 8462 * @param[out] pkts 8463 * The counter hits packets number to save. 8464 * @param[out] bytes 8465 * The counter hits bytes number to save. 8466 * 8467 * @return 8468 * 0 on success, a negative errno value otherwise. 8469 */ 8470 int 8471 mlx5_counter_query(struct rte_eth_dev *dev, uint32_t cnt, 8472 bool clear, uint64_t *pkts, uint64_t *bytes, void **action) 8473 { 8474 const struct mlx5_flow_driver_ops *fops; 8475 struct rte_flow_attr attr = { .transfer = 0 }; 8476 8477 if (flow_get_drv_type(dev, &attr) == MLX5_FLOW_TYPE_DV) { 8478 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_DV); 8479 return fops->counter_query(dev, cnt, clear, pkts, 8480 bytes, action); 8481 } 8482 DRV_LOG(ERR, 8483 "port %u counter query is not supported.", 8484 dev->data->port_id); 8485 return -ENOTSUP; 8486 } 8487 8488 /** 8489 * Get information about HWS pre-configurable resources. 8490 * 8491 * @param[in] dev 8492 * Pointer to the rte_eth_dev structure. 8493 * @param[out] port_info 8494 * Pointer to port information. 8495 * @param[out] queue_info 8496 * Pointer to queue information. 8497 * @param[out] error 8498 * Pointer to error structure. 8499 * 8500 * @return 8501 * 0 on success, a negative errno value otherwise and rte_errno is set. 8502 */ 8503 static int 8504 mlx5_flow_info_get(struct rte_eth_dev *dev, 8505 struct rte_flow_port_info *port_info, 8506 struct rte_flow_queue_info *queue_info, 8507 struct rte_flow_error *error) 8508 { 8509 const struct mlx5_flow_driver_ops *fops; 8510 struct rte_flow_attr attr = {0}; 8511 8512 if (flow_get_drv_type(dev, &attr) != MLX5_FLOW_TYPE_HW) 8513 return rte_flow_error_set(error, ENOTSUP, 8514 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, 8515 NULL, 8516 "info get with incorrect steering mode"); 8517 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_HW); 8518 return fops->info_get(dev, port_info, queue_info, error); 8519 } 8520 8521 /** 8522 * Configure port HWS resources. 8523 * 8524 * @param[in] dev 8525 * Pointer to the rte_eth_dev structure. 8526 * @param[in] port_attr 8527 * Port configuration attributes. 8528 * @param[in] nb_queue 8529 * Number of queue. 8530 * @param[in] queue_attr 8531 * Array that holds attributes for each flow queue. 8532 * @param[out] error 8533 * Pointer to error structure. 8534 * 8535 * @return 8536 * 0 on success, a negative errno value otherwise and rte_errno is set. 8537 */ 8538 static int 8539 mlx5_flow_port_configure(struct rte_eth_dev *dev, 8540 const struct rte_flow_port_attr *port_attr, 8541 uint16_t nb_queue, 8542 const struct rte_flow_queue_attr *queue_attr[], 8543 struct rte_flow_error *error) 8544 { 8545 const struct mlx5_flow_driver_ops *fops; 8546 struct rte_flow_attr attr = {0}; 8547 8548 if (flow_get_drv_type(dev, &attr) != MLX5_FLOW_TYPE_HW) 8549 return rte_flow_error_set(error, ENOTSUP, 8550 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, 8551 NULL, 8552 "port configure with incorrect steering mode"); 8553 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_HW); 8554 return fops->configure(dev, port_attr, nb_queue, queue_attr, error); 8555 } 8556 8557 /** 8558 * Validate item template. 8559 * 8560 * @param[in] dev 8561 * Pointer to the rte_eth_dev structure. 8562 * @param[in] attr 8563 * Pointer to the item template attributes. 8564 * @param[in] items 8565 * The template item pattern. 8566 * @param[out] error 8567 * Pointer to error structure. 8568 * 8569 * @return 8570 * 0 on success, a negative errno value otherwise and rte_errno is set. 8571 */ 8572 int 8573 mlx5_flow_pattern_validate(struct rte_eth_dev *dev, 8574 const struct rte_flow_pattern_template_attr *attr, 8575 const struct rte_flow_item items[], 8576 struct rte_flow_error *error) 8577 { 8578 const struct mlx5_flow_driver_ops *fops; 8579 struct rte_flow_attr fattr = {0}; 8580 8581 if (flow_get_drv_type(dev, &fattr) != MLX5_FLOW_TYPE_HW) { 8582 rte_flow_error_set(error, ENOTSUP, 8583 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, 8584 "pattern validate with incorrect steering mode"); 8585 return -ENOTSUP; 8586 } 8587 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_HW); 8588 return fops->pattern_validate(dev, attr, items, error); 8589 } 8590 8591 /** 8592 * Create flow item template. 8593 * 8594 * @param[in] dev 8595 * Pointer to the rte_eth_dev structure. 8596 * @param[in] attr 8597 * Pointer to the item template attributes. 8598 * @param[in] items 8599 * The template item pattern. 8600 * @param[out] error 8601 * Pointer to error structure. 8602 * 8603 * @return 8604 * 0 on success, a negative errno value otherwise and rte_errno is set. 8605 */ 8606 static struct rte_flow_pattern_template * 8607 mlx5_flow_pattern_template_create(struct rte_eth_dev *dev, 8608 const struct rte_flow_pattern_template_attr *attr, 8609 const struct rte_flow_item items[], 8610 struct rte_flow_error *error) 8611 { 8612 const struct mlx5_flow_driver_ops *fops; 8613 struct rte_flow_attr fattr = {0}; 8614 8615 if (flow_get_drv_type(dev, &fattr) != MLX5_FLOW_TYPE_HW) { 8616 rte_flow_error_set(error, ENOTSUP, 8617 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, 8618 NULL, 8619 "pattern create with incorrect steering mode"); 8620 return NULL; 8621 } 8622 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_HW); 8623 return fops->pattern_template_create(dev, attr, items, error); 8624 } 8625 8626 /** 8627 * Destroy flow item template. 8628 * 8629 * @param[in] dev 8630 * Pointer to the rte_eth_dev structure. 8631 * @param[in] template 8632 * Pointer to the item template to be destroyed. 8633 * @param[out] error 8634 * Pointer to error structure. 8635 * 8636 * @return 8637 * 0 on success, a negative errno value otherwise and rte_errno is set. 8638 */ 8639 static int 8640 mlx5_flow_pattern_template_destroy(struct rte_eth_dev *dev, 8641 struct rte_flow_pattern_template *template, 8642 struct rte_flow_error *error) 8643 { 8644 const struct mlx5_flow_driver_ops *fops; 8645 struct rte_flow_attr attr = {0}; 8646 8647 if (flow_get_drv_type(dev, &attr) != MLX5_FLOW_TYPE_HW) 8648 return rte_flow_error_set(error, ENOTSUP, 8649 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, 8650 NULL, 8651 "pattern destroy with incorrect steering mode"); 8652 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_HW); 8653 return fops->pattern_template_destroy(dev, template, error); 8654 } 8655 8656 /** 8657 * Validate flow actions template. 8658 * 8659 * @param[in] dev 8660 * Pointer to the rte_eth_dev structure. 8661 * @param[in] attr 8662 * Pointer to the action template attributes. 8663 * @param[in] actions 8664 * Associated actions (list terminated by the END action). 8665 * @param[in] masks 8666 * List of actions that marks which of the action's member is constant. 8667 * @param[out] error 8668 * Pointer to error structure. 8669 * 8670 * @return 8671 * 0 on success, a negative errno value otherwise and rte_errno is set. 8672 */ 8673 int 8674 mlx5_flow_actions_validate(struct rte_eth_dev *dev, 8675 const struct rte_flow_actions_template_attr *attr, 8676 const struct rte_flow_action actions[], 8677 const struct rte_flow_action masks[], 8678 struct rte_flow_error *error) 8679 { 8680 const struct mlx5_flow_driver_ops *fops; 8681 struct rte_flow_attr fattr = {0}; 8682 8683 if (flow_get_drv_type(dev, &fattr) != MLX5_FLOW_TYPE_HW) { 8684 rte_flow_error_set(error, ENOTSUP, 8685 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, 8686 "actions validate with incorrect steering mode"); 8687 return -ENOTSUP; 8688 } 8689 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_HW); 8690 return fops->actions_validate(dev, attr, actions, masks, error); 8691 } 8692 8693 /** 8694 * Create flow item template. 8695 * 8696 * @param[in] dev 8697 * Pointer to the rte_eth_dev structure. 8698 * @param[in] attr 8699 * Pointer to the action template attributes. 8700 * @param[in] actions 8701 * Associated actions (list terminated by the END action). 8702 * @param[in] masks 8703 * List of actions that marks which of the action's member is constant. 8704 * @param[out] error 8705 * Pointer to error structure. 8706 * 8707 * @return 8708 * 0 on success, a negative errno value otherwise and rte_errno is set. 8709 */ 8710 static struct rte_flow_actions_template * 8711 mlx5_flow_actions_template_create(struct rte_eth_dev *dev, 8712 const struct rte_flow_actions_template_attr *attr, 8713 const struct rte_flow_action actions[], 8714 const struct rte_flow_action masks[], 8715 struct rte_flow_error *error) 8716 { 8717 const struct mlx5_flow_driver_ops *fops; 8718 struct rte_flow_attr fattr = {0}; 8719 8720 if (flow_get_drv_type(dev, &fattr) != MLX5_FLOW_TYPE_HW) { 8721 rte_flow_error_set(error, ENOTSUP, 8722 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, 8723 NULL, 8724 "action create with incorrect steering mode"); 8725 return NULL; 8726 } 8727 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_HW); 8728 return fops->actions_template_create(dev, attr, actions, masks, error); 8729 } 8730 8731 /** 8732 * Destroy flow action template. 8733 * 8734 * @param[in] dev 8735 * Pointer to the rte_eth_dev structure. 8736 * @param[in] template 8737 * Pointer to the action template to be destroyed. 8738 * @param[out] error 8739 * Pointer to error structure. 8740 * 8741 * @return 8742 * 0 on success, a negative errno value otherwise and rte_errno is set. 8743 */ 8744 static int 8745 mlx5_flow_actions_template_destroy(struct rte_eth_dev *dev, 8746 struct rte_flow_actions_template *template, 8747 struct rte_flow_error *error) 8748 { 8749 const struct mlx5_flow_driver_ops *fops; 8750 struct rte_flow_attr attr = {0}; 8751 8752 if (flow_get_drv_type(dev, &attr) != MLX5_FLOW_TYPE_HW) 8753 return rte_flow_error_set(error, ENOTSUP, 8754 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, 8755 NULL, 8756 "action destroy with incorrect steering mode"); 8757 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_HW); 8758 return fops->actions_template_destroy(dev, template, error); 8759 } 8760 8761 /** 8762 * Create flow table. 8763 * 8764 * @param[in] dev 8765 * Pointer to the rte_eth_dev structure. 8766 * @param[in] attr 8767 * Pointer to the table attributes. 8768 * @param[in] item_templates 8769 * Item template array to be binded to the table. 8770 * @param[in] nb_item_templates 8771 * Number of item template. 8772 * @param[in] action_templates 8773 * Action template array to be binded to the table. 8774 * @param[in] nb_action_templates 8775 * Number of action template. 8776 * @param[out] error 8777 * Pointer to error structure. 8778 * 8779 * @return 8780 * Table on success, NULL otherwise and rte_errno is set. 8781 */ 8782 static struct rte_flow_template_table * 8783 mlx5_flow_table_create(struct rte_eth_dev *dev, 8784 const struct rte_flow_template_table_attr *attr, 8785 struct rte_flow_pattern_template *item_templates[], 8786 uint8_t nb_item_templates, 8787 struct rte_flow_actions_template *action_templates[], 8788 uint8_t nb_action_templates, 8789 struct rte_flow_error *error) 8790 { 8791 const struct mlx5_flow_driver_ops *fops; 8792 struct rte_flow_attr fattr = {0}; 8793 8794 if (flow_get_drv_type(dev, &fattr) != MLX5_FLOW_TYPE_HW) { 8795 rte_flow_error_set(error, ENOTSUP, 8796 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, 8797 NULL, 8798 "table create with incorrect steering mode"); 8799 return NULL; 8800 } 8801 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_HW); 8802 return fops->template_table_create(dev, 8803 attr, 8804 item_templates, 8805 nb_item_templates, 8806 action_templates, 8807 nb_action_templates, 8808 error); 8809 } 8810 8811 /** 8812 * PMD destroy flow table. 8813 * 8814 * @param[in] dev 8815 * Pointer to the rte_eth_dev structure. 8816 * @param[in] table 8817 * Pointer to the table to be destroyed. 8818 * @param[out] error 8819 * Pointer to error structure. 8820 * 8821 * @return 8822 * 0 on success, a negative errno value otherwise and rte_errno is set. 8823 */ 8824 static int 8825 mlx5_flow_table_destroy(struct rte_eth_dev *dev, 8826 struct rte_flow_template_table *table, 8827 struct rte_flow_error *error) 8828 { 8829 const struct mlx5_flow_driver_ops *fops; 8830 struct rte_flow_attr attr = {0}; 8831 8832 if (flow_get_drv_type(dev, &attr) != MLX5_FLOW_TYPE_HW) 8833 return rte_flow_error_set(error, ENOTSUP, 8834 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, 8835 NULL, 8836 "table destroy with incorrect steering mode"); 8837 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_HW); 8838 return fops->template_table_destroy(dev, table, error); 8839 } 8840 8841 /** 8842 * Enqueue flow creation. 8843 * 8844 * @param[in] dev 8845 * Pointer to the rte_eth_dev structure. 8846 * @param[in] queue_id 8847 * The queue to create the flow. 8848 * @param[in] attr 8849 * Pointer to the flow operation attributes. 8850 * @param[in] items 8851 * Items with flow spec value. 8852 * @param[in] pattern_template_index 8853 * The item pattern flow follows from the table. 8854 * @param[in] actions 8855 * Action with flow spec value. 8856 * @param[in] action_template_index 8857 * The action pattern flow follows from the table. 8858 * @param[in] user_data 8859 * Pointer to the user_data. 8860 * @param[out] error 8861 * Pointer to error structure. 8862 * 8863 * @return 8864 * Flow pointer on success, NULL otherwise and rte_errno is set. 8865 */ 8866 static struct rte_flow * 8867 mlx5_flow_async_flow_create(struct rte_eth_dev *dev, 8868 uint32_t queue_id, 8869 const struct rte_flow_op_attr *attr, 8870 struct rte_flow_template_table *table, 8871 const struct rte_flow_item items[], 8872 uint8_t pattern_template_index, 8873 const struct rte_flow_action actions[], 8874 uint8_t action_template_index, 8875 void *user_data, 8876 struct rte_flow_error *error) 8877 { 8878 const struct mlx5_flow_driver_ops *fops; 8879 struct rte_flow_attr fattr = {0}; 8880 8881 if (flow_get_drv_type(dev, &fattr) != MLX5_FLOW_TYPE_HW) { 8882 rte_flow_error_set(error, ENOTSUP, 8883 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, 8884 NULL, 8885 "flow_q create with incorrect steering mode"); 8886 return NULL; 8887 } 8888 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_HW); 8889 return fops->async_flow_create(dev, queue_id, attr, table, 8890 items, pattern_template_index, 8891 actions, action_template_index, 8892 user_data, error); 8893 } 8894 8895 /** 8896 * Enqueue flow destruction. 8897 * 8898 * @param[in] dev 8899 * Pointer to the rte_eth_dev structure. 8900 * @param[in] queue 8901 * The queue to destroy the flow. 8902 * @param[in] attr 8903 * Pointer to the flow operation attributes. 8904 * @param[in] flow 8905 * Pointer to the flow to be destroyed. 8906 * @param[in] user_data 8907 * Pointer to the user_data. 8908 * @param[out] error 8909 * Pointer to error structure. 8910 * 8911 * @return 8912 * 0 on success, negative value otherwise and rte_errno is set. 8913 */ 8914 static int 8915 mlx5_flow_async_flow_destroy(struct rte_eth_dev *dev, 8916 uint32_t queue, 8917 const struct rte_flow_op_attr *attr, 8918 struct rte_flow *flow, 8919 void *user_data, 8920 struct rte_flow_error *error) 8921 { 8922 const struct mlx5_flow_driver_ops *fops; 8923 struct rte_flow_attr fattr = {0}; 8924 8925 if (flow_get_drv_type(dev, &fattr) != MLX5_FLOW_TYPE_HW) 8926 return rte_flow_error_set(error, ENOTSUP, 8927 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, 8928 NULL, 8929 "flow_q destroy with incorrect steering mode"); 8930 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_HW); 8931 return fops->async_flow_destroy(dev, queue, attr, flow, 8932 user_data, error); 8933 } 8934 8935 /** 8936 * Pull the enqueued flows. 8937 * 8938 * @param[in] dev 8939 * Pointer to the rte_eth_dev structure. 8940 * @param[in] queue 8941 * The queue to pull the result. 8942 * @param[in/out] res 8943 * Array to save the results. 8944 * @param[in] n_res 8945 * Available result with the array. 8946 * @param[out] error 8947 * Pointer to error structure. 8948 * 8949 * @return 8950 * Result number on success, negative value otherwise and rte_errno is set. 8951 */ 8952 static int 8953 mlx5_flow_pull(struct rte_eth_dev *dev, 8954 uint32_t queue, 8955 struct rte_flow_op_result res[], 8956 uint16_t n_res, 8957 struct rte_flow_error *error) 8958 { 8959 const struct mlx5_flow_driver_ops *fops; 8960 struct rte_flow_attr attr = {0}; 8961 8962 if (flow_get_drv_type(dev, &attr) != MLX5_FLOW_TYPE_HW) 8963 return rte_flow_error_set(error, ENOTSUP, 8964 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, 8965 NULL, 8966 "flow_q pull with incorrect steering mode"); 8967 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_HW); 8968 return fops->pull(dev, queue, res, n_res, error); 8969 } 8970 8971 /** 8972 * Push the enqueued flows. 8973 * 8974 * @param[in] dev 8975 * Pointer to the rte_eth_dev structure. 8976 * @param[in] queue 8977 * The queue to push the flows. 8978 * @param[out] error 8979 * Pointer to error structure. 8980 * 8981 * @return 8982 * 0 on success, negative value otherwise and rte_errno is set. 8983 */ 8984 static int 8985 mlx5_flow_push(struct rte_eth_dev *dev, 8986 uint32_t queue, 8987 struct rte_flow_error *error) 8988 { 8989 const struct mlx5_flow_driver_ops *fops; 8990 struct rte_flow_attr attr = {0}; 8991 8992 if (flow_get_drv_type(dev, &attr) != MLX5_FLOW_TYPE_HW) 8993 return rte_flow_error_set(error, ENOTSUP, 8994 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, 8995 NULL, 8996 "flow_q push with incorrect steering mode"); 8997 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_HW); 8998 return fops->push(dev, queue, error); 8999 } 9000 9001 /** 9002 * Create shared action. 9003 * 9004 * @param[in] dev 9005 * Pointer to the rte_eth_dev structure. 9006 * @param[in] queue 9007 * Which queue to be used.. 9008 * @param[in] attr 9009 * Operation attribute. 9010 * @param[in] conf 9011 * Indirect action configuration. 9012 * @param[in] action 9013 * rte_flow action detail. 9014 * @param[in] user_data 9015 * Pointer to the user_data. 9016 * @param[out] error 9017 * Pointer to error structure. 9018 * 9019 * @return 9020 * Action handle on success, NULL otherwise and rte_errno is set. 9021 */ 9022 static struct rte_flow_action_handle * 9023 mlx5_flow_async_action_handle_create(struct rte_eth_dev *dev, uint32_t queue, 9024 const struct rte_flow_op_attr *attr, 9025 const struct rte_flow_indir_action_conf *conf, 9026 const struct rte_flow_action *action, 9027 void *user_data, 9028 struct rte_flow_error *error) 9029 { 9030 const struct mlx5_flow_driver_ops *fops = 9031 flow_get_drv_ops(MLX5_FLOW_TYPE_HW); 9032 9033 return fops->async_action_create(dev, queue, attr, conf, action, 9034 user_data, error); 9035 } 9036 9037 /** 9038 * Update shared action. 9039 * 9040 * @param[in] dev 9041 * Pointer to the rte_eth_dev structure. 9042 * @param[in] queue 9043 * Which queue to be used.. 9044 * @param[in] attr 9045 * Operation attribute. 9046 * @param[in] handle 9047 * Action handle to be updated. 9048 * @param[in] update 9049 * Update value. 9050 * @param[in] user_data 9051 * Pointer to the user_data. 9052 * @param[out] error 9053 * Pointer to error structure. 9054 * 9055 * @return 9056 * 0 on success, negative value otherwise and rte_errno is set. 9057 */ 9058 static int 9059 mlx5_flow_async_action_handle_update(struct rte_eth_dev *dev, uint32_t queue, 9060 const struct rte_flow_op_attr *attr, 9061 struct rte_flow_action_handle *handle, 9062 const void *update, 9063 void *user_data, 9064 struct rte_flow_error *error) 9065 { 9066 const struct mlx5_flow_driver_ops *fops = 9067 flow_get_drv_ops(MLX5_FLOW_TYPE_HW); 9068 9069 return fops->async_action_update(dev, queue, attr, handle, 9070 update, user_data, error); 9071 } 9072 9073 /** 9074 * Query shared action. 9075 * 9076 * @param[in] dev 9077 * Pointer to the rte_eth_dev structure. 9078 * @param[in] queue 9079 * Which queue to be used.. 9080 * @param[in] attr 9081 * Operation attribute. 9082 * @param[in] handle 9083 * Action handle to be updated. 9084 * @param[in] data 9085 * Pointer query result data. 9086 * @param[in] user_data 9087 * Pointer to the user_data. 9088 * @param[out] error 9089 * Pointer to error structure. 9090 * 9091 * @return 9092 * 0 on success, negative value otherwise and rte_errno is set. 9093 */ 9094 static int 9095 mlx5_flow_async_action_handle_query(struct rte_eth_dev *dev, uint32_t queue, 9096 const struct rte_flow_op_attr *attr, 9097 const struct rte_flow_action_handle *handle, 9098 void *data, 9099 void *user_data, 9100 struct rte_flow_error *error) 9101 { 9102 const struct mlx5_flow_driver_ops *fops = 9103 flow_get_drv_ops(MLX5_FLOW_TYPE_HW); 9104 9105 return fops->async_action_query(dev, queue, attr, handle, 9106 data, user_data, error); 9107 } 9108 9109 /** 9110 * Destroy shared action. 9111 * 9112 * @param[in] dev 9113 * Pointer to the rte_eth_dev structure. 9114 * @param[in] queue 9115 * Which queue to be used.. 9116 * @param[in] attr 9117 * Operation attribute. 9118 * @param[in] handle 9119 * Action handle to be destroyed. 9120 * @param[in] user_data 9121 * Pointer to the user_data. 9122 * @param[out] error 9123 * Pointer to error structure. 9124 * 9125 * @return 9126 * 0 on success, negative value otherwise and rte_errno is set. 9127 */ 9128 static int 9129 mlx5_flow_async_action_handle_destroy(struct rte_eth_dev *dev, uint32_t queue, 9130 const struct rte_flow_op_attr *attr, 9131 struct rte_flow_action_handle *handle, 9132 void *user_data, 9133 struct rte_flow_error *error) 9134 { 9135 const struct mlx5_flow_driver_ops *fops = 9136 flow_get_drv_ops(MLX5_FLOW_TYPE_HW); 9137 9138 return fops->async_action_destroy(dev, queue, attr, handle, 9139 user_data, error); 9140 } 9141 9142 /** 9143 * Allocate a new memory for the counter values wrapped by all the needed 9144 * management. 9145 * 9146 * @param[in] sh 9147 * Pointer to mlx5_dev_ctx_shared object. 9148 * 9149 * @return 9150 * 0 on success, a negative errno value otherwise. 9151 */ 9152 static int 9153 mlx5_flow_create_counter_stat_mem_mng(struct mlx5_dev_ctx_shared *sh) 9154 { 9155 struct mlx5_counter_stats_mem_mng *mem_mng; 9156 volatile struct flow_counter_stats *raw_data; 9157 int raws_n = MLX5_CNT_MR_ALLOC_BULK + MLX5_MAX_PENDING_QUERIES; 9158 int size = (sizeof(struct flow_counter_stats) * 9159 MLX5_COUNTERS_PER_POOL + 9160 sizeof(struct mlx5_counter_stats_raw)) * raws_n + 9161 sizeof(struct mlx5_counter_stats_mem_mng); 9162 size_t pgsize = rte_mem_page_size(); 9163 uint8_t *mem; 9164 int ret; 9165 int i; 9166 9167 if (pgsize == (size_t)-1) { 9168 DRV_LOG(ERR, "Failed to get mem page size"); 9169 rte_errno = ENOMEM; 9170 return -ENOMEM; 9171 } 9172 mem = mlx5_malloc(MLX5_MEM_ZERO, size, pgsize, SOCKET_ID_ANY); 9173 if (!mem) { 9174 rte_errno = ENOMEM; 9175 return -ENOMEM; 9176 } 9177 mem_mng = (struct mlx5_counter_stats_mem_mng *)(mem + size) - 1; 9178 size = sizeof(*raw_data) * MLX5_COUNTERS_PER_POOL * raws_n; 9179 ret = mlx5_os_wrapped_mkey_create(sh->cdev->ctx, sh->cdev->pd, 9180 sh->cdev->pdn, mem, size, 9181 &mem_mng->wm); 9182 if (ret) { 9183 rte_errno = errno; 9184 mlx5_free(mem); 9185 return -rte_errno; 9186 } 9187 mem_mng->raws = (struct mlx5_counter_stats_raw *)(mem + size); 9188 raw_data = (volatile struct flow_counter_stats *)mem; 9189 for (i = 0; i < raws_n; ++i) { 9190 mem_mng->raws[i].mem_mng = mem_mng; 9191 mem_mng->raws[i].data = raw_data + i * MLX5_COUNTERS_PER_POOL; 9192 } 9193 for (i = 0; i < MLX5_MAX_PENDING_QUERIES; ++i) 9194 LIST_INSERT_HEAD(&sh->sws_cmng.free_stat_raws, 9195 mem_mng->raws + MLX5_CNT_MR_ALLOC_BULK + i, 9196 next); 9197 LIST_INSERT_HEAD(&sh->sws_cmng.mem_mngs, mem_mng, next); 9198 sh->sws_cmng.mem_mng = mem_mng; 9199 return 0; 9200 } 9201 9202 /** 9203 * Set the statistic memory to the new counter pool. 9204 * 9205 * @param[in] sh 9206 * Pointer to mlx5_dev_ctx_shared object. 9207 * @param[in] pool 9208 * Pointer to the pool to set the statistic memory. 9209 * 9210 * @return 9211 * 0 on success, a negative errno value otherwise. 9212 */ 9213 static int 9214 mlx5_flow_set_counter_stat_mem(struct mlx5_dev_ctx_shared *sh, 9215 struct mlx5_flow_counter_pool *pool) 9216 { 9217 struct mlx5_flow_counter_mng *cmng = &sh->sws_cmng; 9218 /* Resize statistic memory once used out. */ 9219 if (!(pool->index % MLX5_CNT_MR_ALLOC_BULK) && 9220 mlx5_flow_create_counter_stat_mem_mng(sh)) { 9221 DRV_LOG(ERR, "Cannot resize counter stat mem."); 9222 return -1; 9223 } 9224 rte_spinlock_lock(&pool->sl); 9225 pool->raw = cmng->mem_mng->raws + pool->index % MLX5_CNT_MR_ALLOC_BULK; 9226 rte_spinlock_unlock(&pool->sl); 9227 pool->raw_hw = NULL; 9228 return 0; 9229 } 9230 9231 #define MLX5_POOL_QUERY_FREQ_US 1000000 9232 9233 /** 9234 * Set the periodic procedure for triggering asynchronous batch queries for all 9235 * the counter pools. 9236 * 9237 * @param[in] sh 9238 * Pointer to mlx5_dev_ctx_shared object. 9239 */ 9240 void 9241 mlx5_set_query_alarm(struct mlx5_dev_ctx_shared *sh) 9242 { 9243 uint32_t pools_n, us; 9244 9245 pools_n = __atomic_load_n(&sh->sws_cmng.n_valid, __ATOMIC_RELAXED); 9246 us = MLX5_POOL_QUERY_FREQ_US / pools_n; 9247 DRV_LOG(DEBUG, "Set alarm for %u pools each %u us", pools_n, us); 9248 if (rte_eal_alarm_set(us, mlx5_flow_query_alarm, sh)) { 9249 sh->sws_cmng.query_thread_on = 0; 9250 DRV_LOG(ERR, "Cannot reinitialize query alarm"); 9251 } else { 9252 sh->sws_cmng.query_thread_on = 1; 9253 } 9254 } 9255 9256 /** 9257 * The periodic procedure for triggering asynchronous batch queries for all the 9258 * counter pools. This function is probably called by the host thread. 9259 * 9260 * @param[in] arg 9261 * The parameter for the alarm process. 9262 */ 9263 void 9264 mlx5_flow_query_alarm(void *arg) 9265 { 9266 struct mlx5_dev_ctx_shared *sh = arg; 9267 struct mlx5_flow_counter_mng *cmng = &sh->sws_cmng; 9268 uint16_t pool_index = cmng->pool_index; 9269 struct mlx5_flow_counter_pool *pool; 9270 uint16_t n_valid; 9271 int ret; 9272 9273 if (cmng->pending_queries >= MLX5_MAX_PENDING_QUERIES) 9274 goto set_alarm; 9275 rte_spinlock_lock(&cmng->pool_update_sl); 9276 pool = cmng->pools[pool_index]; 9277 n_valid = cmng->n_valid; 9278 rte_spinlock_unlock(&cmng->pool_update_sl); 9279 /* Set the statistic memory to the new created pool. */ 9280 if ((!pool->raw && mlx5_flow_set_counter_stat_mem(sh, pool))) 9281 goto set_alarm; 9282 if (pool->raw_hw) 9283 /* There is a pool query in progress. */ 9284 goto set_alarm; 9285 pool->raw_hw = LIST_FIRST(&cmng->free_stat_raws); 9286 if (!pool->raw_hw) 9287 /* No free counter statistics raw memory. */ 9288 goto set_alarm; 9289 /* 9290 * Identify the counters released between query trigger and query 9291 * handle more efficiently. The counter released in this gap period 9292 * should wait for a new round of query as the new arrived packets 9293 * will not be taken into account. 9294 */ 9295 pool->query_gen++; 9296 ret = mlx5_devx_cmd_flow_counter_query(pool->min_dcs, 0, 9297 MLX5_COUNTERS_PER_POOL, 9298 NULL, NULL, 9299 pool->raw_hw->mem_mng->wm.lkey, 9300 (void *)(uintptr_t) 9301 pool->raw_hw->data, 9302 sh->devx_comp, 9303 (uint64_t)(uintptr_t)pool); 9304 if (ret) { 9305 DRV_LOG(ERR, "Failed to trigger asynchronous query for dcs ID" 9306 " %d", pool->min_dcs->id); 9307 pool->raw_hw = NULL; 9308 goto set_alarm; 9309 } 9310 LIST_REMOVE(pool->raw_hw, next); 9311 cmng->pending_queries++; 9312 pool_index++; 9313 if (pool_index >= n_valid) 9314 pool_index = 0; 9315 set_alarm: 9316 cmng->pool_index = pool_index; 9317 mlx5_set_query_alarm(sh); 9318 } 9319 9320 /** 9321 * Check and callback event for new aged flow in the counter pool 9322 * 9323 * @param[in] sh 9324 * Pointer to mlx5_dev_ctx_shared object. 9325 * @param[in] pool 9326 * Pointer to Current counter pool. 9327 */ 9328 static void 9329 mlx5_flow_aging_check(struct mlx5_dev_ctx_shared *sh, 9330 struct mlx5_flow_counter_pool *pool) 9331 { 9332 struct mlx5_priv *priv; 9333 struct mlx5_flow_counter *cnt; 9334 struct mlx5_age_info *age_info; 9335 struct mlx5_age_param *age_param; 9336 struct mlx5_counter_stats_raw *cur = pool->raw_hw; 9337 struct mlx5_counter_stats_raw *prev = pool->raw; 9338 const uint64_t curr_time = MLX5_CURR_TIME_SEC; 9339 const uint32_t time_delta = curr_time - pool->time_of_last_age_check; 9340 uint16_t expected = AGE_CANDIDATE; 9341 uint32_t i; 9342 9343 pool->time_of_last_age_check = curr_time; 9344 for (i = 0; i < MLX5_COUNTERS_PER_POOL; ++i) { 9345 cnt = MLX5_POOL_GET_CNT(pool, i); 9346 age_param = MLX5_CNT_TO_AGE(cnt); 9347 if (__atomic_load_n(&age_param->state, 9348 __ATOMIC_RELAXED) != AGE_CANDIDATE) 9349 continue; 9350 if (cur->data[i].hits != prev->data[i].hits) { 9351 __atomic_store_n(&age_param->sec_since_last_hit, 0, 9352 __ATOMIC_RELAXED); 9353 continue; 9354 } 9355 if (__atomic_add_fetch(&age_param->sec_since_last_hit, 9356 time_delta, 9357 __ATOMIC_RELAXED) <= age_param->timeout) 9358 continue; 9359 /** 9360 * Hold the lock first, or if between the 9361 * state AGE_TMOUT and tailq operation the 9362 * release happened, the release procedure 9363 * may delete a non-existent tailq node. 9364 */ 9365 priv = rte_eth_devices[age_param->port_id].data->dev_private; 9366 age_info = GET_PORT_AGE_INFO(priv); 9367 rte_spinlock_lock(&age_info->aged_sl); 9368 if (__atomic_compare_exchange_n(&age_param->state, &expected, 9369 AGE_TMOUT, false, 9370 __ATOMIC_RELAXED, 9371 __ATOMIC_RELAXED)) { 9372 TAILQ_INSERT_TAIL(&age_info->aged_counters, cnt, next); 9373 MLX5_AGE_SET(age_info, MLX5_AGE_EVENT_NEW); 9374 } 9375 rte_spinlock_unlock(&age_info->aged_sl); 9376 } 9377 mlx5_age_event_prepare(sh); 9378 } 9379 9380 /** 9381 * Handler for the HW respond about ready values from an asynchronous batch 9382 * query. This function is probably called by the host thread. 9383 * 9384 * @param[in] sh 9385 * The pointer to the shared device context. 9386 * @param[in] async_id 9387 * The Devx async ID. 9388 * @param[in] status 9389 * The status of the completion. 9390 */ 9391 void 9392 mlx5_flow_async_pool_query_handle(struct mlx5_dev_ctx_shared *sh, 9393 uint64_t async_id, int status) 9394 { 9395 struct mlx5_flow_counter_pool *pool = 9396 (struct mlx5_flow_counter_pool *)(uintptr_t)async_id; 9397 struct mlx5_counter_stats_raw *raw_to_free; 9398 uint8_t query_gen = pool->query_gen ^ 1; 9399 struct mlx5_flow_counter_mng *cmng = &sh->sws_cmng; 9400 enum mlx5_counter_type cnt_type = 9401 pool->is_aged ? MLX5_COUNTER_TYPE_AGE : 9402 MLX5_COUNTER_TYPE_ORIGIN; 9403 9404 if (unlikely(status)) { 9405 raw_to_free = pool->raw_hw; 9406 } else { 9407 raw_to_free = pool->raw; 9408 if (pool->is_aged) 9409 mlx5_flow_aging_check(sh, pool); 9410 rte_spinlock_lock(&pool->sl); 9411 pool->raw = pool->raw_hw; 9412 rte_spinlock_unlock(&pool->sl); 9413 /* Be sure the new raw counters data is updated in memory. */ 9414 rte_io_wmb(); 9415 if (!TAILQ_EMPTY(&pool->counters[query_gen])) { 9416 rte_spinlock_lock(&cmng->csl[cnt_type]); 9417 TAILQ_CONCAT(&cmng->counters[cnt_type], 9418 &pool->counters[query_gen], next); 9419 rte_spinlock_unlock(&cmng->csl[cnt_type]); 9420 } 9421 } 9422 LIST_INSERT_HEAD(&sh->sws_cmng.free_stat_raws, raw_to_free, next); 9423 pool->raw_hw = NULL; 9424 sh->sws_cmng.pending_queries--; 9425 } 9426 9427 static int 9428 flow_group_to_table(uint32_t port_id, uint32_t group, uint32_t *table, 9429 const struct flow_grp_info *grp_info, 9430 struct rte_flow_error *error) 9431 { 9432 if (grp_info->transfer && grp_info->external && 9433 grp_info->fdb_def_rule) { 9434 if (group == UINT32_MAX) 9435 return rte_flow_error_set 9436 (error, EINVAL, 9437 RTE_FLOW_ERROR_TYPE_ATTR_GROUP, 9438 NULL, 9439 "group index not supported"); 9440 *table = group + 1; 9441 } else { 9442 *table = group; 9443 } 9444 DRV_LOG(DEBUG, "port %u group=%#x table=%#x", port_id, group, *table); 9445 return 0; 9446 } 9447 9448 /** 9449 * Translate the rte_flow group index to HW table value. 9450 * 9451 * If tunnel offload is disabled, all group ids converted to flow table 9452 * id using the standard method. 9453 * If tunnel offload is enabled, group id can be converted using the 9454 * standard or tunnel conversion method. Group conversion method 9455 * selection depends on flags in `grp_info` parameter: 9456 * - Internal (grp_info.external == 0) groups conversion uses the 9457 * standard method. 9458 * - Group ids in JUMP action converted with the tunnel conversion. 9459 * - Group id in rule attribute conversion depends on a rule type and 9460 * group id value: 9461 * ** non zero group attributes converted with the tunnel method 9462 * ** zero group attribute in non-tunnel rule is converted using the 9463 * standard method - there's only one root table 9464 * ** zero group attribute in steer tunnel rule is converted with the 9465 * standard method - single root table 9466 * ** zero group attribute in match tunnel rule is a special OvS 9467 * case: that value is used for portability reasons. That group 9468 * id is converted with the tunnel conversion method. 9469 * 9470 * @param[in] dev 9471 * Port device 9472 * @param[in] tunnel 9473 * PMD tunnel offload object 9474 * @param[in] group 9475 * rte_flow group index value. 9476 * @param[out] table 9477 * HW table value. 9478 * @param[in] grp_info 9479 * flags used for conversion 9480 * @param[out] error 9481 * Pointer to error structure. 9482 * 9483 * @return 9484 * 0 on success, a negative errno value otherwise and rte_errno is set. 9485 */ 9486 int 9487 mlx5_flow_group_to_table(struct rte_eth_dev *dev, 9488 const struct mlx5_flow_tunnel *tunnel, 9489 uint32_t group, uint32_t *table, 9490 const struct flow_grp_info *grp_info, 9491 struct rte_flow_error *error) 9492 { 9493 int ret; 9494 bool standard_translation; 9495 9496 if (!grp_info->skip_scale && grp_info->external && 9497 group < MLX5_MAX_TABLES_EXTERNAL) 9498 group *= MLX5_FLOW_TABLE_FACTOR; 9499 if (is_tunnel_offload_active(dev)) { 9500 standard_translation = !grp_info->external || 9501 grp_info->std_tbl_fix; 9502 } else { 9503 standard_translation = true; 9504 } 9505 DRV_LOG(DEBUG, 9506 "port %u group=%u transfer=%d external=%d fdb_def_rule=%d translate=%s", 9507 dev->data->port_id, group, grp_info->transfer, 9508 grp_info->external, grp_info->fdb_def_rule, 9509 standard_translation ? "STANDARD" : "TUNNEL"); 9510 if (standard_translation) 9511 ret = flow_group_to_table(dev->data->port_id, group, table, 9512 grp_info, error); 9513 else 9514 ret = tunnel_flow_group_to_flow_table(dev, tunnel, group, 9515 table, error); 9516 9517 return ret; 9518 } 9519 9520 /** 9521 * Discover availability of metadata reg_c's. 9522 * 9523 * Iteratively use test flows to check availability. 9524 * 9525 * @param[in] dev 9526 * Pointer to the Ethernet device structure. 9527 * 9528 * @return 9529 * 0 on success, a negative errno value otherwise and rte_errno is set. 9530 */ 9531 int 9532 mlx5_flow_discover_mreg_c(struct rte_eth_dev *dev) 9533 { 9534 struct mlx5_priv *priv = dev->data->dev_private; 9535 enum modify_reg idx; 9536 int n = 0; 9537 9538 /* reg_c[0] and reg_c[1] are reserved. */ 9539 priv->sh->flow_mreg_c[n++] = REG_C_0; 9540 priv->sh->flow_mreg_c[n++] = REG_C_1; 9541 /* Discover availability of other reg_c's. */ 9542 for (idx = REG_C_2; idx <= REG_C_7; ++idx) { 9543 struct rte_flow_attr attr = { 9544 .group = MLX5_FLOW_MREG_CP_TABLE_GROUP, 9545 .priority = MLX5_FLOW_LOWEST_PRIO_INDICATOR, 9546 .ingress = 1, 9547 }; 9548 struct rte_flow_item items[] = { 9549 [0] = { 9550 .type = RTE_FLOW_ITEM_TYPE_END, 9551 }, 9552 }; 9553 struct rte_flow_action actions[] = { 9554 [0] = { 9555 .type = (enum rte_flow_action_type) 9556 MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG, 9557 .conf = &(struct mlx5_flow_action_copy_mreg){ 9558 .src = REG_C_1, 9559 .dst = idx, 9560 }, 9561 }, 9562 [1] = { 9563 .type = RTE_FLOW_ACTION_TYPE_JUMP, 9564 .conf = &(struct rte_flow_action_jump){ 9565 .group = MLX5_FLOW_MREG_ACT_TABLE_GROUP, 9566 }, 9567 }, 9568 [2] = { 9569 .type = RTE_FLOW_ACTION_TYPE_END, 9570 }, 9571 }; 9572 uint32_t flow_idx; 9573 struct rte_flow *flow; 9574 struct rte_flow_error error; 9575 9576 if (!priv->sh->config.dv_flow_en) 9577 break; 9578 /* Create internal flow, validation skips copy action. */ 9579 flow_idx = flow_list_create(dev, MLX5_FLOW_TYPE_GEN, &attr, 9580 items, actions, false, &error); 9581 flow = mlx5_ipool_get(priv->flows[MLX5_FLOW_TYPE_GEN], 9582 flow_idx); 9583 if (!flow) 9584 continue; 9585 priv->sh->flow_mreg_c[n++] = idx; 9586 flow_list_destroy(dev, MLX5_FLOW_TYPE_GEN, flow_idx); 9587 } 9588 for (; n < MLX5_MREG_C_NUM; ++n) 9589 priv->sh->flow_mreg_c[n] = REG_NON; 9590 priv->sh->metadata_regc_check_flag = 1; 9591 return 0; 9592 } 9593 9594 int 9595 save_dump_file(const uint8_t *data, uint32_t size, 9596 uint32_t type, uint64_t id, void *arg, FILE *file) 9597 { 9598 char line[BUF_SIZE]; 9599 uint32_t out = 0; 9600 uint32_t k; 9601 uint32_t actions_num; 9602 struct rte_flow_query_count *count; 9603 9604 memset(line, 0, BUF_SIZE); 9605 switch (type) { 9606 case DR_DUMP_REC_TYPE_PMD_MODIFY_HDR: 9607 actions_num = *(uint32_t *)(arg); 9608 out += snprintf(line + out, BUF_SIZE - out, "%d,0x%" PRIx64 ",%d,", 9609 type, id, actions_num); 9610 break; 9611 case DR_DUMP_REC_TYPE_PMD_PKT_REFORMAT: 9612 out += snprintf(line + out, BUF_SIZE - out, "%d,0x%" PRIx64 ",", 9613 type, id); 9614 break; 9615 case DR_DUMP_REC_TYPE_PMD_COUNTER: 9616 count = (struct rte_flow_query_count *)arg; 9617 fprintf(file, 9618 "%d,0x%" PRIx64 ",%" PRIu64 ",%" PRIu64 "\n", 9619 type, id, count->hits, count->bytes); 9620 return 0; 9621 default: 9622 return -1; 9623 } 9624 9625 for (k = 0; k < size; k++) { 9626 /* Make sure we do not overrun the line buffer length. */ 9627 if (out >= BUF_SIZE - 4) { 9628 line[out] = '\0'; 9629 break; 9630 } 9631 out += snprintf(line + out, BUF_SIZE - out, "%02x", 9632 (data[k]) & 0xff); 9633 } 9634 fprintf(file, "%s\n", line); 9635 return 0; 9636 } 9637 9638 int 9639 mlx5_flow_query_counter(struct rte_eth_dev *dev, struct rte_flow *flow, 9640 struct rte_flow_query_count *count, struct rte_flow_error *error) 9641 { 9642 struct rte_flow_action action[2]; 9643 enum mlx5_flow_drv_type ftype; 9644 const struct mlx5_flow_driver_ops *fops; 9645 9646 if (!flow) { 9647 return rte_flow_error_set(error, ENOENT, 9648 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, 9649 NULL, 9650 "invalid flow handle"); 9651 } 9652 action[0].type = RTE_FLOW_ACTION_TYPE_COUNT; 9653 action[1].type = RTE_FLOW_ACTION_TYPE_END; 9654 if (flow->counter) { 9655 memset(count, 0, sizeof(struct rte_flow_query_count)); 9656 ftype = (enum mlx5_flow_drv_type)(flow->drv_type); 9657 MLX5_ASSERT(ftype > MLX5_FLOW_TYPE_MIN && 9658 ftype < MLX5_FLOW_TYPE_MAX); 9659 fops = flow_get_drv_ops(ftype); 9660 return fops->query(dev, flow, action, count, error); 9661 } 9662 return -1; 9663 } 9664 9665 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 9666 /** 9667 * Dump flow ipool data to file 9668 * 9669 * @param[in] dev 9670 * The pointer to Ethernet device. 9671 * @param[in] file 9672 * A pointer to a file for output. 9673 * @param[out] error 9674 * Perform verbose error reporting if not NULL. PMDs initialize this 9675 * structure in case of error only. 9676 * @return 9677 * 0 on success, a negative value otherwise. 9678 */ 9679 int 9680 mlx5_flow_dev_dump_ipool(struct rte_eth_dev *dev, 9681 struct rte_flow *flow, FILE *file, 9682 struct rte_flow_error *error) 9683 { 9684 struct mlx5_priv *priv = dev->data->dev_private; 9685 struct mlx5_flow_dv_modify_hdr_resource *modify_hdr; 9686 struct mlx5_flow_dv_encap_decap_resource *encap_decap; 9687 uint32_t handle_idx; 9688 struct mlx5_flow_handle *dh; 9689 struct rte_flow_query_count count; 9690 uint32_t actions_num; 9691 const uint8_t *data; 9692 size_t size; 9693 uint64_t id; 9694 uint32_t type; 9695 void *action = NULL; 9696 9697 if (!flow) { 9698 return rte_flow_error_set(error, ENOENT, 9699 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, 9700 NULL, 9701 "invalid flow handle"); 9702 } 9703 handle_idx = flow->dev_handles; 9704 /* query counter */ 9705 if (flow->counter && 9706 (!mlx5_counter_query(dev, flow->counter, false, 9707 &count.hits, &count.bytes, &action)) && action) { 9708 id = (uint64_t)(uintptr_t)action; 9709 type = DR_DUMP_REC_TYPE_PMD_COUNTER; 9710 save_dump_file(NULL, 0, type, 9711 id, (void *)&count, file); 9712 } 9713 9714 while (handle_idx) { 9715 dh = mlx5_ipool_get(priv->sh->ipool 9716 [MLX5_IPOOL_MLX5_FLOW], handle_idx); 9717 if (!dh) 9718 continue; 9719 handle_idx = dh->next.next; 9720 9721 /* Get modify_hdr and encap_decap buf from ipools. */ 9722 encap_decap = NULL; 9723 modify_hdr = dh->dvh.modify_hdr; 9724 9725 if (dh->dvh.rix_encap_decap) { 9726 encap_decap = mlx5_ipool_get(priv->sh->ipool 9727 [MLX5_IPOOL_DECAP_ENCAP], 9728 dh->dvh.rix_encap_decap); 9729 } 9730 if (modify_hdr) { 9731 data = (const uint8_t *)modify_hdr->actions; 9732 size = (size_t)(modify_hdr->actions_num) * 8; 9733 id = (uint64_t)(uintptr_t)modify_hdr->action; 9734 actions_num = modify_hdr->actions_num; 9735 type = DR_DUMP_REC_TYPE_PMD_MODIFY_HDR; 9736 save_dump_file(data, size, type, id, 9737 (void *)(&actions_num), file); 9738 } 9739 if (encap_decap) { 9740 data = encap_decap->buf; 9741 size = encap_decap->size; 9742 id = (uint64_t)(uintptr_t)encap_decap->action; 9743 type = DR_DUMP_REC_TYPE_PMD_PKT_REFORMAT; 9744 save_dump_file(data, size, type, 9745 id, NULL, file); 9746 } 9747 } 9748 return 0; 9749 } 9750 9751 /** 9752 * Dump all flow's encap_decap/modify_hdr/counter data to file 9753 * 9754 * @param[in] dev 9755 * The pointer to Ethernet device. 9756 * @param[in] file 9757 * A pointer to a file for output. 9758 * @param[out] error 9759 * Perform verbose error reporting if not NULL. PMDs initialize this 9760 * structure in case of error only. 9761 * @return 9762 * 0 on success, a negative value otherwise. 9763 */ 9764 static int 9765 mlx5_flow_dev_dump_sh_all(struct rte_eth_dev *dev, 9766 FILE *file, struct rte_flow_error *error __rte_unused) 9767 { 9768 struct mlx5_priv *priv = dev->data->dev_private; 9769 struct mlx5_dev_ctx_shared *sh = priv->sh; 9770 struct mlx5_hlist *h; 9771 struct mlx5_flow_dv_modify_hdr_resource *modify_hdr; 9772 struct mlx5_flow_dv_encap_decap_resource *encap_decap; 9773 struct rte_flow_query_count count; 9774 uint32_t actions_num; 9775 const uint8_t *data; 9776 size_t size; 9777 uint64_t id; 9778 uint32_t type; 9779 uint32_t i; 9780 uint32_t j; 9781 struct mlx5_list_inconst *l_inconst; 9782 struct mlx5_list_entry *e; 9783 int lcore_index; 9784 struct mlx5_flow_counter_mng *cmng = &priv->sh->sws_cmng; 9785 uint32_t max; 9786 void *action; 9787 9788 /* encap_decap hlist is lcore_share, get global core cache. */ 9789 i = MLX5_LIST_GLOBAL; 9790 h = sh->encaps_decaps; 9791 if (h) { 9792 for (j = 0; j <= h->mask; j++) { 9793 l_inconst = &h->buckets[j].l; 9794 if (!l_inconst || !l_inconst->cache[i]) 9795 continue; 9796 9797 e = LIST_FIRST(&l_inconst->cache[i]->h); 9798 while (e) { 9799 encap_decap = 9800 (struct mlx5_flow_dv_encap_decap_resource *)e; 9801 data = encap_decap->buf; 9802 size = encap_decap->size; 9803 id = (uint64_t)(uintptr_t)encap_decap->action; 9804 type = DR_DUMP_REC_TYPE_PMD_PKT_REFORMAT; 9805 save_dump_file(data, size, type, 9806 id, NULL, file); 9807 e = LIST_NEXT(e, next); 9808 } 9809 } 9810 } 9811 9812 /* get modify_hdr */ 9813 h = sh->modify_cmds; 9814 if (h) { 9815 lcore_index = rte_lcore_index(rte_lcore_id()); 9816 if (unlikely(lcore_index == -1)) { 9817 lcore_index = MLX5_LIST_NLCORE; 9818 rte_spinlock_lock(&h->l_const.lcore_lock); 9819 } 9820 i = lcore_index; 9821 9822 for (j = 0; j <= h->mask; j++) { 9823 l_inconst = &h->buckets[j].l; 9824 if (!l_inconst || !l_inconst->cache[i]) 9825 continue; 9826 9827 e = LIST_FIRST(&l_inconst->cache[i]->h); 9828 while (e) { 9829 modify_hdr = 9830 (struct mlx5_flow_dv_modify_hdr_resource *)e; 9831 data = (const uint8_t *)modify_hdr->actions; 9832 size = (size_t)(modify_hdr->actions_num) * 8; 9833 actions_num = modify_hdr->actions_num; 9834 id = (uint64_t)(uintptr_t)modify_hdr->action; 9835 type = DR_DUMP_REC_TYPE_PMD_MODIFY_HDR; 9836 save_dump_file(data, size, type, id, 9837 (void *)(&actions_num), file); 9838 e = LIST_NEXT(e, next); 9839 } 9840 } 9841 9842 if (unlikely(lcore_index == MLX5_LIST_NLCORE)) 9843 rte_spinlock_unlock(&h->l_const.lcore_lock); 9844 } 9845 9846 /* get counter */ 9847 MLX5_ASSERT(cmng->n_valid <= MLX5_COUNTER_POOLS_MAX_NUM); 9848 max = MLX5_COUNTERS_PER_POOL * cmng->n_valid; 9849 for (j = 1; j <= max; j++) { 9850 action = NULL; 9851 if ((!mlx5_counter_query(dev, j, false, &count.hits, 9852 &count.bytes, &action)) && action) { 9853 id = (uint64_t)(uintptr_t)action; 9854 type = DR_DUMP_REC_TYPE_PMD_COUNTER; 9855 save_dump_file(NULL, 0, type, 9856 id, (void *)&count, file); 9857 } 9858 } 9859 return 0; 9860 } 9861 #endif 9862 9863 /** 9864 * Dump flow raw hw data to file 9865 * 9866 * @param[in] dev 9867 * The pointer to Ethernet device. 9868 * @param[in] file 9869 * A pointer to a file for output. 9870 * @param[out] error 9871 * Perform verbose error reporting if not NULL. PMDs initialize this 9872 * structure in case of error only. 9873 * @return 9874 * 0 on success, a negative value otherwise. 9875 */ 9876 int 9877 mlx5_flow_dev_dump(struct rte_eth_dev *dev, struct rte_flow *flow_idx, 9878 FILE *file, 9879 struct rte_flow_error *error __rte_unused) 9880 { 9881 struct mlx5_priv *priv = dev->data->dev_private; 9882 struct mlx5_dev_ctx_shared *sh = priv->sh; 9883 uint32_t handle_idx; 9884 int ret; 9885 struct mlx5_flow_handle *dh; 9886 struct rte_flow *flow; 9887 9888 if (!sh->config.dv_flow_en) { 9889 if (fputs("device dv flow disabled\n", file) <= 0) 9890 return -errno; 9891 return -ENOTSUP; 9892 } 9893 9894 /* dump all */ 9895 if (!flow_idx) { 9896 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 9897 if (mlx5_flow_dev_dump_sh_all(dev, file, error)) 9898 return -EINVAL; 9899 #endif 9900 return mlx5_devx_cmd_flow_dump(sh->fdb_domain, 9901 sh->rx_domain, 9902 sh->tx_domain, file); 9903 } 9904 /* dump one */ 9905 flow = mlx5_ipool_get(priv->flows[MLX5_FLOW_TYPE_GEN], 9906 (uintptr_t)(void *)flow_idx); 9907 if (!flow) 9908 return -EINVAL; 9909 9910 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 9911 mlx5_flow_dev_dump_ipool(dev, flow, file, error); 9912 #endif 9913 handle_idx = flow->dev_handles; 9914 while (handle_idx) { 9915 dh = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW], 9916 handle_idx); 9917 if (!dh) 9918 return -ENOENT; 9919 if (dh->drv_flow) { 9920 ret = mlx5_devx_cmd_flow_single_dump(dh->drv_flow, 9921 file); 9922 if (ret) 9923 return -ENOENT; 9924 } 9925 handle_idx = dh->next.next; 9926 } 9927 return 0; 9928 } 9929 9930 /** 9931 * Get aged-out flows. 9932 * 9933 * @param[in] dev 9934 * Pointer to the Ethernet device structure. 9935 * @param[in] context 9936 * The address of an array of pointers to the aged-out flows contexts. 9937 * @param[in] nb_countexts 9938 * The length of context array pointers. 9939 * @param[out] error 9940 * Perform verbose error reporting if not NULL. Initialized in case of 9941 * error only. 9942 * 9943 * @return 9944 * how many contexts get in success, otherwise negative errno value. 9945 * if nb_contexts is 0, return the amount of all aged contexts. 9946 * if nb_contexts is not 0 , return the amount of aged flows reported 9947 * in the context array. 9948 */ 9949 int 9950 mlx5_flow_get_aged_flows(struct rte_eth_dev *dev, void **contexts, 9951 uint32_t nb_contexts, struct rte_flow_error *error) 9952 { 9953 const struct mlx5_flow_driver_ops *fops; 9954 struct rte_flow_attr attr = { .transfer = 0 }; 9955 enum mlx5_flow_drv_type type = flow_get_drv_type(dev, &attr); 9956 9957 if (type == MLX5_FLOW_TYPE_DV || type == MLX5_FLOW_TYPE_HW) { 9958 fops = flow_get_drv_ops(type); 9959 return fops->get_aged_flows(dev, contexts, nb_contexts, error); 9960 } 9961 DRV_LOG(ERR, "port %u get aged flows is not supported.", 9962 dev->data->port_id); 9963 return -ENOTSUP; 9964 } 9965 9966 /** 9967 * Get aged-out flows per HWS queue. 9968 * 9969 * @param[in] dev 9970 * Pointer to the Ethernet device structure. 9971 * @param[in] queue_id 9972 * Flow queue to query. 9973 * @param[in] context 9974 * The address of an array of pointers to the aged-out flows contexts. 9975 * @param[in] nb_countexts 9976 * The length of context array pointers. 9977 * @param[out] error 9978 * Perform verbose error reporting if not NULL. Initialized in case of 9979 * error only. 9980 * 9981 * @return 9982 * how many contexts get in success, otherwise negative errno value. 9983 * if nb_contexts is 0, return the amount of all aged contexts. 9984 * if nb_contexts is not 0 , return the amount of aged flows reported 9985 * in the context array. 9986 */ 9987 int 9988 mlx5_flow_get_q_aged_flows(struct rte_eth_dev *dev, uint32_t queue_id, 9989 void **contexts, uint32_t nb_contexts, 9990 struct rte_flow_error *error) 9991 { 9992 const struct mlx5_flow_driver_ops *fops; 9993 struct rte_flow_attr attr = { 0 }; 9994 9995 if (flow_get_drv_type(dev, &attr) == MLX5_FLOW_TYPE_HW) { 9996 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_HW); 9997 return fops->get_q_aged_flows(dev, queue_id, contexts, 9998 nb_contexts, error); 9999 } 10000 DRV_LOG(ERR, "port %u queue %u get aged flows is not supported.", 10001 dev->data->port_id, queue_id); 10002 return rte_flow_error_set(error, ENOTSUP, 10003 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, 10004 "get Q aged flows with incorrect steering mode"); 10005 } 10006 10007 /* Wrapper for driver action_validate op callback */ 10008 static int 10009 flow_drv_action_validate(struct rte_eth_dev *dev, 10010 const struct rte_flow_indir_action_conf *conf, 10011 const struct rte_flow_action *action, 10012 const struct mlx5_flow_driver_ops *fops, 10013 struct rte_flow_error *error) 10014 { 10015 static const char err_msg[] = "indirect action validation unsupported"; 10016 10017 if (!fops->action_validate) { 10018 DRV_LOG(ERR, "port %u %s.", dev->data->port_id, err_msg); 10019 rte_flow_error_set(error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION, 10020 NULL, err_msg); 10021 return -rte_errno; 10022 } 10023 return fops->action_validate(dev, conf, action, error); 10024 } 10025 10026 /** 10027 * Destroys the shared action by handle. 10028 * 10029 * @param dev 10030 * Pointer to Ethernet device structure. 10031 * @param[in] handle 10032 * Handle for the indirect action object to be destroyed. 10033 * @param[out] error 10034 * Perform verbose error reporting if not NULL. PMDs initialize this 10035 * structure in case of error only. 10036 * 10037 * @return 10038 * 0 on success, a negative errno value otherwise and rte_errno is set. 10039 * 10040 * @note: wrapper for driver action_create op callback. 10041 */ 10042 static int 10043 mlx5_action_handle_destroy(struct rte_eth_dev *dev, 10044 struct rte_flow_action_handle *handle, 10045 struct rte_flow_error *error) 10046 { 10047 static const char err_msg[] = "indirect action destruction unsupported"; 10048 struct rte_flow_attr attr = { .transfer = 0 }; 10049 const struct mlx5_flow_driver_ops *fops = 10050 flow_get_drv_ops(flow_get_drv_type(dev, &attr)); 10051 10052 if (!fops->action_destroy) { 10053 DRV_LOG(ERR, "port %u %s.", dev->data->port_id, err_msg); 10054 rte_flow_error_set(error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION, 10055 NULL, err_msg); 10056 return -rte_errno; 10057 } 10058 return fops->action_destroy(dev, handle, error); 10059 } 10060 10061 /* Wrapper for driver action_destroy op callback */ 10062 static int 10063 flow_drv_action_update(struct rte_eth_dev *dev, 10064 struct rte_flow_action_handle *handle, 10065 const void *update, 10066 const struct mlx5_flow_driver_ops *fops, 10067 struct rte_flow_error *error) 10068 { 10069 static const char err_msg[] = "indirect action update unsupported"; 10070 10071 if (!fops->action_update) { 10072 DRV_LOG(ERR, "port %u %s.", dev->data->port_id, err_msg); 10073 rte_flow_error_set(error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION, 10074 NULL, err_msg); 10075 return -rte_errno; 10076 } 10077 return fops->action_update(dev, handle, update, error); 10078 } 10079 10080 /* Wrapper for driver action_destroy op callback */ 10081 static int 10082 flow_drv_action_query(struct rte_eth_dev *dev, 10083 const struct rte_flow_action_handle *handle, 10084 void *data, 10085 const struct mlx5_flow_driver_ops *fops, 10086 struct rte_flow_error *error) 10087 { 10088 static const char err_msg[] = "indirect action query unsupported"; 10089 10090 if (!fops->action_query) { 10091 DRV_LOG(ERR, "port %u %s.", dev->data->port_id, err_msg); 10092 rte_flow_error_set(error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION, 10093 NULL, err_msg); 10094 return -rte_errno; 10095 } 10096 return fops->action_query(dev, handle, data, error); 10097 } 10098 10099 /** 10100 * Create indirect action for reuse in multiple flow rules. 10101 * 10102 * @param dev 10103 * Pointer to Ethernet device structure. 10104 * @param conf 10105 * Pointer to indirect action object configuration. 10106 * @param[in] action 10107 * Action configuration for indirect action object creation. 10108 * @param[out] error 10109 * Perform verbose error reporting if not NULL. PMDs initialize this 10110 * structure in case of error only. 10111 * @return 10112 * A valid handle in case of success, NULL otherwise and rte_errno is set. 10113 */ 10114 static struct rte_flow_action_handle * 10115 mlx5_action_handle_create(struct rte_eth_dev *dev, 10116 const struct rte_flow_indir_action_conf *conf, 10117 const struct rte_flow_action *action, 10118 struct rte_flow_error *error) 10119 { 10120 static const char err_msg[] = "indirect action creation unsupported"; 10121 struct rte_flow_attr attr = { .transfer = 0 }; 10122 const struct mlx5_flow_driver_ops *fops = 10123 flow_get_drv_ops(flow_get_drv_type(dev, &attr)); 10124 10125 if (flow_drv_action_validate(dev, conf, action, fops, error)) 10126 return NULL; 10127 if (!fops->action_create) { 10128 DRV_LOG(ERR, "port %u %s.", dev->data->port_id, err_msg); 10129 rte_flow_error_set(error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION, 10130 NULL, err_msg); 10131 return NULL; 10132 } 10133 return fops->action_create(dev, conf, action, error); 10134 } 10135 10136 /** 10137 * Updates inplace the indirect action configuration pointed by *handle* 10138 * with the configuration provided as *update* argument. 10139 * The update of the indirect action configuration effects all flow rules 10140 * reusing the action via handle. 10141 * 10142 * @param dev 10143 * Pointer to Ethernet device structure. 10144 * @param[in] handle 10145 * Handle for the indirect action to be updated. 10146 * @param[in] update 10147 * Action specification used to modify the action pointed by handle. 10148 * *update* could be of same type with the action pointed by the *handle* 10149 * handle argument, or some other structures like a wrapper, depending on 10150 * the indirect action type. 10151 * @param[out] error 10152 * Perform verbose error reporting if not NULL. PMDs initialize this 10153 * structure in case of error only. 10154 * 10155 * @return 10156 * 0 on success, a negative errno value otherwise and rte_errno is set. 10157 */ 10158 static int 10159 mlx5_action_handle_update(struct rte_eth_dev *dev, 10160 struct rte_flow_action_handle *handle, 10161 const void *update, 10162 struct rte_flow_error *error) 10163 { 10164 struct rte_flow_attr attr = { .transfer = 0 }; 10165 const struct mlx5_flow_driver_ops *fops = 10166 flow_get_drv_ops(flow_get_drv_type(dev, &attr)); 10167 int ret; 10168 10169 ret = flow_drv_action_validate(dev, NULL, 10170 (const struct rte_flow_action *)update, fops, error); 10171 if (ret) 10172 return ret; 10173 return flow_drv_action_update(dev, handle, update, fops, 10174 error); 10175 } 10176 10177 /** 10178 * Query the indirect action by handle. 10179 * 10180 * This function allows retrieving action-specific data such as counters. 10181 * Data is gathered by special action which may be present/referenced in 10182 * more than one flow rule definition. 10183 * 10184 * see @RTE_FLOW_ACTION_TYPE_COUNT 10185 * 10186 * @param dev 10187 * Pointer to Ethernet device structure. 10188 * @param[in] handle 10189 * Handle for the indirect action to query. 10190 * @param[in, out] data 10191 * Pointer to storage for the associated query data type. 10192 * @param[out] error 10193 * Perform verbose error reporting if not NULL. PMDs initialize this 10194 * structure in case of error only. 10195 * 10196 * @return 10197 * 0 on success, a negative errno value otherwise and rte_errno is set. 10198 */ 10199 static int 10200 mlx5_action_handle_query(struct rte_eth_dev *dev, 10201 const struct rte_flow_action_handle *handle, 10202 void *data, 10203 struct rte_flow_error *error) 10204 { 10205 struct rte_flow_attr attr = { .transfer = 0 }; 10206 const struct mlx5_flow_driver_ops *fops = 10207 flow_get_drv_ops(flow_get_drv_type(dev, &attr)); 10208 10209 return flow_drv_action_query(dev, handle, data, fops, error); 10210 } 10211 10212 /** 10213 * Destroy all indirect actions (shared RSS). 10214 * 10215 * @param dev 10216 * Pointer to Ethernet device. 10217 * 10218 * @return 10219 * 0 on success, a negative errno value otherwise and rte_errno is set. 10220 */ 10221 int 10222 mlx5_action_handle_flush(struct rte_eth_dev *dev) 10223 { 10224 struct rte_flow_error error; 10225 struct mlx5_priv *priv = dev->data->dev_private; 10226 struct mlx5_shared_action_rss *shared_rss; 10227 int ret = 0; 10228 uint32_t idx; 10229 10230 ILIST_FOREACH(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], 10231 priv->rss_shared_actions, idx, shared_rss, next) { 10232 ret |= mlx5_action_handle_destroy(dev, 10233 (struct rte_flow_action_handle *)(uintptr_t)idx, &error); 10234 } 10235 return ret; 10236 } 10237 10238 /** 10239 * Validate existing indirect actions against current device configuration 10240 * and attach them to device resources. 10241 * 10242 * @param dev 10243 * Pointer to Ethernet device. 10244 * 10245 * @return 10246 * 0 on success, a negative errno value otherwise and rte_errno is set. 10247 */ 10248 int 10249 mlx5_action_handle_attach(struct rte_eth_dev *dev) 10250 { 10251 struct mlx5_priv *priv = dev->data->dev_private; 10252 int ret = 0; 10253 struct mlx5_ind_table_obj *ind_tbl, *ind_tbl_last; 10254 10255 LIST_FOREACH(ind_tbl, &priv->standalone_ind_tbls, next) { 10256 const char *message; 10257 uint32_t queue_idx; 10258 10259 ret = mlx5_validate_rss_queues(dev, ind_tbl->queues, 10260 ind_tbl->queues_n, 10261 &message, &queue_idx); 10262 if (ret != 0) { 10263 DRV_LOG(ERR, "Port %u cannot use queue %u in RSS: %s", 10264 dev->data->port_id, ind_tbl->queues[queue_idx], 10265 message); 10266 break; 10267 } 10268 } 10269 if (ret != 0) 10270 return ret; 10271 LIST_FOREACH(ind_tbl, &priv->standalone_ind_tbls, next) { 10272 ret = mlx5_ind_table_obj_attach(dev, ind_tbl); 10273 if (ret != 0) { 10274 DRV_LOG(ERR, "Port %u could not attach " 10275 "indirection table obj %p", 10276 dev->data->port_id, (void *)ind_tbl); 10277 goto error; 10278 } 10279 } 10280 10281 return 0; 10282 error: 10283 ind_tbl_last = ind_tbl; 10284 LIST_FOREACH(ind_tbl, &priv->standalone_ind_tbls, next) { 10285 if (ind_tbl == ind_tbl_last) 10286 break; 10287 if (mlx5_ind_table_obj_detach(dev, ind_tbl) != 0) 10288 DRV_LOG(CRIT, "Port %u could not detach " 10289 "indirection table obj %p on rollback", 10290 dev->data->port_id, (void *)ind_tbl); 10291 } 10292 return ret; 10293 } 10294 10295 /** 10296 * Detach indirect actions of the device from its resources. 10297 * 10298 * @param dev 10299 * Pointer to Ethernet device. 10300 * 10301 * @return 10302 * 0 on success, a negative errno value otherwise and rte_errno is set. 10303 */ 10304 int 10305 mlx5_action_handle_detach(struct rte_eth_dev *dev) 10306 { 10307 struct mlx5_priv *priv = dev->data->dev_private; 10308 int ret = 0; 10309 struct mlx5_ind_table_obj *ind_tbl, *ind_tbl_last; 10310 10311 LIST_FOREACH(ind_tbl, &priv->standalone_ind_tbls, next) { 10312 ret = mlx5_ind_table_obj_detach(dev, ind_tbl); 10313 if (ret != 0) { 10314 DRV_LOG(ERR, "Port %u could not detach " 10315 "indirection table obj %p", 10316 dev->data->port_id, (void *)ind_tbl); 10317 goto error; 10318 } 10319 } 10320 return 0; 10321 error: 10322 ind_tbl_last = ind_tbl; 10323 LIST_FOREACH(ind_tbl, &priv->standalone_ind_tbls, next) { 10324 if (ind_tbl == ind_tbl_last) 10325 break; 10326 if (mlx5_ind_table_obj_attach(dev, ind_tbl) != 0) 10327 DRV_LOG(CRIT, "Port %u could not attach " 10328 "indirection table obj %p on rollback", 10329 dev->data->port_id, (void *)ind_tbl); 10330 } 10331 return ret; 10332 } 10333 10334 #ifndef HAVE_MLX5DV_DR 10335 #define MLX5_DOMAIN_SYNC_FLOW ((1 << 0) | (1 << 1)) 10336 #else 10337 #define MLX5_DOMAIN_SYNC_FLOW \ 10338 (MLX5DV_DR_DOMAIN_SYNC_FLAGS_SW | MLX5DV_DR_DOMAIN_SYNC_FLAGS_HW) 10339 #endif 10340 10341 int rte_pmd_mlx5_sync_flow(uint16_t port_id, uint32_t domains) 10342 { 10343 struct rte_eth_dev *dev = &rte_eth_devices[port_id]; 10344 const struct mlx5_flow_driver_ops *fops; 10345 int ret; 10346 struct rte_flow_attr attr = { .transfer = 0 }; 10347 10348 fops = flow_get_drv_ops(flow_get_drv_type(dev, &attr)); 10349 ret = fops->sync_domain(dev, domains, MLX5_DOMAIN_SYNC_FLOW); 10350 if (ret > 0) 10351 ret = -ret; 10352 return ret; 10353 } 10354 10355 const struct mlx5_flow_tunnel * 10356 mlx5_get_tof(const struct rte_flow_item *item, 10357 const struct rte_flow_action *action, 10358 enum mlx5_tof_rule_type *rule_type) 10359 { 10360 for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) { 10361 if (item->type == (typeof(item->type)) 10362 MLX5_RTE_FLOW_ITEM_TYPE_TUNNEL) { 10363 *rule_type = MLX5_TUNNEL_OFFLOAD_MATCH_RULE; 10364 return flow_items_to_tunnel(item); 10365 } 10366 } 10367 for (; action->conf != RTE_FLOW_ACTION_TYPE_END; action++) { 10368 if (action->type == (typeof(action->type)) 10369 MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET) { 10370 *rule_type = MLX5_TUNNEL_OFFLOAD_SET_RULE; 10371 return flow_actions_to_tunnel(action); 10372 } 10373 } 10374 return NULL; 10375 } 10376 10377 /** 10378 * tunnel offload functionality is defined for DV environment only 10379 */ 10380 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 10381 __extension__ 10382 union tunnel_offload_mark { 10383 uint32_t val; 10384 struct { 10385 uint32_t app_reserve:8; 10386 uint32_t table_id:15; 10387 uint32_t transfer:1; 10388 uint32_t _unused_:8; 10389 }; 10390 }; 10391 10392 static bool 10393 mlx5_access_tunnel_offload_db 10394 (struct rte_eth_dev *dev, 10395 bool (*match)(struct rte_eth_dev *, 10396 struct mlx5_flow_tunnel *, const void *), 10397 void (*hit)(struct rte_eth_dev *, struct mlx5_flow_tunnel *, void *), 10398 void (*miss)(struct rte_eth_dev *, void *), 10399 void *ctx, bool lock_op); 10400 10401 static int 10402 flow_tunnel_add_default_miss(struct rte_eth_dev *dev, 10403 struct rte_flow *flow, 10404 const struct rte_flow_attr *attr, 10405 const struct rte_flow_action *app_actions, 10406 uint32_t flow_idx, 10407 const struct mlx5_flow_tunnel *tunnel, 10408 struct tunnel_default_miss_ctx *ctx, 10409 struct rte_flow_error *error) 10410 { 10411 struct mlx5_priv *priv = dev->data->dev_private; 10412 struct mlx5_flow *dev_flow; 10413 struct rte_flow_attr miss_attr = *attr; 10414 const struct rte_flow_item miss_items[2] = { 10415 { 10416 .type = RTE_FLOW_ITEM_TYPE_ETH, 10417 .spec = NULL, 10418 .last = NULL, 10419 .mask = NULL 10420 }, 10421 { 10422 .type = RTE_FLOW_ITEM_TYPE_END, 10423 .spec = NULL, 10424 .last = NULL, 10425 .mask = NULL 10426 } 10427 }; 10428 union tunnel_offload_mark mark_id; 10429 struct rte_flow_action_mark miss_mark; 10430 struct rte_flow_action miss_actions[3] = { 10431 [0] = { .type = RTE_FLOW_ACTION_TYPE_MARK, .conf = &miss_mark }, 10432 [2] = { .type = RTE_FLOW_ACTION_TYPE_END, .conf = NULL } 10433 }; 10434 const struct rte_flow_action_jump *jump_data; 10435 uint32_t i, flow_table = 0; /* prevent compilation warning */ 10436 struct flow_grp_info grp_info = { 10437 .external = 1, 10438 .transfer = attr->transfer, 10439 .fdb_def_rule = !!priv->fdb_def_rule, 10440 .std_tbl_fix = 0, 10441 }; 10442 int ret; 10443 10444 if (!attr->transfer) { 10445 uint32_t q_size; 10446 10447 miss_actions[1].type = RTE_FLOW_ACTION_TYPE_RSS; 10448 q_size = priv->reta_idx_n * sizeof(ctx->queue[0]); 10449 ctx->queue = mlx5_malloc(MLX5_MEM_SYS | MLX5_MEM_ZERO, q_size, 10450 0, SOCKET_ID_ANY); 10451 if (!ctx->queue) 10452 return rte_flow_error_set 10453 (error, ENOMEM, 10454 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 10455 NULL, "invalid default miss RSS"); 10456 ctx->action_rss.func = RTE_ETH_HASH_FUNCTION_DEFAULT, 10457 ctx->action_rss.level = 0, 10458 ctx->action_rss.types = priv->rss_conf.rss_hf, 10459 ctx->action_rss.key_len = priv->rss_conf.rss_key_len, 10460 ctx->action_rss.queue_num = priv->reta_idx_n, 10461 ctx->action_rss.key = priv->rss_conf.rss_key, 10462 ctx->action_rss.queue = ctx->queue; 10463 if (!priv->reta_idx_n || !priv->rxqs_n) 10464 return rte_flow_error_set 10465 (error, EINVAL, 10466 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 10467 NULL, "invalid port configuration"); 10468 if (!(dev->data->dev_conf.rxmode.mq_mode & RTE_ETH_MQ_RX_RSS_FLAG)) 10469 ctx->action_rss.types = 0; 10470 for (i = 0; i != priv->reta_idx_n; ++i) 10471 ctx->queue[i] = (*priv->reta_idx)[i]; 10472 } else { 10473 miss_actions[1].type = RTE_FLOW_ACTION_TYPE_JUMP; 10474 ctx->miss_jump.group = MLX5_TNL_MISS_FDB_JUMP_GRP; 10475 } 10476 miss_actions[1].conf = (typeof(miss_actions[1].conf))ctx->raw; 10477 for (; app_actions->type != RTE_FLOW_ACTION_TYPE_JUMP; app_actions++); 10478 jump_data = app_actions->conf; 10479 miss_attr.priority = MLX5_TNL_MISS_RULE_PRIORITY; 10480 miss_attr.group = jump_data->group; 10481 ret = mlx5_flow_group_to_table(dev, tunnel, jump_data->group, 10482 &flow_table, &grp_info, error); 10483 if (ret) 10484 return rte_flow_error_set(error, EINVAL, 10485 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 10486 NULL, "invalid tunnel id"); 10487 mark_id.app_reserve = 0; 10488 mark_id.table_id = tunnel_flow_tbl_to_id(flow_table); 10489 mark_id.transfer = !!attr->transfer; 10490 mark_id._unused_ = 0; 10491 miss_mark.id = mark_id.val; 10492 dev_flow = flow_drv_prepare(dev, flow, &miss_attr, 10493 miss_items, miss_actions, flow_idx, error); 10494 if (!dev_flow) 10495 return -rte_errno; 10496 dev_flow->flow = flow; 10497 dev_flow->external = true; 10498 dev_flow->tunnel = tunnel; 10499 dev_flow->tof_type = MLX5_TUNNEL_OFFLOAD_MISS_RULE; 10500 /* Subflow object was created, we must include one in the list. */ 10501 SILIST_INSERT(&flow->dev_handles, dev_flow->handle_idx, 10502 dev_flow->handle, next); 10503 DRV_LOG(DEBUG, 10504 "port %u tunnel type=%d id=%u miss rule priority=%u group=%u", 10505 dev->data->port_id, tunnel->app_tunnel.type, 10506 tunnel->tunnel_id, miss_attr.priority, miss_attr.group); 10507 ret = flow_drv_translate(dev, dev_flow, &miss_attr, miss_items, 10508 miss_actions, error); 10509 if (!ret) 10510 ret = flow_mreg_update_copy_table(dev, flow, miss_actions, 10511 error); 10512 10513 return ret; 10514 } 10515 10516 static const struct mlx5_flow_tbl_data_entry * 10517 tunnel_mark_decode(struct rte_eth_dev *dev, uint32_t mark) 10518 { 10519 struct mlx5_priv *priv = dev->data->dev_private; 10520 struct mlx5_dev_ctx_shared *sh = priv->sh; 10521 struct mlx5_list_entry *he; 10522 union tunnel_offload_mark mbits = { .val = mark }; 10523 union mlx5_flow_tbl_key table_key = { 10524 { 10525 .level = tunnel_id_to_flow_tbl(mbits.table_id), 10526 .id = 0, 10527 .reserved = 0, 10528 .dummy = 0, 10529 .is_fdb = !!mbits.transfer, 10530 .is_egress = 0, 10531 } 10532 }; 10533 struct mlx5_flow_cb_ctx ctx = { 10534 .data = &table_key.v64, 10535 }; 10536 10537 he = mlx5_hlist_lookup(sh->flow_tbls, table_key.v64, &ctx); 10538 return he ? 10539 container_of(he, struct mlx5_flow_tbl_data_entry, entry) : NULL; 10540 } 10541 10542 static void 10543 mlx5_flow_tunnel_grp2tbl_remove_cb(void *tool_ctx, 10544 struct mlx5_list_entry *entry) 10545 { 10546 struct mlx5_dev_ctx_shared *sh = tool_ctx; 10547 struct tunnel_tbl_entry *tte = container_of(entry, typeof(*tte), hash); 10548 10549 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_TNL_TBL_ID], 10550 tunnel_flow_tbl_to_id(tte->flow_table)); 10551 mlx5_free(tte); 10552 } 10553 10554 static int 10555 mlx5_flow_tunnel_grp2tbl_match_cb(void *tool_ctx __rte_unused, 10556 struct mlx5_list_entry *entry, void *cb_ctx) 10557 { 10558 struct mlx5_flow_cb_ctx *ctx = cb_ctx; 10559 union tunnel_tbl_key tbl = { 10560 .val = *(uint64_t *)(ctx->data), 10561 }; 10562 struct tunnel_tbl_entry *tte = container_of(entry, typeof(*tte), hash); 10563 10564 return tbl.tunnel_id != tte->tunnel_id || tbl.group != tte->group; 10565 } 10566 10567 static struct mlx5_list_entry * 10568 mlx5_flow_tunnel_grp2tbl_create_cb(void *tool_ctx, void *cb_ctx) 10569 { 10570 struct mlx5_dev_ctx_shared *sh = tool_ctx; 10571 struct mlx5_flow_cb_ctx *ctx = cb_ctx; 10572 struct tunnel_tbl_entry *tte; 10573 union tunnel_tbl_key tbl = { 10574 .val = *(uint64_t *)(ctx->data), 10575 }; 10576 10577 tte = mlx5_malloc(MLX5_MEM_SYS | MLX5_MEM_ZERO, 10578 sizeof(*tte), 0, 10579 SOCKET_ID_ANY); 10580 if (!tte) 10581 goto err; 10582 mlx5_ipool_malloc(sh->ipool[MLX5_IPOOL_TNL_TBL_ID], 10583 &tte->flow_table); 10584 if (tte->flow_table >= MLX5_MAX_TABLES) { 10585 DRV_LOG(ERR, "Tunnel TBL ID %d exceed max limit.", 10586 tte->flow_table); 10587 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_TNL_TBL_ID], 10588 tte->flow_table); 10589 goto err; 10590 } else if (!tte->flow_table) { 10591 goto err; 10592 } 10593 tte->flow_table = tunnel_id_to_flow_tbl(tte->flow_table); 10594 tte->tunnel_id = tbl.tunnel_id; 10595 tte->group = tbl.group; 10596 return &tte->hash; 10597 err: 10598 if (tte) 10599 mlx5_free(tte); 10600 return NULL; 10601 } 10602 10603 static struct mlx5_list_entry * 10604 mlx5_flow_tunnel_grp2tbl_clone_cb(void *tool_ctx __rte_unused, 10605 struct mlx5_list_entry *oentry, 10606 void *cb_ctx __rte_unused) 10607 { 10608 struct tunnel_tbl_entry *tte = mlx5_malloc(MLX5_MEM_SYS, sizeof(*tte), 10609 0, SOCKET_ID_ANY); 10610 10611 if (!tte) 10612 return NULL; 10613 memcpy(tte, oentry, sizeof(*tte)); 10614 return &tte->hash; 10615 } 10616 10617 static void 10618 mlx5_flow_tunnel_grp2tbl_clone_free_cb(void *tool_ctx __rte_unused, 10619 struct mlx5_list_entry *entry) 10620 { 10621 struct tunnel_tbl_entry *tte = container_of(entry, typeof(*tte), hash); 10622 10623 mlx5_free(tte); 10624 } 10625 10626 static uint32_t 10627 tunnel_flow_group_to_flow_table(struct rte_eth_dev *dev, 10628 const struct mlx5_flow_tunnel *tunnel, 10629 uint32_t group, uint32_t *table, 10630 struct rte_flow_error *error) 10631 { 10632 struct mlx5_list_entry *he; 10633 struct tunnel_tbl_entry *tte; 10634 union tunnel_tbl_key key = { 10635 .tunnel_id = tunnel ? tunnel->tunnel_id : 0, 10636 .group = group 10637 }; 10638 struct mlx5_flow_tunnel_hub *thub = mlx5_tunnel_hub(dev); 10639 struct mlx5_hlist *group_hash; 10640 struct mlx5_flow_cb_ctx ctx = { 10641 .data = &key.val, 10642 }; 10643 10644 group_hash = tunnel ? tunnel->groups : thub->groups; 10645 he = mlx5_hlist_register(group_hash, key.val, &ctx); 10646 if (!he) 10647 return rte_flow_error_set(error, EINVAL, 10648 RTE_FLOW_ERROR_TYPE_ATTR_GROUP, 10649 NULL, 10650 "tunnel group index not supported"); 10651 tte = container_of(he, typeof(*tte), hash); 10652 *table = tte->flow_table; 10653 DRV_LOG(DEBUG, "port %u tunnel %u group=%#x table=%#x", 10654 dev->data->port_id, key.tunnel_id, group, *table); 10655 return 0; 10656 } 10657 10658 static void 10659 mlx5_flow_tunnel_free(struct rte_eth_dev *dev, 10660 struct mlx5_flow_tunnel *tunnel) 10661 { 10662 struct mlx5_priv *priv = dev->data->dev_private; 10663 struct mlx5_indexed_pool *ipool; 10664 10665 DRV_LOG(DEBUG, "port %u release pmd tunnel id=0x%x", 10666 dev->data->port_id, tunnel->tunnel_id); 10667 LIST_REMOVE(tunnel, chain); 10668 mlx5_hlist_destroy(tunnel->groups); 10669 ipool = priv->sh->ipool[MLX5_IPOOL_TUNNEL_ID]; 10670 mlx5_ipool_free(ipool, tunnel->tunnel_id); 10671 } 10672 10673 static bool 10674 mlx5_access_tunnel_offload_db 10675 (struct rte_eth_dev *dev, 10676 bool (*match)(struct rte_eth_dev *, 10677 struct mlx5_flow_tunnel *, const void *), 10678 void (*hit)(struct rte_eth_dev *, struct mlx5_flow_tunnel *, void *), 10679 void (*miss)(struct rte_eth_dev *, void *), 10680 void *ctx, bool lock_op) 10681 { 10682 bool verdict = false; 10683 struct mlx5_flow_tunnel_hub *thub = mlx5_tunnel_hub(dev); 10684 struct mlx5_flow_tunnel *tunnel; 10685 10686 rte_spinlock_lock(&thub->sl); 10687 LIST_FOREACH(tunnel, &thub->tunnels, chain) { 10688 verdict = match(dev, tunnel, (const void *)ctx); 10689 if (verdict) 10690 break; 10691 } 10692 if (!lock_op) 10693 rte_spinlock_unlock(&thub->sl); 10694 if (verdict && hit) 10695 hit(dev, tunnel, ctx); 10696 if (!verdict && miss) 10697 miss(dev, ctx); 10698 if (lock_op) 10699 rte_spinlock_unlock(&thub->sl); 10700 10701 return verdict; 10702 } 10703 10704 struct tunnel_db_find_tunnel_id_ctx { 10705 uint32_t tunnel_id; 10706 struct mlx5_flow_tunnel *tunnel; 10707 }; 10708 10709 static bool 10710 find_tunnel_id_match(struct rte_eth_dev *dev, 10711 struct mlx5_flow_tunnel *tunnel, const void *x) 10712 { 10713 const struct tunnel_db_find_tunnel_id_ctx *ctx = x; 10714 10715 RTE_SET_USED(dev); 10716 return tunnel->tunnel_id == ctx->tunnel_id; 10717 } 10718 10719 static void 10720 find_tunnel_id_hit(struct rte_eth_dev *dev, 10721 struct mlx5_flow_tunnel *tunnel, void *x) 10722 { 10723 struct tunnel_db_find_tunnel_id_ctx *ctx = x; 10724 RTE_SET_USED(dev); 10725 ctx->tunnel = tunnel; 10726 } 10727 10728 static struct mlx5_flow_tunnel * 10729 mlx5_find_tunnel_id(struct rte_eth_dev *dev, uint32_t id) 10730 { 10731 struct tunnel_db_find_tunnel_id_ctx ctx = { 10732 .tunnel_id = id, 10733 }; 10734 10735 mlx5_access_tunnel_offload_db(dev, find_tunnel_id_match, 10736 find_tunnel_id_hit, NULL, &ctx, true); 10737 10738 return ctx.tunnel; 10739 } 10740 10741 static struct mlx5_flow_tunnel * 10742 mlx5_flow_tunnel_allocate(struct rte_eth_dev *dev, 10743 const struct rte_flow_tunnel *app_tunnel) 10744 { 10745 struct mlx5_priv *priv = dev->data->dev_private; 10746 struct mlx5_indexed_pool *ipool; 10747 struct mlx5_flow_tunnel *tunnel; 10748 uint32_t id; 10749 10750 ipool = priv->sh->ipool[MLX5_IPOOL_TUNNEL_ID]; 10751 tunnel = mlx5_ipool_zmalloc(ipool, &id); 10752 if (!tunnel) 10753 return NULL; 10754 if (id >= MLX5_MAX_TUNNELS) { 10755 mlx5_ipool_free(ipool, id); 10756 DRV_LOG(ERR, "Tunnel ID %d exceed max limit.", id); 10757 return NULL; 10758 } 10759 tunnel->groups = mlx5_hlist_create("tunnel groups", 64, false, true, 10760 priv->sh, 10761 mlx5_flow_tunnel_grp2tbl_create_cb, 10762 mlx5_flow_tunnel_grp2tbl_match_cb, 10763 mlx5_flow_tunnel_grp2tbl_remove_cb, 10764 mlx5_flow_tunnel_grp2tbl_clone_cb, 10765 mlx5_flow_tunnel_grp2tbl_clone_free_cb); 10766 if (!tunnel->groups) { 10767 mlx5_ipool_free(ipool, id); 10768 return NULL; 10769 } 10770 /* initiate new PMD tunnel */ 10771 memcpy(&tunnel->app_tunnel, app_tunnel, sizeof(*app_tunnel)); 10772 tunnel->tunnel_id = id; 10773 tunnel->action.type = (typeof(tunnel->action.type)) 10774 MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET; 10775 tunnel->action.conf = tunnel; 10776 tunnel->item.type = (typeof(tunnel->item.type)) 10777 MLX5_RTE_FLOW_ITEM_TYPE_TUNNEL; 10778 tunnel->item.spec = tunnel; 10779 tunnel->item.last = NULL; 10780 tunnel->item.mask = NULL; 10781 10782 DRV_LOG(DEBUG, "port %u new pmd tunnel id=0x%x", 10783 dev->data->port_id, tunnel->tunnel_id); 10784 10785 return tunnel; 10786 } 10787 10788 struct tunnel_db_get_tunnel_ctx { 10789 const struct rte_flow_tunnel *app_tunnel; 10790 struct mlx5_flow_tunnel *tunnel; 10791 }; 10792 10793 static bool get_tunnel_match(struct rte_eth_dev *dev, 10794 struct mlx5_flow_tunnel *tunnel, const void *x) 10795 { 10796 const struct tunnel_db_get_tunnel_ctx *ctx = x; 10797 10798 RTE_SET_USED(dev); 10799 return !memcmp(ctx->app_tunnel, &tunnel->app_tunnel, 10800 sizeof(*ctx->app_tunnel)); 10801 } 10802 10803 static void get_tunnel_hit(struct rte_eth_dev *dev, 10804 struct mlx5_flow_tunnel *tunnel, void *x) 10805 { 10806 /* called under tunnel spinlock protection */ 10807 struct tunnel_db_get_tunnel_ctx *ctx = x; 10808 10809 RTE_SET_USED(dev); 10810 tunnel->refctn++; 10811 ctx->tunnel = tunnel; 10812 } 10813 10814 static void get_tunnel_miss(struct rte_eth_dev *dev, void *x) 10815 { 10816 /* called under tunnel spinlock protection */ 10817 struct mlx5_flow_tunnel_hub *thub = mlx5_tunnel_hub(dev); 10818 struct tunnel_db_get_tunnel_ctx *ctx = x; 10819 10820 rte_spinlock_unlock(&thub->sl); 10821 ctx->tunnel = mlx5_flow_tunnel_allocate(dev, ctx->app_tunnel); 10822 rte_spinlock_lock(&thub->sl); 10823 if (ctx->tunnel) { 10824 ctx->tunnel->refctn = 1; 10825 LIST_INSERT_HEAD(&thub->tunnels, ctx->tunnel, chain); 10826 } 10827 } 10828 10829 10830 static int 10831 mlx5_get_flow_tunnel(struct rte_eth_dev *dev, 10832 const struct rte_flow_tunnel *app_tunnel, 10833 struct mlx5_flow_tunnel **tunnel) 10834 { 10835 struct tunnel_db_get_tunnel_ctx ctx = { 10836 .app_tunnel = app_tunnel, 10837 }; 10838 10839 mlx5_access_tunnel_offload_db(dev, get_tunnel_match, get_tunnel_hit, 10840 get_tunnel_miss, &ctx, true); 10841 *tunnel = ctx.tunnel; 10842 return ctx.tunnel ? 0 : -ENOMEM; 10843 } 10844 10845 void mlx5_release_tunnel_hub(struct mlx5_dev_ctx_shared *sh, uint16_t port_id) 10846 { 10847 struct mlx5_flow_tunnel_hub *thub = sh->tunnel_hub; 10848 10849 if (!thub) 10850 return; 10851 if (!LIST_EMPTY(&thub->tunnels)) 10852 DRV_LOG(WARNING, "port %u tunnels present", port_id); 10853 mlx5_hlist_destroy(thub->groups); 10854 mlx5_free(thub); 10855 } 10856 10857 int mlx5_alloc_tunnel_hub(struct mlx5_dev_ctx_shared *sh) 10858 { 10859 int err; 10860 struct mlx5_flow_tunnel_hub *thub; 10861 10862 thub = mlx5_malloc(MLX5_MEM_SYS | MLX5_MEM_ZERO, sizeof(*thub), 10863 0, SOCKET_ID_ANY); 10864 if (!thub) 10865 return -ENOMEM; 10866 LIST_INIT(&thub->tunnels); 10867 rte_spinlock_init(&thub->sl); 10868 thub->groups = mlx5_hlist_create("flow groups", 64, 10869 false, true, sh, 10870 mlx5_flow_tunnel_grp2tbl_create_cb, 10871 mlx5_flow_tunnel_grp2tbl_match_cb, 10872 mlx5_flow_tunnel_grp2tbl_remove_cb, 10873 mlx5_flow_tunnel_grp2tbl_clone_cb, 10874 mlx5_flow_tunnel_grp2tbl_clone_free_cb); 10875 if (!thub->groups) { 10876 err = -rte_errno; 10877 goto err; 10878 } 10879 sh->tunnel_hub = thub; 10880 10881 return 0; 10882 10883 err: 10884 if (thub->groups) 10885 mlx5_hlist_destroy(thub->groups); 10886 if (thub) 10887 mlx5_free(thub); 10888 return err; 10889 } 10890 10891 static inline int 10892 mlx5_flow_tunnel_validate(struct rte_eth_dev *dev, 10893 struct rte_flow_tunnel *tunnel, 10894 struct rte_flow_error *error) 10895 { 10896 struct mlx5_priv *priv = dev->data->dev_private; 10897 10898 if (!priv->sh->config.dv_flow_en) 10899 return rte_flow_error_set(error, ENOTSUP, 10900 RTE_FLOW_ERROR_TYPE_ACTION_CONF, NULL, 10901 "flow DV interface is off"); 10902 if (!is_tunnel_offload_active(dev)) 10903 return rte_flow_error_set(error, ENOTSUP, 10904 RTE_FLOW_ERROR_TYPE_ACTION_CONF, NULL, 10905 "tunnel offload was not activated"); 10906 if (!tunnel) 10907 return rte_flow_error_set(error, EINVAL, 10908 RTE_FLOW_ERROR_TYPE_ACTION_CONF, NULL, 10909 "no application tunnel"); 10910 switch (tunnel->type) { 10911 default: 10912 return rte_flow_error_set(error, EINVAL, 10913 RTE_FLOW_ERROR_TYPE_ACTION_CONF, NULL, 10914 "unsupported tunnel type"); 10915 case RTE_FLOW_ITEM_TYPE_VXLAN: 10916 case RTE_FLOW_ITEM_TYPE_GRE: 10917 case RTE_FLOW_ITEM_TYPE_NVGRE: 10918 case RTE_FLOW_ITEM_TYPE_GENEVE: 10919 break; 10920 } 10921 return 0; 10922 } 10923 10924 static int 10925 mlx5_flow_tunnel_decap_set(struct rte_eth_dev *dev, 10926 struct rte_flow_tunnel *app_tunnel, 10927 struct rte_flow_action **actions, 10928 uint32_t *num_of_actions, 10929 struct rte_flow_error *error) 10930 { 10931 struct mlx5_flow_tunnel *tunnel; 10932 int ret = mlx5_flow_tunnel_validate(dev, app_tunnel, error); 10933 10934 if (ret) 10935 return ret; 10936 ret = mlx5_get_flow_tunnel(dev, app_tunnel, &tunnel); 10937 if (ret < 0) { 10938 return rte_flow_error_set(error, ret, 10939 RTE_FLOW_ERROR_TYPE_ACTION_CONF, NULL, 10940 "failed to initialize pmd tunnel"); 10941 } 10942 *actions = &tunnel->action; 10943 *num_of_actions = 1; 10944 return 0; 10945 } 10946 10947 static int 10948 mlx5_flow_tunnel_match(struct rte_eth_dev *dev, 10949 struct rte_flow_tunnel *app_tunnel, 10950 struct rte_flow_item **items, 10951 uint32_t *num_of_items, 10952 struct rte_flow_error *error) 10953 { 10954 struct mlx5_flow_tunnel *tunnel; 10955 int ret = mlx5_flow_tunnel_validate(dev, app_tunnel, error); 10956 10957 if (ret) 10958 return ret; 10959 ret = mlx5_get_flow_tunnel(dev, app_tunnel, &tunnel); 10960 if (ret < 0) { 10961 return rte_flow_error_set(error, ret, 10962 RTE_FLOW_ERROR_TYPE_HANDLE, NULL, 10963 "failed to initialize pmd tunnel"); 10964 } 10965 *items = &tunnel->item; 10966 *num_of_items = 1; 10967 return 0; 10968 } 10969 10970 struct tunnel_db_element_release_ctx { 10971 struct rte_flow_item *items; 10972 struct rte_flow_action *actions; 10973 uint32_t num_elements; 10974 struct rte_flow_error *error; 10975 int ret; 10976 }; 10977 10978 static bool 10979 tunnel_element_release_match(struct rte_eth_dev *dev, 10980 struct mlx5_flow_tunnel *tunnel, const void *x) 10981 { 10982 const struct tunnel_db_element_release_ctx *ctx = x; 10983 10984 RTE_SET_USED(dev); 10985 if (ctx->num_elements != 1) 10986 return false; 10987 else if (ctx->items) 10988 return ctx->items == &tunnel->item; 10989 else if (ctx->actions) 10990 return ctx->actions == &tunnel->action; 10991 10992 return false; 10993 } 10994 10995 static void 10996 tunnel_element_release_hit(struct rte_eth_dev *dev, 10997 struct mlx5_flow_tunnel *tunnel, void *x) 10998 { 10999 struct tunnel_db_element_release_ctx *ctx = x; 11000 ctx->ret = 0; 11001 if (!__atomic_sub_fetch(&tunnel->refctn, 1, __ATOMIC_RELAXED)) 11002 mlx5_flow_tunnel_free(dev, tunnel); 11003 } 11004 11005 static void 11006 tunnel_element_release_miss(struct rte_eth_dev *dev, void *x) 11007 { 11008 struct tunnel_db_element_release_ctx *ctx = x; 11009 RTE_SET_USED(dev); 11010 ctx->ret = rte_flow_error_set(ctx->error, EINVAL, 11011 RTE_FLOW_ERROR_TYPE_HANDLE, NULL, 11012 "invalid argument"); 11013 } 11014 11015 static int 11016 mlx5_flow_tunnel_item_release(struct rte_eth_dev *dev, 11017 struct rte_flow_item *pmd_items, 11018 uint32_t num_items, struct rte_flow_error *err) 11019 { 11020 struct tunnel_db_element_release_ctx ctx = { 11021 .items = pmd_items, 11022 .actions = NULL, 11023 .num_elements = num_items, 11024 .error = err, 11025 }; 11026 11027 mlx5_access_tunnel_offload_db(dev, tunnel_element_release_match, 11028 tunnel_element_release_hit, 11029 tunnel_element_release_miss, &ctx, false); 11030 11031 return ctx.ret; 11032 } 11033 11034 static int 11035 mlx5_flow_tunnel_action_release(struct rte_eth_dev *dev, 11036 struct rte_flow_action *pmd_actions, 11037 uint32_t num_actions, struct rte_flow_error *err) 11038 { 11039 struct tunnel_db_element_release_ctx ctx = { 11040 .items = NULL, 11041 .actions = pmd_actions, 11042 .num_elements = num_actions, 11043 .error = err, 11044 }; 11045 11046 mlx5_access_tunnel_offload_db(dev, tunnel_element_release_match, 11047 tunnel_element_release_hit, 11048 tunnel_element_release_miss, &ctx, false); 11049 11050 return ctx.ret; 11051 } 11052 11053 static int 11054 mlx5_flow_tunnel_get_restore_info(struct rte_eth_dev *dev, 11055 struct rte_mbuf *m, 11056 struct rte_flow_restore_info *info, 11057 struct rte_flow_error *err) 11058 { 11059 uint64_t ol_flags = m->ol_flags; 11060 const struct mlx5_flow_tbl_data_entry *tble; 11061 const uint64_t mask = RTE_MBUF_F_RX_FDIR | RTE_MBUF_F_RX_FDIR_ID; 11062 11063 if (!is_tunnel_offload_active(dev)) { 11064 info->flags = 0; 11065 return 0; 11066 } 11067 11068 if ((ol_flags & mask) != mask) 11069 goto err; 11070 tble = tunnel_mark_decode(dev, m->hash.fdir.hi); 11071 if (!tble) { 11072 DRV_LOG(DEBUG, "port %u invalid miss tunnel mark %#x", 11073 dev->data->port_id, m->hash.fdir.hi); 11074 goto err; 11075 } 11076 MLX5_ASSERT(tble->tunnel); 11077 memcpy(&info->tunnel, &tble->tunnel->app_tunnel, sizeof(info->tunnel)); 11078 info->group_id = tble->group_id; 11079 info->flags = RTE_FLOW_RESTORE_INFO_TUNNEL | 11080 RTE_FLOW_RESTORE_INFO_GROUP_ID | 11081 RTE_FLOW_RESTORE_INFO_ENCAPSULATED; 11082 11083 return 0; 11084 11085 err: 11086 return rte_flow_error_set(err, EINVAL, 11087 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, 11088 "failed to get restore info"); 11089 } 11090 11091 #else /* HAVE_IBV_FLOW_DV_SUPPORT */ 11092 static int 11093 mlx5_flow_tunnel_decap_set(__rte_unused struct rte_eth_dev *dev, 11094 __rte_unused struct rte_flow_tunnel *app_tunnel, 11095 __rte_unused struct rte_flow_action **actions, 11096 __rte_unused uint32_t *num_of_actions, 11097 __rte_unused struct rte_flow_error *error) 11098 { 11099 return -ENOTSUP; 11100 } 11101 11102 static int 11103 mlx5_flow_tunnel_match(__rte_unused struct rte_eth_dev *dev, 11104 __rte_unused struct rte_flow_tunnel *app_tunnel, 11105 __rte_unused struct rte_flow_item **items, 11106 __rte_unused uint32_t *num_of_items, 11107 __rte_unused struct rte_flow_error *error) 11108 { 11109 return -ENOTSUP; 11110 } 11111 11112 static int 11113 mlx5_flow_tunnel_item_release(__rte_unused struct rte_eth_dev *dev, 11114 __rte_unused struct rte_flow_item *pmd_items, 11115 __rte_unused uint32_t num_items, 11116 __rte_unused struct rte_flow_error *err) 11117 { 11118 return -ENOTSUP; 11119 } 11120 11121 static int 11122 mlx5_flow_tunnel_action_release(__rte_unused struct rte_eth_dev *dev, 11123 __rte_unused struct rte_flow_action *pmd_action, 11124 __rte_unused uint32_t num_actions, 11125 __rte_unused struct rte_flow_error *err) 11126 { 11127 return -ENOTSUP; 11128 } 11129 11130 static int 11131 mlx5_flow_tunnel_get_restore_info(__rte_unused struct rte_eth_dev *dev, 11132 __rte_unused struct rte_mbuf *m, 11133 __rte_unused struct rte_flow_restore_info *i, 11134 __rte_unused struct rte_flow_error *err) 11135 { 11136 return -ENOTSUP; 11137 } 11138 11139 static int 11140 flow_tunnel_add_default_miss(__rte_unused struct rte_eth_dev *dev, 11141 __rte_unused struct rte_flow *flow, 11142 __rte_unused const struct rte_flow_attr *attr, 11143 __rte_unused const struct rte_flow_action *actions, 11144 __rte_unused uint32_t flow_idx, 11145 __rte_unused const struct mlx5_flow_tunnel *tunnel, 11146 __rte_unused struct tunnel_default_miss_ctx *ctx, 11147 __rte_unused struct rte_flow_error *error) 11148 { 11149 return -ENOTSUP; 11150 } 11151 11152 static struct mlx5_flow_tunnel * 11153 mlx5_find_tunnel_id(__rte_unused struct rte_eth_dev *dev, 11154 __rte_unused uint32_t id) 11155 { 11156 return NULL; 11157 } 11158 11159 static void 11160 mlx5_flow_tunnel_free(__rte_unused struct rte_eth_dev *dev, 11161 __rte_unused struct mlx5_flow_tunnel *tunnel) 11162 { 11163 } 11164 11165 static uint32_t 11166 tunnel_flow_group_to_flow_table(__rte_unused struct rte_eth_dev *dev, 11167 __rte_unused const struct mlx5_flow_tunnel *t, 11168 __rte_unused uint32_t group, 11169 __rte_unused uint32_t *table, 11170 struct rte_flow_error *error) 11171 { 11172 return rte_flow_error_set(error, ENOTSUP, 11173 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, 11174 "tunnel offload requires DV support"); 11175 } 11176 11177 void 11178 mlx5_release_tunnel_hub(__rte_unused struct mlx5_dev_ctx_shared *sh, 11179 __rte_unused uint16_t port_id) 11180 { 11181 } 11182 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */ 11183 11184 /* Flex flow item API */ 11185 static struct rte_flow_item_flex_handle * 11186 mlx5_flow_flex_item_create(struct rte_eth_dev *dev, 11187 const struct rte_flow_item_flex_conf *conf, 11188 struct rte_flow_error *error) 11189 { 11190 static const char err_msg[] = "flex item creation unsupported"; 11191 struct mlx5_priv *priv = dev->data->dev_private; 11192 struct rte_flow_attr attr = { .transfer = 0 }; 11193 const struct mlx5_flow_driver_ops *fops = 11194 flow_get_drv_ops(flow_get_drv_type(dev, &attr)); 11195 11196 if (!priv->pci_dev) { 11197 rte_flow_error_set(error, ENOTSUP, 11198 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, 11199 "create flex item on PF only"); 11200 return NULL; 11201 } 11202 switch (priv->pci_dev->id.device_id) { 11203 case PCI_DEVICE_ID_MELLANOX_CONNECTX6DXBF: 11204 case PCI_DEVICE_ID_MELLANOX_CONNECTX7BF: 11205 break; 11206 default: 11207 rte_flow_error_set(error, ENOTSUP, 11208 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, 11209 "flex item available on BlueField ports only"); 11210 return NULL; 11211 } 11212 if (!fops->item_create) { 11213 DRV_LOG(ERR, "port %u %s.", dev->data->port_id, err_msg); 11214 rte_flow_error_set(error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION, 11215 NULL, err_msg); 11216 return NULL; 11217 } 11218 return fops->item_create(dev, conf, error); 11219 } 11220 11221 static int 11222 mlx5_flow_flex_item_release(struct rte_eth_dev *dev, 11223 const struct rte_flow_item_flex_handle *handle, 11224 struct rte_flow_error *error) 11225 { 11226 static const char err_msg[] = "flex item release unsupported"; 11227 struct rte_flow_attr attr = { .transfer = 0 }; 11228 const struct mlx5_flow_driver_ops *fops = 11229 flow_get_drv_ops(flow_get_drv_type(dev, &attr)); 11230 11231 if (!fops->item_release) { 11232 DRV_LOG(ERR, "port %u %s.", dev->data->port_id, err_msg); 11233 rte_flow_error_set(error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION, 11234 NULL, err_msg); 11235 return -rte_errno; 11236 } 11237 return fops->item_release(dev, handle, error); 11238 } 11239 11240 static void 11241 mlx5_dbg__print_pattern(const struct rte_flow_item *item) 11242 { 11243 int ret; 11244 struct rte_flow_error error; 11245 11246 for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) { 11247 char *item_name; 11248 ret = rte_flow_conv(RTE_FLOW_CONV_OP_ITEM_NAME_PTR, &item_name, 11249 sizeof(item_name), 11250 (void *)(uintptr_t)item->type, &error); 11251 if (ret > 0) 11252 printf("%s ", item_name); 11253 else 11254 printf("%d\n", (int)item->type); 11255 } 11256 printf("END\n"); 11257 } 11258 11259 static int 11260 mlx5_flow_is_std_vxlan_port(const struct rte_flow_item *udp_item) 11261 { 11262 const struct rte_flow_item_udp *spec = udp_item->spec; 11263 const struct rte_flow_item_udp *mask = udp_item->mask; 11264 uint16_t udp_dport = 0; 11265 11266 if (spec != NULL) { 11267 if (!mask) 11268 mask = &rte_flow_item_udp_mask; 11269 udp_dport = rte_be_to_cpu_16(spec->hdr.dst_port & 11270 mask->hdr.dst_port); 11271 } 11272 return (!udp_dport || udp_dport == MLX5_UDP_PORT_VXLAN); 11273 } 11274 11275 static const struct mlx5_flow_expand_node * 11276 mlx5_flow_expand_rss_adjust_node(const struct rte_flow_item *pattern, 11277 unsigned int item_idx, 11278 const struct mlx5_flow_expand_node graph[], 11279 const struct mlx5_flow_expand_node *node) 11280 { 11281 const struct rte_flow_item *item = pattern + item_idx, *prev_item; 11282 11283 if (item->type == RTE_FLOW_ITEM_TYPE_VXLAN && 11284 node != NULL && 11285 node->type == RTE_FLOW_ITEM_TYPE_VXLAN) { 11286 /* 11287 * The expansion node is VXLAN and it is also the last 11288 * expandable item in the pattern, so need to continue 11289 * expansion of the inner tunnel. 11290 */ 11291 MLX5_ASSERT(item_idx > 0); 11292 prev_item = pattern + item_idx - 1; 11293 MLX5_ASSERT(prev_item->type == RTE_FLOW_ITEM_TYPE_UDP); 11294 if (mlx5_flow_is_std_vxlan_port(prev_item)) 11295 return &graph[MLX5_EXPANSION_STD_VXLAN]; 11296 return &graph[MLX5_EXPANSION_L3_VXLAN]; 11297 } 11298 return node; 11299 } 11300 11301 /* Map of Verbs to Flow priority with 8 Verbs priorities. */ 11302 static const uint32_t priority_map_3[][MLX5_PRIORITY_MAP_MAX] = { 11303 { 0, 1, 2 }, { 2, 3, 4 }, { 5, 6, 7 }, 11304 }; 11305 11306 /* Map of Verbs to Flow priority with 16 Verbs priorities. */ 11307 static const uint32_t priority_map_5[][MLX5_PRIORITY_MAP_MAX] = { 11308 { 0, 1, 2 }, { 3, 4, 5 }, { 6, 7, 8 }, 11309 { 9, 10, 11 }, { 12, 13, 14 }, 11310 }; 11311 11312 /** 11313 * Discover the number of available flow priorities. 11314 * 11315 * @param dev 11316 * Ethernet device. 11317 * 11318 * @return 11319 * On success, number of available flow priorities. 11320 * On failure, a negative errno-style code and rte_errno is set. 11321 */ 11322 int 11323 mlx5_flow_discover_priorities(struct rte_eth_dev *dev) 11324 { 11325 static const uint16_t vprio[] = {8, 16}; 11326 const struct mlx5_priv *priv = dev->data->dev_private; 11327 const struct mlx5_flow_driver_ops *fops; 11328 enum mlx5_flow_drv_type type; 11329 int ret; 11330 11331 type = mlx5_flow_os_get_type(); 11332 if (type == MLX5_FLOW_TYPE_MAX) { 11333 type = MLX5_FLOW_TYPE_VERBS; 11334 if (priv->sh->cdev->config.devx && priv->sh->config.dv_flow_en) 11335 type = MLX5_FLOW_TYPE_DV; 11336 } 11337 fops = flow_get_drv_ops(type); 11338 if (fops->discover_priorities == NULL) { 11339 DRV_LOG(ERR, "Priority discovery not supported"); 11340 rte_errno = ENOTSUP; 11341 return -rte_errno; 11342 } 11343 ret = fops->discover_priorities(dev, vprio, RTE_DIM(vprio)); 11344 if (ret < 0) 11345 return ret; 11346 switch (ret) { 11347 case 8: 11348 ret = RTE_DIM(priority_map_3); 11349 break; 11350 case 16: 11351 ret = RTE_DIM(priority_map_5); 11352 break; 11353 default: 11354 rte_errno = ENOTSUP; 11355 DRV_LOG(ERR, 11356 "port %u maximum priority: %d expected 8/16", 11357 dev->data->port_id, ret); 11358 return -rte_errno; 11359 } 11360 DRV_LOG(INFO, "port %u supported flow priorities:" 11361 " 0-%d for ingress or egress root table," 11362 " 0-%d for non-root table or transfer root table.", 11363 dev->data->port_id, ret - 2, 11364 MLX5_NON_ROOT_FLOW_MAX_PRIO - 1); 11365 return ret; 11366 } 11367 11368 /** 11369 * Adjust flow priority based on the highest layer and the request priority. 11370 * 11371 * @param[in] dev 11372 * Pointer to the Ethernet device structure. 11373 * @param[in] priority 11374 * The rule base priority. 11375 * @param[in] subpriority 11376 * The priority based on the items. 11377 * 11378 * @return 11379 * The new priority. 11380 */ 11381 uint32_t 11382 mlx5_flow_adjust_priority(struct rte_eth_dev *dev, int32_t priority, 11383 uint32_t subpriority) 11384 { 11385 uint32_t res = 0; 11386 struct mlx5_priv *priv = dev->data->dev_private; 11387 11388 switch (priv->sh->flow_max_priority) { 11389 case RTE_DIM(priority_map_3): 11390 res = priority_map_3[priority][subpriority]; 11391 break; 11392 case RTE_DIM(priority_map_5): 11393 res = priority_map_5[priority][subpriority]; 11394 break; 11395 } 11396 return res; 11397 } 11398 11399 /** 11400 * Get the priority for sending traffic to kernel table. 11401 * 11402 * @param[in] dev 11403 * Pointer to the Ethernet device structure. 11404 * 11405 * @return 11406 * On success: the value of priority for sending traffic to kernel table 11407 * On failure: -1 11408 */ 11409 uint32_t 11410 mlx5_get_send_to_kernel_priority(struct rte_eth_dev *dev) 11411 { 11412 struct mlx5_priv *priv = dev->data->dev_private; 11413 uint32_t res; 11414 11415 switch (priv->sh->flow_max_priority) { 11416 case RTE_DIM(priority_map_5): 11417 res = 15; 11418 break; 11419 case RTE_DIM(priority_map_3): 11420 res = 7; 11421 break; 11422 default: 11423 DRV_LOG(ERR, 11424 "port %u maximum priority: %d expected 8/16", 11425 dev->data->port_id, priv->sh->flow_max_priority); 11426 res = (uint32_t)-1; 11427 } 11428 return res; 11429 } 11430 11431 /** 11432 * Get the E-Switch Manager vport id. 11433 * 11434 * @param[in] dev 11435 * Pointer to the Ethernet device structure. 11436 * 11437 * @return 11438 * The vport id. 11439 */ 11440 int16_t mlx5_flow_get_esw_manager_vport_id(struct rte_eth_dev *dev) 11441 { 11442 struct mlx5_priv *priv = dev->data->dev_private; 11443 struct mlx5_common_device *cdev = priv->sh->cdev; 11444 11445 /* New FW exposes E-Switch Manager vport ID, can use it directly. */ 11446 if (cdev->config.hca_attr.esw_mgr_vport_id_valid) 11447 return (int16_t)cdev->config.hca_attr.esw_mgr_vport_id; 11448 11449 if (priv->pci_dev == NULL) 11450 return 0; 11451 switch (priv->pci_dev->id.device_id) { 11452 case PCI_DEVICE_ID_MELLANOX_CONNECTX5BF: 11453 case PCI_DEVICE_ID_MELLANOX_CONNECTX6DXBF: 11454 case PCI_DEVICE_ID_MELLANOX_CONNECTX7BF: 11455 /* 11456 * In old FW which doesn't expose the E-Switch Manager vport ID in the capability, 11457 * only the BF embedded CPUs control the E-Switch Manager port. Hence, 11458 * ECPF vport ID is selected and not the host port (0) in any BF case. 11459 */ 11460 return (int16_t)MLX5_ECPF_VPORT_ID; 11461 default: 11462 return MLX5_PF_VPORT_ID; 11463 } 11464 } 11465 11466 /** 11467 * Parse item to get the vport id. 11468 * 11469 * @param[in] dev 11470 * Pointer to the Ethernet device structure. 11471 * @param[in] item 11472 * The src port id match item. 11473 * @param[out] vport_id 11474 * Pointer to put the vport id. 11475 * @param[out] all_ports 11476 * Indicate if the item matches all ports. 11477 * @param[out] error 11478 * Pointer to error structure. 11479 * 11480 * @return 11481 * 0 on success, a negative errno value otherwise and rte_errno is set. 11482 */ 11483 int mlx5_flow_get_item_vport_id(struct rte_eth_dev *dev, 11484 const struct rte_flow_item *item, 11485 uint16_t *vport_id, 11486 bool *all_ports, 11487 struct rte_flow_error *error) 11488 { 11489 struct mlx5_priv *port_priv; 11490 const struct rte_flow_item_port_id *pid_v = NULL; 11491 const struct rte_flow_item_ethdev *dev_v = NULL; 11492 uint32_t esw_mgr_port; 11493 uint32_t src_port; 11494 11495 if (all_ports) 11496 *all_ports = false; 11497 switch (item->type) { 11498 case RTE_FLOW_ITEM_TYPE_PORT_ID: 11499 pid_v = item->spec; 11500 if (!pid_v) 11501 return 0; 11502 src_port = pid_v->id; 11503 esw_mgr_port = MLX5_PORT_ESW_MGR; 11504 break; 11505 case RTE_FLOW_ITEM_TYPE_REPRESENTED_PORT: 11506 dev_v = item->spec; 11507 if (!dev_v) { 11508 if (all_ports) 11509 *all_ports = true; 11510 return 0; 11511 } 11512 src_port = dev_v->port_id; 11513 esw_mgr_port = MLX5_REPRESENTED_PORT_ESW_MGR; 11514 break; 11515 case RTE_FLOW_ITEM_TYPE_PORT_REPRESENTOR: 11516 src_port = MLX5_REPRESENTED_PORT_ESW_MGR; 11517 esw_mgr_port = MLX5_REPRESENTED_PORT_ESW_MGR; 11518 break; 11519 default: 11520 return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ITEM_SPEC, 11521 NULL, "Incorrect item type."); 11522 } 11523 if (src_port == esw_mgr_port) { 11524 *vport_id = mlx5_flow_get_esw_manager_vport_id(dev); 11525 } else { 11526 port_priv = mlx5_port_to_eswitch_info(src_port, false); 11527 if (!port_priv) 11528 return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ITEM_SPEC, 11529 NULL, "Failed to get port info."); 11530 *vport_id = port_priv->representor_id; 11531 } 11532 11533 return 0; 11534 } 11535 11536 int 11537 mlx5_flow_pick_transfer_proxy(struct rte_eth_dev *dev, 11538 uint16_t *proxy_port_id, 11539 struct rte_flow_error *error) 11540 { 11541 const struct mlx5_priv *priv = dev->data->dev_private; 11542 uint16_t port_id; 11543 11544 if (!priv->sh->config.dv_esw_en) 11545 return rte_flow_error_set(error, EINVAL, 11546 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, 11547 NULL, 11548 "unable to provide a proxy port" 11549 " without E-Switch configured"); 11550 if (!priv->master && !priv->representor) 11551 return rte_flow_error_set(error, EINVAL, 11552 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, 11553 NULL, 11554 "unable to provide a proxy port" 11555 " for port which is not a master" 11556 " or a representor port"); 11557 if (priv->master) { 11558 *proxy_port_id = dev->data->port_id; 11559 return 0; 11560 } 11561 MLX5_ETH_FOREACH_DEV(port_id, dev->device) { 11562 const struct rte_eth_dev *port_dev = &rte_eth_devices[port_id]; 11563 const struct mlx5_priv *port_priv = port_dev->data->dev_private; 11564 11565 if (port_priv->master && 11566 port_priv->domain_id == priv->domain_id) { 11567 *proxy_port_id = port_id; 11568 return 0; 11569 } 11570 } 11571 return rte_flow_error_set(error, ENODEV, 11572 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, 11573 NULL, "unable to find a proxy port"); 11574 } 11575