1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2016 6WIND S.A. 3 * Copyright 2016 Mellanox Technologies, Ltd 4 */ 5 6 #include <netinet/in.h> 7 #include <sys/queue.h> 8 #include <stdalign.h> 9 #include <stdint.h> 10 #include <string.h> 11 12 /* Verbs header. */ 13 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */ 14 #ifdef PEDANTIC 15 #pragma GCC diagnostic ignored "-Wpedantic" 16 #endif 17 #include <infiniband/verbs.h> 18 #ifdef PEDANTIC 19 #pragma GCC diagnostic error "-Wpedantic" 20 #endif 21 22 #include <rte_common.h> 23 #include <rte_ether.h> 24 #include <rte_ethdev_driver.h> 25 #include <rte_flow.h> 26 #include <rte_flow_driver.h> 27 #include <rte_malloc.h> 28 #include <rte_ip.h> 29 30 #include "mlx5.h" 31 #include "mlx5_defs.h" 32 #include "mlx5_flow.h" 33 #include "mlx5_glue.h" 34 #include "mlx5_prm.h" 35 #include "mlx5_rxtx.h" 36 37 /* Dev ops structure defined in mlx5.c */ 38 extern const struct eth_dev_ops mlx5_dev_ops; 39 extern const struct eth_dev_ops mlx5_dev_ops_isolate; 40 41 /** Device flow drivers. */ 42 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 43 extern const struct mlx5_flow_driver_ops mlx5_flow_dv_drv_ops; 44 #endif 45 extern const struct mlx5_flow_driver_ops mlx5_flow_verbs_drv_ops; 46 47 const struct mlx5_flow_driver_ops mlx5_flow_null_drv_ops; 48 49 const struct mlx5_flow_driver_ops *flow_drv_ops[] = { 50 [MLX5_FLOW_TYPE_MIN] = &mlx5_flow_null_drv_ops, 51 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 52 [MLX5_FLOW_TYPE_DV] = &mlx5_flow_dv_drv_ops, 53 #endif 54 [MLX5_FLOW_TYPE_VERBS] = &mlx5_flow_verbs_drv_ops, 55 [MLX5_FLOW_TYPE_MAX] = &mlx5_flow_null_drv_ops 56 }; 57 58 enum mlx5_expansion { 59 MLX5_EXPANSION_ROOT, 60 MLX5_EXPANSION_ROOT_OUTER, 61 MLX5_EXPANSION_ROOT_ETH_VLAN, 62 MLX5_EXPANSION_ROOT_OUTER_ETH_VLAN, 63 MLX5_EXPANSION_OUTER_ETH, 64 MLX5_EXPANSION_OUTER_ETH_VLAN, 65 MLX5_EXPANSION_OUTER_VLAN, 66 MLX5_EXPANSION_OUTER_IPV4, 67 MLX5_EXPANSION_OUTER_IPV4_UDP, 68 MLX5_EXPANSION_OUTER_IPV4_TCP, 69 MLX5_EXPANSION_OUTER_IPV6, 70 MLX5_EXPANSION_OUTER_IPV6_UDP, 71 MLX5_EXPANSION_OUTER_IPV6_TCP, 72 MLX5_EXPANSION_VXLAN, 73 MLX5_EXPANSION_VXLAN_GPE, 74 MLX5_EXPANSION_GRE, 75 MLX5_EXPANSION_MPLS, 76 MLX5_EXPANSION_ETH, 77 MLX5_EXPANSION_ETH_VLAN, 78 MLX5_EXPANSION_VLAN, 79 MLX5_EXPANSION_IPV4, 80 MLX5_EXPANSION_IPV4_UDP, 81 MLX5_EXPANSION_IPV4_TCP, 82 MLX5_EXPANSION_IPV6, 83 MLX5_EXPANSION_IPV6_UDP, 84 MLX5_EXPANSION_IPV6_TCP, 85 }; 86 87 /** Supported expansion of items. */ 88 static const struct rte_flow_expand_node mlx5_support_expansion[] = { 89 [MLX5_EXPANSION_ROOT] = { 90 .next = RTE_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_ETH, 91 MLX5_EXPANSION_IPV4, 92 MLX5_EXPANSION_IPV6), 93 .type = RTE_FLOW_ITEM_TYPE_END, 94 }, 95 [MLX5_EXPANSION_ROOT_OUTER] = { 96 .next = RTE_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_OUTER_ETH, 97 MLX5_EXPANSION_OUTER_IPV4, 98 MLX5_EXPANSION_OUTER_IPV6), 99 .type = RTE_FLOW_ITEM_TYPE_END, 100 }, 101 [MLX5_EXPANSION_ROOT_ETH_VLAN] = { 102 .next = RTE_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_ETH_VLAN), 103 .type = RTE_FLOW_ITEM_TYPE_END, 104 }, 105 [MLX5_EXPANSION_ROOT_OUTER_ETH_VLAN] = { 106 .next = RTE_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_OUTER_ETH_VLAN), 107 .type = RTE_FLOW_ITEM_TYPE_END, 108 }, 109 [MLX5_EXPANSION_OUTER_ETH] = { 110 .next = RTE_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_OUTER_IPV4, 111 MLX5_EXPANSION_OUTER_IPV6, 112 MLX5_EXPANSION_MPLS), 113 .type = RTE_FLOW_ITEM_TYPE_ETH, 114 .rss_types = 0, 115 }, 116 [MLX5_EXPANSION_OUTER_ETH_VLAN] = { 117 .next = RTE_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_OUTER_VLAN), 118 .type = RTE_FLOW_ITEM_TYPE_ETH, 119 .rss_types = 0, 120 }, 121 [MLX5_EXPANSION_OUTER_VLAN] = { 122 .next = RTE_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_OUTER_IPV4, 123 MLX5_EXPANSION_OUTER_IPV6), 124 .type = RTE_FLOW_ITEM_TYPE_VLAN, 125 }, 126 [MLX5_EXPANSION_OUTER_IPV4] = { 127 .next = RTE_FLOW_EXPAND_RSS_NEXT 128 (MLX5_EXPANSION_OUTER_IPV4_UDP, 129 MLX5_EXPANSION_OUTER_IPV4_TCP, 130 MLX5_EXPANSION_GRE, 131 MLX5_EXPANSION_IPV4, 132 MLX5_EXPANSION_IPV6), 133 .type = RTE_FLOW_ITEM_TYPE_IPV4, 134 .rss_types = ETH_RSS_IPV4 | ETH_RSS_FRAG_IPV4 | 135 ETH_RSS_NONFRAG_IPV4_OTHER, 136 }, 137 [MLX5_EXPANSION_OUTER_IPV4_UDP] = { 138 .next = RTE_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_VXLAN, 139 MLX5_EXPANSION_VXLAN_GPE), 140 .type = RTE_FLOW_ITEM_TYPE_UDP, 141 .rss_types = ETH_RSS_NONFRAG_IPV4_UDP, 142 }, 143 [MLX5_EXPANSION_OUTER_IPV4_TCP] = { 144 .type = RTE_FLOW_ITEM_TYPE_TCP, 145 .rss_types = ETH_RSS_NONFRAG_IPV4_TCP, 146 }, 147 [MLX5_EXPANSION_OUTER_IPV6] = { 148 .next = RTE_FLOW_EXPAND_RSS_NEXT 149 (MLX5_EXPANSION_OUTER_IPV6_UDP, 150 MLX5_EXPANSION_OUTER_IPV6_TCP, 151 MLX5_EXPANSION_IPV4, 152 MLX5_EXPANSION_IPV6), 153 .type = RTE_FLOW_ITEM_TYPE_IPV6, 154 .rss_types = ETH_RSS_IPV6 | ETH_RSS_FRAG_IPV6 | 155 ETH_RSS_NONFRAG_IPV6_OTHER, 156 }, 157 [MLX5_EXPANSION_OUTER_IPV6_UDP] = { 158 .next = RTE_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_VXLAN, 159 MLX5_EXPANSION_VXLAN_GPE), 160 .type = RTE_FLOW_ITEM_TYPE_UDP, 161 .rss_types = ETH_RSS_NONFRAG_IPV6_UDP, 162 }, 163 [MLX5_EXPANSION_OUTER_IPV6_TCP] = { 164 .type = RTE_FLOW_ITEM_TYPE_TCP, 165 .rss_types = ETH_RSS_NONFRAG_IPV6_TCP, 166 }, 167 [MLX5_EXPANSION_VXLAN] = { 168 .next = RTE_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_ETH), 169 .type = RTE_FLOW_ITEM_TYPE_VXLAN, 170 }, 171 [MLX5_EXPANSION_VXLAN_GPE] = { 172 .next = RTE_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_ETH, 173 MLX5_EXPANSION_IPV4, 174 MLX5_EXPANSION_IPV6), 175 .type = RTE_FLOW_ITEM_TYPE_VXLAN_GPE, 176 }, 177 [MLX5_EXPANSION_GRE] = { 178 .next = RTE_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_IPV4), 179 .type = RTE_FLOW_ITEM_TYPE_GRE, 180 }, 181 [MLX5_EXPANSION_MPLS] = { 182 .next = RTE_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_IPV4, 183 MLX5_EXPANSION_IPV6), 184 .type = RTE_FLOW_ITEM_TYPE_MPLS, 185 }, 186 [MLX5_EXPANSION_ETH] = { 187 .next = RTE_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_IPV4, 188 MLX5_EXPANSION_IPV6), 189 .type = RTE_FLOW_ITEM_TYPE_ETH, 190 }, 191 [MLX5_EXPANSION_ETH_VLAN] = { 192 .next = RTE_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_VLAN), 193 .type = RTE_FLOW_ITEM_TYPE_ETH, 194 }, 195 [MLX5_EXPANSION_VLAN] = { 196 .next = RTE_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_IPV4, 197 MLX5_EXPANSION_IPV6), 198 .type = RTE_FLOW_ITEM_TYPE_VLAN, 199 }, 200 [MLX5_EXPANSION_IPV4] = { 201 .next = RTE_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_IPV4_UDP, 202 MLX5_EXPANSION_IPV4_TCP), 203 .type = RTE_FLOW_ITEM_TYPE_IPV4, 204 .rss_types = ETH_RSS_IPV4 | ETH_RSS_FRAG_IPV4 | 205 ETH_RSS_NONFRAG_IPV4_OTHER, 206 }, 207 [MLX5_EXPANSION_IPV4_UDP] = { 208 .type = RTE_FLOW_ITEM_TYPE_UDP, 209 .rss_types = ETH_RSS_NONFRAG_IPV4_UDP, 210 }, 211 [MLX5_EXPANSION_IPV4_TCP] = { 212 .type = RTE_FLOW_ITEM_TYPE_TCP, 213 .rss_types = ETH_RSS_NONFRAG_IPV4_TCP, 214 }, 215 [MLX5_EXPANSION_IPV6] = { 216 .next = RTE_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_IPV6_UDP, 217 MLX5_EXPANSION_IPV6_TCP), 218 .type = RTE_FLOW_ITEM_TYPE_IPV6, 219 .rss_types = ETH_RSS_IPV6 | ETH_RSS_FRAG_IPV6 | 220 ETH_RSS_NONFRAG_IPV6_OTHER, 221 }, 222 [MLX5_EXPANSION_IPV6_UDP] = { 223 .type = RTE_FLOW_ITEM_TYPE_UDP, 224 .rss_types = ETH_RSS_NONFRAG_IPV6_UDP, 225 }, 226 [MLX5_EXPANSION_IPV6_TCP] = { 227 .type = RTE_FLOW_ITEM_TYPE_TCP, 228 .rss_types = ETH_RSS_NONFRAG_IPV6_TCP, 229 }, 230 }; 231 232 static const struct rte_flow_ops mlx5_flow_ops = { 233 .validate = mlx5_flow_validate, 234 .create = mlx5_flow_create, 235 .destroy = mlx5_flow_destroy, 236 .flush = mlx5_flow_flush, 237 .isolate = mlx5_flow_isolate, 238 .query = mlx5_flow_query, 239 }; 240 241 /* Convert FDIR request to Generic flow. */ 242 struct mlx5_fdir { 243 struct rte_flow_attr attr; 244 struct rte_flow_item items[4]; 245 struct rte_flow_item_eth l2; 246 struct rte_flow_item_eth l2_mask; 247 union { 248 struct rte_flow_item_ipv4 ipv4; 249 struct rte_flow_item_ipv6 ipv6; 250 } l3; 251 union { 252 struct rte_flow_item_ipv4 ipv4; 253 struct rte_flow_item_ipv6 ipv6; 254 } l3_mask; 255 union { 256 struct rte_flow_item_udp udp; 257 struct rte_flow_item_tcp tcp; 258 } l4; 259 union { 260 struct rte_flow_item_udp udp; 261 struct rte_flow_item_tcp tcp; 262 } l4_mask; 263 struct rte_flow_action actions[2]; 264 struct rte_flow_action_queue queue; 265 }; 266 267 /* Map of Verbs to Flow priority with 8 Verbs priorities. */ 268 static const uint32_t priority_map_3[][MLX5_PRIORITY_MAP_MAX] = { 269 { 0, 1, 2 }, { 2, 3, 4 }, { 5, 6, 7 }, 270 }; 271 272 /* Map of Verbs to Flow priority with 16 Verbs priorities. */ 273 static const uint32_t priority_map_5[][MLX5_PRIORITY_MAP_MAX] = { 274 { 0, 1, 2 }, { 3, 4, 5 }, { 6, 7, 8 }, 275 { 9, 10, 11 }, { 12, 13, 14 }, 276 }; 277 278 /* Tunnel information. */ 279 struct mlx5_flow_tunnel_info { 280 uint64_t tunnel; /**< Tunnel bit (see MLX5_FLOW_*). */ 281 uint32_t ptype; /**< Tunnel Ptype (see RTE_PTYPE_*). */ 282 }; 283 284 static struct mlx5_flow_tunnel_info tunnels_info[] = { 285 { 286 .tunnel = MLX5_FLOW_LAYER_VXLAN, 287 .ptype = RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_L4_UDP, 288 }, 289 { 290 .tunnel = MLX5_FLOW_LAYER_VXLAN_GPE, 291 .ptype = RTE_PTYPE_TUNNEL_VXLAN_GPE | RTE_PTYPE_L4_UDP, 292 }, 293 { 294 .tunnel = MLX5_FLOW_LAYER_GRE, 295 .ptype = RTE_PTYPE_TUNNEL_GRE, 296 }, 297 { 298 .tunnel = MLX5_FLOW_LAYER_MPLS | MLX5_FLOW_LAYER_OUTER_L4_UDP, 299 .ptype = RTE_PTYPE_TUNNEL_MPLS_IN_UDP | RTE_PTYPE_L4_UDP, 300 }, 301 { 302 .tunnel = MLX5_FLOW_LAYER_MPLS, 303 .ptype = RTE_PTYPE_TUNNEL_MPLS_IN_GRE, 304 }, 305 { 306 .tunnel = MLX5_FLOW_LAYER_NVGRE, 307 .ptype = RTE_PTYPE_TUNNEL_NVGRE, 308 }, 309 { 310 .tunnel = MLX5_FLOW_LAYER_IPIP, 311 .ptype = RTE_PTYPE_TUNNEL_IP, 312 }, 313 { 314 .tunnel = MLX5_FLOW_LAYER_IPV6_ENCAP, 315 .ptype = RTE_PTYPE_TUNNEL_IP, 316 }, 317 }; 318 319 /** 320 * Discover the maximum number of priority available. 321 * 322 * @param[in] dev 323 * Pointer to the Ethernet device structure. 324 * 325 * @return 326 * number of supported flow priority on success, a negative errno 327 * value otherwise and rte_errno is set. 328 */ 329 int 330 mlx5_flow_discover_priorities(struct rte_eth_dev *dev) 331 { 332 struct mlx5_priv *priv = dev->data->dev_private; 333 struct { 334 struct ibv_flow_attr attr; 335 struct ibv_flow_spec_eth eth; 336 struct ibv_flow_spec_action_drop drop; 337 } flow_attr = { 338 .attr = { 339 .num_of_specs = 2, 340 .port = (uint8_t)priv->ibv_port, 341 }, 342 .eth = { 343 .type = IBV_FLOW_SPEC_ETH, 344 .size = sizeof(struct ibv_flow_spec_eth), 345 }, 346 .drop = { 347 .size = sizeof(struct ibv_flow_spec_action_drop), 348 .type = IBV_FLOW_SPEC_ACTION_DROP, 349 }, 350 }; 351 struct ibv_flow *flow; 352 struct mlx5_hrxq *drop = mlx5_hrxq_drop_new(dev); 353 uint16_t vprio[] = { 8, 16 }; 354 int i; 355 int priority = 0; 356 357 if (!drop) { 358 rte_errno = ENOTSUP; 359 return -rte_errno; 360 } 361 for (i = 0; i != RTE_DIM(vprio); i++) { 362 flow_attr.attr.priority = vprio[i] - 1; 363 flow = mlx5_glue->create_flow(drop->qp, &flow_attr.attr); 364 if (!flow) 365 break; 366 claim_zero(mlx5_glue->destroy_flow(flow)); 367 priority = vprio[i]; 368 } 369 mlx5_hrxq_drop_release(dev); 370 switch (priority) { 371 case 8: 372 priority = RTE_DIM(priority_map_3); 373 break; 374 case 16: 375 priority = RTE_DIM(priority_map_5); 376 break; 377 default: 378 rte_errno = ENOTSUP; 379 DRV_LOG(ERR, 380 "port %u verbs maximum priority: %d expected 8/16", 381 dev->data->port_id, priority); 382 return -rte_errno; 383 } 384 DRV_LOG(INFO, "port %u flow maximum priority: %d", 385 dev->data->port_id, priority); 386 return priority; 387 } 388 389 /** 390 * Adjust flow priority based on the highest layer and the request priority. 391 * 392 * @param[in] dev 393 * Pointer to the Ethernet device structure. 394 * @param[in] priority 395 * The rule base priority. 396 * @param[in] subpriority 397 * The priority based on the items. 398 * 399 * @return 400 * The new priority. 401 */ 402 uint32_t mlx5_flow_adjust_priority(struct rte_eth_dev *dev, int32_t priority, 403 uint32_t subpriority) 404 { 405 uint32_t res = 0; 406 struct mlx5_priv *priv = dev->data->dev_private; 407 408 switch (priv->config.flow_prio) { 409 case RTE_DIM(priority_map_3): 410 res = priority_map_3[priority][subpriority]; 411 break; 412 case RTE_DIM(priority_map_5): 413 res = priority_map_5[priority][subpriority]; 414 break; 415 } 416 return res; 417 } 418 419 /** 420 * Verify the @p item specifications (spec, last, mask) are compatible with the 421 * NIC capabilities. 422 * 423 * @param[in] item 424 * Item specification. 425 * @param[in] mask 426 * @p item->mask or flow default bit-masks. 427 * @param[in] nic_mask 428 * Bit-masks covering supported fields by the NIC to compare with user mask. 429 * @param[in] size 430 * Bit-masks size in bytes. 431 * @param[out] error 432 * Pointer to error structure. 433 * 434 * @return 435 * 0 on success, a negative errno value otherwise and rte_errno is set. 436 */ 437 int 438 mlx5_flow_item_acceptable(const struct rte_flow_item *item, 439 const uint8_t *mask, 440 const uint8_t *nic_mask, 441 unsigned int size, 442 struct rte_flow_error *error) 443 { 444 unsigned int i; 445 446 assert(nic_mask); 447 for (i = 0; i < size; ++i) 448 if ((nic_mask[i] | mask[i]) != nic_mask[i]) 449 return rte_flow_error_set(error, ENOTSUP, 450 RTE_FLOW_ERROR_TYPE_ITEM, 451 item, 452 "mask enables non supported" 453 " bits"); 454 if (!item->spec && (item->mask || item->last)) 455 return rte_flow_error_set(error, EINVAL, 456 RTE_FLOW_ERROR_TYPE_ITEM, item, 457 "mask/last without a spec is not" 458 " supported"); 459 if (item->spec && item->last) { 460 uint8_t spec[size]; 461 uint8_t last[size]; 462 unsigned int i; 463 int ret; 464 465 for (i = 0; i < size; ++i) { 466 spec[i] = ((const uint8_t *)item->spec)[i] & mask[i]; 467 last[i] = ((const uint8_t *)item->last)[i] & mask[i]; 468 } 469 ret = memcmp(spec, last, size); 470 if (ret != 0) 471 return rte_flow_error_set(error, EINVAL, 472 RTE_FLOW_ERROR_TYPE_ITEM, 473 item, 474 "range is not valid"); 475 } 476 return 0; 477 } 478 479 /** 480 * Adjust the hash fields according to the @p flow information. 481 * 482 * @param[in] dev_flow. 483 * Pointer to the mlx5_flow. 484 * @param[in] tunnel 485 * 1 when the hash field is for a tunnel item. 486 * @param[in] layer_types 487 * ETH_RSS_* types. 488 * @param[in] hash_fields 489 * Item hash fields. 490 * 491 * @return 492 * The hash fields that should be used. 493 */ 494 uint64_t 495 mlx5_flow_hashfields_adjust(struct mlx5_flow *dev_flow, 496 int tunnel __rte_unused, uint64_t layer_types, 497 uint64_t hash_fields) 498 { 499 struct rte_flow *flow = dev_flow->flow; 500 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT 501 int rss_request_inner = flow->rss.level >= 2; 502 503 /* Check RSS hash level for tunnel. */ 504 if (tunnel && rss_request_inner) 505 hash_fields |= IBV_RX_HASH_INNER; 506 else if (tunnel || rss_request_inner) 507 return 0; 508 #endif 509 /* Check if requested layer matches RSS hash fields. */ 510 if (!(flow->rss.types & layer_types)) 511 return 0; 512 return hash_fields; 513 } 514 515 /** 516 * Lookup and set the ptype in the data Rx part. A single Ptype can be used, 517 * if several tunnel rules are used on this queue, the tunnel ptype will be 518 * cleared. 519 * 520 * @param rxq_ctrl 521 * Rx queue to update. 522 */ 523 static void 524 flow_rxq_tunnel_ptype_update(struct mlx5_rxq_ctrl *rxq_ctrl) 525 { 526 unsigned int i; 527 uint32_t tunnel_ptype = 0; 528 529 /* Look up for the ptype to use. */ 530 for (i = 0; i != MLX5_FLOW_TUNNEL; ++i) { 531 if (!rxq_ctrl->flow_tunnels_n[i]) 532 continue; 533 if (!tunnel_ptype) { 534 tunnel_ptype = tunnels_info[i].ptype; 535 } else { 536 tunnel_ptype = 0; 537 break; 538 } 539 } 540 rxq_ctrl->rxq.tunnel = tunnel_ptype; 541 } 542 543 /** 544 * Set the Rx queue flags (Mark/Flag and Tunnel Ptypes) according to the devive 545 * flow. 546 * 547 * @param[in] dev 548 * Pointer to the Ethernet device structure. 549 * @param[in] dev_flow 550 * Pointer to device flow structure. 551 */ 552 static void 553 flow_drv_rxq_flags_set(struct rte_eth_dev *dev, struct mlx5_flow *dev_flow) 554 { 555 struct mlx5_priv *priv = dev->data->dev_private; 556 struct rte_flow *flow = dev_flow->flow; 557 const int mark = !!(flow->actions & 558 (MLX5_FLOW_ACTION_FLAG | MLX5_FLOW_ACTION_MARK)); 559 const int tunnel = !!(dev_flow->layers & MLX5_FLOW_LAYER_TUNNEL); 560 unsigned int i; 561 562 for (i = 0; i != flow->rss.queue_num; ++i) { 563 int idx = (*flow->queue)[i]; 564 struct mlx5_rxq_ctrl *rxq_ctrl = 565 container_of((*priv->rxqs)[idx], 566 struct mlx5_rxq_ctrl, rxq); 567 568 if (mark) { 569 rxq_ctrl->rxq.mark = 1; 570 rxq_ctrl->flow_mark_n++; 571 } 572 if (tunnel) { 573 unsigned int j; 574 575 /* Increase the counter matching the flow. */ 576 for (j = 0; j != MLX5_FLOW_TUNNEL; ++j) { 577 if ((tunnels_info[j].tunnel & 578 dev_flow->layers) == 579 tunnels_info[j].tunnel) { 580 rxq_ctrl->flow_tunnels_n[j]++; 581 break; 582 } 583 } 584 flow_rxq_tunnel_ptype_update(rxq_ctrl); 585 } 586 } 587 } 588 589 /** 590 * Set the Rx queue flags (Mark/Flag and Tunnel Ptypes) for a flow 591 * 592 * @param[in] dev 593 * Pointer to the Ethernet device structure. 594 * @param[in] flow 595 * Pointer to flow structure. 596 */ 597 static void 598 flow_rxq_flags_set(struct rte_eth_dev *dev, struct rte_flow *flow) 599 { 600 struct mlx5_flow *dev_flow; 601 602 LIST_FOREACH(dev_flow, &flow->dev_flows, next) 603 flow_drv_rxq_flags_set(dev, dev_flow); 604 } 605 606 /** 607 * Clear the Rx queue flags (Mark/Flag and Tunnel Ptype) associated with the 608 * device flow if no other flow uses it with the same kind of request. 609 * 610 * @param dev 611 * Pointer to Ethernet device. 612 * @param[in] dev_flow 613 * Pointer to the device flow. 614 */ 615 static void 616 flow_drv_rxq_flags_trim(struct rte_eth_dev *dev, struct mlx5_flow *dev_flow) 617 { 618 struct mlx5_priv *priv = dev->data->dev_private; 619 struct rte_flow *flow = dev_flow->flow; 620 const int mark = !!(flow->actions & 621 (MLX5_FLOW_ACTION_FLAG | MLX5_FLOW_ACTION_MARK)); 622 const int tunnel = !!(dev_flow->layers & MLX5_FLOW_LAYER_TUNNEL); 623 unsigned int i; 624 625 assert(dev->data->dev_started); 626 for (i = 0; i != flow->rss.queue_num; ++i) { 627 int idx = (*flow->queue)[i]; 628 struct mlx5_rxq_ctrl *rxq_ctrl = 629 container_of((*priv->rxqs)[idx], 630 struct mlx5_rxq_ctrl, rxq); 631 632 if (mark) { 633 rxq_ctrl->flow_mark_n--; 634 rxq_ctrl->rxq.mark = !!rxq_ctrl->flow_mark_n; 635 } 636 if (tunnel) { 637 unsigned int j; 638 639 /* Decrease the counter matching the flow. */ 640 for (j = 0; j != MLX5_FLOW_TUNNEL; ++j) { 641 if ((tunnels_info[j].tunnel & 642 dev_flow->layers) == 643 tunnels_info[j].tunnel) { 644 rxq_ctrl->flow_tunnels_n[j]--; 645 break; 646 } 647 } 648 flow_rxq_tunnel_ptype_update(rxq_ctrl); 649 } 650 } 651 } 652 653 /** 654 * Clear the Rx queue flags (Mark/Flag and Tunnel Ptype) associated with the 655 * @p flow if no other flow uses it with the same kind of request. 656 * 657 * @param dev 658 * Pointer to Ethernet device. 659 * @param[in] flow 660 * Pointer to the flow. 661 */ 662 static void 663 flow_rxq_flags_trim(struct rte_eth_dev *dev, struct rte_flow *flow) 664 { 665 struct mlx5_flow *dev_flow; 666 667 LIST_FOREACH(dev_flow, &flow->dev_flows, next) 668 flow_drv_rxq_flags_trim(dev, dev_flow); 669 } 670 671 /** 672 * Clear the Mark/Flag and Tunnel ptype information in all Rx queues. 673 * 674 * @param dev 675 * Pointer to Ethernet device. 676 */ 677 static void 678 flow_rxq_flags_clear(struct rte_eth_dev *dev) 679 { 680 struct mlx5_priv *priv = dev->data->dev_private; 681 unsigned int i; 682 683 for (i = 0; i != priv->rxqs_n; ++i) { 684 struct mlx5_rxq_ctrl *rxq_ctrl; 685 unsigned int j; 686 687 if (!(*priv->rxqs)[i]) 688 continue; 689 rxq_ctrl = container_of((*priv->rxqs)[i], 690 struct mlx5_rxq_ctrl, rxq); 691 rxq_ctrl->flow_mark_n = 0; 692 rxq_ctrl->rxq.mark = 0; 693 for (j = 0; j != MLX5_FLOW_TUNNEL; ++j) 694 rxq_ctrl->flow_tunnels_n[j] = 0; 695 rxq_ctrl->rxq.tunnel = 0; 696 } 697 } 698 699 /* 700 * return a pointer to the desired action in the list of actions. 701 * 702 * @param[in] actions 703 * The list of actions to search the action in. 704 * @param[in] action 705 * The action to find. 706 * 707 * @return 708 * Pointer to the action in the list, if found. NULL otherwise. 709 */ 710 const struct rte_flow_action * 711 mlx5_flow_find_action(const struct rte_flow_action *actions, 712 enum rte_flow_action_type action) 713 { 714 if (actions == NULL) 715 return NULL; 716 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) 717 if (actions->type == action) 718 return actions; 719 return NULL; 720 } 721 722 /* 723 * Validate the flag action. 724 * 725 * @param[in] action_flags 726 * Bit-fields that holds the actions detected until now. 727 * @param[in] attr 728 * Attributes of flow that includes this action. 729 * @param[out] error 730 * Pointer to error structure. 731 * 732 * @return 733 * 0 on success, a negative errno value otherwise and rte_errno is set. 734 */ 735 int 736 mlx5_flow_validate_action_flag(uint64_t action_flags, 737 const struct rte_flow_attr *attr, 738 struct rte_flow_error *error) 739 { 740 741 if (action_flags & MLX5_FLOW_ACTION_DROP) 742 return rte_flow_error_set(error, EINVAL, 743 RTE_FLOW_ERROR_TYPE_ACTION, NULL, 744 "can't drop and flag in same flow"); 745 if (action_flags & MLX5_FLOW_ACTION_MARK) 746 return rte_flow_error_set(error, EINVAL, 747 RTE_FLOW_ERROR_TYPE_ACTION, NULL, 748 "can't mark and flag in same flow"); 749 if (action_flags & MLX5_FLOW_ACTION_FLAG) 750 return rte_flow_error_set(error, EINVAL, 751 RTE_FLOW_ERROR_TYPE_ACTION, NULL, 752 "can't have 2 flag" 753 " actions in same flow"); 754 if (attr->egress) 755 return rte_flow_error_set(error, ENOTSUP, 756 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, NULL, 757 "flag action not supported for " 758 "egress"); 759 return 0; 760 } 761 762 /* 763 * Validate the mark action. 764 * 765 * @param[in] action 766 * Pointer to the queue action. 767 * @param[in] action_flags 768 * Bit-fields that holds the actions detected until now. 769 * @param[in] attr 770 * Attributes of flow that includes this action. 771 * @param[out] error 772 * Pointer to error structure. 773 * 774 * @return 775 * 0 on success, a negative errno value otherwise and rte_errno is set. 776 */ 777 int 778 mlx5_flow_validate_action_mark(const struct rte_flow_action *action, 779 uint64_t action_flags, 780 const struct rte_flow_attr *attr, 781 struct rte_flow_error *error) 782 { 783 const struct rte_flow_action_mark *mark = action->conf; 784 785 if (!mark) 786 return rte_flow_error_set(error, EINVAL, 787 RTE_FLOW_ERROR_TYPE_ACTION, 788 action, 789 "configuration cannot be null"); 790 if (mark->id >= MLX5_FLOW_MARK_MAX) 791 return rte_flow_error_set(error, EINVAL, 792 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 793 &mark->id, 794 "mark id must in 0 <= id < " 795 RTE_STR(MLX5_FLOW_MARK_MAX)); 796 if (action_flags & MLX5_FLOW_ACTION_DROP) 797 return rte_flow_error_set(error, EINVAL, 798 RTE_FLOW_ERROR_TYPE_ACTION, NULL, 799 "can't drop and mark in same flow"); 800 if (action_flags & MLX5_FLOW_ACTION_FLAG) 801 return rte_flow_error_set(error, EINVAL, 802 RTE_FLOW_ERROR_TYPE_ACTION, NULL, 803 "can't flag and mark in same flow"); 804 if (action_flags & MLX5_FLOW_ACTION_MARK) 805 return rte_flow_error_set(error, EINVAL, 806 RTE_FLOW_ERROR_TYPE_ACTION, NULL, 807 "can't have 2 mark actions in same" 808 " flow"); 809 if (attr->egress) 810 return rte_flow_error_set(error, ENOTSUP, 811 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, NULL, 812 "mark action not supported for " 813 "egress"); 814 return 0; 815 } 816 817 /* 818 * Validate the drop action. 819 * 820 * @param[in] action_flags 821 * Bit-fields that holds the actions detected until now. 822 * @param[in] attr 823 * Attributes of flow that includes this action. 824 * @param[out] error 825 * Pointer to error structure. 826 * 827 * @return 828 * 0 on success, a negative errno value otherwise and rte_errno is set. 829 */ 830 int 831 mlx5_flow_validate_action_drop(uint64_t action_flags, 832 const struct rte_flow_attr *attr, 833 struct rte_flow_error *error) 834 { 835 if (action_flags & MLX5_FLOW_ACTION_FLAG) 836 return rte_flow_error_set(error, EINVAL, 837 RTE_FLOW_ERROR_TYPE_ACTION, NULL, 838 "can't drop and flag in same flow"); 839 if (action_flags & MLX5_FLOW_ACTION_MARK) 840 return rte_flow_error_set(error, EINVAL, 841 RTE_FLOW_ERROR_TYPE_ACTION, NULL, 842 "can't drop and mark in same flow"); 843 if (action_flags & (MLX5_FLOW_FATE_ACTIONS | 844 MLX5_FLOW_FATE_ESWITCH_ACTIONS)) 845 return rte_flow_error_set(error, EINVAL, 846 RTE_FLOW_ERROR_TYPE_ACTION, NULL, 847 "can't have 2 fate actions in" 848 " same flow"); 849 if (attr->egress) 850 return rte_flow_error_set(error, ENOTSUP, 851 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, NULL, 852 "drop action not supported for " 853 "egress"); 854 return 0; 855 } 856 857 /* 858 * Validate the queue action. 859 * 860 * @param[in] action 861 * Pointer to the queue action. 862 * @param[in] action_flags 863 * Bit-fields that holds the actions detected until now. 864 * @param[in] dev 865 * Pointer to the Ethernet device structure. 866 * @param[in] attr 867 * Attributes of flow that includes this action. 868 * @param[out] error 869 * Pointer to error structure. 870 * 871 * @return 872 * 0 on success, a negative errno value otherwise and rte_errno is set. 873 */ 874 int 875 mlx5_flow_validate_action_queue(const struct rte_flow_action *action, 876 uint64_t action_flags, 877 struct rte_eth_dev *dev, 878 const struct rte_flow_attr *attr, 879 struct rte_flow_error *error) 880 { 881 struct mlx5_priv *priv = dev->data->dev_private; 882 const struct rte_flow_action_queue *queue = action->conf; 883 884 if (action_flags & MLX5_FLOW_FATE_ACTIONS) 885 return rte_flow_error_set(error, EINVAL, 886 RTE_FLOW_ERROR_TYPE_ACTION, NULL, 887 "can't have 2 fate actions in" 888 " same flow"); 889 if (!priv->rxqs_n) 890 return rte_flow_error_set(error, EINVAL, 891 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 892 NULL, "No Rx queues configured"); 893 if (queue->index >= priv->rxqs_n) 894 return rte_flow_error_set(error, EINVAL, 895 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 896 &queue->index, 897 "queue index out of range"); 898 if (!(*priv->rxqs)[queue->index]) 899 return rte_flow_error_set(error, EINVAL, 900 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 901 &queue->index, 902 "queue is not configured"); 903 if (attr->egress) 904 return rte_flow_error_set(error, ENOTSUP, 905 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, NULL, 906 "queue action not supported for " 907 "egress"); 908 return 0; 909 } 910 911 /* 912 * Validate the rss action. 913 * 914 * @param[in] action 915 * Pointer to the queue action. 916 * @param[in] action_flags 917 * Bit-fields that holds the actions detected until now. 918 * @param[in] dev 919 * Pointer to the Ethernet device structure. 920 * @param[in] attr 921 * Attributes of flow that includes this action. 922 * @param[in] item_flags 923 * Items that were detected. 924 * @param[out] error 925 * Pointer to error structure. 926 * 927 * @return 928 * 0 on success, a negative errno value otherwise and rte_errno is set. 929 */ 930 int 931 mlx5_flow_validate_action_rss(const struct rte_flow_action *action, 932 uint64_t action_flags, 933 struct rte_eth_dev *dev, 934 const struct rte_flow_attr *attr, 935 uint64_t item_flags, 936 struct rte_flow_error *error) 937 { 938 struct mlx5_priv *priv = dev->data->dev_private; 939 const struct rte_flow_action_rss *rss = action->conf; 940 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL); 941 unsigned int i; 942 943 if (action_flags & MLX5_FLOW_FATE_ACTIONS) 944 return rte_flow_error_set(error, EINVAL, 945 RTE_FLOW_ERROR_TYPE_ACTION, NULL, 946 "can't have 2 fate actions" 947 " in same flow"); 948 if (rss->func != RTE_ETH_HASH_FUNCTION_DEFAULT && 949 rss->func != RTE_ETH_HASH_FUNCTION_TOEPLITZ) 950 return rte_flow_error_set(error, ENOTSUP, 951 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 952 &rss->func, 953 "RSS hash function not supported"); 954 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT 955 if (rss->level > 2) 956 #else 957 if (rss->level > 1) 958 #endif 959 return rte_flow_error_set(error, ENOTSUP, 960 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 961 &rss->level, 962 "tunnel RSS is not supported"); 963 /* allow RSS key_len 0 in case of NULL (default) RSS key. */ 964 if (rss->key_len == 0 && rss->key != NULL) 965 return rte_flow_error_set(error, ENOTSUP, 966 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 967 &rss->key_len, 968 "RSS hash key length 0"); 969 if (rss->key_len > 0 && rss->key_len < MLX5_RSS_HASH_KEY_LEN) 970 return rte_flow_error_set(error, ENOTSUP, 971 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 972 &rss->key_len, 973 "RSS hash key too small"); 974 if (rss->key_len > MLX5_RSS_HASH_KEY_LEN) 975 return rte_flow_error_set(error, ENOTSUP, 976 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 977 &rss->key_len, 978 "RSS hash key too large"); 979 if (rss->queue_num > priv->config.ind_table_max_size) 980 return rte_flow_error_set(error, ENOTSUP, 981 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 982 &rss->queue_num, 983 "number of queues too large"); 984 if (rss->types & MLX5_RSS_HF_MASK) 985 return rte_flow_error_set(error, ENOTSUP, 986 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 987 &rss->types, 988 "some RSS protocols are not" 989 " supported"); 990 if (!priv->rxqs_n) 991 return rte_flow_error_set(error, EINVAL, 992 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 993 NULL, "No Rx queues configured"); 994 if (!rss->queue_num) 995 return rte_flow_error_set(error, EINVAL, 996 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 997 NULL, "No queues configured"); 998 for (i = 0; i != rss->queue_num; ++i) { 999 if (!(*priv->rxqs)[rss->queue[i]]) 1000 return rte_flow_error_set 1001 (error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION_CONF, 1002 &rss->queue[i], "queue is not configured"); 1003 } 1004 if (attr->egress) 1005 return rte_flow_error_set(error, ENOTSUP, 1006 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, NULL, 1007 "rss action not supported for " 1008 "egress"); 1009 if (rss->level > 1 && !tunnel) 1010 return rte_flow_error_set(error, EINVAL, 1011 RTE_FLOW_ERROR_TYPE_ACTION_CONF, NULL, 1012 "inner RSS is not supported for " 1013 "non-tunnel flows"); 1014 return 0; 1015 } 1016 1017 /* 1018 * Validate the count action. 1019 * 1020 * @param[in] dev 1021 * Pointer to the Ethernet device structure. 1022 * @param[in] attr 1023 * Attributes of flow that includes this action. 1024 * @param[out] error 1025 * Pointer to error structure. 1026 * 1027 * @return 1028 * 0 on success, a negative errno value otherwise and rte_errno is set. 1029 */ 1030 int 1031 mlx5_flow_validate_action_count(struct rte_eth_dev *dev __rte_unused, 1032 const struct rte_flow_attr *attr, 1033 struct rte_flow_error *error) 1034 { 1035 if (attr->egress) 1036 return rte_flow_error_set(error, ENOTSUP, 1037 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, NULL, 1038 "count action not supported for " 1039 "egress"); 1040 return 0; 1041 } 1042 1043 /** 1044 * Verify the @p attributes will be correctly understood by the NIC and store 1045 * them in the @p flow if everything is correct. 1046 * 1047 * @param[in] dev 1048 * Pointer to the Ethernet device structure. 1049 * @param[in] attributes 1050 * Pointer to flow attributes 1051 * @param[out] error 1052 * Pointer to error structure. 1053 * 1054 * @return 1055 * 0 on success, a negative errno value otherwise and rte_errno is set. 1056 */ 1057 int 1058 mlx5_flow_validate_attributes(struct rte_eth_dev *dev, 1059 const struct rte_flow_attr *attributes, 1060 struct rte_flow_error *error) 1061 { 1062 struct mlx5_priv *priv = dev->data->dev_private; 1063 uint32_t priority_max = priv->config.flow_prio - 1; 1064 1065 if (attributes->group) 1066 return rte_flow_error_set(error, ENOTSUP, 1067 RTE_FLOW_ERROR_TYPE_ATTR_GROUP, 1068 NULL, "groups is not supported"); 1069 if (attributes->priority != MLX5_FLOW_PRIO_RSVD && 1070 attributes->priority >= priority_max) 1071 return rte_flow_error_set(error, ENOTSUP, 1072 RTE_FLOW_ERROR_TYPE_ATTR_PRIORITY, 1073 NULL, "priority out of range"); 1074 if (attributes->egress) 1075 return rte_flow_error_set(error, ENOTSUP, 1076 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, NULL, 1077 "egress is not supported"); 1078 if (attributes->transfer && !priv->config.dv_esw_en) 1079 return rte_flow_error_set(error, ENOTSUP, 1080 RTE_FLOW_ERROR_TYPE_ATTR_TRANSFER, 1081 NULL, "transfer is not supported"); 1082 if (!attributes->ingress) 1083 return rte_flow_error_set(error, EINVAL, 1084 RTE_FLOW_ERROR_TYPE_ATTR_INGRESS, 1085 NULL, 1086 "ingress attribute is mandatory"); 1087 return 0; 1088 } 1089 1090 /** 1091 * Validate ICMP6 item. 1092 * 1093 * @param[in] item 1094 * Item specification. 1095 * @param[in] item_flags 1096 * Bit-fields that holds the items detected until now. 1097 * @param[out] error 1098 * Pointer to error structure. 1099 * 1100 * @return 1101 * 0 on success, a negative errno value otherwise and rte_errno is set. 1102 */ 1103 int 1104 mlx5_flow_validate_item_icmp6(const struct rte_flow_item *item, 1105 uint64_t item_flags, 1106 uint8_t target_protocol, 1107 struct rte_flow_error *error) 1108 { 1109 const struct rte_flow_item_icmp6 *mask = item->mask; 1110 const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL); 1111 const uint64_t l3m = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 : 1112 MLX5_FLOW_LAYER_OUTER_L3_IPV6; 1113 const uint64_t l4m = tunnel ? MLX5_FLOW_LAYER_INNER_L4 : 1114 MLX5_FLOW_LAYER_OUTER_L4; 1115 int ret; 1116 1117 if (target_protocol != 0xFF && target_protocol != IPPROTO_ICMPV6) 1118 return rte_flow_error_set(error, EINVAL, 1119 RTE_FLOW_ERROR_TYPE_ITEM, item, 1120 "protocol filtering not compatible" 1121 " with ICMP6 layer"); 1122 if (!(item_flags & l3m)) 1123 return rte_flow_error_set(error, EINVAL, 1124 RTE_FLOW_ERROR_TYPE_ITEM, item, 1125 "IPv6 is mandatory to filter on" 1126 " ICMP6"); 1127 if (item_flags & l4m) 1128 return rte_flow_error_set(error, EINVAL, 1129 RTE_FLOW_ERROR_TYPE_ITEM, item, 1130 "multiple L4 layers not supported"); 1131 if (!mask) 1132 mask = &rte_flow_item_icmp6_mask; 1133 ret = mlx5_flow_item_acceptable 1134 (item, (const uint8_t *)mask, 1135 (const uint8_t *)&rte_flow_item_icmp6_mask, 1136 sizeof(struct rte_flow_item_icmp6), error); 1137 if (ret < 0) 1138 return ret; 1139 return 0; 1140 } 1141 1142 /** 1143 * Validate ICMP item. 1144 * 1145 * @param[in] item 1146 * Item specification. 1147 * @param[in] item_flags 1148 * Bit-fields that holds the items detected until now. 1149 * @param[out] error 1150 * Pointer to error structure. 1151 * 1152 * @return 1153 * 0 on success, a negative errno value otherwise and rte_errno is set. 1154 */ 1155 int 1156 mlx5_flow_validate_item_icmp(const struct rte_flow_item *item, 1157 uint64_t item_flags, 1158 uint8_t target_protocol, 1159 struct rte_flow_error *error) 1160 { 1161 const struct rte_flow_item_icmp *mask = item->mask; 1162 const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL); 1163 const uint64_t l3m = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 : 1164 MLX5_FLOW_LAYER_OUTER_L3_IPV4; 1165 const uint64_t l4m = tunnel ? MLX5_FLOW_LAYER_INNER_L4 : 1166 MLX5_FLOW_LAYER_OUTER_L4; 1167 int ret; 1168 1169 if (target_protocol != 0xFF && target_protocol != IPPROTO_ICMP) 1170 return rte_flow_error_set(error, EINVAL, 1171 RTE_FLOW_ERROR_TYPE_ITEM, item, 1172 "protocol filtering not compatible" 1173 " with ICMP layer"); 1174 if (!(item_flags & l3m)) 1175 return rte_flow_error_set(error, EINVAL, 1176 RTE_FLOW_ERROR_TYPE_ITEM, item, 1177 "IPv4 is mandatory to filter" 1178 " on ICMP"); 1179 if (item_flags & l4m) 1180 return rte_flow_error_set(error, EINVAL, 1181 RTE_FLOW_ERROR_TYPE_ITEM, item, 1182 "multiple L4 layers not supported"); 1183 if (!mask) 1184 mask = &rte_flow_item_icmp_mask; 1185 ret = mlx5_flow_item_acceptable 1186 (item, (const uint8_t *)mask, 1187 (const uint8_t *)&rte_flow_item_icmp_mask, 1188 sizeof(struct rte_flow_item_icmp), error); 1189 if (ret < 0) 1190 return ret; 1191 return 0; 1192 } 1193 1194 /** 1195 * Validate Ethernet item. 1196 * 1197 * @param[in] item 1198 * Item specification. 1199 * @param[in] item_flags 1200 * Bit-fields that holds the items detected until now. 1201 * @param[out] error 1202 * Pointer to error structure. 1203 * 1204 * @return 1205 * 0 on success, a negative errno value otherwise and rte_errno is set. 1206 */ 1207 int 1208 mlx5_flow_validate_item_eth(const struct rte_flow_item *item, 1209 uint64_t item_flags, 1210 struct rte_flow_error *error) 1211 { 1212 const struct rte_flow_item_eth *mask = item->mask; 1213 const struct rte_flow_item_eth nic_mask = { 1214 .dst.addr_bytes = "\xff\xff\xff\xff\xff\xff", 1215 .src.addr_bytes = "\xff\xff\xff\xff\xff\xff", 1216 .type = RTE_BE16(0xffff), 1217 }; 1218 int ret; 1219 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL); 1220 const uint64_t ethm = tunnel ? MLX5_FLOW_LAYER_INNER_L2 : 1221 MLX5_FLOW_LAYER_OUTER_L2; 1222 1223 if (item_flags & ethm) 1224 return rte_flow_error_set(error, ENOTSUP, 1225 RTE_FLOW_ERROR_TYPE_ITEM, item, 1226 "multiple L2 layers not supported"); 1227 if (!mask) 1228 mask = &rte_flow_item_eth_mask; 1229 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask, 1230 (const uint8_t *)&nic_mask, 1231 sizeof(struct rte_flow_item_eth), 1232 error); 1233 return ret; 1234 } 1235 1236 /** 1237 * Validate VLAN item. 1238 * 1239 * @param[in] item 1240 * Item specification. 1241 * @param[in] item_flags 1242 * Bit-fields that holds the items detected until now. 1243 * @param[in] dev 1244 * Ethernet device flow is being created on. 1245 * @param[out] error 1246 * Pointer to error structure. 1247 * 1248 * @return 1249 * 0 on success, a negative errno value otherwise and rte_errno is set. 1250 */ 1251 int 1252 mlx5_flow_validate_item_vlan(const struct rte_flow_item *item, 1253 uint64_t item_flags, 1254 struct rte_eth_dev *dev, 1255 struct rte_flow_error *error) 1256 { 1257 const struct rte_flow_item_vlan *spec = item->spec; 1258 const struct rte_flow_item_vlan *mask = item->mask; 1259 const struct rte_flow_item_vlan nic_mask = { 1260 .tci = RTE_BE16(UINT16_MAX), 1261 .inner_type = RTE_BE16(UINT16_MAX), 1262 }; 1263 uint16_t vlan_tag = 0; 1264 const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL); 1265 int ret; 1266 const uint64_t l34m = tunnel ? (MLX5_FLOW_LAYER_INNER_L3 | 1267 MLX5_FLOW_LAYER_INNER_L4) : 1268 (MLX5_FLOW_LAYER_OUTER_L3 | 1269 MLX5_FLOW_LAYER_OUTER_L4); 1270 const uint64_t vlanm = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN : 1271 MLX5_FLOW_LAYER_OUTER_VLAN; 1272 1273 if (item_flags & vlanm) 1274 return rte_flow_error_set(error, EINVAL, 1275 RTE_FLOW_ERROR_TYPE_ITEM, item, 1276 "multiple VLAN layers not supported"); 1277 else if ((item_flags & l34m) != 0) 1278 return rte_flow_error_set(error, EINVAL, 1279 RTE_FLOW_ERROR_TYPE_ITEM, item, 1280 "L2 layer cannot follow L3/L4 layer"); 1281 if (!mask) 1282 mask = &rte_flow_item_vlan_mask; 1283 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask, 1284 (const uint8_t *)&nic_mask, 1285 sizeof(struct rte_flow_item_vlan), 1286 error); 1287 if (ret) 1288 return ret; 1289 if (!tunnel && mask->tci != RTE_BE16(0x0fff)) { 1290 struct mlx5_priv *priv = dev->data->dev_private; 1291 1292 if (priv->vmwa_context) { 1293 /* 1294 * Non-NULL context means we have a virtual machine 1295 * and SR-IOV enabled, we have to create VLAN interface 1296 * to make hypervisor to setup E-Switch vport 1297 * context correctly. We avoid creating the multiple 1298 * VLAN interfaces, so we cannot support VLAN tag mask. 1299 */ 1300 return rte_flow_error_set(error, EINVAL, 1301 RTE_FLOW_ERROR_TYPE_ITEM, 1302 item, 1303 "VLAN tag mask is not" 1304 " supported in virtual" 1305 " environment"); 1306 } 1307 } 1308 if (spec) { 1309 vlan_tag = spec->tci; 1310 vlan_tag &= mask->tci; 1311 } 1312 /* 1313 * From verbs perspective an empty VLAN is equivalent 1314 * to a packet without VLAN layer. 1315 */ 1316 if (!vlan_tag) 1317 return rte_flow_error_set(error, EINVAL, 1318 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, 1319 item->spec, 1320 "VLAN cannot be empty"); 1321 return 0; 1322 } 1323 1324 /** 1325 * Validate IPV4 item. 1326 * 1327 * @param[in] item 1328 * Item specification. 1329 * @param[in] item_flags 1330 * Bit-fields that holds the items detected until now. 1331 * @param[in] acc_mask 1332 * Acceptable mask, if NULL default internal default mask 1333 * will be used to check whether item fields are supported. 1334 * @param[out] error 1335 * Pointer to error structure. 1336 * 1337 * @return 1338 * 0 on success, a negative errno value otherwise and rte_errno is set. 1339 */ 1340 int 1341 mlx5_flow_validate_item_ipv4(const struct rte_flow_item *item, 1342 uint64_t item_flags, 1343 const struct rte_flow_item_ipv4 *acc_mask, 1344 struct rte_flow_error *error) 1345 { 1346 const struct rte_flow_item_ipv4 *mask = item->mask; 1347 const struct rte_flow_item_ipv4 *spec = item->spec; 1348 const struct rte_flow_item_ipv4 nic_mask = { 1349 .hdr = { 1350 .src_addr = RTE_BE32(0xffffffff), 1351 .dst_addr = RTE_BE32(0xffffffff), 1352 .type_of_service = 0xff, 1353 .next_proto_id = 0xff, 1354 }, 1355 }; 1356 const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL); 1357 const uint64_t l3m = tunnel ? MLX5_FLOW_LAYER_INNER_L3 : 1358 MLX5_FLOW_LAYER_OUTER_L3; 1359 const uint64_t l4m = tunnel ? MLX5_FLOW_LAYER_INNER_L4 : 1360 MLX5_FLOW_LAYER_OUTER_L4; 1361 int ret; 1362 uint8_t next_proto = 0xFF; 1363 1364 if (item_flags & MLX5_FLOW_LAYER_IPIP) { 1365 if (mask && spec) 1366 next_proto = mask->hdr.next_proto_id & 1367 spec->hdr.next_proto_id; 1368 if (next_proto == IPPROTO_IPIP || next_proto == IPPROTO_IPV6) 1369 return rte_flow_error_set(error, EINVAL, 1370 RTE_FLOW_ERROR_TYPE_ITEM, 1371 item, 1372 "multiple tunnel " 1373 "not supported"); 1374 } 1375 if (item_flags & MLX5_FLOW_LAYER_IPV6_ENCAP) 1376 return rte_flow_error_set(error, EINVAL, 1377 RTE_FLOW_ERROR_TYPE_ITEM, item, 1378 "wrong tunnel type - IPv6 specified " 1379 "but IPv4 item provided"); 1380 if (item_flags & l3m) 1381 return rte_flow_error_set(error, ENOTSUP, 1382 RTE_FLOW_ERROR_TYPE_ITEM, item, 1383 "multiple L3 layers not supported"); 1384 else if (item_flags & l4m) 1385 return rte_flow_error_set(error, EINVAL, 1386 RTE_FLOW_ERROR_TYPE_ITEM, item, 1387 "L3 cannot follow an L4 layer."); 1388 else if ((item_flags & MLX5_FLOW_LAYER_NVGRE) && 1389 !(item_flags & MLX5_FLOW_LAYER_INNER_L2)) 1390 return rte_flow_error_set(error, EINVAL, 1391 RTE_FLOW_ERROR_TYPE_ITEM, item, 1392 "L3 cannot follow an NVGRE layer."); 1393 if (!mask) 1394 mask = &rte_flow_item_ipv4_mask; 1395 else if (mask->hdr.next_proto_id != 0 && 1396 mask->hdr.next_proto_id != 0xff) 1397 return rte_flow_error_set(error, EINVAL, 1398 RTE_FLOW_ERROR_TYPE_ITEM_MASK, mask, 1399 "partial mask is not supported" 1400 " for protocol"); 1401 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask, 1402 acc_mask ? (const uint8_t *)acc_mask 1403 : (const uint8_t *)&nic_mask, 1404 sizeof(struct rte_flow_item_ipv4), 1405 error); 1406 if (ret < 0) 1407 return ret; 1408 return 0; 1409 } 1410 1411 /** 1412 * Validate IPV6 item. 1413 * 1414 * @param[in] item 1415 * Item specification. 1416 * @param[in] item_flags 1417 * Bit-fields that holds the items detected until now. 1418 * @param[in] acc_mask 1419 * Acceptable mask, if NULL default internal default mask 1420 * will be used to check whether item fields are supported. 1421 * @param[out] error 1422 * Pointer to error structure. 1423 * 1424 * @return 1425 * 0 on success, a negative errno value otherwise and rte_errno is set. 1426 */ 1427 int 1428 mlx5_flow_validate_item_ipv6(const struct rte_flow_item *item, 1429 uint64_t item_flags, 1430 const struct rte_flow_item_ipv6 *acc_mask, 1431 struct rte_flow_error *error) 1432 { 1433 const struct rte_flow_item_ipv6 *mask = item->mask; 1434 const struct rte_flow_item_ipv6 *spec = item->spec; 1435 const struct rte_flow_item_ipv6 nic_mask = { 1436 .hdr = { 1437 .src_addr = 1438 "\xff\xff\xff\xff\xff\xff\xff\xff" 1439 "\xff\xff\xff\xff\xff\xff\xff\xff", 1440 .dst_addr = 1441 "\xff\xff\xff\xff\xff\xff\xff\xff" 1442 "\xff\xff\xff\xff\xff\xff\xff\xff", 1443 .vtc_flow = RTE_BE32(0xffffffff), 1444 .proto = 0xff, 1445 .hop_limits = 0xff, 1446 }, 1447 }; 1448 const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL); 1449 const uint64_t l3m = tunnel ? MLX5_FLOW_LAYER_INNER_L3 : 1450 MLX5_FLOW_LAYER_OUTER_L3; 1451 const uint64_t l4m = tunnel ? MLX5_FLOW_LAYER_INNER_L4 : 1452 MLX5_FLOW_LAYER_OUTER_L4; 1453 int ret; 1454 uint8_t next_proto = 0xFF; 1455 1456 if (item_flags & MLX5_FLOW_LAYER_IPV6_ENCAP) { 1457 if (mask && spec) 1458 next_proto = mask->hdr.proto & spec->hdr.proto; 1459 if (next_proto == IPPROTO_IPIP || next_proto == IPPROTO_IPV6) 1460 return rte_flow_error_set(error, EINVAL, 1461 RTE_FLOW_ERROR_TYPE_ITEM, 1462 item, 1463 "multiple tunnel " 1464 "not supported"); 1465 } 1466 if (item_flags & MLX5_FLOW_LAYER_IPIP) 1467 return rte_flow_error_set(error, EINVAL, 1468 RTE_FLOW_ERROR_TYPE_ITEM, item, 1469 "wrong tunnel type - IPv4 specified " 1470 "but IPv6 item provided"); 1471 if (item_flags & l3m) 1472 return rte_flow_error_set(error, ENOTSUP, 1473 RTE_FLOW_ERROR_TYPE_ITEM, item, 1474 "multiple L3 layers not supported"); 1475 else if (item_flags & l4m) 1476 return rte_flow_error_set(error, EINVAL, 1477 RTE_FLOW_ERROR_TYPE_ITEM, item, 1478 "L3 cannot follow an L4 layer."); 1479 else if ((item_flags & MLX5_FLOW_LAYER_NVGRE) && 1480 !(item_flags & MLX5_FLOW_LAYER_INNER_L2)) 1481 return rte_flow_error_set(error, EINVAL, 1482 RTE_FLOW_ERROR_TYPE_ITEM, item, 1483 "L3 cannot follow an NVGRE layer."); 1484 if (!mask) 1485 mask = &rte_flow_item_ipv6_mask; 1486 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask, 1487 acc_mask ? (const uint8_t *)acc_mask 1488 : (const uint8_t *)&nic_mask, 1489 sizeof(struct rte_flow_item_ipv6), 1490 error); 1491 if (ret < 0) 1492 return ret; 1493 return 0; 1494 } 1495 1496 /** 1497 * Validate UDP item. 1498 * 1499 * @param[in] item 1500 * Item specification. 1501 * @param[in] item_flags 1502 * Bit-fields that holds the items detected until now. 1503 * @param[in] target_protocol 1504 * The next protocol in the previous item. 1505 * @param[in] flow_mask 1506 * mlx5 flow-specific (DV, verbs, etc.) supported header fields mask. 1507 * @param[out] error 1508 * Pointer to error structure. 1509 * 1510 * @return 1511 * 0 on success, a negative errno value otherwise and rte_errno is set. 1512 */ 1513 int 1514 mlx5_flow_validate_item_udp(const struct rte_flow_item *item, 1515 uint64_t item_flags, 1516 uint8_t target_protocol, 1517 struct rte_flow_error *error) 1518 { 1519 const struct rte_flow_item_udp *mask = item->mask; 1520 const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL); 1521 const uint64_t l3m = tunnel ? MLX5_FLOW_LAYER_INNER_L3 : 1522 MLX5_FLOW_LAYER_OUTER_L3; 1523 const uint64_t l4m = tunnel ? MLX5_FLOW_LAYER_INNER_L4 : 1524 MLX5_FLOW_LAYER_OUTER_L4; 1525 int ret; 1526 1527 if (target_protocol != 0xff && target_protocol != IPPROTO_UDP) 1528 return rte_flow_error_set(error, EINVAL, 1529 RTE_FLOW_ERROR_TYPE_ITEM, item, 1530 "protocol filtering not compatible" 1531 " with UDP layer"); 1532 if (!(item_flags & l3m)) 1533 return rte_flow_error_set(error, EINVAL, 1534 RTE_FLOW_ERROR_TYPE_ITEM, item, 1535 "L3 is mandatory to filter on L4"); 1536 if (item_flags & l4m) 1537 return rte_flow_error_set(error, EINVAL, 1538 RTE_FLOW_ERROR_TYPE_ITEM, item, 1539 "multiple L4 layers not supported"); 1540 if (!mask) 1541 mask = &rte_flow_item_udp_mask; 1542 ret = mlx5_flow_item_acceptable 1543 (item, (const uint8_t *)mask, 1544 (const uint8_t *)&rte_flow_item_udp_mask, 1545 sizeof(struct rte_flow_item_udp), error); 1546 if (ret < 0) 1547 return ret; 1548 return 0; 1549 } 1550 1551 /** 1552 * Validate TCP item. 1553 * 1554 * @param[in] item 1555 * Item specification. 1556 * @param[in] item_flags 1557 * Bit-fields that holds the items detected until now. 1558 * @param[in] target_protocol 1559 * The next protocol in the previous item. 1560 * @param[out] error 1561 * Pointer to error structure. 1562 * 1563 * @return 1564 * 0 on success, a negative errno value otherwise and rte_errno is set. 1565 */ 1566 int 1567 mlx5_flow_validate_item_tcp(const struct rte_flow_item *item, 1568 uint64_t item_flags, 1569 uint8_t target_protocol, 1570 const struct rte_flow_item_tcp *flow_mask, 1571 struct rte_flow_error *error) 1572 { 1573 const struct rte_flow_item_tcp *mask = item->mask; 1574 const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL); 1575 const uint64_t l3m = tunnel ? MLX5_FLOW_LAYER_INNER_L3 : 1576 MLX5_FLOW_LAYER_OUTER_L3; 1577 const uint64_t l4m = tunnel ? MLX5_FLOW_LAYER_INNER_L4 : 1578 MLX5_FLOW_LAYER_OUTER_L4; 1579 int ret; 1580 1581 assert(flow_mask); 1582 if (target_protocol != 0xff && target_protocol != IPPROTO_TCP) 1583 return rte_flow_error_set(error, EINVAL, 1584 RTE_FLOW_ERROR_TYPE_ITEM, item, 1585 "protocol filtering not compatible" 1586 " with TCP layer"); 1587 if (!(item_flags & l3m)) 1588 return rte_flow_error_set(error, EINVAL, 1589 RTE_FLOW_ERROR_TYPE_ITEM, item, 1590 "L3 is mandatory to filter on L4"); 1591 if (item_flags & l4m) 1592 return rte_flow_error_set(error, EINVAL, 1593 RTE_FLOW_ERROR_TYPE_ITEM, item, 1594 "multiple L4 layers not supported"); 1595 if (!mask) 1596 mask = &rte_flow_item_tcp_mask; 1597 ret = mlx5_flow_item_acceptable 1598 (item, (const uint8_t *)mask, 1599 (const uint8_t *)flow_mask, 1600 sizeof(struct rte_flow_item_tcp), error); 1601 if (ret < 0) 1602 return ret; 1603 return 0; 1604 } 1605 1606 /** 1607 * Validate VXLAN item. 1608 * 1609 * @param[in] item 1610 * Item specification. 1611 * @param[in] item_flags 1612 * Bit-fields that holds the items detected until now. 1613 * @param[in] target_protocol 1614 * The next protocol in the previous item. 1615 * @param[out] error 1616 * Pointer to error structure. 1617 * 1618 * @return 1619 * 0 on success, a negative errno value otherwise and rte_errno is set. 1620 */ 1621 int 1622 mlx5_flow_validate_item_vxlan(const struct rte_flow_item *item, 1623 uint64_t item_flags, 1624 struct rte_flow_error *error) 1625 { 1626 const struct rte_flow_item_vxlan *spec = item->spec; 1627 const struct rte_flow_item_vxlan *mask = item->mask; 1628 int ret; 1629 union vni { 1630 uint32_t vlan_id; 1631 uint8_t vni[4]; 1632 } id = { .vlan_id = 0, }; 1633 uint32_t vlan_id = 0; 1634 1635 1636 if (item_flags & MLX5_FLOW_LAYER_TUNNEL) 1637 return rte_flow_error_set(error, ENOTSUP, 1638 RTE_FLOW_ERROR_TYPE_ITEM, item, 1639 "multiple tunnel layers not" 1640 " supported"); 1641 /* 1642 * Verify only UDPv4 is present as defined in 1643 * https://tools.ietf.org/html/rfc7348 1644 */ 1645 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_UDP)) 1646 return rte_flow_error_set(error, EINVAL, 1647 RTE_FLOW_ERROR_TYPE_ITEM, item, 1648 "no outer UDP layer found"); 1649 if (!mask) 1650 mask = &rte_flow_item_vxlan_mask; 1651 ret = mlx5_flow_item_acceptable 1652 (item, (const uint8_t *)mask, 1653 (const uint8_t *)&rte_flow_item_vxlan_mask, 1654 sizeof(struct rte_flow_item_vxlan), 1655 error); 1656 if (ret < 0) 1657 return ret; 1658 if (spec) { 1659 memcpy(&id.vni[1], spec->vni, 3); 1660 vlan_id = id.vlan_id; 1661 memcpy(&id.vni[1], mask->vni, 3); 1662 vlan_id &= id.vlan_id; 1663 } 1664 /* 1665 * Tunnel id 0 is equivalent as not adding a VXLAN layer, if 1666 * only this layer is defined in the Verbs specification it is 1667 * interpreted as wildcard and all packets will match this 1668 * rule, if it follows a full stack layer (ex: eth / ipv4 / 1669 * udp), all packets matching the layers before will also 1670 * match this rule. To avoid such situation, VNI 0 is 1671 * currently refused. 1672 */ 1673 if (!vlan_id) 1674 return rte_flow_error_set(error, ENOTSUP, 1675 RTE_FLOW_ERROR_TYPE_ITEM, item, 1676 "VXLAN vni cannot be 0"); 1677 if (!(item_flags & MLX5_FLOW_LAYER_OUTER)) 1678 return rte_flow_error_set(error, ENOTSUP, 1679 RTE_FLOW_ERROR_TYPE_ITEM, item, 1680 "VXLAN tunnel must be fully defined"); 1681 return 0; 1682 } 1683 1684 /** 1685 * Validate VXLAN_GPE item. 1686 * 1687 * @param[in] item 1688 * Item specification. 1689 * @param[in] item_flags 1690 * Bit-fields that holds the items detected until now. 1691 * @param[in] priv 1692 * Pointer to the private data structure. 1693 * @param[in] target_protocol 1694 * The next protocol in the previous item. 1695 * @param[out] error 1696 * Pointer to error structure. 1697 * 1698 * @return 1699 * 0 on success, a negative errno value otherwise and rte_errno is set. 1700 */ 1701 int 1702 mlx5_flow_validate_item_vxlan_gpe(const struct rte_flow_item *item, 1703 uint64_t item_flags, 1704 struct rte_eth_dev *dev, 1705 struct rte_flow_error *error) 1706 { 1707 struct mlx5_priv *priv = dev->data->dev_private; 1708 const struct rte_flow_item_vxlan_gpe *spec = item->spec; 1709 const struct rte_flow_item_vxlan_gpe *mask = item->mask; 1710 int ret; 1711 union vni { 1712 uint32_t vlan_id; 1713 uint8_t vni[4]; 1714 } id = { .vlan_id = 0, }; 1715 uint32_t vlan_id = 0; 1716 1717 if (!priv->config.l3_vxlan_en) 1718 return rte_flow_error_set(error, ENOTSUP, 1719 RTE_FLOW_ERROR_TYPE_ITEM, item, 1720 "L3 VXLAN is not enabled by device" 1721 " parameter and/or not configured in" 1722 " firmware"); 1723 if (item_flags & MLX5_FLOW_LAYER_TUNNEL) 1724 return rte_flow_error_set(error, ENOTSUP, 1725 RTE_FLOW_ERROR_TYPE_ITEM, item, 1726 "multiple tunnel layers not" 1727 " supported"); 1728 /* 1729 * Verify only UDPv4 is present as defined in 1730 * https://tools.ietf.org/html/rfc7348 1731 */ 1732 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_UDP)) 1733 return rte_flow_error_set(error, EINVAL, 1734 RTE_FLOW_ERROR_TYPE_ITEM, item, 1735 "no outer UDP layer found"); 1736 if (!mask) 1737 mask = &rte_flow_item_vxlan_gpe_mask; 1738 ret = mlx5_flow_item_acceptable 1739 (item, (const uint8_t *)mask, 1740 (const uint8_t *)&rte_flow_item_vxlan_gpe_mask, 1741 sizeof(struct rte_flow_item_vxlan_gpe), 1742 error); 1743 if (ret < 0) 1744 return ret; 1745 if (spec) { 1746 if (spec->protocol) 1747 return rte_flow_error_set(error, ENOTSUP, 1748 RTE_FLOW_ERROR_TYPE_ITEM, 1749 item, 1750 "VxLAN-GPE protocol" 1751 " not supported"); 1752 memcpy(&id.vni[1], spec->vni, 3); 1753 vlan_id = id.vlan_id; 1754 memcpy(&id.vni[1], mask->vni, 3); 1755 vlan_id &= id.vlan_id; 1756 } 1757 /* 1758 * Tunnel id 0 is equivalent as not adding a VXLAN layer, if only this 1759 * layer is defined in the Verbs specification it is interpreted as 1760 * wildcard and all packets will match this rule, if it follows a full 1761 * stack layer (ex: eth / ipv4 / udp), all packets matching the layers 1762 * before will also match this rule. To avoid such situation, VNI 0 1763 * is currently refused. 1764 */ 1765 if (!vlan_id) 1766 return rte_flow_error_set(error, ENOTSUP, 1767 RTE_FLOW_ERROR_TYPE_ITEM, item, 1768 "VXLAN-GPE vni cannot be 0"); 1769 if (!(item_flags & MLX5_FLOW_LAYER_OUTER)) 1770 return rte_flow_error_set(error, ENOTSUP, 1771 RTE_FLOW_ERROR_TYPE_ITEM, item, 1772 "VXLAN-GPE tunnel must be fully" 1773 " defined"); 1774 return 0; 1775 } 1776 /** 1777 * Validate GRE Key item. 1778 * 1779 * @param[in] item 1780 * Item specification. 1781 * @param[in] item_flags 1782 * Bit flags to mark detected items. 1783 * @param[in] gre_item 1784 * Pointer to gre_item 1785 * @param[out] error 1786 * Pointer to error structure. 1787 * 1788 * @return 1789 * 0 on success, a negative errno value otherwise and rte_errno is set. 1790 */ 1791 int 1792 mlx5_flow_validate_item_gre_key(const struct rte_flow_item *item, 1793 uint64_t item_flags, 1794 const struct rte_flow_item *gre_item, 1795 struct rte_flow_error *error) 1796 { 1797 const rte_be32_t *mask = item->mask; 1798 int ret = 0; 1799 rte_be32_t gre_key_default_mask = RTE_BE32(UINT32_MAX); 1800 const struct rte_flow_item_gre *gre_spec = gre_item->spec; 1801 const struct rte_flow_item_gre *gre_mask = gre_item->mask; 1802 1803 if (item_flags & MLX5_FLOW_LAYER_GRE_KEY) 1804 return rte_flow_error_set(error, ENOTSUP, 1805 RTE_FLOW_ERROR_TYPE_ITEM, item, 1806 "Multiple GRE key not support"); 1807 if (!(item_flags & MLX5_FLOW_LAYER_GRE)) 1808 return rte_flow_error_set(error, ENOTSUP, 1809 RTE_FLOW_ERROR_TYPE_ITEM, item, 1810 "No preceding GRE header"); 1811 if (item_flags & MLX5_FLOW_LAYER_INNER) 1812 return rte_flow_error_set(error, ENOTSUP, 1813 RTE_FLOW_ERROR_TYPE_ITEM, item, 1814 "GRE key following a wrong item"); 1815 if (!gre_mask) 1816 gre_mask = &rte_flow_item_gre_mask; 1817 if (gre_spec && (gre_mask->c_rsvd0_ver & RTE_BE16(0x2000)) && 1818 !(gre_spec->c_rsvd0_ver & RTE_BE16(0x2000))) 1819 return rte_flow_error_set(error, EINVAL, 1820 RTE_FLOW_ERROR_TYPE_ITEM, item, 1821 "Key bit must be on"); 1822 1823 if (!mask) 1824 mask = &gre_key_default_mask; 1825 ret = mlx5_flow_item_acceptable 1826 (item, (const uint8_t *)mask, 1827 (const uint8_t *)&gre_key_default_mask, 1828 sizeof(rte_be32_t), error); 1829 return ret; 1830 } 1831 1832 /** 1833 * Validate GRE item. 1834 * 1835 * @param[in] item 1836 * Item specification. 1837 * @param[in] item_flags 1838 * Bit flags to mark detected items. 1839 * @param[in] target_protocol 1840 * The next protocol in the previous item. 1841 * @param[out] error 1842 * Pointer to error structure. 1843 * 1844 * @return 1845 * 0 on success, a negative errno value otherwise and rte_errno is set. 1846 */ 1847 int 1848 mlx5_flow_validate_item_gre(const struct rte_flow_item *item, 1849 uint64_t item_flags, 1850 uint8_t target_protocol, 1851 struct rte_flow_error *error) 1852 { 1853 const struct rte_flow_item_gre *spec __rte_unused = item->spec; 1854 const struct rte_flow_item_gre *mask = item->mask; 1855 int ret; 1856 const struct rte_flow_item_gre nic_mask = { 1857 .c_rsvd0_ver = RTE_BE16(0xB000), 1858 .protocol = RTE_BE16(UINT16_MAX), 1859 }; 1860 1861 if (target_protocol != 0xff && target_protocol != IPPROTO_GRE) 1862 return rte_flow_error_set(error, EINVAL, 1863 RTE_FLOW_ERROR_TYPE_ITEM, item, 1864 "protocol filtering not compatible" 1865 " with this GRE layer"); 1866 if (item_flags & MLX5_FLOW_LAYER_TUNNEL) 1867 return rte_flow_error_set(error, ENOTSUP, 1868 RTE_FLOW_ERROR_TYPE_ITEM, item, 1869 "multiple tunnel layers not" 1870 " supported"); 1871 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L3)) 1872 return rte_flow_error_set(error, ENOTSUP, 1873 RTE_FLOW_ERROR_TYPE_ITEM, item, 1874 "L3 Layer is missing"); 1875 if (!mask) 1876 mask = &rte_flow_item_gre_mask; 1877 ret = mlx5_flow_item_acceptable 1878 (item, (const uint8_t *)mask, 1879 (const uint8_t *)&nic_mask, 1880 sizeof(struct rte_flow_item_gre), error); 1881 if (ret < 0) 1882 return ret; 1883 #ifndef HAVE_MLX5DV_DR 1884 #ifndef HAVE_IBV_DEVICE_MPLS_SUPPORT 1885 if (spec && (spec->protocol & mask->protocol)) 1886 return rte_flow_error_set(error, ENOTSUP, 1887 RTE_FLOW_ERROR_TYPE_ITEM, item, 1888 "without MPLS support the" 1889 " specification cannot be used for" 1890 " filtering"); 1891 #endif 1892 #endif 1893 return 0; 1894 } 1895 1896 /** 1897 * Validate MPLS item. 1898 * 1899 * @param[in] dev 1900 * Pointer to the rte_eth_dev structure. 1901 * @param[in] item 1902 * Item specification. 1903 * @param[in] item_flags 1904 * Bit-fields that holds the items detected until now. 1905 * @param[in] prev_layer 1906 * The protocol layer indicated in previous item. 1907 * @param[out] error 1908 * Pointer to error structure. 1909 * 1910 * @return 1911 * 0 on success, a negative errno value otherwise and rte_errno is set. 1912 */ 1913 int 1914 mlx5_flow_validate_item_mpls(struct rte_eth_dev *dev __rte_unused, 1915 const struct rte_flow_item *item __rte_unused, 1916 uint64_t item_flags __rte_unused, 1917 uint64_t prev_layer __rte_unused, 1918 struct rte_flow_error *error) 1919 { 1920 #ifdef HAVE_IBV_DEVICE_MPLS_SUPPORT 1921 const struct rte_flow_item_mpls *mask = item->mask; 1922 struct mlx5_priv *priv = dev->data->dev_private; 1923 int ret; 1924 1925 if (!priv->config.mpls_en) 1926 return rte_flow_error_set(error, ENOTSUP, 1927 RTE_FLOW_ERROR_TYPE_ITEM, item, 1928 "MPLS not supported or" 1929 " disabled in firmware" 1930 " configuration."); 1931 /* MPLS over IP, UDP, GRE is allowed */ 1932 if (!(prev_layer & (MLX5_FLOW_LAYER_OUTER_L3 | 1933 MLX5_FLOW_LAYER_OUTER_L4_UDP | 1934 MLX5_FLOW_LAYER_GRE))) 1935 return rte_flow_error_set(error, EINVAL, 1936 RTE_FLOW_ERROR_TYPE_ITEM, item, 1937 "protocol filtering not compatible" 1938 " with MPLS layer"); 1939 /* Multi-tunnel isn't allowed but MPLS over GRE is an exception. */ 1940 if ((item_flags & MLX5_FLOW_LAYER_TUNNEL) && 1941 !(item_flags & MLX5_FLOW_LAYER_GRE)) 1942 return rte_flow_error_set(error, ENOTSUP, 1943 RTE_FLOW_ERROR_TYPE_ITEM, item, 1944 "multiple tunnel layers not" 1945 " supported"); 1946 if (!mask) 1947 mask = &rte_flow_item_mpls_mask; 1948 ret = mlx5_flow_item_acceptable 1949 (item, (const uint8_t *)mask, 1950 (const uint8_t *)&rte_flow_item_mpls_mask, 1951 sizeof(struct rte_flow_item_mpls), error); 1952 if (ret < 0) 1953 return ret; 1954 return 0; 1955 #endif 1956 return rte_flow_error_set(error, ENOTSUP, 1957 RTE_FLOW_ERROR_TYPE_ITEM, item, 1958 "MPLS is not supported by Verbs, please" 1959 " update."); 1960 } 1961 1962 /** 1963 * Validate NVGRE item. 1964 * 1965 * @param[in] item 1966 * Item specification. 1967 * @param[in] item_flags 1968 * Bit flags to mark detected items. 1969 * @param[in] target_protocol 1970 * The next protocol in the previous item. 1971 * @param[out] error 1972 * Pointer to error structure. 1973 * 1974 * @return 1975 * 0 on success, a negative errno value otherwise and rte_errno is set. 1976 */ 1977 int 1978 mlx5_flow_validate_item_nvgre(const struct rte_flow_item *item, 1979 uint64_t item_flags, 1980 uint8_t target_protocol, 1981 struct rte_flow_error *error) 1982 { 1983 const struct rte_flow_item_nvgre *mask = item->mask; 1984 int ret; 1985 1986 if (target_protocol != 0xff && target_protocol != IPPROTO_GRE) 1987 return rte_flow_error_set(error, EINVAL, 1988 RTE_FLOW_ERROR_TYPE_ITEM, item, 1989 "protocol filtering not compatible" 1990 " with this GRE layer"); 1991 if (item_flags & MLX5_FLOW_LAYER_TUNNEL) 1992 return rte_flow_error_set(error, ENOTSUP, 1993 RTE_FLOW_ERROR_TYPE_ITEM, item, 1994 "multiple tunnel layers not" 1995 " supported"); 1996 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L3)) 1997 return rte_flow_error_set(error, ENOTSUP, 1998 RTE_FLOW_ERROR_TYPE_ITEM, item, 1999 "L3 Layer is missing"); 2000 if (!mask) 2001 mask = &rte_flow_item_nvgre_mask; 2002 ret = mlx5_flow_item_acceptable 2003 (item, (const uint8_t *)mask, 2004 (const uint8_t *)&rte_flow_item_nvgre_mask, 2005 sizeof(struct rte_flow_item_nvgre), error); 2006 if (ret < 0) 2007 return ret; 2008 return 0; 2009 } 2010 2011 static int 2012 flow_null_validate(struct rte_eth_dev *dev __rte_unused, 2013 const struct rte_flow_attr *attr __rte_unused, 2014 const struct rte_flow_item items[] __rte_unused, 2015 const struct rte_flow_action actions[] __rte_unused, 2016 bool external __rte_unused, 2017 struct rte_flow_error *error) 2018 { 2019 return rte_flow_error_set(error, ENOTSUP, 2020 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, NULL); 2021 } 2022 2023 static struct mlx5_flow * 2024 flow_null_prepare(const struct rte_flow_attr *attr __rte_unused, 2025 const struct rte_flow_item items[] __rte_unused, 2026 const struct rte_flow_action actions[] __rte_unused, 2027 struct rte_flow_error *error) 2028 { 2029 rte_flow_error_set(error, ENOTSUP, 2030 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, NULL); 2031 return NULL; 2032 } 2033 2034 static int 2035 flow_null_translate(struct rte_eth_dev *dev __rte_unused, 2036 struct mlx5_flow *dev_flow __rte_unused, 2037 const struct rte_flow_attr *attr __rte_unused, 2038 const struct rte_flow_item items[] __rte_unused, 2039 const struct rte_flow_action actions[] __rte_unused, 2040 struct rte_flow_error *error) 2041 { 2042 return rte_flow_error_set(error, ENOTSUP, 2043 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, NULL); 2044 } 2045 2046 static int 2047 flow_null_apply(struct rte_eth_dev *dev __rte_unused, 2048 struct rte_flow *flow __rte_unused, 2049 struct rte_flow_error *error) 2050 { 2051 return rte_flow_error_set(error, ENOTSUP, 2052 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, NULL); 2053 } 2054 2055 static void 2056 flow_null_remove(struct rte_eth_dev *dev __rte_unused, 2057 struct rte_flow *flow __rte_unused) 2058 { 2059 } 2060 2061 static void 2062 flow_null_destroy(struct rte_eth_dev *dev __rte_unused, 2063 struct rte_flow *flow __rte_unused) 2064 { 2065 } 2066 2067 static int 2068 flow_null_query(struct rte_eth_dev *dev __rte_unused, 2069 struct rte_flow *flow __rte_unused, 2070 const struct rte_flow_action *actions __rte_unused, 2071 void *data __rte_unused, 2072 struct rte_flow_error *error) 2073 { 2074 return rte_flow_error_set(error, ENOTSUP, 2075 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, NULL); 2076 } 2077 2078 /* Void driver to protect from null pointer reference. */ 2079 const struct mlx5_flow_driver_ops mlx5_flow_null_drv_ops = { 2080 .validate = flow_null_validate, 2081 .prepare = flow_null_prepare, 2082 .translate = flow_null_translate, 2083 .apply = flow_null_apply, 2084 .remove = flow_null_remove, 2085 .destroy = flow_null_destroy, 2086 .query = flow_null_query, 2087 }; 2088 2089 /** 2090 * Select flow driver type according to flow attributes and device 2091 * configuration. 2092 * 2093 * @param[in] dev 2094 * Pointer to the dev structure. 2095 * @param[in] attr 2096 * Pointer to the flow attributes. 2097 * 2098 * @return 2099 * flow driver type, MLX5_FLOW_TYPE_MAX otherwise. 2100 */ 2101 static enum mlx5_flow_drv_type 2102 flow_get_drv_type(struct rte_eth_dev *dev, const struct rte_flow_attr *attr) 2103 { 2104 struct mlx5_priv *priv = dev->data->dev_private; 2105 enum mlx5_flow_drv_type type = MLX5_FLOW_TYPE_MAX; 2106 2107 if (attr->transfer && priv->config.dv_esw_en) 2108 type = MLX5_FLOW_TYPE_DV; 2109 if (!attr->transfer) 2110 type = priv->config.dv_flow_en ? MLX5_FLOW_TYPE_DV : 2111 MLX5_FLOW_TYPE_VERBS; 2112 return type; 2113 } 2114 2115 #define flow_get_drv_ops(type) flow_drv_ops[type] 2116 2117 /** 2118 * Flow driver validation API. This abstracts calling driver specific functions. 2119 * The type of flow driver is determined according to flow attributes. 2120 * 2121 * @param[in] dev 2122 * Pointer to the dev structure. 2123 * @param[in] attr 2124 * Pointer to the flow attributes. 2125 * @param[in] items 2126 * Pointer to the list of items. 2127 * @param[in] actions 2128 * Pointer to the list of actions. 2129 * @param[in] external 2130 * This flow rule is created by request external to PMD. 2131 * @param[out] error 2132 * Pointer to the error structure. 2133 * 2134 * @return 2135 * 0 on success, a negative errno value otherwise and rte_errno is set. 2136 */ 2137 static inline int 2138 flow_drv_validate(struct rte_eth_dev *dev, 2139 const struct rte_flow_attr *attr, 2140 const struct rte_flow_item items[], 2141 const struct rte_flow_action actions[], 2142 bool external, struct rte_flow_error *error) 2143 { 2144 const struct mlx5_flow_driver_ops *fops; 2145 enum mlx5_flow_drv_type type = flow_get_drv_type(dev, attr); 2146 2147 fops = flow_get_drv_ops(type); 2148 return fops->validate(dev, attr, items, actions, external, error); 2149 } 2150 2151 /** 2152 * Flow driver preparation API. This abstracts calling driver specific 2153 * functions. Parent flow (rte_flow) should have driver type (drv_type). It 2154 * calculates the size of memory required for device flow, allocates the memory, 2155 * initializes the device flow and returns the pointer. 2156 * 2157 * @note 2158 * This function initializes device flow structure such as dv or verbs in 2159 * struct mlx5_flow. However, it is caller's responsibility to initialize the 2160 * rest. For example, adding returning device flow to flow->dev_flow list and 2161 * setting backward reference to the flow should be done out of this function. 2162 * layers field is not filled either. 2163 * 2164 * @param[in] attr 2165 * Pointer to the flow attributes. 2166 * @param[in] items 2167 * Pointer to the list of items. 2168 * @param[in] actions 2169 * Pointer to the list of actions. 2170 * @param[out] error 2171 * Pointer to the error structure. 2172 * 2173 * @return 2174 * Pointer to device flow on success, otherwise NULL and rte_errno is set. 2175 */ 2176 static inline struct mlx5_flow * 2177 flow_drv_prepare(const struct rte_flow *flow, 2178 const struct rte_flow_attr *attr, 2179 const struct rte_flow_item items[], 2180 const struct rte_flow_action actions[], 2181 struct rte_flow_error *error) 2182 { 2183 const struct mlx5_flow_driver_ops *fops; 2184 enum mlx5_flow_drv_type type = flow->drv_type; 2185 2186 assert(type > MLX5_FLOW_TYPE_MIN && type < MLX5_FLOW_TYPE_MAX); 2187 fops = flow_get_drv_ops(type); 2188 return fops->prepare(attr, items, actions, error); 2189 } 2190 2191 /** 2192 * Flow driver translation API. This abstracts calling driver specific 2193 * functions. Parent flow (rte_flow) should have driver type (drv_type). It 2194 * translates a generic flow into a driver flow. flow_drv_prepare() must 2195 * precede. 2196 * 2197 * @note 2198 * dev_flow->layers could be filled as a result of parsing during translation 2199 * if needed by flow_drv_apply(). dev_flow->flow->actions can also be filled 2200 * if necessary. As a flow can have multiple dev_flows by RSS flow expansion, 2201 * flow->actions could be overwritten even though all the expanded dev_flows 2202 * have the same actions. 2203 * 2204 * @param[in] dev 2205 * Pointer to the rte dev structure. 2206 * @param[in, out] dev_flow 2207 * Pointer to the mlx5 flow. 2208 * @param[in] attr 2209 * Pointer to the flow attributes. 2210 * @param[in] items 2211 * Pointer to the list of items. 2212 * @param[in] actions 2213 * Pointer to the list of actions. 2214 * @param[out] error 2215 * Pointer to the error structure. 2216 * 2217 * @return 2218 * 0 on success, a negative errno value otherwise and rte_errno is set. 2219 */ 2220 static inline int 2221 flow_drv_translate(struct rte_eth_dev *dev, struct mlx5_flow *dev_flow, 2222 const struct rte_flow_attr *attr, 2223 const struct rte_flow_item items[], 2224 const struct rte_flow_action actions[], 2225 struct rte_flow_error *error) 2226 { 2227 const struct mlx5_flow_driver_ops *fops; 2228 enum mlx5_flow_drv_type type = dev_flow->flow->drv_type; 2229 2230 assert(type > MLX5_FLOW_TYPE_MIN && type < MLX5_FLOW_TYPE_MAX); 2231 fops = flow_get_drv_ops(type); 2232 return fops->translate(dev, dev_flow, attr, items, actions, error); 2233 } 2234 2235 /** 2236 * Flow driver apply API. This abstracts calling driver specific functions. 2237 * Parent flow (rte_flow) should have driver type (drv_type). It applies 2238 * translated driver flows on to device. flow_drv_translate() must precede. 2239 * 2240 * @param[in] dev 2241 * Pointer to Ethernet device structure. 2242 * @param[in, out] flow 2243 * Pointer to flow structure. 2244 * @param[out] error 2245 * Pointer to error structure. 2246 * 2247 * @return 2248 * 0 on success, a negative errno value otherwise and rte_errno is set. 2249 */ 2250 static inline int 2251 flow_drv_apply(struct rte_eth_dev *dev, struct rte_flow *flow, 2252 struct rte_flow_error *error) 2253 { 2254 const struct mlx5_flow_driver_ops *fops; 2255 enum mlx5_flow_drv_type type = flow->drv_type; 2256 2257 assert(type > MLX5_FLOW_TYPE_MIN && type < MLX5_FLOW_TYPE_MAX); 2258 fops = flow_get_drv_ops(type); 2259 return fops->apply(dev, flow, error); 2260 } 2261 2262 /** 2263 * Flow driver remove API. This abstracts calling driver specific functions. 2264 * Parent flow (rte_flow) should have driver type (drv_type). It removes a flow 2265 * on device. All the resources of the flow should be freed by calling 2266 * flow_drv_destroy(). 2267 * 2268 * @param[in] dev 2269 * Pointer to Ethernet device. 2270 * @param[in, out] flow 2271 * Pointer to flow structure. 2272 */ 2273 static inline void 2274 flow_drv_remove(struct rte_eth_dev *dev, struct rte_flow *flow) 2275 { 2276 const struct mlx5_flow_driver_ops *fops; 2277 enum mlx5_flow_drv_type type = flow->drv_type; 2278 2279 assert(type > MLX5_FLOW_TYPE_MIN && type < MLX5_FLOW_TYPE_MAX); 2280 fops = flow_get_drv_ops(type); 2281 fops->remove(dev, flow); 2282 } 2283 2284 /** 2285 * Flow driver destroy API. This abstracts calling driver specific functions. 2286 * Parent flow (rte_flow) should have driver type (drv_type). It removes a flow 2287 * on device and releases resources of the flow. 2288 * 2289 * @param[in] dev 2290 * Pointer to Ethernet device. 2291 * @param[in, out] flow 2292 * Pointer to flow structure. 2293 */ 2294 static inline void 2295 flow_drv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow) 2296 { 2297 const struct mlx5_flow_driver_ops *fops; 2298 enum mlx5_flow_drv_type type = flow->drv_type; 2299 2300 assert(type > MLX5_FLOW_TYPE_MIN && type < MLX5_FLOW_TYPE_MAX); 2301 fops = flow_get_drv_ops(type); 2302 fops->destroy(dev, flow); 2303 } 2304 2305 /** 2306 * Validate a flow supported by the NIC. 2307 * 2308 * @see rte_flow_validate() 2309 * @see rte_flow_ops 2310 */ 2311 int 2312 mlx5_flow_validate(struct rte_eth_dev *dev, 2313 const struct rte_flow_attr *attr, 2314 const struct rte_flow_item items[], 2315 const struct rte_flow_action actions[], 2316 struct rte_flow_error *error) 2317 { 2318 int ret; 2319 2320 ret = flow_drv_validate(dev, attr, items, actions, true, error); 2321 if (ret < 0) 2322 return ret; 2323 return 0; 2324 } 2325 2326 /** 2327 * Get RSS action from the action list. 2328 * 2329 * @param[in] actions 2330 * Pointer to the list of actions. 2331 * 2332 * @return 2333 * Pointer to the RSS action if exist, else return NULL. 2334 */ 2335 static const struct rte_flow_action_rss* 2336 flow_get_rss_action(const struct rte_flow_action actions[]) 2337 { 2338 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) { 2339 switch (actions->type) { 2340 case RTE_FLOW_ACTION_TYPE_RSS: 2341 return (const struct rte_flow_action_rss *) 2342 actions->conf; 2343 default: 2344 break; 2345 } 2346 } 2347 return NULL; 2348 } 2349 2350 static unsigned int 2351 find_graph_root(const struct rte_flow_item pattern[], uint32_t rss_level) 2352 { 2353 const struct rte_flow_item *item; 2354 unsigned int has_vlan = 0; 2355 2356 for (item = pattern; item->type != RTE_FLOW_ITEM_TYPE_END; item++) { 2357 if (item->type == RTE_FLOW_ITEM_TYPE_VLAN) { 2358 has_vlan = 1; 2359 break; 2360 } 2361 } 2362 if (has_vlan) 2363 return rss_level < 2 ? MLX5_EXPANSION_ROOT_ETH_VLAN : 2364 MLX5_EXPANSION_ROOT_OUTER_ETH_VLAN; 2365 return rss_level < 2 ? MLX5_EXPANSION_ROOT : 2366 MLX5_EXPANSION_ROOT_OUTER; 2367 } 2368 2369 /** 2370 * Create a flow and add it to @p list. 2371 * 2372 * @param dev 2373 * Pointer to Ethernet device. 2374 * @param list 2375 * Pointer to a TAILQ flow list. 2376 * @param[in] attr 2377 * Flow rule attributes. 2378 * @param[in] items 2379 * Pattern specification (list terminated by the END pattern item). 2380 * @param[in] actions 2381 * Associated actions (list terminated by the END action). 2382 * @param[in] external 2383 * This flow rule is created by request external to PMD. 2384 * @param[out] error 2385 * Perform verbose error reporting if not NULL. 2386 * 2387 * @return 2388 * A flow on success, NULL otherwise and rte_errno is set. 2389 */ 2390 static struct rte_flow * 2391 flow_list_create(struct rte_eth_dev *dev, struct mlx5_flows *list, 2392 const struct rte_flow_attr *attr, 2393 const struct rte_flow_item items[], 2394 const struct rte_flow_action actions[], 2395 bool external, struct rte_flow_error *error) 2396 { 2397 struct rte_flow *flow = NULL; 2398 struct mlx5_flow *dev_flow; 2399 const struct rte_flow_action_rss *rss; 2400 union { 2401 struct rte_flow_expand_rss buf; 2402 uint8_t buffer[2048]; 2403 } expand_buffer; 2404 struct rte_flow_expand_rss *buf = &expand_buffer.buf; 2405 int ret; 2406 uint32_t i; 2407 uint32_t flow_size; 2408 2409 ret = flow_drv_validate(dev, attr, items, actions, external, error); 2410 if (ret < 0) 2411 return NULL; 2412 flow_size = sizeof(struct rte_flow); 2413 rss = flow_get_rss_action(actions); 2414 if (rss) 2415 flow_size += RTE_ALIGN_CEIL(rss->queue_num * sizeof(uint16_t), 2416 sizeof(void *)); 2417 else 2418 flow_size += RTE_ALIGN_CEIL(sizeof(uint16_t), sizeof(void *)); 2419 flow = rte_calloc(__func__, 1, flow_size, 0); 2420 if (!flow) { 2421 rte_errno = ENOMEM; 2422 return NULL; 2423 } 2424 flow->drv_type = flow_get_drv_type(dev, attr); 2425 flow->ingress = attr->ingress; 2426 flow->transfer = attr->transfer; 2427 assert(flow->drv_type > MLX5_FLOW_TYPE_MIN && 2428 flow->drv_type < MLX5_FLOW_TYPE_MAX); 2429 flow->queue = (void *)(flow + 1); 2430 LIST_INIT(&flow->dev_flows); 2431 if (rss && rss->types) { 2432 unsigned int graph_root; 2433 2434 graph_root = find_graph_root(items, rss->level); 2435 ret = rte_flow_expand_rss(buf, sizeof(expand_buffer.buffer), 2436 items, rss->types, 2437 mlx5_support_expansion, 2438 graph_root); 2439 assert(ret > 0 && 2440 (unsigned int)ret < sizeof(expand_buffer.buffer)); 2441 } else { 2442 buf->entries = 1; 2443 buf->entry[0].pattern = (void *)(uintptr_t)items; 2444 } 2445 for (i = 0; i < buf->entries; ++i) { 2446 dev_flow = flow_drv_prepare(flow, attr, buf->entry[i].pattern, 2447 actions, error); 2448 if (!dev_flow) 2449 goto error; 2450 dev_flow->flow = flow; 2451 dev_flow->external = external; 2452 LIST_INSERT_HEAD(&flow->dev_flows, dev_flow, next); 2453 ret = flow_drv_translate(dev, dev_flow, attr, 2454 buf->entry[i].pattern, 2455 actions, error); 2456 if (ret < 0) 2457 goto error; 2458 } 2459 if (dev->data->dev_started) { 2460 ret = flow_drv_apply(dev, flow, error); 2461 if (ret < 0) 2462 goto error; 2463 } 2464 TAILQ_INSERT_TAIL(list, flow, next); 2465 flow_rxq_flags_set(dev, flow); 2466 return flow; 2467 error: 2468 ret = rte_errno; /* Save rte_errno before cleanup. */ 2469 assert(flow); 2470 flow_drv_destroy(dev, flow); 2471 rte_free(flow); 2472 rte_errno = ret; /* Restore rte_errno. */ 2473 return NULL; 2474 } 2475 2476 /** 2477 * Create a dedicated flow rule on e-switch table 0 (root table), to direct all 2478 * incoming packets to table 1. 2479 * 2480 * Other flow rules, requested for group n, will be created in 2481 * e-switch table n+1. 2482 * Jump action to e-switch group n will be created to group n+1. 2483 * 2484 * Used when working in switchdev mode, to utilise advantages of table 1 2485 * and above. 2486 * 2487 * @param dev 2488 * Pointer to Ethernet device. 2489 * 2490 * @return 2491 * Pointer to flow on success, NULL otherwise and rte_errno is set. 2492 */ 2493 struct rte_flow * 2494 mlx5_flow_create_esw_table_zero_flow(struct rte_eth_dev *dev) 2495 { 2496 const struct rte_flow_attr attr = { 2497 .group = 0, 2498 .priority = 0, 2499 .ingress = 1, 2500 .egress = 0, 2501 .transfer = 1, 2502 }; 2503 const struct rte_flow_item pattern = { 2504 .type = RTE_FLOW_ITEM_TYPE_END, 2505 }; 2506 struct rte_flow_action_jump jump = { 2507 .group = 1, 2508 }; 2509 const struct rte_flow_action actions[] = { 2510 { 2511 .type = RTE_FLOW_ACTION_TYPE_JUMP, 2512 .conf = &jump, 2513 }, 2514 { 2515 .type = RTE_FLOW_ACTION_TYPE_END, 2516 }, 2517 }; 2518 struct mlx5_priv *priv = dev->data->dev_private; 2519 struct rte_flow_error error; 2520 2521 return flow_list_create(dev, &priv->ctrl_flows, &attr, &pattern, 2522 actions, false, &error); 2523 } 2524 2525 /** 2526 * Create a flow. 2527 * 2528 * @see rte_flow_create() 2529 * @see rte_flow_ops 2530 */ 2531 struct rte_flow * 2532 mlx5_flow_create(struct rte_eth_dev *dev, 2533 const struct rte_flow_attr *attr, 2534 const struct rte_flow_item items[], 2535 const struct rte_flow_action actions[], 2536 struct rte_flow_error *error) 2537 { 2538 struct mlx5_priv *priv = dev->data->dev_private; 2539 2540 return flow_list_create(dev, &priv->flows, 2541 attr, items, actions, true, error); 2542 } 2543 2544 /** 2545 * Destroy a flow in a list. 2546 * 2547 * @param dev 2548 * Pointer to Ethernet device. 2549 * @param list 2550 * Pointer to a TAILQ flow list. 2551 * @param[in] flow 2552 * Flow to destroy. 2553 */ 2554 static void 2555 flow_list_destroy(struct rte_eth_dev *dev, struct mlx5_flows *list, 2556 struct rte_flow *flow) 2557 { 2558 /* 2559 * Update RX queue flags only if port is started, otherwise it is 2560 * already clean. 2561 */ 2562 if (dev->data->dev_started) 2563 flow_rxq_flags_trim(dev, flow); 2564 flow_drv_destroy(dev, flow); 2565 TAILQ_REMOVE(list, flow, next); 2566 rte_free(flow->fdir); 2567 rte_free(flow); 2568 } 2569 2570 /** 2571 * Destroy all flows. 2572 * 2573 * @param dev 2574 * Pointer to Ethernet device. 2575 * @param list 2576 * Pointer to a TAILQ flow list. 2577 */ 2578 void 2579 mlx5_flow_list_flush(struct rte_eth_dev *dev, struct mlx5_flows *list) 2580 { 2581 while (!TAILQ_EMPTY(list)) { 2582 struct rte_flow *flow; 2583 2584 flow = TAILQ_FIRST(list); 2585 flow_list_destroy(dev, list, flow); 2586 } 2587 } 2588 2589 /** 2590 * Remove all flows. 2591 * 2592 * @param dev 2593 * Pointer to Ethernet device. 2594 * @param list 2595 * Pointer to a TAILQ flow list. 2596 */ 2597 void 2598 mlx5_flow_stop(struct rte_eth_dev *dev, struct mlx5_flows *list) 2599 { 2600 struct rte_flow *flow; 2601 2602 TAILQ_FOREACH_REVERSE(flow, list, mlx5_flows, next) 2603 flow_drv_remove(dev, flow); 2604 flow_rxq_flags_clear(dev); 2605 } 2606 2607 /** 2608 * Add all flows. 2609 * 2610 * @param dev 2611 * Pointer to Ethernet device. 2612 * @param list 2613 * Pointer to a TAILQ flow list. 2614 * 2615 * @return 2616 * 0 on success, a negative errno value otherwise and rte_errno is set. 2617 */ 2618 int 2619 mlx5_flow_start(struct rte_eth_dev *dev, struct mlx5_flows *list) 2620 { 2621 struct rte_flow *flow; 2622 struct rte_flow_error error; 2623 int ret = 0; 2624 2625 TAILQ_FOREACH(flow, list, next) { 2626 ret = flow_drv_apply(dev, flow, &error); 2627 if (ret < 0) 2628 goto error; 2629 flow_rxq_flags_set(dev, flow); 2630 } 2631 return 0; 2632 error: 2633 ret = rte_errno; /* Save rte_errno before cleanup. */ 2634 mlx5_flow_stop(dev, list); 2635 rte_errno = ret; /* Restore rte_errno. */ 2636 return -rte_errno; 2637 } 2638 2639 /** 2640 * Verify the flow list is empty 2641 * 2642 * @param dev 2643 * Pointer to Ethernet device. 2644 * 2645 * @return the number of flows not released. 2646 */ 2647 int 2648 mlx5_flow_verify(struct rte_eth_dev *dev) 2649 { 2650 struct mlx5_priv *priv = dev->data->dev_private; 2651 struct rte_flow *flow; 2652 int ret = 0; 2653 2654 TAILQ_FOREACH(flow, &priv->flows, next) { 2655 DRV_LOG(DEBUG, "port %u flow %p still referenced", 2656 dev->data->port_id, (void *)flow); 2657 ++ret; 2658 } 2659 return ret; 2660 } 2661 2662 /** 2663 * Enable a control flow configured from the control plane. 2664 * 2665 * @param dev 2666 * Pointer to Ethernet device. 2667 * @param eth_spec 2668 * An Ethernet flow spec to apply. 2669 * @param eth_mask 2670 * An Ethernet flow mask to apply. 2671 * @param vlan_spec 2672 * A VLAN flow spec to apply. 2673 * @param vlan_mask 2674 * A VLAN flow mask to apply. 2675 * 2676 * @return 2677 * 0 on success, a negative errno value otherwise and rte_errno is set. 2678 */ 2679 int 2680 mlx5_ctrl_flow_vlan(struct rte_eth_dev *dev, 2681 struct rte_flow_item_eth *eth_spec, 2682 struct rte_flow_item_eth *eth_mask, 2683 struct rte_flow_item_vlan *vlan_spec, 2684 struct rte_flow_item_vlan *vlan_mask) 2685 { 2686 struct mlx5_priv *priv = dev->data->dev_private; 2687 const struct rte_flow_attr attr = { 2688 .ingress = 1, 2689 .priority = MLX5_FLOW_PRIO_RSVD, 2690 }; 2691 struct rte_flow_item items[] = { 2692 { 2693 .type = RTE_FLOW_ITEM_TYPE_ETH, 2694 .spec = eth_spec, 2695 .last = NULL, 2696 .mask = eth_mask, 2697 }, 2698 { 2699 .type = (vlan_spec) ? RTE_FLOW_ITEM_TYPE_VLAN : 2700 RTE_FLOW_ITEM_TYPE_END, 2701 .spec = vlan_spec, 2702 .last = NULL, 2703 .mask = vlan_mask, 2704 }, 2705 { 2706 .type = RTE_FLOW_ITEM_TYPE_END, 2707 }, 2708 }; 2709 uint16_t queue[priv->reta_idx_n]; 2710 struct rte_flow_action_rss action_rss = { 2711 .func = RTE_ETH_HASH_FUNCTION_DEFAULT, 2712 .level = 0, 2713 .types = priv->rss_conf.rss_hf, 2714 .key_len = priv->rss_conf.rss_key_len, 2715 .queue_num = priv->reta_idx_n, 2716 .key = priv->rss_conf.rss_key, 2717 .queue = queue, 2718 }; 2719 struct rte_flow_action actions[] = { 2720 { 2721 .type = RTE_FLOW_ACTION_TYPE_RSS, 2722 .conf = &action_rss, 2723 }, 2724 { 2725 .type = RTE_FLOW_ACTION_TYPE_END, 2726 }, 2727 }; 2728 struct rte_flow *flow; 2729 struct rte_flow_error error; 2730 unsigned int i; 2731 2732 if (!priv->reta_idx_n || !priv->rxqs_n) { 2733 return 0; 2734 } 2735 for (i = 0; i != priv->reta_idx_n; ++i) 2736 queue[i] = (*priv->reta_idx)[i]; 2737 flow = flow_list_create(dev, &priv->ctrl_flows, 2738 &attr, items, actions, false, &error); 2739 if (!flow) 2740 return -rte_errno; 2741 return 0; 2742 } 2743 2744 /** 2745 * Enable a flow control configured from the control plane. 2746 * 2747 * @param dev 2748 * Pointer to Ethernet device. 2749 * @param eth_spec 2750 * An Ethernet flow spec to apply. 2751 * @param eth_mask 2752 * An Ethernet flow mask to apply. 2753 * 2754 * @return 2755 * 0 on success, a negative errno value otherwise and rte_errno is set. 2756 */ 2757 int 2758 mlx5_ctrl_flow(struct rte_eth_dev *dev, 2759 struct rte_flow_item_eth *eth_spec, 2760 struct rte_flow_item_eth *eth_mask) 2761 { 2762 return mlx5_ctrl_flow_vlan(dev, eth_spec, eth_mask, NULL, NULL); 2763 } 2764 2765 /** 2766 * Destroy a flow. 2767 * 2768 * @see rte_flow_destroy() 2769 * @see rte_flow_ops 2770 */ 2771 int 2772 mlx5_flow_destroy(struct rte_eth_dev *dev, 2773 struct rte_flow *flow, 2774 struct rte_flow_error *error __rte_unused) 2775 { 2776 struct mlx5_priv *priv = dev->data->dev_private; 2777 2778 flow_list_destroy(dev, &priv->flows, flow); 2779 return 0; 2780 } 2781 2782 /** 2783 * Destroy all flows. 2784 * 2785 * @see rte_flow_flush() 2786 * @see rte_flow_ops 2787 */ 2788 int 2789 mlx5_flow_flush(struct rte_eth_dev *dev, 2790 struct rte_flow_error *error __rte_unused) 2791 { 2792 struct mlx5_priv *priv = dev->data->dev_private; 2793 2794 mlx5_flow_list_flush(dev, &priv->flows); 2795 return 0; 2796 } 2797 2798 /** 2799 * Isolated mode. 2800 * 2801 * @see rte_flow_isolate() 2802 * @see rte_flow_ops 2803 */ 2804 int 2805 mlx5_flow_isolate(struct rte_eth_dev *dev, 2806 int enable, 2807 struct rte_flow_error *error) 2808 { 2809 struct mlx5_priv *priv = dev->data->dev_private; 2810 2811 if (dev->data->dev_started) { 2812 rte_flow_error_set(error, EBUSY, 2813 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, 2814 NULL, 2815 "port must be stopped first"); 2816 return -rte_errno; 2817 } 2818 priv->isolated = !!enable; 2819 if (enable) 2820 dev->dev_ops = &mlx5_dev_ops_isolate; 2821 else 2822 dev->dev_ops = &mlx5_dev_ops; 2823 return 0; 2824 } 2825 2826 /** 2827 * Query a flow. 2828 * 2829 * @see rte_flow_query() 2830 * @see rte_flow_ops 2831 */ 2832 static int 2833 flow_drv_query(struct rte_eth_dev *dev, 2834 struct rte_flow *flow, 2835 const struct rte_flow_action *actions, 2836 void *data, 2837 struct rte_flow_error *error) 2838 { 2839 const struct mlx5_flow_driver_ops *fops; 2840 enum mlx5_flow_drv_type ftype = flow->drv_type; 2841 2842 assert(ftype > MLX5_FLOW_TYPE_MIN && ftype < MLX5_FLOW_TYPE_MAX); 2843 fops = flow_get_drv_ops(ftype); 2844 2845 return fops->query(dev, flow, actions, data, error); 2846 } 2847 2848 /** 2849 * Query a flow. 2850 * 2851 * @see rte_flow_query() 2852 * @see rte_flow_ops 2853 */ 2854 int 2855 mlx5_flow_query(struct rte_eth_dev *dev, 2856 struct rte_flow *flow, 2857 const struct rte_flow_action *actions, 2858 void *data, 2859 struct rte_flow_error *error) 2860 { 2861 int ret; 2862 2863 ret = flow_drv_query(dev, flow, actions, data, error); 2864 if (ret < 0) 2865 return ret; 2866 return 0; 2867 } 2868 2869 /** 2870 * Convert a flow director filter to a generic flow. 2871 * 2872 * @param dev 2873 * Pointer to Ethernet device. 2874 * @param fdir_filter 2875 * Flow director filter to add. 2876 * @param attributes 2877 * Generic flow parameters structure. 2878 * 2879 * @return 2880 * 0 on success, a negative errno value otherwise and rte_errno is set. 2881 */ 2882 static int 2883 flow_fdir_filter_convert(struct rte_eth_dev *dev, 2884 const struct rte_eth_fdir_filter *fdir_filter, 2885 struct mlx5_fdir *attributes) 2886 { 2887 struct mlx5_priv *priv = dev->data->dev_private; 2888 const struct rte_eth_fdir_input *input = &fdir_filter->input; 2889 const struct rte_eth_fdir_masks *mask = 2890 &dev->data->dev_conf.fdir_conf.mask; 2891 2892 /* Validate queue number. */ 2893 if (fdir_filter->action.rx_queue >= priv->rxqs_n) { 2894 DRV_LOG(ERR, "port %u invalid queue number %d", 2895 dev->data->port_id, fdir_filter->action.rx_queue); 2896 rte_errno = EINVAL; 2897 return -rte_errno; 2898 } 2899 attributes->attr.ingress = 1; 2900 attributes->items[0] = (struct rte_flow_item) { 2901 .type = RTE_FLOW_ITEM_TYPE_ETH, 2902 .spec = &attributes->l2, 2903 .mask = &attributes->l2_mask, 2904 }; 2905 switch (fdir_filter->action.behavior) { 2906 case RTE_ETH_FDIR_ACCEPT: 2907 attributes->actions[0] = (struct rte_flow_action){ 2908 .type = RTE_FLOW_ACTION_TYPE_QUEUE, 2909 .conf = &attributes->queue, 2910 }; 2911 break; 2912 case RTE_ETH_FDIR_REJECT: 2913 attributes->actions[0] = (struct rte_flow_action){ 2914 .type = RTE_FLOW_ACTION_TYPE_DROP, 2915 }; 2916 break; 2917 default: 2918 DRV_LOG(ERR, "port %u invalid behavior %d", 2919 dev->data->port_id, 2920 fdir_filter->action.behavior); 2921 rte_errno = ENOTSUP; 2922 return -rte_errno; 2923 } 2924 attributes->queue.index = fdir_filter->action.rx_queue; 2925 /* Handle L3. */ 2926 switch (fdir_filter->input.flow_type) { 2927 case RTE_ETH_FLOW_NONFRAG_IPV4_UDP: 2928 case RTE_ETH_FLOW_NONFRAG_IPV4_TCP: 2929 case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER: 2930 attributes->l3.ipv4.hdr = (struct rte_ipv4_hdr){ 2931 .src_addr = input->flow.ip4_flow.src_ip, 2932 .dst_addr = input->flow.ip4_flow.dst_ip, 2933 .time_to_live = input->flow.ip4_flow.ttl, 2934 .type_of_service = input->flow.ip4_flow.tos, 2935 }; 2936 attributes->l3_mask.ipv4.hdr = (struct rte_ipv4_hdr){ 2937 .src_addr = mask->ipv4_mask.src_ip, 2938 .dst_addr = mask->ipv4_mask.dst_ip, 2939 .time_to_live = mask->ipv4_mask.ttl, 2940 .type_of_service = mask->ipv4_mask.tos, 2941 .next_proto_id = mask->ipv4_mask.proto, 2942 }; 2943 attributes->items[1] = (struct rte_flow_item){ 2944 .type = RTE_FLOW_ITEM_TYPE_IPV4, 2945 .spec = &attributes->l3, 2946 .mask = &attributes->l3_mask, 2947 }; 2948 break; 2949 case RTE_ETH_FLOW_NONFRAG_IPV6_UDP: 2950 case RTE_ETH_FLOW_NONFRAG_IPV6_TCP: 2951 case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER: 2952 attributes->l3.ipv6.hdr = (struct rte_ipv6_hdr){ 2953 .hop_limits = input->flow.ipv6_flow.hop_limits, 2954 .proto = input->flow.ipv6_flow.proto, 2955 }; 2956 2957 memcpy(attributes->l3.ipv6.hdr.src_addr, 2958 input->flow.ipv6_flow.src_ip, 2959 RTE_DIM(attributes->l3.ipv6.hdr.src_addr)); 2960 memcpy(attributes->l3.ipv6.hdr.dst_addr, 2961 input->flow.ipv6_flow.dst_ip, 2962 RTE_DIM(attributes->l3.ipv6.hdr.src_addr)); 2963 memcpy(attributes->l3_mask.ipv6.hdr.src_addr, 2964 mask->ipv6_mask.src_ip, 2965 RTE_DIM(attributes->l3_mask.ipv6.hdr.src_addr)); 2966 memcpy(attributes->l3_mask.ipv6.hdr.dst_addr, 2967 mask->ipv6_mask.dst_ip, 2968 RTE_DIM(attributes->l3_mask.ipv6.hdr.src_addr)); 2969 attributes->items[1] = (struct rte_flow_item){ 2970 .type = RTE_FLOW_ITEM_TYPE_IPV6, 2971 .spec = &attributes->l3, 2972 .mask = &attributes->l3_mask, 2973 }; 2974 break; 2975 default: 2976 DRV_LOG(ERR, "port %u invalid flow type%d", 2977 dev->data->port_id, fdir_filter->input.flow_type); 2978 rte_errno = ENOTSUP; 2979 return -rte_errno; 2980 } 2981 /* Handle L4. */ 2982 switch (fdir_filter->input.flow_type) { 2983 case RTE_ETH_FLOW_NONFRAG_IPV4_UDP: 2984 attributes->l4.udp.hdr = (struct rte_udp_hdr){ 2985 .src_port = input->flow.udp4_flow.src_port, 2986 .dst_port = input->flow.udp4_flow.dst_port, 2987 }; 2988 attributes->l4_mask.udp.hdr = (struct rte_udp_hdr){ 2989 .src_port = mask->src_port_mask, 2990 .dst_port = mask->dst_port_mask, 2991 }; 2992 attributes->items[2] = (struct rte_flow_item){ 2993 .type = RTE_FLOW_ITEM_TYPE_UDP, 2994 .spec = &attributes->l4, 2995 .mask = &attributes->l4_mask, 2996 }; 2997 break; 2998 case RTE_ETH_FLOW_NONFRAG_IPV4_TCP: 2999 attributes->l4.tcp.hdr = (struct rte_tcp_hdr){ 3000 .src_port = input->flow.tcp4_flow.src_port, 3001 .dst_port = input->flow.tcp4_flow.dst_port, 3002 }; 3003 attributes->l4_mask.tcp.hdr = (struct rte_tcp_hdr){ 3004 .src_port = mask->src_port_mask, 3005 .dst_port = mask->dst_port_mask, 3006 }; 3007 attributes->items[2] = (struct rte_flow_item){ 3008 .type = RTE_FLOW_ITEM_TYPE_TCP, 3009 .spec = &attributes->l4, 3010 .mask = &attributes->l4_mask, 3011 }; 3012 break; 3013 case RTE_ETH_FLOW_NONFRAG_IPV6_UDP: 3014 attributes->l4.udp.hdr = (struct rte_udp_hdr){ 3015 .src_port = input->flow.udp6_flow.src_port, 3016 .dst_port = input->flow.udp6_flow.dst_port, 3017 }; 3018 attributes->l4_mask.udp.hdr = (struct rte_udp_hdr){ 3019 .src_port = mask->src_port_mask, 3020 .dst_port = mask->dst_port_mask, 3021 }; 3022 attributes->items[2] = (struct rte_flow_item){ 3023 .type = RTE_FLOW_ITEM_TYPE_UDP, 3024 .spec = &attributes->l4, 3025 .mask = &attributes->l4_mask, 3026 }; 3027 break; 3028 case RTE_ETH_FLOW_NONFRAG_IPV6_TCP: 3029 attributes->l4.tcp.hdr = (struct rte_tcp_hdr){ 3030 .src_port = input->flow.tcp6_flow.src_port, 3031 .dst_port = input->flow.tcp6_flow.dst_port, 3032 }; 3033 attributes->l4_mask.tcp.hdr = (struct rte_tcp_hdr){ 3034 .src_port = mask->src_port_mask, 3035 .dst_port = mask->dst_port_mask, 3036 }; 3037 attributes->items[2] = (struct rte_flow_item){ 3038 .type = RTE_FLOW_ITEM_TYPE_TCP, 3039 .spec = &attributes->l4, 3040 .mask = &attributes->l4_mask, 3041 }; 3042 break; 3043 case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER: 3044 case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER: 3045 break; 3046 default: 3047 DRV_LOG(ERR, "port %u invalid flow type%d", 3048 dev->data->port_id, fdir_filter->input.flow_type); 3049 rte_errno = ENOTSUP; 3050 return -rte_errno; 3051 } 3052 return 0; 3053 } 3054 3055 #define FLOW_FDIR_CMP(f1, f2, fld) \ 3056 memcmp(&(f1)->fld, &(f2)->fld, sizeof(f1->fld)) 3057 3058 /** 3059 * Compare two FDIR flows. If items and actions are identical, the two flows are 3060 * regarded as same. 3061 * 3062 * @param dev 3063 * Pointer to Ethernet device. 3064 * @param f1 3065 * FDIR flow to compare. 3066 * @param f2 3067 * FDIR flow to compare. 3068 * 3069 * @return 3070 * Zero on match, 1 otherwise. 3071 */ 3072 static int 3073 flow_fdir_cmp(const struct mlx5_fdir *f1, const struct mlx5_fdir *f2) 3074 { 3075 if (FLOW_FDIR_CMP(f1, f2, attr) || 3076 FLOW_FDIR_CMP(f1, f2, l2) || 3077 FLOW_FDIR_CMP(f1, f2, l2_mask) || 3078 FLOW_FDIR_CMP(f1, f2, l3) || 3079 FLOW_FDIR_CMP(f1, f2, l3_mask) || 3080 FLOW_FDIR_CMP(f1, f2, l4) || 3081 FLOW_FDIR_CMP(f1, f2, l4_mask) || 3082 FLOW_FDIR_CMP(f1, f2, actions[0].type)) 3083 return 1; 3084 if (f1->actions[0].type == RTE_FLOW_ACTION_TYPE_QUEUE && 3085 FLOW_FDIR_CMP(f1, f2, queue)) 3086 return 1; 3087 return 0; 3088 } 3089 3090 /** 3091 * Search device flow list to find out a matched FDIR flow. 3092 * 3093 * @param dev 3094 * Pointer to Ethernet device. 3095 * @param fdir_flow 3096 * FDIR flow to lookup. 3097 * 3098 * @return 3099 * Pointer of flow if found, NULL otherwise. 3100 */ 3101 static struct rte_flow * 3102 flow_fdir_filter_lookup(struct rte_eth_dev *dev, struct mlx5_fdir *fdir_flow) 3103 { 3104 struct mlx5_priv *priv = dev->data->dev_private; 3105 struct rte_flow *flow = NULL; 3106 3107 assert(fdir_flow); 3108 TAILQ_FOREACH(flow, &priv->flows, next) { 3109 if (flow->fdir && !flow_fdir_cmp(flow->fdir, fdir_flow)) { 3110 DRV_LOG(DEBUG, "port %u found FDIR flow %p", 3111 dev->data->port_id, (void *)flow); 3112 break; 3113 } 3114 } 3115 return flow; 3116 } 3117 3118 /** 3119 * Add new flow director filter and store it in list. 3120 * 3121 * @param dev 3122 * Pointer to Ethernet device. 3123 * @param fdir_filter 3124 * Flow director filter to add. 3125 * 3126 * @return 3127 * 0 on success, a negative errno value otherwise and rte_errno is set. 3128 */ 3129 static int 3130 flow_fdir_filter_add(struct rte_eth_dev *dev, 3131 const struct rte_eth_fdir_filter *fdir_filter) 3132 { 3133 struct mlx5_priv *priv = dev->data->dev_private; 3134 struct mlx5_fdir *fdir_flow; 3135 struct rte_flow *flow; 3136 int ret; 3137 3138 fdir_flow = rte_zmalloc(__func__, sizeof(*fdir_flow), 0); 3139 if (!fdir_flow) { 3140 rte_errno = ENOMEM; 3141 return -rte_errno; 3142 } 3143 ret = flow_fdir_filter_convert(dev, fdir_filter, fdir_flow); 3144 if (ret) 3145 goto error; 3146 flow = flow_fdir_filter_lookup(dev, fdir_flow); 3147 if (flow) { 3148 rte_errno = EEXIST; 3149 goto error; 3150 } 3151 flow = flow_list_create(dev, &priv->flows, &fdir_flow->attr, 3152 fdir_flow->items, fdir_flow->actions, true, 3153 NULL); 3154 if (!flow) 3155 goto error; 3156 assert(!flow->fdir); 3157 flow->fdir = fdir_flow; 3158 DRV_LOG(DEBUG, "port %u created FDIR flow %p", 3159 dev->data->port_id, (void *)flow); 3160 return 0; 3161 error: 3162 rte_free(fdir_flow); 3163 return -rte_errno; 3164 } 3165 3166 /** 3167 * Delete specific filter. 3168 * 3169 * @param dev 3170 * Pointer to Ethernet device. 3171 * @param fdir_filter 3172 * Filter to be deleted. 3173 * 3174 * @return 3175 * 0 on success, a negative errno value otherwise and rte_errno is set. 3176 */ 3177 static int 3178 flow_fdir_filter_delete(struct rte_eth_dev *dev, 3179 const struct rte_eth_fdir_filter *fdir_filter) 3180 { 3181 struct mlx5_priv *priv = dev->data->dev_private; 3182 struct rte_flow *flow; 3183 struct mlx5_fdir fdir_flow = { 3184 .attr.group = 0, 3185 }; 3186 int ret; 3187 3188 ret = flow_fdir_filter_convert(dev, fdir_filter, &fdir_flow); 3189 if (ret) 3190 return -rte_errno; 3191 flow = flow_fdir_filter_lookup(dev, &fdir_flow); 3192 if (!flow) { 3193 rte_errno = ENOENT; 3194 return -rte_errno; 3195 } 3196 flow_list_destroy(dev, &priv->flows, flow); 3197 DRV_LOG(DEBUG, "port %u deleted FDIR flow %p", 3198 dev->data->port_id, (void *)flow); 3199 return 0; 3200 } 3201 3202 /** 3203 * Update queue for specific filter. 3204 * 3205 * @param dev 3206 * Pointer to Ethernet device. 3207 * @param fdir_filter 3208 * Filter to be updated. 3209 * 3210 * @return 3211 * 0 on success, a negative errno value otherwise and rte_errno is set. 3212 */ 3213 static int 3214 flow_fdir_filter_update(struct rte_eth_dev *dev, 3215 const struct rte_eth_fdir_filter *fdir_filter) 3216 { 3217 int ret; 3218 3219 ret = flow_fdir_filter_delete(dev, fdir_filter); 3220 if (ret) 3221 return ret; 3222 return flow_fdir_filter_add(dev, fdir_filter); 3223 } 3224 3225 /** 3226 * Flush all filters. 3227 * 3228 * @param dev 3229 * Pointer to Ethernet device. 3230 */ 3231 static void 3232 flow_fdir_filter_flush(struct rte_eth_dev *dev) 3233 { 3234 struct mlx5_priv *priv = dev->data->dev_private; 3235 3236 mlx5_flow_list_flush(dev, &priv->flows); 3237 } 3238 3239 /** 3240 * Get flow director information. 3241 * 3242 * @param dev 3243 * Pointer to Ethernet device. 3244 * @param[out] fdir_info 3245 * Resulting flow director information. 3246 */ 3247 static void 3248 flow_fdir_info_get(struct rte_eth_dev *dev, struct rte_eth_fdir_info *fdir_info) 3249 { 3250 struct rte_eth_fdir_masks *mask = 3251 &dev->data->dev_conf.fdir_conf.mask; 3252 3253 fdir_info->mode = dev->data->dev_conf.fdir_conf.mode; 3254 fdir_info->guarant_spc = 0; 3255 rte_memcpy(&fdir_info->mask, mask, sizeof(fdir_info->mask)); 3256 fdir_info->max_flexpayload = 0; 3257 fdir_info->flow_types_mask[0] = 0; 3258 fdir_info->flex_payload_unit = 0; 3259 fdir_info->max_flex_payload_segment_num = 0; 3260 fdir_info->flex_payload_limit = 0; 3261 memset(&fdir_info->flex_conf, 0, sizeof(fdir_info->flex_conf)); 3262 } 3263 3264 /** 3265 * Deal with flow director operations. 3266 * 3267 * @param dev 3268 * Pointer to Ethernet device. 3269 * @param filter_op 3270 * Operation to perform. 3271 * @param arg 3272 * Pointer to operation-specific structure. 3273 * 3274 * @return 3275 * 0 on success, a negative errno value otherwise and rte_errno is set. 3276 */ 3277 static int 3278 flow_fdir_ctrl_func(struct rte_eth_dev *dev, enum rte_filter_op filter_op, 3279 void *arg) 3280 { 3281 enum rte_fdir_mode fdir_mode = 3282 dev->data->dev_conf.fdir_conf.mode; 3283 3284 if (filter_op == RTE_ETH_FILTER_NOP) 3285 return 0; 3286 if (fdir_mode != RTE_FDIR_MODE_PERFECT && 3287 fdir_mode != RTE_FDIR_MODE_PERFECT_MAC_VLAN) { 3288 DRV_LOG(ERR, "port %u flow director mode %d not supported", 3289 dev->data->port_id, fdir_mode); 3290 rte_errno = EINVAL; 3291 return -rte_errno; 3292 } 3293 switch (filter_op) { 3294 case RTE_ETH_FILTER_ADD: 3295 return flow_fdir_filter_add(dev, arg); 3296 case RTE_ETH_FILTER_UPDATE: 3297 return flow_fdir_filter_update(dev, arg); 3298 case RTE_ETH_FILTER_DELETE: 3299 return flow_fdir_filter_delete(dev, arg); 3300 case RTE_ETH_FILTER_FLUSH: 3301 flow_fdir_filter_flush(dev); 3302 break; 3303 case RTE_ETH_FILTER_INFO: 3304 flow_fdir_info_get(dev, arg); 3305 break; 3306 default: 3307 DRV_LOG(DEBUG, "port %u unknown operation %u", 3308 dev->data->port_id, filter_op); 3309 rte_errno = EINVAL; 3310 return -rte_errno; 3311 } 3312 return 0; 3313 } 3314 3315 /** 3316 * Manage filter operations. 3317 * 3318 * @param dev 3319 * Pointer to Ethernet device structure. 3320 * @param filter_type 3321 * Filter type. 3322 * @param filter_op 3323 * Operation to perform. 3324 * @param arg 3325 * Pointer to operation-specific structure. 3326 * 3327 * @return 3328 * 0 on success, a negative errno value otherwise and rte_errno is set. 3329 */ 3330 int 3331 mlx5_dev_filter_ctrl(struct rte_eth_dev *dev, 3332 enum rte_filter_type filter_type, 3333 enum rte_filter_op filter_op, 3334 void *arg) 3335 { 3336 switch (filter_type) { 3337 case RTE_ETH_FILTER_GENERIC: 3338 if (filter_op != RTE_ETH_FILTER_GET) { 3339 rte_errno = EINVAL; 3340 return -rte_errno; 3341 } 3342 *(const void **)arg = &mlx5_flow_ops; 3343 return 0; 3344 case RTE_ETH_FILTER_FDIR: 3345 return flow_fdir_ctrl_func(dev, filter_op, arg); 3346 default: 3347 DRV_LOG(ERR, "port %u filter type (%d) not supported", 3348 dev->data->port_id, filter_type); 3349 rte_errno = ENOTSUP; 3350 return -rte_errno; 3351 } 3352 return 0; 3353 } 3354 3355 #define MLX5_POOL_QUERY_FREQ_US 1000000 3356 3357 /** 3358 * Set the periodic procedure for triggering asynchronous batch queries for all 3359 * the counter pools. 3360 * 3361 * @param[in] sh 3362 * Pointer to mlx5_ibv_shared object. 3363 */ 3364 void 3365 mlx5_set_query_alarm(struct mlx5_ibv_shared *sh) 3366 { 3367 struct mlx5_pools_container *cont = MLX5_CNT_CONTAINER(sh, 0, 0); 3368 uint32_t pools_n = rte_atomic16_read(&cont->n_valid); 3369 uint32_t us; 3370 3371 cont = MLX5_CNT_CONTAINER(sh, 1, 0); 3372 pools_n += rte_atomic16_read(&cont->n_valid); 3373 us = MLX5_POOL_QUERY_FREQ_US / pools_n; 3374 DRV_LOG(DEBUG, "Set alarm for %u pools each %u us\n", pools_n, us); 3375 if (rte_eal_alarm_set(us, mlx5_flow_query_alarm, sh)) { 3376 sh->cmng.query_thread_on = 0; 3377 DRV_LOG(ERR, "Cannot reinitialize query alarm\n"); 3378 } else { 3379 sh->cmng.query_thread_on = 1; 3380 } 3381 } 3382 3383 /** 3384 * The periodic procedure for triggering asynchronous batch queries for all the 3385 * counter pools. This function is probably called by the host thread. 3386 * 3387 * @param[in] arg 3388 * The parameter for the alarm process. 3389 */ 3390 void 3391 mlx5_flow_query_alarm(void *arg) 3392 { 3393 struct mlx5_ibv_shared *sh = arg; 3394 struct mlx5_devx_obj *dcs; 3395 uint16_t offset; 3396 int ret; 3397 uint8_t batch = sh->cmng.batch; 3398 uint16_t pool_index = sh->cmng.pool_index; 3399 struct mlx5_pools_container *cont; 3400 struct mlx5_pools_container *mcont; 3401 struct mlx5_flow_counter_pool *pool; 3402 3403 if (sh->cmng.pending_queries >= MLX5_MAX_PENDING_QUERIES) 3404 goto set_alarm; 3405 next_container: 3406 cont = MLX5_CNT_CONTAINER(sh, batch, 1); 3407 mcont = MLX5_CNT_CONTAINER(sh, batch, 0); 3408 /* Check if resize was done and need to flip a container. */ 3409 if (cont != mcont) { 3410 if (cont->pools) { 3411 /* Clean the old container. */ 3412 rte_free(cont->pools); 3413 memset(cont, 0, sizeof(*cont)); 3414 } 3415 rte_cio_wmb(); 3416 /* Flip the host container. */ 3417 sh->cmng.mhi[batch] ^= (uint8_t)2; 3418 cont = mcont; 3419 } 3420 if (!cont->pools) { 3421 /* 2 empty containers case is unexpected. */ 3422 if (unlikely(batch != sh->cmng.batch)) 3423 goto set_alarm; 3424 batch ^= 0x1; 3425 pool_index = 0; 3426 goto next_container; 3427 } 3428 pool = cont->pools[pool_index]; 3429 if (pool->raw_hw) 3430 /* There is a pool query in progress. */ 3431 goto set_alarm; 3432 pool->raw_hw = 3433 LIST_FIRST(&sh->cmng.free_stat_raws); 3434 if (!pool->raw_hw) 3435 /* No free counter statistics raw memory. */ 3436 goto set_alarm; 3437 dcs = (struct mlx5_devx_obj *)(uintptr_t)rte_atomic64_read 3438 (&pool->a64_dcs); 3439 offset = batch ? 0 : dcs->id % MLX5_COUNTERS_PER_POOL; 3440 ret = mlx5_devx_cmd_flow_counter_query(dcs, 0, MLX5_COUNTERS_PER_POOL - 3441 offset, NULL, NULL, 3442 pool->raw_hw->mem_mng->dm->id, 3443 (void *)(uintptr_t) 3444 (pool->raw_hw->data + offset), 3445 sh->devx_comp, 3446 (uint64_t)(uintptr_t)pool); 3447 if (ret) { 3448 DRV_LOG(ERR, "Failed to trigger asynchronous query for dcs ID" 3449 " %d\n", pool->min_dcs->id); 3450 pool->raw_hw = NULL; 3451 goto set_alarm; 3452 } 3453 pool->raw_hw->min_dcs_id = dcs->id; 3454 LIST_REMOVE(pool->raw_hw, next); 3455 sh->cmng.pending_queries++; 3456 pool_index++; 3457 if (pool_index >= rte_atomic16_read(&cont->n_valid)) { 3458 batch ^= 0x1; 3459 pool_index = 0; 3460 } 3461 set_alarm: 3462 sh->cmng.batch = batch; 3463 sh->cmng.pool_index = pool_index; 3464 mlx5_set_query_alarm(sh); 3465 } 3466 3467 /** 3468 * Handler for the HW respond about ready values from an asynchronous batch 3469 * query. This function is probably called by the host thread. 3470 * 3471 * @param[in] sh 3472 * The pointer to the shared IB device context. 3473 * @param[in] async_id 3474 * The Devx async ID. 3475 * @param[in] status 3476 * The status of the completion. 3477 */ 3478 void 3479 mlx5_flow_async_pool_query_handle(struct mlx5_ibv_shared *sh, 3480 uint64_t async_id, int status) 3481 { 3482 struct mlx5_flow_counter_pool *pool = 3483 (struct mlx5_flow_counter_pool *)(uintptr_t)async_id; 3484 struct mlx5_counter_stats_raw *raw_to_free; 3485 3486 if (unlikely(status)) { 3487 raw_to_free = pool->raw_hw; 3488 } else { 3489 raw_to_free = pool->raw; 3490 rte_spinlock_lock(&pool->sl); 3491 pool->raw = pool->raw_hw; 3492 rte_spinlock_unlock(&pool->sl); 3493 rte_atomic64_add(&pool->query_gen, 1); 3494 /* Be sure the new raw counters data is updated in memory. */ 3495 rte_cio_wmb(); 3496 } 3497 LIST_INSERT_HEAD(&sh->cmng.free_stat_raws, raw_to_free, next); 3498 pool->raw_hw = NULL; 3499 sh->cmng.pending_queries--; 3500 } 3501 3502 /** 3503 * Translate the rte_flow group index to HW table value. 3504 * 3505 * @param[in] attributes 3506 * Pointer to flow attributes 3507 * @param[in] external 3508 * Value is part of flow rule created by request external to PMD. 3509 * @param[in] group 3510 * rte_flow group index value. 3511 * @param[out] table 3512 * HW table value. 3513 * @param[out] error 3514 * Pointer to error structure. 3515 * 3516 * @return 3517 * 0 on success, a negative errno value otherwise and rte_errno is set. 3518 */ 3519 int 3520 mlx5_flow_group_to_table(const struct rte_flow_attr *attributes, bool external, 3521 uint32_t group, uint32_t *table, 3522 struct rte_flow_error *error) 3523 { 3524 if (attributes->transfer && external) { 3525 if (group == UINT32_MAX) 3526 return rte_flow_error_set 3527 (error, EINVAL, 3528 RTE_FLOW_ERROR_TYPE_ATTR_GROUP, 3529 NULL, 3530 "group index not supported"); 3531 *table = group + 1; 3532 } else { 3533 *table = group; 3534 } 3535 return 0; 3536 } 3537