1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2016 6WIND S.A. 3 * Copyright 2016 Mellanox Technologies, Ltd 4 */ 5 6 #include <stdalign.h> 7 #include <stdint.h> 8 #include <string.h> 9 #include <stdbool.h> 10 #include <sys/queue.h> 11 12 #include <rte_common.h> 13 #include <rte_ether.h> 14 #include <ethdev_driver.h> 15 #include <rte_eal_paging.h> 16 #include <rte_flow.h> 17 #include <rte_cycles.h> 18 #include <rte_flow_driver.h> 19 #include <rte_malloc.h> 20 #include <rte_ip.h> 21 22 #include <mlx5_glue.h> 23 #include <mlx5_devx_cmds.h> 24 #include <mlx5_prm.h> 25 #include <mlx5_malloc.h> 26 27 #include "mlx5_defs.h" 28 #include "mlx5.h" 29 #include "mlx5_flow.h" 30 #include "mlx5_flow_os.h" 31 #include "mlx5_rx.h" 32 #include "mlx5_tx.h" 33 #include "mlx5_common_os.h" 34 #include "rte_pmd_mlx5.h" 35 36 /* 37 * Shared array for quick translation between port_id and vport mask/values 38 * used for HWS rules. 39 */ 40 struct flow_hw_port_info mlx5_flow_hw_port_infos[RTE_MAX_ETHPORTS]; 41 42 /* 43 * A global structure to save the available REG_C_x for tags usage. 44 * The Meter color REG (ASO) and the last available one will be reserved 45 * for PMD internal usage. 46 * Since there is no "port" concept in the driver, it is assumed that the 47 * available tags set will be the minimum intersection. 48 * 3 - in FDB mode / 5 - in legacy mode 49 */ 50 uint32_t mlx5_flow_hw_avl_tags_init_cnt; 51 enum modify_reg mlx5_flow_hw_avl_tags[MLX5_FLOW_HW_TAGS_MAX] = {REG_NON}; 52 enum modify_reg mlx5_flow_hw_aso_tag; 53 54 struct tunnel_default_miss_ctx { 55 uint16_t *queue; 56 __extension__ 57 union { 58 struct rte_flow_action_rss action_rss; 59 struct rte_flow_action_queue miss_queue; 60 struct rte_flow_action_jump miss_jump; 61 uint8_t raw[0]; 62 }; 63 }; 64 65 static int 66 flow_tunnel_add_default_miss(struct rte_eth_dev *dev, 67 struct rte_flow *flow, 68 const struct rte_flow_attr *attr, 69 const struct rte_flow_action *app_actions, 70 uint32_t flow_idx, 71 const struct mlx5_flow_tunnel *tunnel, 72 struct tunnel_default_miss_ctx *ctx, 73 struct rte_flow_error *error); 74 static struct mlx5_flow_tunnel * 75 mlx5_find_tunnel_id(struct rte_eth_dev *dev, uint32_t id); 76 static void 77 mlx5_flow_tunnel_free(struct rte_eth_dev *dev, struct mlx5_flow_tunnel *tunnel); 78 static uint32_t 79 tunnel_flow_group_to_flow_table(struct rte_eth_dev *dev, 80 const struct mlx5_flow_tunnel *tunnel, 81 uint32_t group, uint32_t *table, 82 struct rte_flow_error *error); 83 84 /** Device flow drivers. */ 85 extern const struct mlx5_flow_driver_ops mlx5_flow_verbs_drv_ops; 86 87 const struct mlx5_flow_driver_ops mlx5_flow_null_drv_ops; 88 89 const struct mlx5_flow_driver_ops *flow_drv_ops[] = { 90 [MLX5_FLOW_TYPE_MIN] = &mlx5_flow_null_drv_ops, 91 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H) 92 [MLX5_FLOW_TYPE_DV] = &mlx5_flow_dv_drv_ops, 93 #endif 94 #ifdef HAVE_MLX5_HWS_SUPPORT 95 [MLX5_FLOW_TYPE_HW] = &mlx5_flow_hw_drv_ops, 96 #endif 97 [MLX5_FLOW_TYPE_VERBS] = &mlx5_flow_verbs_drv_ops, 98 [MLX5_FLOW_TYPE_MAX] = &mlx5_flow_null_drv_ops 99 }; 100 101 /** Helper macro to build input graph for mlx5_flow_expand_rss(). */ 102 #define MLX5_FLOW_EXPAND_RSS_NEXT(...) \ 103 (const int []){ \ 104 __VA_ARGS__, 0, \ 105 } 106 107 /** Node object of input graph for mlx5_flow_expand_rss(). */ 108 struct mlx5_flow_expand_node { 109 const int *const next; 110 /**< 111 * List of next node indexes. Index 0 is interpreted as a terminator. 112 */ 113 const enum rte_flow_item_type type; 114 /**< Pattern item type of current node. */ 115 uint64_t rss_types; 116 /**< 117 * RSS types bit-field associated with this node 118 * (see RTE_ETH_RSS_* definitions). 119 */ 120 uint64_t node_flags; 121 /**< 122 * Bit-fields that define how the node is used in the expansion. 123 * (see MLX5_EXPANSION_NODE_* definitions). 124 */ 125 }; 126 127 /** Keep same format with mlx5_flow_expand_rss to share the buffer for expansion. */ 128 struct mlx5_flow_expand_sqn { 129 uint32_t entries; /** Number of entries */ 130 struct { 131 struct rte_flow_item *pattern; /**< Expanded pattern array. */ 132 uint32_t priority; /**< Priority offset for each expansion. */ 133 } entry[]; 134 }; 135 136 /* Optional expand field. The expansion alg will not go deeper. */ 137 #define MLX5_EXPANSION_NODE_OPTIONAL (UINT64_C(1) << 0) 138 139 /* The node is not added implicitly as expansion to the flow pattern. 140 * If the node type does not match the flow pattern item type, the 141 * expansion alg will go deeper to its next items. 142 * In the current implementation, the list of next nodes indexes can 143 * have up to one node with this flag set and it has to be the last 144 * node index (before the list terminator). 145 */ 146 #define MLX5_EXPANSION_NODE_EXPLICIT (UINT64_C(1) << 1) 147 148 /** Object returned by mlx5_flow_expand_rss(). */ 149 struct mlx5_flow_expand_rss { 150 uint32_t entries; 151 /**< Number of entries @p patterns and @p priorities. */ 152 struct { 153 struct rte_flow_item *pattern; /**< Expanded pattern array. */ 154 uint32_t priority; /**< Priority offset for each expansion. */ 155 } entry[]; 156 }; 157 158 static void 159 mlx5_dbg__print_pattern(const struct rte_flow_item *item); 160 161 static const struct mlx5_flow_expand_node * 162 mlx5_flow_expand_rss_adjust_node(const struct rte_flow_item *pattern, 163 unsigned int item_idx, 164 const struct mlx5_flow_expand_node graph[], 165 const struct mlx5_flow_expand_node *node); 166 167 static bool 168 mlx5_flow_is_rss_expandable_item(const struct rte_flow_item *item) 169 { 170 switch (item->type) { 171 case RTE_FLOW_ITEM_TYPE_ETH: 172 case RTE_FLOW_ITEM_TYPE_VLAN: 173 case RTE_FLOW_ITEM_TYPE_IPV4: 174 case RTE_FLOW_ITEM_TYPE_IPV6: 175 case RTE_FLOW_ITEM_TYPE_UDP: 176 case RTE_FLOW_ITEM_TYPE_TCP: 177 case RTE_FLOW_ITEM_TYPE_ESP: 178 case RTE_FLOW_ITEM_TYPE_ICMP: 179 case RTE_FLOW_ITEM_TYPE_ICMP6: 180 case RTE_FLOW_ITEM_TYPE_VXLAN: 181 case RTE_FLOW_ITEM_TYPE_NVGRE: 182 case RTE_FLOW_ITEM_TYPE_GRE: 183 case RTE_FLOW_ITEM_TYPE_GENEVE: 184 case RTE_FLOW_ITEM_TYPE_MPLS: 185 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE: 186 case RTE_FLOW_ITEM_TYPE_GRE_KEY: 187 case RTE_FLOW_ITEM_TYPE_IPV6_FRAG_EXT: 188 case RTE_FLOW_ITEM_TYPE_GTP: 189 return true; 190 default: 191 break; 192 } 193 return false; 194 } 195 196 /** 197 * Network Service Header (NSH) and its next protocol values 198 * are described in RFC-8393. 199 */ 200 static enum rte_flow_item_type 201 mlx5_nsh_proto_to_item_type(uint8_t proto_spec, uint8_t proto_mask) 202 { 203 enum rte_flow_item_type type; 204 205 switch (proto_mask & proto_spec) { 206 case 0: 207 type = RTE_FLOW_ITEM_TYPE_VOID; 208 break; 209 case RTE_VXLAN_GPE_TYPE_IPV4: 210 type = RTE_FLOW_ITEM_TYPE_IPV4; 211 break; 212 case RTE_VXLAN_GPE_TYPE_IPV6: 213 type = RTE_VXLAN_GPE_TYPE_IPV6; 214 break; 215 case RTE_VXLAN_GPE_TYPE_ETH: 216 type = RTE_FLOW_ITEM_TYPE_ETH; 217 break; 218 default: 219 type = RTE_FLOW_ITEM_TYPE_END; 220 } 221 return type; 222 } 223 224 static enum rte_flow_item_type 225 mlx5_inet_proto_to_item_type(uint8_t proto_spec, uint8_t proto_mask) 226 { 227 enum rte_flow_item_type type; 228 229 switch (proto_mask & proto_spec) { 230 case 0: 231 type = RTE_FLOW_ITEM_TYPE_VOID; 232 break; 233 case IPPROTO_UDP: 234 type = RTE_FLOW_ITEM_TYPE_UDP; 235 break; 236 case IPPROTO_TCP: 237 type = RTE_FLOW_ITEM_TYPE_TCP; 238 break; 239 case IPPROTO_IPIP: 240 type = RTE_FLOW_ITEM_TYPE_IPV4; 241 break; 242 case IPPROTO_IPV6: 243 type = RTE_FLOW_ITEM_TYPE_IPV6; 244 break; 245 case IPPROTO_ESP: 246 type = RTE_FLOW_ITEM_TYPE_ESP; 247 break; 248 default: 249 type = RTE_FLOW_ITEM_TYPE_END; 250 } 251 return type; 252 } 253 254 static enum rte_flow_item_type 255 mlx5_ethertype_to_item_type(rte_be16_t type_spec, 256 rte_be16_t type_mask, bool is_tunnel) 257 { 258 enum rte_flow_item_type type; 259 260 switch (rte_be_to_cpu_16(type_spec & type_mask)) { 261 case 0: 262 type = RTE_FLOW_ITEM_TYPE_VOID; 263 break; 264 case RTE_ETHER_TYPE_TEB: 265 type = is_tunnel ? 266 RTE_FLOW_ITEM_TYPE_ETH : RTE_FLOW_ITEM_TYPE_END; 267 break; 268 case RTE_ETHER_TYPE_VLAN: 269 type = !is_tunnel ? 270 RTE_FLOW_ITEM_TYPE_VLAN : RTE_FLOW_ITEM_TYPE_END; 271 break; 272 case RTE_ETHER_TYPE_IPV4: 273 type = RTE_FLOW_ITEM_TYPE_IPV4; 274 break; 275 case RTE_ETHER_TYPE_IPV6: 276 type = RTE_FLOW_ITEM_TYPE_IPV6; 277 break; 278 default: 279 type = RTE_FLOW_ITEM_TYPE_END; 280 } 281 return type; 282 } 283 284 static enum rte_flow_item_type 285 mlx5_flow_expand_rss_item_complete(const struct rte_flow_item *item) 286 { 287 #define MLX5_XSET_ITEM_MASK_SPEC(type, fld) \ 288 do { \ 289 const void *m = item->mask; \ 290 const void *s = item->spec; \ 291 mask = m ? \ 292 ((const struct rte_flow_item_##type *)m)->fld : \ 293 rte_flow_item_##type##_mask.fld; \ 294 spec = ((const struct rte_flow_item_##type *)s)->fld; \ 295 } while (0) 296 297 enum rte_flow_item_type ret; 298 uint16_t spec, mask; 299 300 if (item == NULL || item->spec == NULL) 301 return RTE_FLOW_ITEM_TYPE_VOID; 302 switch (item->type) { 303 case RTE_FLOW_ITEM_TYPE_ETH: 304 MLX5_XSET_ITEM_MASK_SPEC(eth, type); 305 if (!mask) 306 return RTE_FLOW_ITEM_TYPE_VOID; 307 ret = mlx5_ethertype_to_item_type(spec, mask, false); 308 break; 309 case RTE_FLOW_ITEM_TYPE_VLAN: 310 MLX5_XSET_ITEM_MASK_SPEC(vlan, inner_type); 311 if (!mask) 312 return RTE_FLOW_ITEM_TYPE_VOID; 313 ret = mlx5_ethertype_to_item_type(spec, mask, false); 314 break; 315 case RTE_FLOW_ITEM_TYPE_IPV4: 316 MLX5_XSET_ITEM_MASK_SPEC(ipv4, hdr.next_proto_id); 317 if (!mask) 318 return RTE_FLOW_ITEM_TYPE_VOID; 319 ret = mlx5_inet_proto_to_item_type(spec, mask); 320 break; 321 case RTE_FLOW_ITEM_TYPE_IPV6: 322 MLX5_XSET_ITEM_MASK_SPEC(ipv6, hdr.proto); 323 if (!mask) 324 return RTE_FLOW_ITEM_TYPE_VOID; 325 ret = mlx5_inet_proto_to_item_type(spec, mask); 326 break; 327 case RTE_FLOW_ITEM_TYPE_GENEVE: 328 MLX5_XSET_ITEM_MASK_SPEC(geneve, protocol); 329 ret = mlx5_ethertype_to_item_type(spec, mask, true); 330 break; 331 case RTE_FLOW_ITEM_TYPE_GRE: 332 MLX5_XSET_ITEM_MASK_SPEC(gre, protocol); 333 ret = mlx5_ethertype_to_item_type(spec, mask, true); 334 break; 335 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE: 336 MLX5_XSET_ITEM_MASK_SPEC(vxlan_gpe, protocol); 337 ret = mlx5_nsh_proto_to_item_type(spec, mask); 338 break; 339 default: 340 ret = RTE_FLOW_ITEM_TYPE_VOID; 341 break; 342 } 343 return ret; 344 #undef MLX5_XSET_ITEM_MASK_SPEC 345 } 346 347 static const int * 348 mlx5_flow_expand_rss_skip_explicit(const struct mlx5_flow_expand_node graph[], 349 const int *next_node) 350 { 351 const struct mlx5_flow_expand_node *node = NULL; 352 const int *next = next_node; 353 354 while (next && *next) { 355 /* 356 * Skip the nodes with the MLX5_EXPANSION_NODE_EXPLICIT 357 * flag set, because they were not found in the flow pattern. 358 */ 359 node = &graph[*next]; 360 if (!(node->node_flags & MLX5_EXPANSION_NODE_EXPLICIT)) 361 break; 362 next = node->next; 363 } 364 return next; 365 } 366 367 #define MLX5_RSS_EXP_ELT_N 16 368 369 /** 370 * Expand RSS flows into several possible flows according to the RSS hash 371 * fields requested and the driver capabilities. 372 * 373 * @param[out] buf 374 * Buffer to store the result expansion. 375 * @param[in] size 376 * Buffer size in bytes. If 0, @p buf can be NULL. 377 * @param[in] pattern 378 * User flow pattern. 379 * @param[in] types 380 * RSS types to expand (see RTE_ETH_RSS_* definitions). 381 * @param[in] graph 382 * Input graph to expand @p pattern according to @p types. 383 * @param[in] graph_root_index 384 * Index of root node in @p graph, typically 0. 385 * 386 * @return 387 * A positive value representing the size of @p buf in bytes regardless of 388 * @p size on success, a negative errno value otherwise and rte_errno is 389 * set, the following errors are defined: 390 * 391 * -E2BIG: graph-depth @p graph is too deep. 392 * -EINVAL: @p size has not enough space for expanded pattern. 393 */ 394 static int 395 mlx5_flow_expand_rss(struct mlx5_flow_expand_rss *buf, size_t size, 396 const struct rte_flow_item *pattern, uint64_t types, 397 const struct mlx5_flow_expand_node graph[], 398 int graph_root_index) 399 { 400 const struct rte_flow_item *item; 401 const struct mlx5_flow_expand_node *node = &graph[graph_root_index]; 402 const int *next_node; 403 const int *stack[MLX5_RSS_EXP_ELT_N]; 404 int stack_pos = 0; 405 struct rte_flow_item flow_items[MLX5_RSS_EXP_ELT_N]; 406 unsigned int i, item_idx, last_expand_item_idx = 0; 407 size_t lsize; 408 size_t user_pattern_size = 0; 409 void *addr = NULL; 410 const struct mlx5_flow_expand_node *next = NULL; 411 struct rte_flow_item missed_item; 412 int missed = 0; 413 int elt = 0; 414 const struct rte_flow_item *last_expand_item = NULL; 415 416 memset(&missed_item, 0, sizeof(missed_item)); 417 lsize = offsetof(struct mlx5_flow_expand_rss, entry) + 418 MLX5_RSS_EXP_ELT_N * sizeof(buf->entry[0]); 419 if (lsize > size) 420 return -EINVAL; 421 buf->entry[0].priority = 0; 422 buf->entry[0].pattern = (void *)&buf->entry[MLX5_RSS_EXP_ELT_N]; 423 buf->entries = 0; 424 addr = buf->entry[0].pattern; 425 for (item = pattern, item_idx = 0; 426 item->type != RTE_FLOW_ITEM_TYPE_END; 427 item++, item_idx++) { 428 if (!mlx5_flow_is_rss_expandable_item(item)) { 429 user_pattern_size += sizeof(*item); 430 continue; 431 } 432 last_expand_item = item; 433 last_expand_item_idx = item_idx; 434 i = 0; 435 while (node->next && node->next[i]) { 436 next = &graph[node->next[i]]; 437 if (next->type == item->type) 438 break; 439 if (next->node_flags & MLX5_EXPANSION_NODE_EXPLICIT) { 440 node = next; 441 i = 0; 442 } else { 443 ++i; 444 } 445 } 446 if (next) 447 node = next; 448 user_pattern_size += sizeof(*item); 449 } 450 user_pattern_size += sizeof(*item); /* Handle END item. */ 451 lsize += user_pattern_size; 452 if (lsize > size) 453 return -EINVAL; 454 /* Copy the user pattern in the first entry of the buffer. */ 455 rte_memcpy(addr, pattern, user_pattern_size); 456 addr = (void *)(((uintptr_t)addr) + user_pattern_size); 457 buf->entries = 1; 458 /* Start expanding. */ 459 memset(flow_items, 0, sizeof(flow_items)); 460 user_pattern_size -= sizeof(*item); 461 /* 462 * Check if the last valid item has spec set, need complete pattern, 463 * and the pattern can be used for expansion. 464 */ 465 missed_item.type = mlx5_flow_expand_rss_item_complete(last_expand_item); 466 if (missed_item.type == RTE_FLOW_ITEM_TYPE_END) { 467 /* Item type END indicates expansion is not required. */ 468 return lsize; 469 } 470 if (missed_item.type != RTE_FLOW_ITEM_TYPE_VOID) { 471 next = NULL; 472 missed = 1; 473 i = 0; 474 while (node->next && node->next[i]) { 475 next = &graph[node->next[i]]; 476 if (next->type == missed_item.type) { 477 flow_items[0].type = missed_item.type; 478 flow_items[1].type = RTE_FLOW_ITEM_TYPE_END; 479 break; 480 } 481 if (next->node_flags & MLX5_EXPANSION_NODE_EXPLICIT) { 482 node = next; 483 i = 0; 484 } else { 485 ++i; 486 } 487 next = NULL; 488 } 489 } 490 if (next && missed) { 491 elt = 2; /* missed item + item end. */ 492 node = next; 493 lsize += elt * sizeof(*item) + user_pattern_size; 494 if (lsize > size) 495 return -EINVAL; 496 if (node->rss_types & types) { 497 buf->entry[buf->entries].priority = 1; 498 buf->entry[buf->entries].pattern = addr; 499 buf->entries++; 500 rte_memcpy(addr, buf->entry[0].pattern, 501 user_pattern_size); 502 addr = (void *)(((uintptr_t)addr) + user_pattern_size); 503 rte_memcpy(addr, flow_items, elt * sizeof(*item)); 504 addr = (void *)(((uintptr_t)addr) + 505 elt * sizeof(*item)); 506 } 507 } else if (last_expand_item != NULL) { 508 node = mlx5_flow_expand_rss_adjust_node(pattern, 509 last_expand_item_idx, graph, node); 510 } 511 memset(flow_items, 0, sizeof(flow_items)); 512 next_node = mlx5_flow_expand_rss_skip_explicit(graph, 513 node->next); 514 stack[stack_pos] = next_node; 515 node = next_node ? &graph[*next_node] : NULL; 516 while (node) { 517 flow_items[stack_pos].type = node->type; 518 if (node->rss_types & types) { 519 size_t n; 520 /* 521 * compute the number of items to copy from the 522 * expansion and copy it. 523 * When the stack_pos is 0, there are 1 element in it, 524 * plus the addition END item. 525 */ 526 elt = stack_pos + 2; 527 flow_items[stack_pos + 1].type = RTE_FLOW_ITEM_TYPE_END; 528 lsize += elt * sizeof(*item) + user_pattern_size; 529 if (lsize > size) 530 return -EINVAL; 531 n = elt * sizeof(*item); 532 buf->entry[buf->entries].priority = 533 stack_pos + 1 + missed; 534 buf->entry[buf->entries].pattern = addr; 535 buf->entries++; 536 rte_memcpy(addr, buf->entry[0].pattern, 537 user_pattern_size); 538 addr = (void *)(((uintptr_t)addr) + 539 user_pattern_size); 540 rte_memcpy(addr, &missed_item, 541 missed * sizeof(*item)); 542 addr = (void *)(((uintptr_t)addr) + 543 missed * sizeof(*item)); 544 rte_memcpy(addr, flow_items, n); 545 addr = (void *)(((uintptr_t)addr) + n); 546 } 547 /* Go deeper. */ 548 if (!(node->node_flags & MLX5_EXPANSION_NODE_OPTIONAL) && 549 node->next) { 550 next_node = mlx5_flow_expand_rss_skip_explicit(graph, 551 node->next); 552 if (stack_pos++ == MLX5_RSS_EXP_ELT_N) { 553 rte_errno = E2BIG; 554 return -rte_errno; 555 } 556 stack[stack_pos] = next_node; 557 } else if (*(next_node + 1)) { 558 /* Follow up with the next possibility. */ 559 next_node = mlx5_flow_expand_rss_skip_explicit(graph, 560 ++next_node); 561 } else if (!stack_pos) { 562 /* 563 * Completing the traverse over the different paths. 564 * The next_node is advanced to the terminator. 565 */ 566 ++next_node; 567 } else { 568 /* Move to the next path. */ 569 while (stack_pos) { 570 next_node = stack[--stack_pos]; 571 next_node++; 572 if (*next_node) 573 break; 574 } 575 next_node = mlx5_flow_expand_rss_skip_explicit(graph, 576 next_node); 577 stack[stack_pos] = next_node; 578 } 579 node = next_node && *next_node ? &graph[*next_node] : NULL; 580 }; 581 return lsize; 582 } 583 584 /** 585 * Expand SQN flows into several possible flows according to the Tx queue 586 * number 587 * 588 * @param[in] buf 589 * Buffer to store the result expansion. 590 * @param[in] size 591 * Buffer size in bytes. If 0, @p buf can be NULL. 592 * @param[in] pattern 593 * User flow pattern. 594 * @param[in] sq_specs 595 * Buffer to store sq spec. 596 * 597 * @return 598 * 0 for success and negative value for failure 599 * 600 */ 601 static int 602 mlx5_flow_expand_sqn(struct mlx5_flow_expand_sqn *buf, size_t size, 603 const struct rte_flow_item *pattern, 604 struct mlx5_rte_flow_item_sq *sq_specs) 605 { 606 const struct rte_flow_item *item; 607 bool port_representor = false; 608 size_t user_pattern_size = 0; 609 struct rte_eth_dev *dev; 610 struct mlx5_priv *priv; 611 void *addr = NULL; 612 uint16_t port_id; 613 size_t lsize; 614 int elt = 2; 615 uint16_t i; 616 617 buf->entries = 0; 618 for (item = pattern; item->type != RTE_FLOW_ITEM_TYPE_END; item++) { 619 if (item->type == RTE_FLOW_ITEM_TYPE_PORT_REPRESENTOR) { 620 const struct rte_flow_item_ethdev *pid_v = item->spec; 621 622 if (!pid_v) 623 return 0; 624 port_id = pid_v->port_id; 625 port_representor = true; 626 } 627 user_pattern_size += sizeof(*item); 628 } 629 if (!port_representor) 630 return 0; 631 dev = &rte_eth_devices[port_id]; 632 priv = dev->data->dev_private; 633 buf->entry[0].pattern = (void *)&buf->entry[priv->txqs_n]; 634 lsize = offsetof(struct mlx5_flow_expand_sqn, entry) + 635 sizeof(buf->entry[0]) * priv->txqs_n; 636 if (lsize + (user_pattern_size + sizeof(struct rte_flow_item) * elt) * priv->txqs_n > size) 637 return -EINVAL; 638 addr = buf->entry[0].pattern; 639 for (i = 0; i != priv->txqs_n; ++i) { 640 struct rte_flow_item pattern_add[] = { 641 { 642 .type = (enum rte_flow_item_type) 643 MLX5_RTE_FLOW_ITEM_TYPE_SQ, 644 .spec = &sq_specs[i], 645 }, 646 { 647 .type = RTE_FLOW_ITEM_TYPE_END, 648 }, 649 }; 650 struct mlx5_txq_ctrl *txq = mlx5_txq_get(dev, i); 651 652 if (txq == NULL) 653 return -EINVAL; 654 buf->entry[i].pattern = addr; 655 sq_specs[i].queue = mlx5_txq_get_sqn(txq); 656 mlx5_txq_release(dev, i); 657 rte_memcpy(addr, pattern, user_pattern_size); 658 addr = (void *)(((uintptr_t)addr) + user_pattern_size); 659 rte_memcpy(addr, pattern_add, sizeof(struct rte_flow_item) * elt); 660 addr = (void *)(((uintptr_t)addr) + sizeof(struct rte_flow_item) * elt); 661 buf->entries++; 662 } 663 return 0; 664 } 665 666 enum mlx5_expansion { 667 MLX5_EXPANSION_ROOT, 668 MLX5_EXPANSION_ROOT_OUTER, 669 MLX5_EXPANSION_OUTER_ETH, 670 MLX5_EXPANSION_OUTER_VLAN, 671 MLX5_EXPANSION_OUTER_IPV4, 672 MLX5_EXPANSION_OUTER_IPV4_UDP, 673 MLX5_EXPANSION_OUTER_IPV4_TCP, 674 MLX5_EXPANSION_OUTER_IPV4_ESP, 675 MLX5_EXPANSION_OUTER_IPV4_ICMP, 676 MLX5_EXPANSION_OUTER_IPV6, 677 MLX5_EXPANSION_OUTER_IPV6_UDP, 678 MLX5_EXPANSION_OUTER_IPV6_TCP, 679 MLX5_EXPANSION_OUTER_IPV6_ESP, 680 MLX5_EXPANSION_OUTER_IPV6_ICMP6, 681 MLX5_EXPANSION_VXLAN, 682 MLX5_EXPANSION_STD_VXLAN, 683 MLX5_EXPANSION_L3_VXLAN, 684 MLX5_EXPANSION_VXLAN_GPE, 685 MLX5_EXPANSION_GRE, 686 MLX5_EXPANSION_NVGRE, 687 MLX5_EXPANSION_GRE_KEY, 688 MLX5_EXPANSION_MPLS, 689 MLX5_EXPANSION_ETH, 690 MLX5_EXPANSION_VLAN, 691 MLX5_EXPANSION_IPV4, 692 MLX5_EXPANSION_IPV4_UDP, 693 MLX5_EXPANSION_IPV4_TCP, 694 MLX5_EXPANSION_IPV4_ESP, 695 MLX5_EXPANSION_IPV4_ICMP, 696 MLX5_EXPANSION_IPV6, 697 MLX5_EXPANSION_IPV6_UDP, 698 MLX5_EXPANSION_IPV6_TCP, 699 MLX5_EXPANSION_IPV6_ESP, 700 MLX5_EXPANSION_IPV6_ICMP6, 701 MLX5_EXPANSION_IPV6_FRAG_EXT, 702 MLX5_EXPANSION_GTP, 703 MLX5_EXPANSION_GENEVE, 704 }; 705 706 /** Supported expansion of items. */ 707 static const struct mlx5_flow_expand_node mlx5_support_expansion[] = { 708 [MLX5_EXPANSION_ROOT] = { 709 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_ETH, 710 MLX5_EXPANSION_IPV4, 711 MLX5_EXPANSION_IPV6), 712 .type = RTE_FLOW_ITEM_TYPE_END, 713 }, 714 [MLX5_EXPANSION_ROOT_OUTER] = { 715 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_OUTER_ETH, 716 MLX5_EXPANSION_OUTER_IPV4, 717 MLX5_EXPANSION_OUTER_IPV6), 718 .type = RTE_FLOW_ITEM_TYPE_END, 719 }, 720 [MLX5_EXPANSION_OUTER_ETH] = { 721 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_OUTER_VLAN), 722 .type = RTE_FLOW_ITEM_TYPE_ETH, 723 .rss_types = 0, 724 }, 725 [MLX5_EXPANSION_OUTER_VLAN] = { 726 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_OUTER_IPV4, 727 MLX5_EXPANSION_OUTER_IPV6), 728 .type = RTE_FLOW_ITEM_TYPE_VLAN, 729 .node_flags = MLX5_EXPANSION_NODE_EXPLICIT, 730 }, 731 [MLX5_EXPANSION_OUTER_IPV4] = { 732 .next = MLX5_FLOW_EXPAND_RSS_NEXT 733 (MLX5_EXPANSION_OUTER_IPV4_UDP, 734 MLX5_EXPANSION_OUTER_IPV4_TCP, 735 MLX5_EXPANSION_OUTER_IPV4_ESP, 736 MLX5_EXPANSION_OUTER_IPV4_ICMP, 737 MLX5_EXPANSION_GRE, 738 MLX5_EXPANSION_NVGRE, 739 MLX5_EXPANSION_IPV4, 740 MLX5_EXPANSION_IPV6), 741 .type = RTE_FLOW_ITEM_TYPE_IPV4, 742 .rss_types = RTE_ETH_RSS_IPV4 | RTE_ETH_RSS_FRAG_IPV4 | 743 RTE_ETH_RSS_NONFRAG_IPV4_OTHER, 744 }, 745 [MLX5_EXPANSION_OUTER_IPV4_UDP] = { 746 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_VXLAN, 747 MLX5_EXPANSION_VXLAN_GPE, 748 MLX5_EXPANSION_MPLS, 749 MLX5_EXPANSION_GENEVE, 750 MLX5_EXPANSION_GTP), 751 .type = RTE_FLOW_ITEM_TYPE_UDP, 752 .rss_types = RTE_ETH_RSS_NONFRAG_IPV4_UDP, 753 }, 754 [MLX5_EXPANSION_OUTER_IPV4_TCP] = { 755 .type = RTE_FLOW_ITEM_TYPE_TCP, 756 .rss_types = RTE_ETH_RSS_NONFRAG_IPV4_TCP, 757 }, 758 [MLX5_EXPANSION_OUTER_IPV4_ESP] = { 759 .type = RTE_FLOW_ITEM_TYPE_ESP, 760 .rss_types = RTE_ETH_RSS_ESP, 761 }, 762 [MLX5_EXPANSION_OUTER_IPV4_ICMP] = { 763 .type = RTE_FLOW_ITEM_TYPE_ICMP, 764 }, 765 [MLX5_EXPANSION_OUTER_IPV6] = { 766 .next = MLX5_FLOW_EXPAND_RSS_NEXT 767 (MLX5_EXPANSION_OUTER_IPV6_UDP, 768 MLX5_EXPANSION_OUTER_IPV6_TCP, 769 MLX5_EXPANSION_OUTER_IPV6_ESP, 770 MLX5_EXPANSION_OUTER_IPV6_ICMP6, 771 MLX5_EXPANSION_IPV4, 772 MLX5_EXPANSION_IPV6, 773 MLX5_EXPANSION_GRE, 774 MLX5_EXPANSION_NVGRE), 775 .type = RTE_FLOW_ITEM_TYPE_IPV6, 776 .rss_types = RTE_ETH_RSS_IPV6 | RTE_ETH_RSS_FRAG_IPV6 | 777 RTE_ETH_RSS_NONFRAG_IPV6_OTHER, 778 }, 779 [MLX5_EXPANSION_OUTER_IPV6_UDP] = { 780 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_VXLAN, 781 MLX5_EXPANSION_VXLAN_GPE, 782 MLX5_EXPANSION_MPLS, 783 MLX5_EXPANSION_GENEVE, 784 MLX5_EXPANSION_GTP), 785 .type = RTE_FLOW_ITEM_TYPE_UDP, 786 .rss_types = RTE_ETH_RSS_NONFRAG_IPV6_UDP, 787 }, 788 [MLX5_EXPANSION_OUTER_IPV6_TCP] = { 789 .type = RTE_FLOW_ITEM_TYPE_TCP, 790 .rss_types = RTE_ETH_RSS_NONFRAG_IPV6_TCP, 791 }, 792 [MLX5_EXPANSION_OUTER_IPV6_ESP] = { 793 .type = RTE_FLOW_ITEM_TYPE_ESP, 794 .rss_types = RTE_ETH_RSS_ESP, 795 }, 796 [MLX5_EXPANSION_OUTER_IPV6_ICMP6] = { 797 .type = RTE_FLOW_ITEM_TYPE_ICMP6, 798 }, 799 [MLX5_EXPANSION_VXLAN] = { 800 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_ETH, 801 MLX5_EXPANSION_IPV4, 802 MLX5_EXPANSION_IPV6), 803 .type = RTE_FLOW_ITEM_TYPE_VXLAN, 804 }, 805 [MLX5_EXPANSION_STD_VXLAN] = { 806 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_ETH), 807 .type = RTE_FLOW_ITEM_TYPE_VXLAN, 808 }, 809 [MLX5_EXPANSION_L3_VXLAN] = { 810 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_IPV4, 811 MLX5_EXPANSION_IPV6), 812 .type = RTE_FLOW_ITEM_TYPE_VXLAN, 813 }, 814 [MLX5_EXPANSION_VXLAN_GPE] = { 815 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_ETH, 816 MLX5_EXPANSION_IPV4, 817 MLX5_EXPANSION_IPV6), 818 .type = RTE_FLOW_ITEM_TYPE_VXLAN_GPE, 819 }, 820 [MLX5_EXPANSION_GRE] = { 821 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_ETH, 822 MLX5_EXPANSION_IPV4, 823 MLX5_EXPANSION_IPV6, 824 MLX5_EXPANSION_GRE_KEY, 825 MLX5_EXPANSION_MPLS), 826 .type = RTE_FLOW_ITEM_TYPE_GRE, 827 }, 828 [MLX5_EXPANSION_GRE_KEY] = { 829 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_IPV4, 830 MLX5_EXPANSION_IPV6, 831 MLX5_EXPANSION_MPLS), 832 .type = RTE_FLOW_ITEM_TYPE_GRE_KEY, 833 .node_flags = MLX5_EXPANSION_NODE_OPTIONAL, 834 }, 835 [MLX5_EXPANSION_NVGRE] = { 836 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_ETH), 837 .type = RTE_FLOW_ITEM_TYPE_NVGRE, 838 }, 839 [MLX5_EXPANSION_MPLS] = { 840 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_IPV4, 841 MLX5_EXPANSION_IPV6, 842 MLX5_EXPANSION_ETH), 843 .type = RTE_FLOW_ITEM_TYPE_MPLS, 844 .node_flags = MLX5_EXPANSION_NODE_OPTIONAL, 845 }, 846 [MLX5_EXPANSION_ETH] = { 847 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_VLAN), 848 .type = RTE_FLOW_ITEM_TYPE_ETH, 849 }, 850 [MLX5_EXPANSION_VLAN] = { 851 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_IPV4, 852 MLX5_EXPANSION_IPV6), 853 .type = RTE_FLOW_ITEM_TYPE_VLAN, 854 .node_flags = MLX5_EXPANSION_NODE_EXPLICIT, 855 }, 856 [MLX5_EXPANSION_IPV4] = { 857 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_IPV4_UDP, 858 MLX5_EXPANSION_IPV4_TCP, 859 MLX5_EXPANSION_IPV4_ESP, 860 MLX5_EXPANSION_IPV4_ICMP), 861 .type = RTE_FLOW_ITEM_TYPE_IPV4, 862 .rss_types = RTE_ETH_RSS_IPV4 | RTE_ETH_RSS_FRAG_IPV4 | 863 RTE_ETH_RSS_NONFRAG_IPV4_OTHER, 864 }, 865 [MLX5_EXPANSION_IPV4_UDP] = { 866 .type = RTE_FLOW_ITEM_TYPE_UDP, 867 .rss_types = RTE_ETH_RSS_NONFRAG_IPV4_UDP, 868 }, 869 [MLX5_EXPANSION_IPV4_TCP] = { 870 .type = RTE_FLOW_ITEM_TYPE_TCP, 871 .rss_types = RTE_ETH_RSS_NONFRAG_IPV4_TCP, 872 }, 873 [MLX5_EXPANSION_IPV4_ESP] = { 874 .type = RTE_FLOW_ITEM_TYPE_ESP, 875 .rss_types = RTE_ETH_RSS_ESP, 876 }, 877 [MLX5_EXPANSION_IPV4_ICMP] = { 878 .type = RTE_FLOW_ITEM_TYPE_ICMP, 879 }, 880 [MLX5_EXPANSION_IPV6] = { 881 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_IPV6_UDP, 882 MLX5_EXPANSION_IPV6_TCP, 883 MLX5_EXPANSION_IPV6_ESP, 884 MLX5_EXPANSION_IPV6_ICMP6, 885 MLX5_EXPANSION_IPV6_FRAG_EXT), 886 .type = RTE_FLOW_ITEM_TYPE_IPV6, 887 .rss_types = RTE_ETH_RSS_IPV6 | RTE_ETH_RSS_FRAG_IPV6 | 888 RTE_ETH_RSS_NONFRAG_IPV6_OTHER, 889 }, 890 [MLX5_EXPANSION_IPV6_UDP] = { 891 .type = RTE_FLOW_ITEM_TYPE_UDP, 892 .rss_types = RTE_ETH_RSS_NONFRAG_IPV6_UDP, 893 }, 894 [MLX5_EXPANSION_IPV6_TCP] = { 895 .type = RTE_FLOW_ITEM_TYPE_TCP, 896 .rss_types = RTE_ETH_RSS_NONFRAG_IPV6_TCP, 897 }, 898 [MLX5_EXPANSION_IPV6_ESP] = { 899 .type = RTE_FLOW_ITEM_TYPE_ESP, 900 .rss_types = RTE_ETH_RSS_ESP, 901 }, 902 [MLX5_EXPANSION_IPV6_FRAG_EXT] = { 903 .type = RTE_FLOW_ITEM_TYPE_IPV6_FRAG_EXT, 904 }, 905 [MLX5_EXPANSION_IPV6_ICMP6] = { 906 .type = RTE_FLOW_ITEM_TYPE_ICMP6, 907 }, 908 [MLX5_EXPANSION_GTP] = { 909 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_IPV4, 910 MLX5_EXPANSION_IPV6), 911 .type = RTE_FLOW_ITEM_TYPE_GTP, 912 }, 913 [MLX5_EXPANSION_GENEVE] = { 914 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_ETH, 915 MLX5_EXPANSION_IPV4, 916 MLX5_EXPANSION_IPV6), 917 .type = RTE_FLOW_ITEM_TYPE_GENEVE, 918 }, 919 }; 920 921 static struct rte_flow_action_handle * 922 mlx5_action_handle_create(struct rte_eth_dev *dev, 923 const struct rte_flow_indir_action_conf *conf, 924 const struct rte_flow_action *action, 925 struct rte_flow_error *error); 926 static int mlx5_action_handle_destroy 927 (struct rte_eth_dev *dev, 928 struct rte_flow_action_handle *handle, 929 struct rte_flow_error *error); 930 static int mlx5_action_handle_update 931 (struct rte_eth_dev *dev, 932 struct rte_flow_action_handle *handle, 933 const void *update, 934 struct rte_flow_error *error); 935 static int mlx5_action_handle_query 936 (struct rte_eth_dev *dev, 937 const struct rte_flow_action_handle *handle, 938 void *data, 939 struct rte_flow_error *error); 940 static int 941 mlx5_flow_tunnel_decap_set(struct rte_eth_dev *dev, 942 struct rte_flow_tunnel *app_tunnel, 943 struct rte_flow_action **actions, 944 uint32_t *num_of_actions, 945 struct rte_flow_error *error); 946 static int 947 mlx5_flow_tunnel_match(struct rte_eth_dev *dev, 948 struct rte_flow_tunnel *app_tunnel, 949 struct rte_flow_item **items, 950 uint32_t *num_of_items, 951 struct rte_flow_error *error); 952 static int 953 mlx5_flow_tunnel_item_release(struct rte_eth_dev *dev, 954 struct rte_flow_item *pmd_items, 955 uint32_t num_items, struct rte_flow_error *err); 956 static int 957 mlx5_flow_tunnel_action_release(struct rte_eth_dev *dev, 958 struct rte_flow_action *pmd_actions, 959 uint32_t num_actions, 960 struct rte_flow_error *err); 961 static int 962 mlx5_flow_tunnel_get_restore_info(struct rte_eth_dev *dev, 963 struct rte_mbuf *m, 964 struct rte_flow_restore_info *info, 965 struct rte_flow_error *err); 966 static struct rte_flow_item_flex_handle * 967 mlx5_flow_flex_item_create(struct rte_eth_dev *dev, 968 const struct rte_flow_item_flex_conf *conf, 969 struct rte_flow_error *error); 970 static int 971 mlx5_flow_flex_item_release(struct rte_eth_dev *dev, 972 const struct rte_flow_item_flex_handle *handle, 973 struct rte_flow_error *error); 974 static int 975 mlx5_flow_info_get(struct rte_eth_dev *dev, 976 struct rte_flow_port_info *port_info, 977 struct rte_flow_queue_info *queue_info, 978 struct rte_flow_error *error); 979 static int 980 mlx5_flow_port_configure(struct rte_eth_dev *dev, 981 const struct rte_flow_port_attr *port_attr, 982 uint16_t nb_queue, 983 const struct rte_flow_queue_attr *queue_attr[], 984 struct rte_flow_error *err); 985 986 static struct rte_flow_pattern_template * 987 mlx5_flow_pattern_template_create(struct rte_eth_dev *dev, 988 const struct rte_flow_pattern_template_attr *attr, 989 const struct rte_flow_item items[], 990 struct rte_flow_error *error); 991 992 static int 993 mlx5_flow_pattern_template_destroy(struct rte_eth_dev *dev, 994 struct rte_flow_pattern_template *template, 995 struct rte_flow_error *error); 996 static struct rte_flow_actions_template * 997 mlx5_flow_actions_template_create(struct rte_eth_dev *dev, 998 const struct rte_flow_actions_template_attr *attr, 999 const struct rte_flow_action actions[], 1000 const struct rte_flow_action masks[], 1001 struct rte_flow_error *error); 1002 static int 1003 mlx5_flow_actions_template_destroy(struct rte_eth_dev *dev, 1004 struct rte_flow_actions_template *template, 1005 struct rte_flow_error *error); 1006 1007 static struct rte_flow_template_table * 1008 mlx5_flow_table_create(struct rte_eth_dev *dev, 1009 const struct rte_flow_template_table_attr *attr, 1010 struct rte_flow_pattern_template *item_templates[], 1011 uint8_t nb_item_templates, 1012 struct rte_flow_actions_template *action_templates[], 1013 uint8_t nb_action_templates, 1014 struct rte_flow_error *error); 1015 static int 1016 mlx5_flow_table_destroy(struct rte_eth_dev *dev, 1017 struct rte_flow_template_table *table, 1018 struct rte_flow_error *error); 1019 static struct rte_flow * 1020 mlx5_flow_async_flow_create(struct rte_eth_dev *dev, 1021 uint32_t queue, 1022 const struct rte_flow_op_attr *attr, 1023 struct rte_flow_template_table *table, 1024 const struct rte_flow_item items[], 1025 uint8_t pattern_template_index, 1026 const struct rte_flow_action actions[], 1027 uint8_t action_template_index, 1028 void *user_data, 1029 struct rte_flow_error *error); 1030 static int 1031 mlx5_flow_async_flow_destroy(struct rte_eth_dev *dev, 1032 uint32_t queue, 1033 const struct rte_flow_op_attr *attr, 1034 struct rte_flow *flow, 1035 void *user_data, 1036 struct rte_flow_error *error); 1037 static int 1038 mlx5_flow_pull(struct rte_eth_dev *dev, 1039 uint32_t queue, 1040 struct rte_flow_op_result res[], 1041 uint16_t n_res, 1042 struct rte_flow_error *error); 1043 static int 1044 mlx5_flow_push(struct rte_eth_dev *dev, 1045 uint32_t queue, 1046 struct rte_flow_error *error); 1047 1048 static struct rte_flow_action_handle * 1049 mlx5_flow_async_action_handle_create(struct rte_eth_dev *dev, uint32_t queue, 1050 const struct rte_flow_op_attr *attr, 1051 const struct rte_flow_indir_action_conf *conf, 1052 const struct rte_flow_action *action, 1053 void *user_data, 1054 struct rte_flow_error *error); 1055 1056 static int 1057 mlx5_flow_async_action_handle_update(struct rte_eth_dev *dev, uint32_t queue, 1058 const struct rte_flow_op_attr *attr, 1059 struct rte_flow_action_handle *handle, 1060 const void *update, 1061 void *user_data, 1062 struct rte_flow_error *error); 1063 1064 static int 1065 mlx5_flow_async_action_handle_destroy(struct rte_eth_dev *dev, uint32_t queue, 1066 const struct rte_flow_op_attr *attr, 1067 struct rte_flow_action_handle *handle, 1068 void *user_data, 1069 struct rte_flow_error *error); 1070 1071 static int 1072 mlx5_flow_async_action_handle_query(struct rte_eth_dev *dev, uint32_t queue, 1073 const struct rte_flow_op_attr *attr, 1074 const struct rte_flow_action_handle *handle, 1075 void *data, 1076 void *user_data, 1077 struct rte_flow_error *error); 1078 1079 static const struct rte_flow_ops mlx5_flow_ops = { 1080 .validate = mlx5_flow_validate, 1081 .create = mlx5_flow_create, 1082 .destroy = mlx5_flow_destroy, 1083 .flush = mlx5_flow_flush, 1084 .isolate = mlx5_flow_isolate, 1085 .query = mlx5_flow_query, 1086 .dev_dump = mlx5_flow_dev_dump, 1087 .get_q_aged_flows = mlx5_flow_get_q_aged_flows, 1088 .get_aged_flows = mlx5_flow_get_aged_flows, 1089 .action_handle_create = mlx5_action_handle_create, 1090 .action_handle_destroy = mlx5_action_handle_destroy, 1091 .action_handle_update = mlx5_action_handle_update, 1092 .action_handle_query = mlx5_action_handle_query, 1093 .tunnel_decap_set = mlx5_flow_tunnel_decap_set, 1094 .tunnel_match = mlx5_flow_tunnel_match, 1095 .tunnel_action_decap_release = mlx5_flow_tunnel_action_release, 1096 .tunnel_item_release = mlx5_flow_tunnel_item_release, 1097 .get_restore_info = mlx5_flow_tunnel_get_restore_info, 1098 .flex_item_create = mlx5_flow_flex_item_create, 1099 .flex_item_release = mlx5_flow_flex_item_release, 1100 .info_get = mlx5_flow_info_get, 1101 .pick_transfer_proxy = mlx5_flow_pick_transfer_proxy, 1102 .configure = mlx5_flow_port_configure, 1103 .pattern_template_create = mlx5_flow_pattern_template_create, 1104 .pattern_template_destroy = mlx5_flow_pattern_template_destroy, 1105 .actions_template_create = mlx5_flow_actions_template_create, 1106 .actions_template_destroy = mlx5_flow_actions_template_destroy, 1107 .template_table_create = mlx5_flow_table_create, 1108 .template_table_destroy = mlx5_flow_table_destroy, 1109 .async_create = mlx5_flow_async_flow_create, 1110 .async_destroy = mlx5_flow_async_flow_destroy, 1111 .pull = mlx5_flow_pull, 1112 .push = mlx5_flow_push, 1113 .async_action_handle_create = mlx5_flow_async_action_handle_create, 1114 .async_action_handle_update = mlx5_flow_async_action_handle_update, 1115 .async_action_handle_query = mlx5_flow_async_action_handle_query, 1116 .async_action_handle_destroy = mlx5_flow_async_action_handle_destroy, 1117 }; 1118 1119 /* Tunnel information. */ 1120 struct mlx5_flow_tunnel_info { 1121 uint64_t tunnel; /**< Tunnel bit (see MLX5_FLOW_*). */ 1122 uint32_t ptype; /**< Tunnel Ptype (see RTE_PTYPE_*). */ 1123 }; 1124 1125 static struct mlx5_flow_tunnel_info tunnels_info[] = { 1126 { 1127 .tunnel = MLX5_FLOW_LAYER_VXLAN, 1128 .ptype = RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_L4_UDP, 1129 }, 1130 { 1131 .tunnel = MLX5_FLOW_LAYER_GENEVE, 1132 .ptype = RTE_PTYPE_TUNNEL_GENEVE | RTE_PTYPE_L4_UDP, 1133 }, 1134 { 1135 .tunnel = MLX5_FLOW_LAYER_VXLAN_GPE, 1136 .ptype = RTE_PTYPE_TUNNEL_VXLAN_GPE | RTE_PTYPE_L4_UDP, 1137 }, 1138 { 1139 .tunnel = MLX5_FLOW_LAYER_GRE, 1140 .ptype = RTE_PTYPE_TUNNEL_GRE, 1141 }, 1142 { 1143 .tunnel = MLX5_FLOW_LAYER_MPLS | MLX5_FLOW_LAYER_OUTER_L4_UDP, 1144 .ptype = RTE_PTYPE_TUNNEL_MPLS_IN_UDP | RTE_PTYPE_L4_UDP, 1145 }, 1146 { 1147 .tunnel = MLX5_FLOW_LAYER_MPLS, 1148 .ptype = RTE_PTYPE_TUNNEL_MPLS_IN_GRE, 1149 }, 1150 { 1151 .tunnel = MLX5_FLOW_LAYER_NVGRE, 1152 .ptype = RTE_PTYPE_TUNNEL_NVGRE, 1153 }, 1154 { 1155 .tunnel = MLX5_FLOW_LAYER_IPIP, 1156 .ptype = RTE_PTYPE_TUNNEL_IP, 1157 }, 1158 { 1159 .tunnel = MLX5_FLOW_LAYER_IPV6_ENCAP, 1160 .ptype = RTE_PTYPE_TUNNEL_IP, 1161 }, 1162 { 1163 .tunnel = MLX5_FLOW_LAYER_GTP, 1164 .ptype = RTE_PTYPE_TUNNEL_GTPU, 1165 }, 1166 }; 1167 1168 1169 1170 /** 1171 * Translate tag ID to register. 1172 * 1173 * @param[in] dev 1174 * Pointer to the Ethernet device structure. 1175 * @param[in] feature 1176 * The feature that request the register. 1177 * @param[in] id 1178 * The request register ID. 1179 * @param[out] error 1180 * Error description in case of any. 1181 * 1182 * @return 1183 * The request register on success, a negative errno 1184 * value otherwise and rte_errno is set. 1185 */ 1186 int 1187 mlx5_flow_get_reg_id(struct rte_eth_dev *dev, 1188 enum mlx5_feature_name feature, 1189 uint32_t id, 1190 struct rte_flow_error *error) 1191 { 1192 struct mlx5_priv *priv = dev->data->dev_private; 1193 struct mlx5_sh_config *config = &priv->sh->config; 1194 enum modify_reg start_reg; 1195 bool skip_mtr_reg = false; 1196 1197 switch (feature) { 1198 case MLX5_HAIRPIN_RX: 1199 return REG_B; 1200 case MLX5_HAIRPIN_TX: 1201 return REG_A; 1202 case MLX5_METADATA_RX: 1203 switch (config->dv_xmeta_en) { 1204 case MLX5_XMETA_MODE_LEGACY: 1205 return REG_B; 1206 case MLX5_XMETA_MODE_META16: 1207 return REG_C_0; 1208 case MLX5_XMETA_MODE_META32: 1209 return REG_C_1; 1210 case MLX5_XMETA_MODE_META32_HWS: 1211 return REG_C_1; 1212 } 1213 break; 1214 case MLX5_METADATA_TX: 1215 if (config->dv_flow_en == 2 && config->dv_xmeta_en == MLX5_XMETA_MODE_META32_HWS) { 1216 return REG_C_1; 1217 } else { 1218 return REG_A; 1219 } 1220 case MLX5_METADATA_FDB: 1221 switch (config->dv_xmeta_en) { 1222 case MLX5_XMETA_MODE_LEGACY: 1223 return REG_NON; 1224 case MLX5_XMETA_MODE_META16: 1225 return REG_C_0; 1226 case MLX5_XMETA_MODE_META32: 1227 return REG_C_1; 1228 case MLX5_XMETA_MODE_META32_HWS: 1229 return REG_C_1; 1230 } 1231 break; 1232 case MLX5_FLOW_MARK: 1233 switch (config->dv_xmeta_en) { 1234 case MLX5_XMETA_MODE_LEGACY: 1235 case MLX5_XMETA_MODE_META32_HWS: 1236 return REG_NON; 1237 case MLX5_XMETA_MODE_META16: 1238 return REG_C_1; 1239 case MLX5_XMETA_MODE_META32: 1240 return REG_C_0; 1241 } 1242 break; 1243 case MLX5_MTR_ID: 1244 /* 1245 * If meter color and meter id share one register, flow match 1246 * should use the meter color register for match. 1247 */ 1248 if (priv->mtr_reg_share) 1249 return priv->mtr_color_reg; 1250 else 1251 return priv->mtr_color_reg != REG_C_2 ? REG_C_2 : 1252 REG_C_3; 1253 case MLX5_MTR_COLOR: 1254 case MLX5_ASO_FLOW_HIT: 1255 case MLX5_ASO_CONNTRACK: 1256 case MLX5_SAMPLE_ID: 1257 /* All features use the same REG_C. */ 1258 MLX5_ASSERT(priv->mtr_color_reg != REG_NON); 1259 return priv->mtr_color_reg; 1260 case MLX5_COPY_MARK: 1261 /* 1262 * Metadata COPY_MARK register using is in meter suffix sub 1263 * flow while with meter. It's safe to share the same register. 1264 */ 1265 return priv->mtr_color_reg != REG_C_2 ? REG_C_2 : REG_C_3; 1266 case MLX5_APP_TAG: 1267 /* 1268 * If meter is enable, it will engage the register for color 1269 * match and flow match. If meter color match is not using the 1270 * REG_C_2, need to skip the REG_C_x be used by meter color 1271 * match. 1272 * If meter is disable, free to use all available registers. 1273 */ 1274 start_reg = priv->mtr_color_reg != REG_C_2 ? REG_C_2 : 1275 (priv->mtr_reg_share ? REG_C_3 : REG_C_4); 1276 skip_mtr_reg = !!(priv->mtr_en && start_reg == REG_C_2); 1277 if (id > (uint32_t)(REG_C_7 - start_reg)) 1278 return rte_flow_error_set(error, EINVAL, 1279 RTE_FLOW_ERROR_TYPE_ITEM, 1280 NULL, "invalid tag id"); 1281 if (priv->sh->flow_mreg_c[id + start_reg - REG_C_0] == REG_NON) 1282 return rte_flow_error_set(error, ENOTSUP, 1283 RTE_FLOW_ERROR_TYPE_ITEM, 1284 NULL, "unsupported tag id"); 1285 /* 1286 * This case means meter is using the REG_C_x great than 2. 1287 * Take care not to conflict with meter color REG_C_x. 1288 * If the available index REG_C_y >= REG_C_x, skip the 1289 * color register. 1290 */ 1291 if (skip_mtr_reg && priv->sh->flow_mreg_c 1292 [id + start_reg - REG_C_0] >= priv->mtr_color_reg) { 1293 if (id >= (uint32_t)(REG_C_7 - start_reg)) 1294 return rte_flow_error_set(error, EINVAL, 1295 RTE_FLOW_ERROR_TYPE_ITEM, 1296 NULL, "invalid tag id"); 1297 if (priv->sh->flow_mreg_c 1298 [id + 1 + start_reg - REG_C_0] != REG_NON) 1299 return priv->sh->flow_mreg_c 1300 [id + 1 + start_reg - REG_C_0]; 1301 return rte_flow_error_set(error, ENOTSUP, 1302 RTE_FLOW_ERROR_TYPE_ITEM, 1303 NULL, "unsupported tag id"); 1304 } 1305 return priv->sh->flow_mreg_c[id + start_reg - REG_C_0]; 1306 } 1307 MLX5_ASSERT(false); 1308 return rte_flow_error_set(error, EINVAL, 1309 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, 1310 NULL, "invalid feature name"); 1311 } 1312 1313 /** 1314 * Check extensive flow metadata register support. 1315 * 1316 * @param dev 1317 * Pointer to rte_eth_dev structure. 1318 * 1319 * @return 1320 * True if device supports extensive flow metadata register, otherwise false. 1321 */ 1322 bool 1323 mlx5_flow_ext_mreg_supported(struct rte_eth_dev *dev) 1324 { 1325 struct mlx5_priv *priv = dev->data->dev_private; 1326 1327 /* 1328 * Having available reg_c can be regarded inclusively as supporting 1329 * extensive flow metadata register, which could mean, 1330 * - metadata register copy action by modify header. 1331 * - 16 modify header actions is supported. 1332 * - reg_c's are preserved across different domain (FDB and NIC) on 1333 * packet loopback by flow lookup miss. 1334 */ 1335 return priv->sh->flow_mreg_c[2] != REG_NON; 1336 } 1337 1338 /** 1339 * Get the lowest priority. 1340 * 1341 * @param[in] dev 1342 * Pointer to the Ethernet device structure. 1343 * @param[in] attributes 1344 * Pointer to device flow rule attributes. 1345 * 1346 * @return 1347 * The value of lowest priority of flow. 1348 */ 1349 uint32_t 1350 mlx5_get_lowest_priority(struct rte_eth_dev *dev, 1351 const struct rte_flow_attr *attr) 1352 { 1353 struct mlx5_priv *priv = dev->data->dev_private; 1354 1355 if (!attr->group && !(attr->transfer && priv->fdb_def_rule)) 1356 return priv->sh->flow_max_priority - 2; 1357 return MLX5_NON_ROOT_FLOW_MAX_PRIO - 1; 1358 } 1359 1360 /** 1361 * Calculate matcher priority of the flow. 1362 * 1363 * @param[in] dev 1364 * Pointer to the Ethernet device structure. 1365 * @param[in] attr 1366 * Pointer to device flow rule attributes. 1367 * @param[in] subpriority 1368 * The priority based on the items. 1369 * @param[in] external 1370 * Flow is user flow. 1371 * @return 1372 * The matcher priority of the flow. 1373 */ 1374 uint16_t 1375 mlx5_get_matcher_priority(struct rte_eth_dev *dev, 1376 const struct rte_flow_attr *attr, 1377 uint32_t subpriority, bool external) 1378 { 1379 uint16_t priority = (uint16_t)attr->priority; 1380 struct mlx5_priv *priv = dev->data->dev_private; 1381 1382 /* NIC root rules */ 1383 if (!attr->group && !attr->transfer) { 1384 if (attr->priority == MLX5_FLOW_LOWEST_PRIO_INDICATOR) 1385 priority = priv->sh->flow_max_priority - 1; 1386 return mlx5_os_flow_adjust_priority(dev, priority, subpriority); 1387 /* FDB root rules */ 1388 } else if (attr->transfer && (!external || !priv->fdb_def_rule) && 1389 attr->group == 0 && 1390 attr->priority == MLX5_FLOW_LOWEST_PRIO_INDICATOR) { 1391 return (priv->sh->flow_max_priority - 1) * 3; 1392 } 1393 if (attr->priority == MLX5_FLOW_LOWEST_PRIO_INDICATOR) 1394 priority = MLX5_NON_ROOT_FLOW_MAX_PRIO; 1395 return priority * 3 + subpriority; 1396 } 1397 1398 /** 1399 * Verify the @p item specifications (spec, last, mask) are compatible with the 1400 * NIC capabilities. 1401 * 1402 * @param[in] item 1403 * Item specification. 1404 * @param[in] mask 1405 * @p item->mask or flow default bit-masks. 1406 * @param[in] nic_mask 1407 * Bit-masks covering supported fields by the NIC to compare with user mask. 1408 * @param[in] size 1409 * Bit-masks size in bytes. 1410 * @param[in] range_accepted 1411 * True if range of values is accepted for specific fields, false otherwise. 1412 * @param[out] error 1413 * Pointer to error structure. 1414 * 1415 * @return 1416 * 0 on success, a negative errno value otherwise and rte_errno is set. 1417 */ 1418 int 1419 mlx5_flow_item_acceptable(const struct rte_flow_item *item, 1420 const uint8_t *mask, 1421 const uint8_t *nic_mask, 1422 unsigned int size, 1423 bool range_accepted, 1424 struct rte_flow_error *error) 1425 { 1426 unsigned int i; 1427 1428 MLX5_ASSERT(nic_mask); 1429 for (i = 0; i < size; ++i) 1430 if ((nic_mask[i] | mask[i]) != nic_mask[i]) 1431 return rte_flow_error_set(error, ENOTSUP, 1432 RTE_FLOW_ERROR_TYPE_ITEM, 1433 item, 1434 "mask enables non supported" 1435 " bits"); 1436 if (!item->spec && (item->mask || item->last)) 1437 return rte_flow_error_set(error, EINVAL, 1438 RTE_FLOW_ERROR_TYPE_ITEM, item, 1439 "mask/last without a spec is not" 1440 " supported"); 1441 if (item->spec && item->last && !range_accepted) { 1442 uint8_t spec[size]; 1443 uint8_t last[size]; 1444 unsigned int i; 1445 int ret; 1446 1447 for (i = 0; i < size; ++i) { 1448 spec[i] = ((const uint8_t *)item->spec)[i] & mask[i]; 1449 last[i] = ((const uint8_t *)item->last)[i] & mask[i]; 1450 } 1451 ret = memcmp(spec, last, size); 1452 if (ret != 0) 1453 return rte_flow_error_set(error, EINVAL, 1454 RTE_FLOW_ERROR_TYPE_ITEM, 1455 item, 1456 "range is not valid"); 1457 } 1458 return 0; 1459 } 1460 1461 /** 1462 * Adjust the hash fields according to the @p flow information. 1463 * 1464 * @param[in] dev_flow. 1465 * Pointer to the mlx5_flow. 1466 * @param[in] tunnel 1467 * 1 when the hash field is for a tunnel item. 1468 * @param[in] layer_types 1469 * RTE_ETH_RSS_* types. 1470 * @param[in] hash_fields 1471 * Item hash fields. 1472 * 1473 * @return 1474 * The hash fields that should be used. 1475 */ 1476 uint64_t 1477 mlx5_flow_hashfields_adjust(struct mlx5_flow_rss_desc *rss_desc, 1478 int tunnel __rte_unused, uint64_t layer_types, 1479 uint64_t hash_fields) 1480 { 1481 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT 1482 int rss_request_inner = rss_desc->level >= 2; 1483 1484 /* Check RSS hash level for tunnel. */ 1485 if (tunnel && rss_request_inner) 1486 hash_fields |= IBV_RX_HASH_INNER; 1487 else if (tunnel || rss_request_inner) 1488 return 0; 1489 #endif 1490 /* Check if requested layer matches RSS hash fields. */ 1491 if (!(rss_desc->types & layer_types)) 1492 return 0; 1493 return hash_fields; 1494 } 1495 1496 /** 1497 * Lookup and set the ptype in the data Rx part. A single Ptype can be used, 1498 * if several tunnel rules are used on this queue, the tunnel ptype will be 1499 * cleared. 1500 * 1501 * @param rxq_ctrl 1502 * Rx queue to update. 1503 */ 1504 static void 1505 flow_rxq_tunnel_ptype_update(struct mlx5_rxq_ctrl *rxq_ctrl) 1506 { 1507 unsigned int i; 1508 uint32_t tunnel_ptype = 0; 1509 1510 /* Look up for the ptype to use. */ 1511 for (i = 0; i != MLX5_FLOW_TUNNEL; ++i) { 1512 if (!rxq_ctrl->flow_tunnels_n[i]) 1513 continue; 1514 if (!tunnel_ptype) { 1515 tunnel_ptype = tunnels_info[i].ptype; 1516 } else { 1517 tunnel_ptype = 0; 1518 break; 1519 } 1520 } 1521 rxq_ctrl->rxq.tunnel = tunnel_ptype; 1522 } 1523 1524 /** 1525 * Set the Rx queue flags (Mark/Flag and Tunnel Ptypes) according to the device 1526 * flow. 1527 * 1528 * @param[in] dev 1529 * Pointer to the Ethernet device structure. 1530 * @param[in] dev_handle 1531 * Pointer to device flow handle structure. 1532 */ 1533 void 1534 flow_drv_rxq_flags_set(struct rte_eth_dev *dev, 1535 struct mlx5_flow_handle *dev_handle) 1536 { 1537 struct mlx5_priv *priv = dev->data->dev_private; 1538 const int tunnel = !!(dev_handle->layers & MLX5_FLOW_LAYER_TUNNEL); 1539 struct mlx5_ind_table_obj *ind_tbl = NULL; 1540 unsigned int i; 1541 1542 if (dev_handle->fate_action == MLX5_FLOW_FATE_QUEUE) { 1543 struct mlx5_hrxq *hrxq; 1544 1545 hrxq = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_HRXQ], 1546 dev_handle->rix_hrxq); 1547 if (hrxq) 1548 ind_tbl = hrxq->ind_table; 1549 } else if (dev_handle->fate_action == MLX5_FLOW_FATE_SHARED_RSS) { 1550 struct mlx5_shared_action_rss *shared_rss; 1551 1552 shared_rss = mlx5_ipool_get 1553 (priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], 1554 dev_handle->rix_srss); 1555 if (shared_rss) 1556 ind_tbl = shared_rss->ind_tbl; 1557 } 1558 if (!ind_tbl) 1559 return; 1560 for (i = 0; i != ind_tbl->queues_n; ++i) { 1561 int idx = ind_tbl->queues[i]; 1562 struct mlx5_rxq_ctrl *rxq_ctrl; 1563 1564 if (mlx5_is_external_rxq(dev, idx)) 1565 continue; 1566 rxq_ctrl = mlx5_rxq_ctrl_get(dev, idx); 1567 MLX5_ASSERT(rxq_ctrl != NULL); 1568 if (rxq_ctrl == NULL) 1569 continue; 1570 /* 1571 * To support metadata register copy on Tx loopback, 1572 * this must be always enabled (metadata may arive 1573 * from other port - not from local flows only. 1574 */ 1575 if (tunnel) { 1576 unsigned int j; 1577 1578 /* Increase the counter matching the flow. */ 1579 for (j = 0; j != MLX5_FLOW_TUNNEL; ++j) { 1580 if ((tunnels_info[j].tunnel & 1581 dev_handle->layers) == 1582 tunnels_info[j].tunnel) { 1583 rxq_ctrl->flow_tunnels_n[j]++; 1584 break; 1585 } 1586 } 1587 flow_rxq_tunnel_ptype_update(rxq_ctrl); 1588 } 1589 } 1590 } 1591 1592 static void 1593 flow_rxq_mark_flag_set(struct rte_eth_dev *dev) 1594 { 1595 struct mlx5_priv *priv = dev->data->dev_private; 1596 struct mlx5_rxq_ctrl *rxq_ctrl; 1597 uint16_t port_id; 1598 1599 if (priv->sh->shared_mark_enabled) 1600 return; 1601 if (priv->master || priv->representor) { 1602 MLX5_ETH_FOREACH_DEV(port_id, dev->device) { 1603 struct mlx5_priv *opriv = 1604 rte_eth_devices[port_id].data->dev_private; 1605 1606 if (!opriv || 1607 opriv->sh != priv->sh || 1608 opriv->domain_id != priv->domain_id || 1609 opriv->mark_enabled) 1610 continue; 1611 LIST_FOREACH(rxq_ctrl, &opriv->rxqsctrl, next) { 1612 rxq_ctrl->rxq.mark = 1; 1613 } 1614 opriv->mark_enabled = 1; 1615 } 1616 } else { 1617 LIST_FOREACH(rxq_ctrl, &priv->rxqsctrl, next) { 1618 rxq_ctrl->rxq.mark = 1; 1619 } 1620 priv->mark_enabled = 1; 1621 } 1622 priv->sh->shared_mark_enabled = 1; 1623 } 1624 1625 /** 1626 * Set the Rx queue flags (Mark/Flag and Tunnel Ptypes) for a flow 1627 * 1628 * @param[in] dev 1629 * Pointer to the Ethernet device structure. 1630 * @param[in] flow 1631 * Pointer to flow structure. 1632 */ 1633 static void 1634 flow_rxq_flags_set(struct rte_eth_dev *dev, struct rte_flow *flow) 1635 { 1636 struct mlx5_priv *priv = dev->data->dev_private; 1637 uint32_t handle_idx; 1638 struct mlx5_flow_handle *dev_handle; 1639 struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace(); 1640 1641 MLX5_ASSERT(wks); 1642 if (wks->mark) 1643 flow_rxq_mark_flag_set(dev); 1644 SILIST_FOREACH(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW], flow->dev_handles, 1645 handle_idx, dev_handle, next) 1646 flow_drv_rxq_flags_set(dev, dev_handle); 1647 } 1648 1649 /** 1650 * Clear the Rx queue flags (Mark/Flag and Tunnel Ptype) associated with the 1651 * device flow if no other flow uses it with the same kind of request. 1652 * 1653 * @param dev 1654 * Pointer to Ethernet device. 1655 * @param[in] dev_handle 1656 * Pointer to the device flow handle structure. 1657 */ 1658 static void 1659 flow_drv_rxq_flags_trim(struct rte_eth_dev *dev, 1660 struct mlx5_flow_handle *dev_handle) 1661 { 1662 struct mlx5_priv *priv = dev->data->dev_private; 1663 const int tunnel = !!(dev_handle->layers & MLX5_FLOW_LAYER_TUNNEL); 1664 struct mlx5_ind_table_obj *ind_tbl = NULL; 1665 unsigned int i; 1666 1667 if (dev_handle->fate_action == MLX5_FLOW_FATE_QUEUE) { 1668 struct mlx5_hrxq *hrxq; 1669 1670 hrxq = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_HRXQ], 1671 dev_handle->rix_hrxq); 1672 if (hrxq) 1673 ind_tbl = hrxq->ind_table; 1674 } else if (dev_handle->fate_action == MLX5_FLOW_FATE_SHARED_RSS) { 1675 struct mlx5_shared_action_rss *shared_rss; 1676 1677 shared_rss = mlx5_ipool_get 1678 (priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], 1679 dev_handle->rix_srss); 1680 if (shared_rss) 1681 ind_tbl = shared_rss->ind_tbl; 1682 } 1683 if (!ind_tbl) 1684 return; 1685 MLX5_ASSERT(dev->data->dev_started); 1686 for (i = 0; i != ind_tbl->queues_n; ++i) { 1687 int idx = ind_tbl->queues[i]; 1688 struct mlx5_rxq_ctrl *rxq_ctrl; 1689 1690 if (mlx5_is_external_rxq(dev, idx)) 1691 continue; 1692 rxq_ctrl = mlx5_rxq_ctrl_get(dev, idx); 1693 MLX5_ASSERT(rxq_ctrl != NULL); 1694 if (rxq_ctrl == NULL) 1695 continue; 1696 if (tunnel) { 1697 unsigned int j; 1698 1699 /* Decrease the counter matching the flow. */ 1700 for (j = 0; j != MLX5_FLOW_TUNNEL; ++j) { 1701 if ((tunnels_info[j].tunnel & 1702 dev_handle->layers) == 1703 tunnels_info[j].tunnel) { 1704 rxq_ctrl->flow_tunnels_n[j]--; 1705 break; 1706 } 1707 } 1708 flow_rxq_tunnel_ptype_update(rxq_ctrl); 1709 } 1710 } 1711 } 1712 1713 /** 1714 * Clear the Rx queue flags (Mark/Flag and Tunnel Ptype) associated with the 1715 * @p flow if no other flow uses it with the same kind of request. 1716 * 1717 * @param dev 1718 * Pointer to Ethernet device. 1719 * @param[in] flow 1720 * Pointer to the flow. 1721 */ 1722 static void 1723 flow_rxq_flags_trim(struct rte_eth_dev *dev, struct rte_flow *flow) 1724 { 1725 struct mlx5_priv *priv = dev->data->dev_private; 1726 uint32_t handle_idx; 1727 struct mlx5_flow_handle *dev_handle; 1728 1729 SILIST_FOREACH(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW], flow->dev_handles, 1730 handle_idx, dev_handle, next) 1731 flow_drv_rxq_flags_trim(dev, dev_handle); 1732 } 1733 1734 /** 1735 * Clear the Mark/Flag and Tunnel ptype information in all Rx queues. 1736 * 1737 * @param dev 1738 * Pointer to Ethernet device. 1739 */ 1740 static void 1741 flow_rxq_flags_clear(struct rte_eth_dev *dev) 1742 { 1743 struct mlx5_priv *priv = dev->data->dev_private; 1744 unsigned int i; 1745 1746 for (i = 0; i != priv->rxqs_n; ++i) { 1747 struct mlx5_rxq_priv *rxq = mlx5_rxq_get(dev, i); 1748 unsigned int j; 1749 1750 if (rxq == NULL || rxq->ctrl == NULL) 1751 continue; 1752 rxq->ctrl->rxq.mark = 0; 1753 for (j = 0; j != MLX5_FLOW_TUNNEL; ++j) 1754 rxq->ctrl->flow_tunnels_n[j] = 0; 1755 rxq->ctrl->rxq.tunnel = 0; 1756 } 1757 priv->mark_enabled = 0; 1758 priv->sh->shared_mark_enabled = 0; 1759 } 1760 1761 /** 1762 * Set the Rx queue dynamic metadata (mask and offset) for a flow 1763 * 1764 * @param[in] dev 1765 * Pointer to the Ethernet device structure. 1766 */ 1767 void 1768 mlx5_flow_rxq_dynf_metadata_set(struct rte_eth_dev *dev) 1769 { 1770 struct mlx5_priv *priv = dev->data->dev_private; 1771 unsigned int i; 1772 1773 for (i = 0; i != priv->rxqs_n; ++i) { 1774 struct mlx5_rxq_priv *rxq = mlx5_rxq_get(dev, i); 1775 struct mlx5_rxq_data *data; 1776 1777 if (rxq == NULL || rxq->ctrl == NULL) 1778 continue; 1779 data = &rxq->ctrl->rxq; 1780 if (!rte_flow_dynf_metadata_avail()) { 1781 data->dynf_meta = 0; 1782 data->flow_meta_mask = 0; 1783 data->flow_meta_offset = -1; 1784 data->flow_meta_port_mask = 0; 1785 } else { 1786 data->dynf_meta = 1; 1787 data->flow_meta_mask = rte_flow_dynf_metadata_mask; 1788 data->flow_meta_offset = rte_flow_dynf_metadata_offs; 1789 data->flow_meta_port_mask = priv->sh->dv_meta_mask; 1790 } 1791 } 1792 } 1793 1794 /* 1795 * return a pointer to the desired action in the list of actions. 1796 * 1797 * @param[in] actions 1798 * The list of actions to search the action in. 1799 * @param[in] action 1800 * The action to find. 1801 * 1802 * @return 1803 * Pointer to the action in the list, if found. NULL otherwise. 1804 */ 1805 const struct rte_flow_action * 1806 mlx5_flow_find_action(const struct rte_flow_action *actions, 1807 enum rte_flow_action_type action) 1808 { 1809 if (actions == NULL) 1810 return NULL; 1811 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) 1812 if (actions->type == action) 1813 return actions; 1814 return NULL; 1815 } 1816 1817 /* 1818 * Validate the flag action. 1819 * 1820 * @param[in] action_flags 1821 * Bit-fields that holds the actions detected until now. 1822 * @param[in] attr 1823 * Attributes of flow that includes this action. 1824 * @param[out] error 1825 * Pointer to error structure. 1826 * 1827 * @return 1828 * 0 on success, a negative errno value otherwise and rte_errno is set. 1829 */ 1830 int 1831 mlx5_flow_validate_action_flag(uint64_t action_flags, 1832 const struct rte_flow_attr *attr, 1833 struct rte_flow_error *error) 1834 { 1835 if (action_flags & MLX5_FLOW_ACTION_MARK) 1836 return rte_flow_error_set(error, EINVAL, 1837 RTE_FLOW_ERROR_TYPE_ACTION, NULL, 1838 "can't mark and flag in same flow"); 1839 if (action_flags & MLX5_FLOW_ACTION_FLAG) 1840 return rte_flow_error_set(error, EINVAL, 1841 RTE_FLOW_ERROR_TYPE_ACTION, NULL, 1842 "can't have 2 flag" 1843 " actions in same flow"); 1844 if (attr->egress) 1845 return rte_flow_error_set(error, ENOTSUP, 1846 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, NULL, 1847 "flag action not supported for " 1848 "egress"); 1849 return 0; 1850 } 1851 1852 /* 1853 * Validate the mark action. 1854 * 1855 * @param[in] action 1856 * Pointer to the queue action. 1857 * @param[in] action_flags 1858 * Bit-fields that holds the actions detected until now. 1859 * @param[in] attr 1860 * Attributes of flow that includes this action. 1861 * @param[out] error 1862 * Pointer to error structure. 1863 * 1864 * @return 1865 * 0 on success, a negative errno value otherwise and rte_errno is set. 1866 */ 1867 int 1868 mlx5_flow_validate_action_mark(const struct rte_flow_action *action, 1869 uint64_t action_flags, 1870 const struct rte_flow_attr *attr, 1871 struct rte_flow_error *error) 1872 { 1873 const struct rte_flow_action_mark *mark = action->conf; 1874 1875 if (!mark) 1876 return rte_flow_error_set(error, EINVAL, 1877 RTE_FLOW_ERROR_TYPE_ACTION, 1878 action, 1879 "configuration cannot be null"); 1880 if (mark->id >= MLX5_FLOW_MARK_MAX) 1881 return rte_flow_error_set(error, EINVAL, 1882 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 1883 &mark->id, 1884 "mark id must in 0 <= id < " 1885 RTE_STR(MLX5_FLOW_MARK_MAX)); 1886 if (action_flags & MLX5_FLOW_ACTION_FLAG) 1887 return rte_flow_error_set(error, EINVAL, 1888 RTE_FLOW_ERROR_TYPE_ACTION, NULL, 1889 "can't flag and mark in same flow"); 1890 if (action_flags & MLX5_FLOW_ACTION_MARK) 1891 return rte_flow_error_set(error, EINVAL, 1892 RTE_FLOW_ERROR_TYPE_ACTION, NULL, 1893 "can't have 2 mark actions in same" 1894 " flow"); 1895 if (attr->egress) 1896 return rte_flow_error_set(error, ENOTSUP, 1897 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, NULL, 1898 "mark action not supported for " 1899 "egress"); 1900 return 0; 1901 } 1902 1903 /* 1904 * Validate the drop action. 1905 * 1906 * @param[in] action_flags 1907 * Bit-fields that holds the actions detected until now. 1908 * @param[in] attr 1909 * Attributes of flow that includes this action. 1910 * @param[out] error 1911 * Pointer to error structure. 1912 * 1913 * @return 1914 * 0 on success, a negative errno value otherwise and rte_errno is set. 1915 */ 1916 int 1917 mlx5_flow_validate_action_drop(uint64_t action_flags __rte_unused, 1918 const struct rte_flow_attr *attr, 1919 struct rte_flow_error *error) 1920 { 1921 if (attr->egress) 1922 return rte_flow_error_set(error, ENOTSUP, 1923 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, NULL, 1924 "drop action not supported for " 1925 "egress"); 1926 return 0; 1927 } 1928 1929 /* 1930 * Validate the queue action. 1931 * 1932 * @param[in] action 1933 * Pointer to the queue action. 1934 * @param[in] action_flags 1935 * Bit-fields that holds the actions detected until now. 1936 * @param[in] dev 1937 * Pointer to the Ethernet device structure. 1938 * @param[in] attr 1939 * Attributes of flow that includes this action. 1940 * @param[out] error 1941 * Pointer to error structure. 1942 * 1943 * @return 1944 * 0 on success, a negative errno value otherwise and rte_errno is set. 1945 */ 1946 int 1947 mlx5_flow_validate_action_queue(const struct rte_flow_action *action, 1948 uint64_t action_flags, 1949 struct rte_eth_dev *dev, 1950 const struct rte_flow_attr *attr, 1951 struct rte_flow_error *error) 1952 { 1953 struct mlx5_priv *priv = dev->data->dev_private; 1954 const struct rte_flow_action_queue *queue = action->conf; 1955 1956 if (action_flags & MLX5_FLOW_FATE_ACTIONS) 1957 return rte_flow_error_set(error, EINVAL, 1958 RTE_FLOW_ERROR_TYPE_ACTION, NULL, 1959 "can't have 2 fate actions in" 1960 " same flow"); 1961 if (attr->egress) 1962 return rte_flow_error_set(error, ENOTSUP, 1963 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, NULL, 1964 "queue action not supported for egress."); 1965 if (mlx5_is_external_rxq(dev, queue->index)) 1966 return 0; 1967 if (!priv->rxqs_n) 1968 return rte_flow_error_set(error, EINVAL, 1969 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 1970 NULL, "No Rx queues configured"); 1971 if (queue->index >= priv->rxqs_n) 1972 return rte_flow_error_set(error, EINVAL, 1973 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 1974 &queue->index, 1975 "queue index out of range"); 1976 if (mlx5_rxq_get(dev, queue->index) == NULL) 1977 return rte_flow_error_set(error, EINVAL, 1978 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 1979 &queue->index, 1980 "queue is not configured"); 1981 return 0; 1982 } 1983 1984 /** 1985 * Validate queue numbers for device RSS. 1986 * 1987 * @param[in] dev 1988 * Configured device. 1989 * @param[in] queues 1990 * Array of queue numbers. 1991 * @param[in] queues_n 1992 * Size of the @p queues array. 1993 * @param[out] error 1994 * On error, filled with a textual error description. 1995 * @param[out] queue_idx 1996 * On error, filled with an offending queue index in @p queues array. 1997 * 1998 * @return 1999 * 0 on success, a negative errno code on error. 2000 */ 2001 static int 2002 mlx5_validate_rss_queues(struct rte_eth_dev *dev, 2003 const uint16_t *queues, uint32_t queues_n, 2004 const char **error, uint32_t *queue_idx) 2005 { 2006 const struct mlx5_priv *priv = dev->data->dev_private; 2007 bool is_hairpin = false; 2008 bool is_ext_rss = false; 2009 uint32_t i; 2010 2011 for (i = 0; i != queues_n; ++i) { 2012 struct mlx5_rxq_ctrl *rxq_ctrl; 2013 2014 if (mlx5_is_external_rxq(dev, queues[0])) { 2015 is_ext_rss = true; 2016 continue; 2017 } 2018 if (is_ext_rss) { 2019 *error = "Combining external and regular RSS queues is not supported"; 2020 *queue_idx = i; 2021 return -ENOTSUP; 2022 } 2023 if (queues[i] >= priv->rxqs_n) { 2024 *error = "queue index out of range"; 2025 *queue_idx = i; 2026 return -EINVAL; 2027 } 2028 rxq_ctrl = mlx5_rxq_ctrl_get(dev, queues[i]); 2029 if (rxq_ctrl == NULL) { 2030 *error = "queue is not configured"; 2031 *queue_idx = i; 2032 return -EINVAL; 2033 } 2034 if (i == 0 && rxq_ctrl->is_hairpin) 2035 is_hairpin = true; 2036 if (is_hairpin != rxq_ctrl->is_hairpin) { 2037 *error = "combining hairpin and regular RSS queues is not supported"; 2038 *queue_idx = i; 2039 return -ENOTSUP; 2040 } 2041 } 2042 return 0; 2043 } 2044 2045 /* 2046 * Validate the rss action. 2047 * 2048 * @param[in] dev 2049 * Pointer to the Ethernet device structure. 2050 * @param[in] action 2051 * Pointer to the queue action. 2052 * @param[out] error 2053 * Pointer to error structure. 2054 * 2055 * @return 2056 * 0 on success, a negative errno value otherwise and rte_errno is set. 2057 */ 2058 int 2059 mlx5_validate_action_rss(struct rte_eth_dev *dev, 2060 const struct rte_flow_action *action, 2061 struct rte_flow_error *error) 2062 { 2063 struct mlx5_priv *priv = dev->data->dev_private; 2064 const struct rte_flow_action_rss *rss = action->conf; 2065 int ret; 2066 const char *message; 2067 uint32_t queue_idx; 2068 2069 if (rss->func != RTE_ETH_HASH_FUNCTION_DEFAULT && 2070 rss->func != RTE_ETH_HASH_FUNCTION_TOEPLITZ) 2071 return rte_flow_error_set(error, ENOTSUP, 2072 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 2073 &rss->func, 2074 "RSS hash function not supported"); 2075 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT 2076 if (rss->level > 2) 2077 #else 2078 if (rss->level > 1) 2079 #endif 2080 return rte_flow_error_set(error, ENOTSUP, 2081 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 2082 &rss->level, 2083 "tunnel RSS is not supported"); 2084 /* allow RSS key_len 0 in case of NULL (default) RSS key. */ 2085 if (rss->key_len == 0 && rss->key != NULL) 2086 return rte_flow_error_set(error, ENOTSUP, 2087 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 2088 &rss->key_len, 2089 "RSS hash key length 0"); 2090 if (rss->key_len > 0 && rss->key_len < MLX5_RSS_HASH_KEY_LEN) 2091 return rte_flow_error_set(error, ENOTSUP, 2092 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 2093 &rss->key_len, 2094 "RSS hash key too small"); 2095 if (rss->key_len > MLX5_RSS_HASH_KEY_LEN) 2096 return rte_flow_error_set(error, ENOTSUP, 2097 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 2098 &rss->key_len, 2099 "RSS hash key too large"); 2100 if (rss->queue_num > priv->sh->dev_cap.ind_table_max_size) 2101 return rte_flow_error_set(error, ENOTSUP, 2102 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 2103 &rss->queue_num, 2104 "number of queues too large"); 2105 if (rss->types & MLX5_RSS_HF_MASK) 2106 return rte_flow_error_set(error, ENOTSUP, 2107 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 2108 &rss->types, 2109 "some RSS protocols are not" 2110 " supported"); 2111 if ((rss->types & (RTE_ETH_RSS_L3_SRC_ONLY | RTE_ETH_RSS_L3_DST_ONLY)) && 2112 !(rss->types & RTE_ETH_RSS_IP)) 2113 return rte_flow_error_set(error, EINVAL, 2114 RTE_FLOW_ERROR_TYPE_ACTION_CONF, NULL, 2115 "L3 partial RSS requested but L3 RSS" 2116 " type not specified"); 2117 if ((rss->types & (RTE_ETH_RSS_L4_SRC_ONLY | RTE_ETH_RSS_L4_DST_ONLY)) && 2118 !(rss->types & (RTE_ETH_RSS_UDP | RTE_ETH_RSS_TCP))) 2119 return rte_flow_error_set(error, EINVAL, 2120 RTE_FLOW_ERROR_TYPE_ACTION_CONF, NULL, 2121 "L4 partial RSS requested but L4 RSS" 2122 " type not specified"); 2123 if (!priv->rxqs_n && priv->ext_rxqs == NULL) 2124 return rte_flow_error_set(error, EINVAL, 2125 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 2126 NULL, "No Rx queues configured"); 2127 if (!rss->queue_num) 2128 return rte_flow_error_set(error, EINVAL, 2129 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 2130 NULL, "No queues configured"); 2131 ret = mlx5_validate_rss_queues(dev, rss->queue, rss->queue_num, 2132 &message, &queue_idx); 2133 if (ret != 0) { 2134 return rte_flow_error_set(error, -ret, 2135 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 2136 &rss->queue[queue_idx], message); 2137 } 2138 return 0; 2139 } 2140 2141 /* 2142 * Validate the rss action. 2143 * 2144 * @param[in] action 2145 * Pointer to the queue action. 2146 * @param[in] action_flags 2147 * Bit-fields that holds the actions detected until now. 2148 * @param[in] dev 2149 * Pointer to the Ethernet device structure. 2150 * @param[in] attr 2151 * Attributes of flow that includes this action. 2152 * @param[in] item_flags 2153 * Items that were detected. 2154 * @param[out] error 2155 * Pointer to error structure. 2156 * 2157 * @return 2158 * 0 on success, a negative errno value otherwise and rte_errno is set. 2159 */ 2160 int 2161 mlx5_flow_validate_action_rss(const struct rte_flow_action *action, 2162 uint64_t action_flags, 2163 struct rte_eth_dev *dev, 2164 const struct rte_flow_attr *attr, 2165 uint64_t item_flags, 2166 struct rte_flow_error *error) 2167 { 2168 const struct rte_flow_action_rss *rss = action->conf; 2169 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL); 2170 int ret; 2171 2172 if (action_flags & MLX5_FLOW_FATE_ACTIONS) 2173 return rte_flow_error_set(error, EINVAL, 2174 RTE_FLOW_ERROR_TYPE_ACTION, NULL, 2175 "can't have 2 fate actions" 2176 " in same flow"); 2177 ret = mlx5_validate_action_rss(dev, action, error); 2178 if (ret) 2179 return ret; 2180 if (attr->egress) 2181 return rte_flow_error_set(error, ENOTSUP, 2182 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, NULL, 2183 "rss action not supported for " 2184 "egress"); 2185 if (rss->level > 1 && !tunnel) 2186 return rte_flow_error_set(error, EINVAL, 2187 RTE_FLOW_ERROR_TYPE_ACTION_CONF, NULL, 2188 "inner RSS is not supported for " 2189 "non-tunnel flows"); 2190 if ((item_flags & MLX5_FLOW_LAYER_ECPRI) && 2191 !(item_flags & MLX5_FLOW_LAYER_INNER_L4_UDP)) { 2192 return rte_flow_error_set(error, EINVAL, 2193 RTE_FLOW_ERROR_TYPE_ACTION_CONF, NULL, 2194 "RSS on eCPRI is not supported now"); 2195 } 2196 if ((item_flags & MLX5_FLOW_LAYER_MPLS) && 2197 !(item_flags & 2198 (MLX5_FLOW_LAYER_INNER_L2 | MLX5_FLOW_LAYER_INNER_L3)) && 2199 rss->level > 1) 2200 return rte_flow_error_set(error, EINVAL, 2201 RTE_FLOW_ERROR_TYPE_ITEM, NULL, 2202 "MPLS inner RSS needs to specify inner L2/L3 items after MPLS in pattern"); 2203 return 0; 2204 } 2205 2206 /* 2207 * Validate the default miss action. 2208 * 2209 * @param[in] action_flags 2210 * Bit-fields that holds the actions detected until now. 2211 * @param[out] error 2212 * Pointer to error structure. 2213 * 2214 * @return 2215 * 0 on success, a negative errno value otherwise and rte_errno is set. 2216 */ 2217 int 2218 mlx5_flow_validate_action_default_miss(uint64_t action_flags, 2219 const struct rte_flow_attr *attr, 2220 struct rte_flow_error *error) 2221 { 2222 if (action_flags & MLX5_FLOW_FATE_ACTIONS) 2223 return rte_flow_error_set(error, EINVAL, 2224 RTE_FLOW_ERROR_TYPE_ACTION, NULL, 2225 "can't have 2 fate actions in" 2226 " same flow"); 2227 if (attr->egress) 2228 return rte_flow_error_set(error, ENOTSUP, 2229 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, NULL, 2230 "default miss action not supported " 2231 "for egress"); 2232 if (attr->group) 2233 return rte_flow_error_set(error, ENOTSUP, 2234 RTE_FLOW_ERROR_TYPE_ATTR_GROUP, NULL, 2235 "only group 0 is supported"); 2236 if (attr->transfer) 2237 return rte_flow_error_set(error, ENOTSUP, 2238 RTE_FLOW_ERROR_TYPE_ATTR_TRANSFER, 2239 NULL, "transfer is not supported"); 2240 return 0; 2241 } 2242 2243 /* 2244 * Validate the count action. 2245 * 2246 * @param[in] dev 2247 * Pointer to the Ethernet device structure. 2248 * @param[in] attr 2249 * Attributes of flow that includes this action. 2250 * @param[out] error 2251 * Pointer to error structure. 2252 * 2253 * @return 2254 * 0 on success, a negative errno value otherwise and rte_errno is set. 2255 */ 2256 int 2257 mlx5_flow_validate_action_count(struct rte_eth_dev *dev __rte_unused, 2258 const struct rte_flow_attr *attr, 2259 struct rte_flow_error *error) 2260 { 2261 if (attr->egress) 2262 return rte_flow_error_set(error, ENOTSUP, 2263 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, NULL, 2264 "count action not supported for " 2265 "egress"); 2266 return 0; 2267 } 2268 2269 /* 2270 * Validate the ASO CT action. 2271 * 2272 * @param[in] dev 2273 * Pointer to the Ethernet device structure. 2274 * @param[in] conntrack 2275 * Pointer to the CT action profile. 2276 * @param[out] error 2277 * Pointer to error structure. 2278 * 2279 * @return 2280 * 0 on success, a negative errno value otherwise and rte_errno is set. 2281 */ 2282 int 2283 mlx5_validate_action_ct(struct rte_eth_dev *dev, 2284 const struct rte_flow_action_conntrack *conntrack, 2285 struct rte_flow_error *error) 2286 { 2287 RTE_SET_USED(dev); 2288 2289 if (conntrack->state > RTE_FLOW_CONNTRACK_STATE_TIME_WAIT) 2290 return rte_flow_error_set(error, EINVAL, 2291 RTE_FLOW_ERROR_TYPE_ACTION, NULL, 2292 "Invalid CT state"); 2293 if (conntrack->last_index > RTE_FLOW_CONNTRACK_FLAG_RST) 2294 return rte_flow_error_set(error, EINVAL, 2295 RTE_FLOW_ERROR_TYPE_ACTION, NULL, 2296 "Invalid last TCP packet flag"); 2297 return 0; 2298 } 2299 2300 /** 2301 * Validate ICMP6 item. 2302 * 2303 * @param[in] item 2304 * Item specification. 2305 * @param[in] item_flags 2306 * Bit-fields that holds the items detected until now. 2307 * @param[in] ext_vlan_sup 2308 * Whether extended VLAN features are supported or not. 2309 * @param[out] error 2310 * Pointer to error structure. 2311 * 2312 * @return 2313 * 0 on success, a negative errno value otherwise and rte_errno is set. 2314 */ 2315 int 2316 mlx5_flow_validate_item_icmp6(const struct rte_flow_item *item, 2317 uint64_t item_flags, 2318 uint8_t target_protocol, 2319 struct rte_flow_error *error) 2320 { 2321 const struct rte_flow_item_icmp6 *mask = item->mask; 2322 const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL); 2323 const uint64_t l3m = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 : 2324 MLX5_FLOW_LAYER_OUTER_L3_IPV6; 2325 const uint64_t l4m = tunnel ? MLX5_FLOW_LAYER_INNER_L4 : 2326 MLX5_FLOW_LAYER_OUTER_L4; 2327 int ret; 2328 2329 if (target_protocol != 0xFF && target_protocol != IPPROTO_ICMPV6) 2330 return rte_flow_error_set(error, EINVAL, 2331 RTE_FLOW_ERROR_TYPE_ITEM, item, 2332 "protocol filtering not compatible" 2333 " with ICMP6 layer"); 2334 if (!(item_flags & l3m)) 2335 return rte_flow_error_set(error, EINVAL, 2336 RTE_FLOW_ERROR_TYPE_ITEM, item, 2337 "IPv6 is mandatory to filter on" 2338 " ICMP6"); 2339 if (item_flags & l4m) 2340 return rte_flow_error_set(error, EINVAL, 2341 RTE_FLOW_ERROR_TYPE_ITEM, item, 2342 "multiple L4 layers not supported"); 2343 if (!mask) 2344 mask = &rte_flow_item_icmp6_mask; 2345 ret = mlx5_flow_item_acceptable 2346 (item, (const uint8_t *)mask, 2347 (const uint8_t *)&rte_flow_item_icmp6_mask, 2348 sizeof(struct rte_flow_item_icmp6), 2349 MLX5_ITEM_RANGE_NOT_ACCEPTED, error); 2350 if (ret < 0) 2351 return ret; 2352 return 0; 2353 } 2354 2355 /** 2356 * Validate ICMP item. 2357 * 2358 * @param[in] item 2359 * Item specification. 2360 * @param[in] item_flags 2361 * Bit-fields that holds the items detected until now. 2362 * @param[out] error 2363 * Pointer to error structure. 2364 * 2365 * @return 2366 * 0 on success, a negative errno value otherwise and rte_errno is set. 2367 */ 2368 int 2369 mlx5_flow_validate_item_icmp(const struct rte_flow_item *item, 2370 uint64_t item_flags, 2371 uint8_t target_protocol, 2372 struct rte_flow_error *error) 2373 { 2374 const struct rte_flow_item_icmp *mask = item->mask; 2375 const struct rte_flow_item_icmp nic_mask = { 2376 .hdr.icmp_type = 0xff, 2377 .hdr.icmp_code = 0xff, 2378 .hdr.icmp_ident = RTE_BE16(0xffff), 2379 .hdr.icmp_seq_nb = RTE_BE16(0xffff), 2380 }; 2381 const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL); 2382 const uint64_t l3m = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 : 2383 MLX5_FLOW_LAYER_OUTER_L3_IPV4; 2384 const uint64_t l4m = tunnel ? MLX5_FLOW_LAYER_INNER_L4 : 2385 MLX5_FLOW_LAYER_OUTER_L4; 2386 int ret; 2387 2388 if (target_protocol != 0xFF && target_protocol != IPPROTO_ICMP) 2389 return rte_flow_error_set(error, EINVAL, 2390 RTE_FLOW_ERROR_TYPE_ITEM, item, 2391 "protocol filtering not compatible" 2392 " with ICMP layer"); 2393 if (!(item_flags & l3m)) 2394 return rte_flow_error_set(error, EINVAL, 2395 RTE_FLOW_ERROR_TYPE_ITEM, item, 2396 "IPv4 is mandatory to filter" 2397 " on ICMP"); 2398 if (item_flags & l4m) 2399 return rte_flow_error_set(error, EINVAL, 2400 RTE_FLOW_ERROR_TYPE_ITEM, item, 2401 "multiple L4 layers not supported"); 2402 if (!mask) 2403 mask = &nic_mask; 2404 ret = mlx5_flow_item_acceptable 2405 (item, (const uint8_t *)mask, 2406 (const uint8_t *)&nic_mask, 2407 sizeof(struct rte_flow_item_icmp), 2408 MLX5_ITEM_RANGE_NOT_ACCEPTED, error); 2409 if (ret < 0) 2410 return ret; 2411 return 0; 2412 } 2413 2414 /** 2415 * Validate Ethernet item. 2416 * 2417 * @param[in] item 2418 * Item specification. 2419 * @param[in] item_flags 2420 * Bit-fields that holds the items detected until now. 2421 * @param[out] error 2422 * Pointer to error structure. 2423 * 2424 * @return 2425 * 0 on success, a negative errno value otherwise and rte_errno is set. 2426 */ 2427 int 2428 mlx5_flow_validate_item_eth(const struct rte_flow_item *item, 2429 uint64_t item_flags, bool ext_vlan_sup, 2430 struct rte_flow_error *error) 2431 { 2432 const struct rte_flow_item_eth *mask = item->mask; 2433 const struct rte_flow_item_eth nic_mask = { 2434 .dst.addr_bytes = "\xff\xff\xff\xff\xff\xff", 2435 .src.addr_bytes = "\xff\xff\xff\xff\xff\xff", 2436 .type = RTE_BE16(0xffff), 2437 .has_vlan = ext_vlan_sup ? 1 : 0, 2438 }; 2439 int ret; 2440 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL); 2441 const uint64_t ethm = tunnel ? MLX5_FLOW_LAYER_INNER_L2 : 2442 MLX5_FLOW_LAYER_OUTER_L2; 2443 2444 if (item_flags & ethm) 2445 return rte_flow_error_set(error, ENOTSUP, 2446 RTE_FLOW_ERROR_TYPE_ITEM, item, 2447 "multiple L2 layers not supported"); 2448 if ((!tunnel && (item_flags & MLX5_FLOW_LAYER_OUTER_L3)) || 2449 (tunnel && (item_flags & MLX5_FLOW_LAYER_INNER_L3))) 2450 return rte_flow_error_set(error, EINVAL, 2451 RTE_FLOW_ERROR_TYPE_ITEM, item, 2452 "L2 layer should not follow " 2453 "L3 layers"); 2454 if ((!tunnel && (item_flags & MLX5_FLOW_LAYER_OUTER_VLAN)) || 2455 (tunnel && (item_flags & MLX5_FLOW_LAYER_INNER_VLAN))) 2456 return rte_flow_error_set(error, EINVAL, 2457 RTE_FLOW_ERROR_TYPE_ITEM, item, 2458 "L2 layer should not follow VLAN"); 2459 if (item_flags & MLX5_FLOW_LAYER_GTP) 2460 return rte_flow_error_set(error, EINVAL, 2461 RTE_FLOW_ERROR_TYPE_ITEM, item, 2462 "L2 layer should not follow GTP"); 2463 if (!mask) 2464 mask = &rte_flow_item_eth_mask; 2465 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask, 2466 (const uint8_t *)&nic_mask, 2467 sizeof(struct rte_flow_item_eth), 2468 MLX5_ITEM_RANGE_NOT_ACCEPTED, error); 2469 return ret; 2470 } 2471 2472 /** 2473 * Validate VLAN item. 2474 * 2475 * @param[in] item 2476 * Item specification. 2477 * @param[in] item_flags 2478 * Bit-fields that holds the items detected until now. 2479 * @param[in] dev 2480 * Ethernet device flow is being created on. 2481 * @param[out] error 2482 * Pointer to error structure. 2483 * 2484 * @return 2485 * 0 on success, a negative errno value otherwise and rte_errno is set. 2486 */ 2487 int 2488 mlx5_flow_validate_item_vlan(const struct rte_flow_item *item, 2489 uint64_t item_flags, 2490 struct rte_eth_dev *dev, 2491 struct rte_flow_error *error) 2492 { 2493 const struct rte_flow_item_vlan *spec = item->spec; 2494 const struct rte_flow_item_vlan *mask = item->mask; 2495 const struct rte_flow_item_vlan nic_mask = { 2496 .tci = RTE_BE16(UINT16_MAX), 2497 .inner_type = RTE_BE16(UINT16_MAX), 2498 }; 2499 uint16_t vlan_tag = 0; 2500 const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL); 2501 int ret; 2502 const uint64_t l34m = tunnel ? (MLX5_FLOW_LAYER_INNER_L3 | 2503 MLX5_FLOW_LAYER_INNER_L4) : 2504 (MLX5_FLOW_LAYER_OUTER_L3 | 2505 MLX5_FLOW_LAYER_OUTER_L4); 2506 const uint64_t vlanm = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN : 2507 MLX5_FLOW_LAYER_OUTER_VLAN; 2508 2509 if (item_flags & vlanm) 2510 return rte_flow_error_set(error, EINVAL, 2511 RTE_FLOW_ERROR_TYPE_ITEM, item, 2512 "multiple VLAN layers not supported"); 2513 else if ((item_flags & l34m) != 0) 2514 return rte_flow_error_set(error, EINVAL, 2515 RTE_FLOW_ERROR_TYPE_ITEM, item, 2516 "VLAN cannot follow L3/L4 layer"); 2517 if (!mask) 2518 mask = &rte_flow_item_vlan_mask; 2519 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask, 2520 (const uint8_t *)&nic_mask, 2521 sizeof(struct rte_flow_item_vlan), 2522 MLX5_ITEM_RANGE_NOT_ACCEPTED, error); 2523 if (ret) 2524 return ret; 2525 if (!tunnel && mask->tci != RTE_BE16(0x0fff)) { 2526 struct mlx5_priv *priv = dev->data->dev_private; 2527 2528 if (priv->vmwa_context) { 2529 /* 2530 * Non-NULL context means we have a virtual machine 2531 * and SR-IOV enabled, we have to create VLAN interface 2532 * to make hypervisor to setup E-Switch vport 2533 * context correctly. We avoid creating the multiple 2534 * VLAN interfaces, so we cannot support VLAN tag mask. 2535 */ 2536 return rte_flow_error_set(error, EINVAL, 2537 RTE_FLOW_ERROR_TYPE_ITEM, 2538 item, 2539 "VLAN tag mask is not" 2540 " supported in virtual" 2541 " environment"); 2542 } 2543 } 2544 if (spec) { 2545 vlan_tag = spec->tci; 2546 vlan_tag &= mask->tci; 2547 } 2548 /* 2549 * From verbs perspective an empty VLAN is equivalent 2550 * to a packet without VLAN layer. 2551 */ 2552 if (!vlan_tag) 2553 return rte_flow_error_set(error, EINVAL, 2554 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, 2555 item->spec, 2556 "VLAN cannot be empty"); 2557 return 0; 2558 } 2559 2560 /** 2561 * Validate IPV4 item. 2562 * 2563 * @param[in] item 2564 * Item specification. 2565 * @param[in] item_flags 2566 * Bit-fields that holds the items detected until now. 2567 * @param[in] last_item 2568 * Previous validated item in the pattern items. 2569 * @param[in] ether_type 2570 * Type in the ethernet layer header (including dot1q). 2571 * @param[in] acc_mask 2572 * Acceptable mask, if NULL default internal default mask 2573 * will be used to check whether item fields are supported. 2574 * @param[in] range_accepted 2575 * True if range of values is accepted for specific fields, false otherwise. 2576 * @param[out] error 2577 * Pointer to error structure. 2578 * 2579 * @return 2580 * 0 on success, a negative errno value otherwise and rte_errno is set. 2581 */ 2582 int 2583 mlx5_flow_validate_item_ipv4(const struct rte_flow_item *item, 2584 uint64_t item_flags, 2585 uint64_t last_item, 2586 uint16_t ether_type, 2587 const struct rte_flow_item_ipv4 *acc_mask, 2588 bool range_accepted, 2589 struct rte_flow_error *error) 2590 { 2591 const struct rte_flow_item_ipv4 *mask = item->mask; 2592 const struct rte_flow_item_ipv4 *spec = item->spec; 2593 const struct rte_flow_item_ipv4 nic_mask = { 2594 .hdr = { 2595 .src_addr = RTE_BE32(0xffffffff), 2596 .dst_addr = RTE_BE32(0xffffffff), 2597 .type_of_service = 0xff, 2598 .next_proto_id = 0xff, 2599 }, 2600 }; 2601 const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL); 2602 const uint64_t l3m = tunnel ? MLX5_FLOW_LAYER_INNER_L3 : 2603 MLX5_FLOW_LAYER_OUTER_L3; 2604 const uint64_t l4m = tunnel ? MLX5_FLOW_LAYER_INNER_L4 : 2605 MLX5_FLOW_LAYER_OUTER_L4; 2606 int ret; 2607 uint8_t next_proto = 0xFF; 2608 const uint64_t l2_vlan = (MLX5_FLOW_LAYER_L2 | 2609 MLX5_FLOW_LAYER_OUTER_VLAN | 2610 MLX5_FLOW_LAYER_INNER_VLAN); 2611 2612 if ((last_item & l2_vlan) && ether_type && 2613 ether_type != RTE_ETHER_TYPE_IPV4) 2614 return rte_flow_error_set(error, EINVAL, 2615 RTE_FLOW_ERROR_TYPE_ITEM, item, 2616 "IPv4 cannot follow L2/VLAN layer " 2617 "which ether type is not IPv4"); 2618 if (item_flags & MLX5_FLOW_LAYER_IPIP) { 2619 if (mask && spec) 2620 next_proto = mask->hdr.next_proto_id & 2621 spec->hdr.next_proto_id; 2622 if (next_proto == IPPROTO_IPIP || next_proto == IPPROTO_IPV6) 2623 return rte_flow_error_set(error, EINVAL, 2624 RTE_FLOW_ERROR_TYPE_ITEM, 2625 item, 2626 "multiple tunnel " 2627 "not supported"); 2628 } 2629 if (item_flags & MLX5_FLOW_LAYER_IPV6_ENCAP) 2630 return rte_flow_error_set(error, EINVAL, 2631 RTE_FLOW_ERROR_TYPE_ITEM, item, 2632 "wrong tunnel type - IPv6 specified " 2633 "but IPv4 item provided"); 2634 if (item_flags & l3m) 2635 return rte_flow_error_set(error, ENOTSUP, 2636 RTE_FLOW_ERROR_TYPE_ITEM, item, 2637 "multiple L3 layers not supported"); 2638 else if (item_flags & l4m) 2639 return rte_flow_error_set(error, EINVAL, 2640 RTE_FLOW_ERROR_TYPE_ITEM, item, 2641 "L3 cannot follow an L4 layer."); 2642 else if ((item_flags & MLX5_FLOW_LAYER_NVGRE) && 2643 !(item_flags & MLX5_FLOW_LAYER_INNER_L2)) 2644 return rte_flow_error_set(error, EINVAL, 2645 RTE_FLOW_ERROR_TYPE_ITEM, item, 2646 "L3 cannot follow an NVGRE layer."); 2647 if (!mask) 2648 mask = &rte_flow_item_ipv4_mask; 2649 else if (mask->hdr.next_proto_id != 0 && 2650 mask->hdr.next_proto_id != 0xff) 2651 return rte_flow_error_set(error, EINVAL, 2652 RTE_FLOW_ERROR_TYPE_ITEM_MASK, mask, 2653 "partial mask is not supported" 2654 " for protocol"); 2655 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask, 2656 acc_mask ? (const uint8_t *)acc_mask 2657 : (const uint8_t *)&nic_mask, 2658 sizeof(struct rte_flow_item_ipv4), 2659 range_accepted, error); 2660 if (ret < 0) 2661 return ret; 2662 return 0; 2663 } 2664 2665 /** 2666 * Validate IPV6 item. 2667 * 2668 * @param[in] item 2669 * Item specification. 2670 * @param[in] item_flags 2671 * Bit-fields that holds the items detected until now. 2672 * @param[in] last_item 2673 * Previous validated item in the pattern items. 2674 * @param[in] ether_type 2675 * Type in the ethernet layer header (including dot1q). 2676 * @param[in] acc_mask 2677 * Acceptable mask, if NULL default internal default mask 2678 * will be used to check whether item fields are supported. 2679 * @param[out] error 2680 * Pointer to error structure. 2681 * 2682 * @return 2683 * 0 on success, a negative errno value otherwise and rte_errno is set. 2684 */ 2685 int 2686 mlx5_flow_validate_item_ipv6(const struct rte_flow_item *item, 2687 uint64_t item_flags, 2688 uint64_t last_item, 2689 uint16_t ether_type, 2690 const struct rte_flow_item_ipv6 *acc_mask, 2691 struct rte_flow_error *error) 2692 { 2693 const struct rte_flow_item_ipv6 *mask = item->mask; 2694 const struct rte_flow_item_ipv6 *spec = item->spec; 2695 const struct rte_flow_item_ipv6 nic_mask = { 2696 .hdr = { 2697 .src_addr = 2698 "\xff\xff\xff\xff\xff\xff\xff\xff" 2699 "\xff\xff\xff\xff\xff\xff\xff\xff", 2700 .dst_addr = 2701 "\xff\xff\xff\xff\xff\xff\xff\xff" 2702 "\xff\xff\xff\xff\xff\xff\xff\xff", 2703 .vtc_flow = RTE_BE32(0xffffffff), 2704 .proto = 0xff, 2705 }, 2706 }; 2707 const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL); 2708 const uint64_t l3m = tunnel ? MLX5_FLOW_LAYER_INNER_L3 : 2709 MLX5_FLOW_LAYER_OUTER_L3; 2710 const uint64_t l4m = tunnel ? MLX5_FLOW_LAYER_INNER_L4 : 2711 MLX5_FLOW_LAYER_OUTER_L4; 2712 int ret; 2713 uint8_t next_proto = 0xFF; 2714 const uint64_t l2_vlan = (MLX5_FLOW_LAYER_L2 | 2715 MLX5_FLOW_LAYER_OUTER_VLAN | 2716 MLX5_FLOW_LAYER_INNER_VLAN); 2717 2718 if ((last_item & l2_vlan) && ether_type && 2719 ether_type != RTE_ETHER_TYPE_IPV6) 2720 return rte_flow_error_set(error, EINVAL, 2721 RTE_FLOW_ERROR_TYPE_ITEM, item, 2722 "IPv6 cannot follow L2/VLAN layer " 2723 "which ether type is not IPv6"); 2724 if (mask && mask->hdr.proto == UINT8_MAX && spec) 2725 next_proto = spec->hdr.proto; 2726 if (item_flags & MLX5_FLOW_LAYER_IPIP) { 2727 if (next_proto == IPPROTO_IPIP || next_proto == IPPROTO_IPV6) 2728 return rte_flow_error_set(error, EINVAL, 2729 RTE_FLOW_ERROR_TYPE_ITEM, 2730 item, 2731 "multiple tunnel " 2732 "not supported"); 2733 } 2734 if (next_proto == IPPROTO_HOPOPTS || 2735 next_proto == IPPROTO_ROUTING || 2736 next_proto == IPPROTO_FRAGMENT || 2737 next_proto == IPPROTO_ESP || 2738 next_proto == IPPROTO_AH || 2739 next_proto == IPPROTO_DSTOPTS) 2740 return rte_flow_error_set(error, EINVAL, 2741 RTE_FLOW_ERROR_TYPE_ITEM, item, 2742 "IPv6 proto (next header) should " 2743 "not be set as extension header"); 2744 if (item_flags & MLX5_FLOW_LAYER_IPIP) 2745 return rte_flow_error_set(error, EINVAL, 2746 RTE_FLOW_ERROR_TYPE_ITEM, item, 2747 "wrong tunnel type - IPv4 specified " 2748 "but IPv6 item provided"); 2749 if (item_flags & l3m) 2750 return rte_flow_error_set(error, ENOTSUP, 2751 RTE_FLOW_ERROR_TYPE_ITEM, item, 2752 "multiple L3 layers not supported"); 2753 else if (item_flags & l4m) 2754 return rte_flow_error_set(error, EINVAL, 2755 RTE_FLOW_ERROR_TYPE_ITEM, item, 2756 "L3 cannot follow an L4 layer."); 2757 else if ((item_flags & MLX5_FLOW_LAYER_NVGRE) && 2758 !(item_flags & MLX5_FLOW_LAYER_INNER_L2)) 2759 return rte_flow_error_set(error, EINVAL, 2760 RTE_FLOW_ERROR_TYPE_ITEM, item, 2761 "L3 cannot follow an NVGRE layer."); 2762 if (!mask) 2763 mask = &rte_flow_item_ipv6_mask; 2764 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask, 2765 acc_mask ? (const uint8_t *)acc_mask 2766 : (const uint8_t *)&nic_mask, 2767 sizeof(struct rte_flow_item_ipv6), 2768 MLX5_ITEM_RANGE_NOT_ACCEPTED, error); 2769 if (ret < 0) 2770 return ret; 2771 return 0; 2772 } 2773 2774 /** 2775 * Validate UDP item. 2776 * 2777 * @param[in] item 2778 * Item specification. 2779 * @param[in] item_flags 2780 * Bit-fields that holds the items detected until now. 2781 * @param[in] target_protocol 2782 * The next protocol in the previous item. 2783 * @param[in] flow_mask 2784 * mlx5 flow-specific (DV, verbs, etc.) supported header fields mask. 2785 * @param[out] error 2786 * Pointer to error structure. 2787 * 2788 * @return 2789 * 0 on success, a negative errno value otherwise and rte_errno is set. 2790 */ 2791 int 2792 mlx5_flow_validate_item_udp(const struct rte_flow_item *item, 2793 uint64_t item_flags, 2794 uint8_t target_protocol, 2795 struct rte_flow_error *error) 2796 { 2797 const struct rte_flow_item_udp *mask = item->mask; 2798 const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL); 2799 const uint64_t l3m = tunnel ? MLX5_FLOW_LAYER_INNER_L3 : 2800 MLX5_FLOW_LAYER_OUTER_L3; 2801 const uint64_t l4m = tunnel ? MLX5_FLOW_LAYER_INNER_L4 : 2802 MLX5_FLOW_LAYER_OUTER_L4; 2803 int ret; 2804 2805 if (target_protocol != 0xff && target_protocol != IPPROTO_UDP) 2806 return rte_flow_error_set(error, EINVAL, 2807 RTE_FLOW_ERROR_TYPE_ITEM, item, 2808 "protocol filtering not compatible" 2809 " with UDP layer"); 2810 if (!(item_flags & l3m)) 2811 return rte_flow_error_set(error, EINVAL, 2812 RTE_FLOW_ERROR_TYPE_ITEM, item, 2813 "L3 is mandatory to filter on L4"); 2814 if (item_flags & l4m) 2815 return rte_flow_error_set(error, EINVAL, 2816 RTE_FLOW_ERROR_TYPE_ITEM, item, 2817 "multiple L4 layers not supported"); 2818 if (!mask) 2819 mask = &rte_flow_item_udp_mask; 2820 ret = mlx5_flow_item_acceptable 2821 (item, (const uint8_t *)mask, 2822 (const uint8_t *)&rte_flow_item_udp_mask, 2823 sizeof(struct rte_flow_item_udp), MLX5_ITEM_RANGE_NOT_ACCEPTED, 2824 error); 2825 if (ret < 0) 2826 return ret; 2827 return 0; 2828 } 2829 2830 /** 2831 * Validate TCP item. 2832 * 2833 * @param[in] item 2834 * Item specification. 2835 * @param[in] item_flags 2836 * Bit-fields that holds the items detected until now. 2837 * @param[in] target_protocol 2838 * The next protocol in the previous item. 2839 * @param[out] error 2840 * Pointer to error structure. 2841 * 2842 * @return 2843 * 0 on success, a negative errno value otherwise and rte_errno is set. 2844 */ 2845 int 2846 mlx5_flow_validate_item_tcp(const struct rte_flow_item *item, 2847 uint64_t item_flags, 2848 uint8_t target_protocol, 2849 const struct rte_flow_item_tcp *flow_mask, 2850 struct rte_flow_error *error) 2851 { 2852 const struct rte_flow_item_tcp *mask = item->mask; 2853 const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL); 2854 const uint64_t l3m = tunnel ? MLX5_FLOW_LAYER_INNER_L3 : 2855 MLX5_FLOW_LAYER_OUTER_L3; 2856 const uint64_t l4m = tunnel ? MLX5_FLOW_LAYER_INNER_L4 : 2857 MLX5_FLOW_LAYER_OUTER_L4; 2858 int ret; 2859 2860 MLX5_ASSERT(flow_mask); 2861 if (target_protocol != 0xff && target_protocol != IPPROTO_TCP) 2862 return rte_flow_error_set(error, EINVAL, 2863 RTE_FLOW_ERROR_TYPE_ITEM, item, 2864 "protocol filtering not compatible" 2865 " with TCP layer"); 2866 if (!(item_flags & l3m)) 2867 return rte_flow_error_set(error, EINVAL, 2868 RTE_FLOW_ERROR_TYPE_ITEM, item, 2869 "L3 is mandatory to filter on L4"); 2870 if (item_flags & l4m) 2871 return rte_flow_error_set(error, EINVAL, 2872 RTE_FLOW_ERROR_TYPE_ITEM, item, 2873 "multiple L4 layers not supported"); 2874 if (!mask) 2875 mask = &rte_flow_item_tcp_mask; 2876 ret = mlx5_flow_item_acceptable 2877 (item, (const uint8_t *)mask, 2878 (const uint8_t *)flow_mask, 2879 sizeof(struct rte_flow_item_tcp), MLX5_ITEM_RANGE_NOT_ACCEPTED, 2880 error); 2881 if (ret < 0) 2882 return ret; 2883 return 0; 2884 } 2885 2886 /** 2887 * Validate VXLAN item. 2888 * 2889 * @param[in] dev 2890 * Pointer to the Ethernet device structure. 2891 * @param[in] udp_dport 2892 * UDP destination port 2893 * @param[in] item 2894 * Item specification. 2895 * @param[in] item_flags 2896 * Bit-fields that holds the items detected until now. 2897 * @param root 2898 * Whether action is on root table. 2899 * @param[out] error 2900 * Pointer to error structure. 2901 * 2902 * @return 2903 * 0 on success, a negative errno value otherwise and rte_errno is set. 2904 */ 2905 int 2906 mlx5_flow_validate_item_vxlan(struct rte_eth_dev *dev, 2907 uint16_t udp_dport, 2908 const struct rte_flow_item *item, 2909 uint64_t item_flags, 2910 bool root, 2911 struct rte_flow_error *error) 2912 { 2913 const struct rte_flow_item_vxlan *spec = item->spec; 2914 const struct rte_flow_item_vxlan *mask = item->mask; 2915 int ret; 2916 struct mlx5_priv *priv = dev->data->dev_private; 2917 union vni { 2918 uint32_t vlan_id; 2919 uint8_t vni[4]; 2920 } id = { .vlan_id = 0, }; 2921 const struct rte_flow_item_vxlan nic_mask = { 2922 .vni = "\xff\xff\xff", 2923 .rsvd1 = 0xff, 2924 }; 2925 const struct rte_flow_item_vxlan *valid_mask; 2926 2927 if (item_flags & MLX5_FLOW_LAYER_TUNNEL) 2928 return rte_flow_error_set(error, ENOTSUP, 2929 RTE_FLOW_ERROR_TYPE_ITEM, item, 2930 "multiple tunnel layers not" 2931 " supported"); 2932 valid_mask = &rte_flow_item_vxlan_mask; 2933 /* 2934 * Verify only UDPv4 is present as defined in 2935 * https://tools.ietf.org/html/rfc7348 2936 */ 2937 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_UDP)) 2938 return rte_flow_error_set(error, EINVAL, 2939 RTE_FLOW_ERROR_TYPE_ITEM, item, 2940 "no outer UDP layer found"); 2941 if (!mask) 2942 mask = &rte_flow_item_vxlan_mask; 2943 2944 if (priv->sh->steering_format_version != 2945 MLX5_STEERING_LOGIC_FORMAT_CONNECTX_5 || 2946 !udp_dport || udp_dport == MLX5_UDP_PORT_VXLAN) { 2947 /* non-root table */ 2948 if (!root && priv->sh->misc5_cap) 2949 valid_mask = &nic_mask; 2950 /* Group zero in NIC domain */ 2951 if (!root && priv->sh->tunnel_header_0_1) 2952 valid_mask = &nic_mask; 2953 } 2954 ret = mlx5_flow_item_acceptable 2955 (item, (const uint8_t *)mask, 2956 (const uint8_t *)valid_mask, 2957 sizeof(struct rte_flow_item_vxlan), 2958 MLX5_ITEM_RANGE_NOT_ACCEPTED, error); 2959 if (ret < 0) 2960 return ret; 2961 if (spec) { 2962 memcpy(&id.vni[1], spec->vni, 3); 2963 memcpy(&id.vni[1], mask->vni, 3); 2964 } 2965 if (!(item_flags & MLX5_FLOW_LAYER_OUTER)) 2966 return rte_flow_error_set(error, ENOTSUP, 2967 RTE_FLOW_ERROR_TYPE_ITEM, item, 2968 "VXLAN tunnel must be fully defined"); 2969 return 0; 2970 } 2971 2972 /** 2973 * Validate VXLAN_GPE item. 2974 * 2975 * @param[in] item 2976 * Item specification. 2977 * @param[in] item_flags 2978 * Bit-fields that holds the items detected until now. 2979 * @param[in] priv 2980 * Pointer to the private data structure. 2981 * @param[in] target_protocol 2982 * The next protocol in the previous item. 2983 * @param[out] error 2984 * Pointer to error structure. 2985 * 2986 * @return 2987 * 0 on success, a negative errno value otherwise and rte_errno is set. 2988 */ 2989 int 2990 mlx5_flow_validate_item_vxlan_gpe(const struct rte_flow_item *item, 2991 uint64_t item_flags, 2992 struct rte_eth_dev *dev, 2993 struct rte_flow_error *error) 2994 { 2995 struct mlx5_priv *priv = dev->data->dev_private; 2996 const struct rte_flow_item_vxlan_gpe *spec = item->spec; 2997 const struct rte_flow_item_vxlan_gpe *mask = item->mask; 2998 int ret; 2999 union vni { 3000 uint32_t vlan_id; 3001 uint8_t vni[4]; 3002 } id = { .vlan_id = 0, }; 3003 3004 if (!priv->sh->config.l3_vxlan_en) 3005 return rte_flow_error_set(error, ENOTSUP, 3006 RTE_FLOW_ERROR_TYPE_ITEM, item, 3007 "L3 VXLAN is not enabled by device" 3008 " parameter and/or not configured in" 3009 " firmware"); 3010 if (item_flags & MLX5_FLOW_LAYER_TUNNEL) 3011 return rte_flow_error_set(error, ENOTSUP, 3012 RTE_FLOW_ERROR_TYPE_ITEM, item, 3013 "multiple tunnel layers not" 3014 " supported"); 3015 /* 3016 * Verify only UDPv4 is present as defined in 3017 * https://tools.ietf.org/html/rfc7348 3018 */ 3019 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_UDP)) 3020 return rte_flow_error_set(error, EINVAL, 3021 RTE_FLOW_ERROR_TYPE_ITEM, item, 3022 "no outer UDP layer found"); 3023 if (!mask) 3024 mask = &rte_flow_item_vxlan_gpe_mask; 3025 ret = mlx5_flow_item_acceptable 3026 (item, (const uint8_t *)mask, 3027 (const uint8_t *)&rte_flow_item_vxlan_gpe_mask, 3028 sizeof(struct rte_flow_item_vxlan_gpe), 3029 MLX5_ITEM_RANGE_NOT_ACCEPTED, error); 3030 if (ret < 0) 3031 return ret; 3032 if (spec) { 3033 if (spec->protocol) 3034 return rte_flow_error_set(error, ENOTSUP, 3035 RTE_FLOW_ERROR_TYPE_ITEM, 3036 item, 3037 "VxLAN-GPE protocol" 3038 " not supported"); 3039 memcpy(&id.vni[1], spec->vni, 3); 3040 memcpy(&id.vni[1], mask->vni, 3); 3041 } 3042 if (!(item_flags & MLX5_FLOW_LAYER_OUTER)) 3043 return rte_flow_error_set(error, ENOTSUP, 3044 RTE_FLOW_ERROR_TYPE_ITEM, item, 3045 "VXLAN-GPE tunnel must be fully" 3046 " defined"); 3047 return 0; 3048 } 3049 /** 3050 * Validate GRE Key item. 3051 * 3052 * @param[in] item 3053 * Item specification. 3054 * @param[in] item_flags 3055 * Bit flags to mark detected items. 3056 * @param[in] gre_item 3057 * Pointer to gre_item 3058 * @param[out] error 3059 * Pointer to error structure. 3060 * 3061 * @return 3062 * 0 on success, a negative errno value otherwise and rte_errno is set. 3063 */ 3064 int 3065 mlx5_flow_validate_item_gre_key(const struct rte_flow_item *item, 3066 uint64_t item_flags, 3067 const struct rte_flow_item *gre_item, 3068 struct rte_flow_error *error) 3069 { 3070 const rte_be32_t *mask = item->mask; 3071 int ret = 0; 3072 rte_be32_t gre_key_default_mask = RTE_BE32(UINT32_MAX); 3073 const struct rte_flow_item_gre *gre_spec; 3074 const struct rte_flow_item_gre *gre_mask; 3075 3076 if (item_flags & MLX5_FLOW_LAYER_GRE_KEY) 3077 return rte_flow_error_set(error, ENOTSUP, 3078 RTE_FLOW_ERROR_TYPE_ITEM, item, 3079 "Multiple GRE key not support"); 3080 if (!(item_flags & MLX5_FLOW_LAYER_GRE)) 3081 return rte_flow_error_set(error, ENOTSUP, 3082 RTE_FLOW_ERROR_TYPE_ITEM, item, 3083 "No preceding GRE header"); 3084 if (item_flags & MLX5_FLOW_LAYER_INNER) 3085 return rte_flow_error_set(error, ENOTSUP, 3086 RTE_FLOW_ERROR_TYPE_ITEM, item, 3087 "GRE key following a wrong item"); 3088 gre_mask = gre_item->mask; 3089 if (!gre_mask) 3090 gre_mask = &rte_flow_item_gre_mask; 3091 gre_spec = gre_item->spec; 3092 if (gre_spec && (gre_mask->c_rsvd0_ver & RTE_BE16(0x2000)) && 3093 !(gre_spec->c_rsvd0_ver & RTE_BE16(0x2000))) 3094 return rte_flow_error_set(error, EINVAL, 3095 RTE_FLOW_ERROR_TYPE_ITEM, item, 3096 "Key bit must be on"); 3097 3098 if (!mask) 3099 mask = &gre_key_default_mask; 3100 ret = mlx5_flow_item_acceptable 3101 (item, (const uint8_t *)mask, 3102 (const uint8_t *)&gre_key_default_mask, 3103 sizeof(rte_be32_t), MLX5_ITEM_RANGE_NOT_ACCEPTED, error); 3104 return ret; 3105 } 3106 3107 /** 3108 * Validate GRE optional item. 3109 * 3110 * @param[in] dev 3111 * Pointer to the Ethernet device structure. 3112 * @param[in] item 3113 * Item specification. 3114 * @param[in] item_flags 3115 * Bit flags to mark detected items. 3116 * @param[in] attr 3117 * Flow rule attributes. 3118 * @param[in] gre_item 3119 * Pointer to gre_item 3120 * @param[out] error 3121 * Pointer to error structure. 3122 * 3123 * @return 3124 * 0 on success, a negative errno value otherwise and rte_errno is set. 3125 */ 3126 int 3127 mlx5_flow_validate_item_gre_option(struct rte_eth_dev *dev, 3128 const struct rte_flow_item *item, 3129 uint64_t item_flags, 3130 const struct rte_flow_attr *attr, 3131 const struct rte_flow_item *gre_item, 3132 struct rte_flow_error *error) 3133 { 3134 const struct rte_flow_item_gre *gre_spec = gre_item->spec; 3135 const struct rte_flow_item_gre *gre_mask = gre_item->mask; 3136 const struct rte_flow_item_gre_opt *spec = item->spec; 3137 const struct rte_flow_item_gre_opt *mask = item->mask; 3138 struct mlx5_priv *priv = dev->data->dev_private; 3139 int ret = 0; 3140 struct rte_flow_item_gre_opt nic_mask = { 3141 .checksum_rsvd = { 3142 .checksum = RTE_BE16(UINT16_MAX), 3143 .reserved1 = 0x0, 3144 }, 3145 .key = { 3146 .key = RTE_BE32(UINT32_MAX), 3147 }, 3148 .sequence = { 3149 .sequence = RTE_BE32(UINT32_MAX), 3150 }, 3151 }; 3152 3153 if (!(item_flags & MLX5_FLOW_LAYER_GRE)) 3154 return rte_flow_error_set(error, ENOTSUP, 3155 RTE_FLOW_ERROR_TYPE_ITEM, item, 3156 "No preceding GRE header"); 3157 if (item_flags & MLX5_FLOW_LAYER_INNER) 3158 return rte_flow_error_set(error, ENOTSUP, 3159 RTE_FLOW_ERROR_TYPE_ITEM, item, 3160 "GRE option following a wrong item"); 3161 if (!spec || !mask) 3162 return rte_flow_error_set(error, EINVAL, 3163 RTE_FLOW_ERROR_TYPE_ITEM, item, 3164 "At least one field gre_option(checksum/key/sequence) must be specified"); 3165 if (!gre_mask) 3166 gre_mask = &rte_flow_item_gre_mask; 3167 if (mask->checksum_rsvd.checksum) 3168 if (gre_spec && (gre_mask->c_rsvd0_ver & RTE_BE16(0x8000)) && 3169 !(gre_spec->c_rsvd0_ver & RTE_BE16(0x8000))) 3170 return rte_flow_error_set(error, EINVAL, 3171 RTE_FLOW_ERROR_TYPE_ITEM, 3172 item, 3173 "Checksum bit must be on"); 3174 if (mask->key.key) 3175 if (gre_spec && (gre_mask->c_rsvd0_ver & RTE_BE16(0x2000)) && 3176 !(gre_spec->c_rsvd0_ver & RTE_BE16(0x2000))) 3177 return rte_flow_error_set(error, EINVAL, 3178 RTE_FLOW_ERROR_TYPE_ITEM, 3179 item, "Key bit must be on"); 3180 if (mask->sequence.sequence) 3181 if (gre_spec && (gre_mask->c_rsvd0_ver & RTE_BE16(0x1000)) && 3182 !(gre_spec->c_rsvd0_ver & RTE_BE16(0x1000))) 3183 return rte_flow_error_set(error, EINVAL, 3184 RTE_FLOW_ERROR_TYPE_ITEM, 3185 item, 3186 "Sequence bit must be on"); 3187 if (mask->checksum_rsvd.checksum || mask->sequence.sequence) { 3188 if (priv->sh->steering_format_version == 3189 MLX5_STEERING_LOGIC_FORMAT_CONNECTX_5 || 3190 ((attr->group || (attr->transfer && priv->fdb_def_rule)) && 3191 !priv->sh->misc5_cap) || 3192 (!(priv->sh->tunnel_header_0_1 && 3193 priv->sh->tunnel_header_2_3) && 3194 !attr->group && (!attr->transfer || !priv->fdb_def_rule))) 3195 return rte_flow_error_set(error, EINVAL, 3196 RTE_FLOW_ERROR_TYPE_ITEM, 3197 item, 3198 "Checksum/Sequence not supported"); 3199 } 3200 ret = mlx5_flow_item_acceptable 3201 (item, (const uint8_t *)mask, 3202 (const uint8_t *)&nic_mask, 3203 sizeof(struct rte_flow_item_gre_opt), 3204 MLX5_ITEM_RANGE_NOT_ACCEPTED, error); 3205 return ret; 3206 } 3207 3208 /** 3209 * Validate GRE item. 3210 * 3211 * @param[in] item 3212 * Item specification. 3213 * @param[in] item_flags 3214 * Bit flags to mark detected items. 3215 * @param[in] target_protocol 3216 * The next protocol in the previous item. 3217 * @param[out] error 3218 * Pointer to error structure. 3219 * 3220 * @return 3221 * 0 on success, a negative errno value otherwise and rte_errno is set. 3222 */ 3223 int 3224 mlx5_flow_validate_item_gre(const struct rte_flow_item *item, 3225 uint64_t item_flags, 3226 uint8_t target_protocol, 3227 struct rte_flow_error *error) 3228 { 3229 const struct rte_flow_item_gre *spec __rte_unused = item->spec; 3230 const struct rte_flow_item_gre *mask = item->mask; 3231 int ret; 3232 const struct rte_flow_item_gre nic_mask = { 3233 .c_rsvd0_ver = RTE_BE16(0xB000), 3234 .protocol = RTE_BE16(UINT16_MAX), 3235 }; 3236 3237 if (target_protocol != 0xff && target_protocol != IPPROTO_GRE) 3238 return rte_flow_error_set(error, EINVAL, 3239 RTE_FLOW_ERROR_TYPE_ITEM, item, 3240 "protocol filtering not compatible" 3241 " with this GRE layer"); 3242 if (item_flags & MLX5_FLOW_LAYER_TUNNEL) 3243 return rte_flow_error_set(error, ENOTSUP, 3244 RTE_FLOW_ERROR_TYPE_ITEM, item, 3245 "multiple tunnel layers not" 3246 " supported"); 3247 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L3)) 3248 return rte_flow_error_set(error, ENOTSUP, 3249 RTE_FLOW_ERROR_TYPE_ITEM, item, 3250 "L3 Layer is missing"); 3251 if (!mask) 3252 mask = &rte_flow_item_gre_mask; 3253 ret = mlx5_flow_item_acceptable 3254 (item, (const uint8_t *)mask, 3255 (const uint8_t *)&nic_mask, 3256 sizeof(struct rte_flow_item_gre), MLX5_ITEM_RANGE_NOT_ACCEPTED, 3257 error); 3258 if (ret < 0) 3259 return ret; 3260 #ifndef HAVE_MLX5DV_DR 3261 #ifndef HAVE_IBV_DEVICE_MPLS_SUPPORT 3262 if (spec && (spec->protocol & mask->protocol)) 3263 return rte_flow_error_set(error, ENOTSUP, 3264 RTE_FLOW_ERROR_TYPE_ITEM, item, 3265 "without MPLS support the" 3266 " specification cannot be used for" 3267 " filtering"); 3268 #endif 3269 #endif 3270 return 0; 3271 } 3272 3273 /** 3274 * Validate Geneve item. 3275 * 3276 * @param[in] item 3277 * Item specification. 3278 * @param[in] itemFlags 3279 * Bit-fields that holds the items detected until now. 3280 * @param[in] enPriv 3281 * Pointer to the private data structure. 3282 * @param[out] error 3283 * Pointer to error structure. 3284 * 3285 * @return 3286 * 0 on success, a negative errno value otherwise and rte_errno is set. 3287 */ 3288 3289 int 3290 mlx5_flow_validate_item_geneve(const struct rte_flow_item *item, 3291 uint64_t item_flags, 3292 struct rte_eth_dev *dev, 3293 struct rte_flow_error *error) 3294 { 3295 struct mlx5_priv *priv = dev->data->dev_private; 3296 const struct rte_flow_item_geneve *spec = item->spec; 3297 const struct rte_flow_item_geneve *mask = item->mask; 3298 int ret; 3299 uint16_t gbhdr; 3300 uint8_t opt_len = priv->sh->cdev->config.hca_attr.geneve_max_opt_len ? 3301 MLX5_GENEVE_OPT_LEN_1 : MLX5_GENEVE_OPT_LEN_0; 3302 const struct rte_flow_item_geneve nic_mask = { 3303 .ver_opt_len_o_c_rsvd0 = RTE_BE16(0x3f80), 3304 .vni = "\xff\xff\xff", 3305 .protocol = RTE_BE16(UINT16_MAX), 3306 }; 3307 3308 if (!priv->sh->cdev->config.hca_attr.tunnel_stateless_geneve_rx) 3309 return rte_flow_error_set(error, ENOTSUP, 3310 RTE_FLOW_ERROR_TYPE_ITEM, item, 3311 "L3 Geneve is not enabled by device" 3312 " parameter and/or not configured in" 3313 " firmware"); 3314 if (item_flags & MLX5_FLOW_LAYER_TUNNEL) 3315 return rte_flow_error_set(error, ENOTSUP, 3316 RTE_FLOW_ERROR_TYPE_ITEM, item, 3317 "multiple tunnel layers not" 3318 " supported"); 3319 /* 3320 * Verify only UDPv4 is present as defined in 3321 * https://tools.ietf.org/html/rfc7348 3322 */ 3323 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_UDP)) 3324 return rte_flow_error_set(error, EINVAL, 3325 RTE_FLOW_ERROR_TYPE_ITEM, item, 3326 "no outer UDP layer found"); 3327 if (!mask) 3328 mask = &rte_flow_item_geneve_mask; 3329 ret = mlx5_flow_item_acceptable 3330 (item, (const uint8_t *)mask, 3331 (const uint8_t *)&nic_mask, 3332 sizeof(struct rte_flow_item_geneve), 3333 MLX5_ITEM_RANGE_NOT_ACCEPTED, error); 3334 if (ret) 3335 return ret; 3336 if (spec) { 3337 gbhdr = rte_be_to_cpu_16(spec->ver_opt_len_o_c_rsvd0); 3338 if (MLX5_GENEVE_VER_VAL(gbhdr) || 3339 MLX5_GENEVE_CRITO_VAL(gbhdr) || 3340 MLX5_GENEVE_RSVD_VAL(gbhdr) || spec->rsvd1) 3341 return rte_flow_error_set(error, ENOTSUP, 3342 RTE_FLOW_ERROR_TYPE_ITEM, 3343 item, 3344 "Geneve protocol unsupported" 3345 " fields are being used"); 3346 if (MLX5_GENEVE_OPTLEN_VAL(gbhdr) > opt_len) 3347 return rte_flow_error_set 3348 (error, ENOTSUP, 3349 RTE_FLOW_ERROR_TYPE_ITEM, 3350 item, 3351 "Unsupported Geneve options length"); 3352 } 3353 if (!(item_flags & MLX5_FLOW_LAYER_OUTER)) 3354 return rte_flow_error_set 3355 (error, ENOTSUP, 3356 RTE_FLOW_ERROR_TYPE_ITEM, item, 3357 "Geneve tunnel must be fully defined"); 3358 return 0; 3359 } 3360 3361 /** 3362 * Validate Geneve TLV option item. 3363 * 3364 * @param[in] item 3365 * Item specification. 3366 * @param[in] last_item 3367 * Previous validated item in the pattern items. 3368 * @param[in] geneve_item 3369 * Previous GENEVE item specification. 3370 * @param[in] dev 3371 * Pointer to the rte_eth_dev structure. 3372 * @param[out] error 3373 * Pointer to error structure. 3374 * 3375 * @return 3376 * 0 on success, a negative errno value otherwise and rte_errno is set. 3377 */ 3378 int 3379 mlx5_flow_validate_item_geneve_opt(const struct rte_flow_item *item, 3380 uint64_t last_item, 3381 const struct rte_flow_item *geneve_item, 3382 struct rte_eth_dev *dev, 3383 struct rte_flow_error *error) 3384 { 3385 struct mlx5_priv *priv = dev->data->dev_private; 3386 struct mlx5_dev_ctx_shared *sh = priv->sh; 3387 struct mlx5_geneve_tlv_option_resource *geneve_opt_resource; 3388 struct mlx5_hca_attr *hca_attr = &sh->cdev->config.hca_attr; 3389 uint8_t data_max_supported = 3390 hca_attr->max_geneve_tlv_option_data_len * 4; 3391 const struct rte_flow_item_geneve *geneve_spec; 3392 const struct rte_flow_item_geneve *geneve_mask; 3393 const struct rte_flow_item_geneve_opt *spec = item->spec; 3394 const struct rte_flow_item_geneve_opt *mask = item->mask; 3395 unsigned int i; 3396 unsigned int data_len; 3397 uint8_t tlv_option_len; 3398 uint16_t optlen_m, optlen_v; 3399 const struct rte_flow_item_geneve_opt full_mask = { 3400 .option_class = RTE_BE16(0xffff), 3401 .option_type = 0xff, 3402 .option_len = 0x1f, 3403 }; 3404 3405 if (!mask) 3406 mask = &rte_flow_item_geneve_opt_mask; 3407 if (!spec) 3408 return rte_flow_error_set 3409 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item, 3410 "Geneve TLV opt class/type/length must be specified"); 3411 if ((uint32_t)spec->option_len > MLX5_GENEVE_OPTLEN_MASK) 3412 return rte_flow_error_set 3413 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item, 3414 "Geneve TLV opt length exceeds the limit (31)"); 3415 /* Check if class type and length masks are full. */ 3416 if (full_mask.option_class != mask->option_class || 3417 full_mask.option_type != mask->option_type || 3418 full_mask.option_len != (mask->option_len & full_mask.option_len)) 3419 return rte_flow_error_set 3420 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item, 3421 "Geneve TLV opt class/type/length masks must be full"); 3422 /* Check if length is supported */ 3423 if ((uint32_t)spec->option_len > 3424 hca_attr->max_geneve_tlv_option_data_len) 3425 return rte_flow_error_set 3426 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item, 3427 "Geneve TLV opt length not supported"); 3428 if (hca_attr->max_geneve_tlv_options > 1) 3429 DRV_LOG(DEBUG, 3430 "max_geneve_tlv_options supports more than 1 option"); 3431 /* Check GENEVE item preceding. */ 3432 if (!geneve_item || !(last_item & MLX5_FLOW_LAYER_GENEVE)) 3433 return rte_flow_error_set 3434 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item, 3435 "Geneve opt item must be preceded with Geneve item"); 3436 geneve_spec = geneve_item->spec; 3437 geneve_mask = geneve_item->mask ? geneve_item->mask : 3438 &rte_flow_item_geneve_mask; 3439 /* Check if GENEVE TLV option size doesn't exceed option length */ 3440 if (geneve_spec && (geneve_mask->ver_opt_len_o_c_rsvd0 || 3441 geneve_spec->ver_opt_len_o_c_rsvd0)) { 3442 tlv_option_len = spec->option_len & mask->option_len; 3443 optlen_v = rte_be_to_cpu_16(geneve_spec->ver_opt_len_o_c_rsvd0); 3444 optlen_v = MLX5_GENEVE_OPTLEN_VAL(optlen_v); 3445 optlen_m = rte_be_to_cpu_16(geneve_mask->ver_opt_len_o_c_rsvd0); 3446 optlen_m = MLX5_GENEVE_OPTLEN_VAL(optlen_m); 3447 if ((optlen_v & optlen_m) <= tlv_option_len) 3448 return rte_flow_error_set 3449 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item, 3450 "GENEVE TLV option length exceeds optlen"); 3451 } 3452 /* Check if length is 0 or data is 0. */ 3453 if (spec->data == NULL || spec->option_len == 0) 3454 return rte_flow_error_set 3455 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item, 3456 "Geneve TLV opt with zero data/length not supported"); 3457 /* Check not all data & mask are 0. */ 3458 data_len = spec->option_len * 4; 3459 if (mask->data == NULL) { 3460 for (i = 0; i < data_len; i++) 3461 if (spec->data[i]) 3462 break; 3463 if (i == data_len) 3464 return rte_flow_error_set(error, ENOTSUP, 3465 RTE_FLOW_ERROR_TYPE_ITEM, item, 3466 "Can't match on Geneve option data 0"); 3467 } else { 3468 for (i = 0; i < data_len; i++) 3469 if (spec->data[i] & mask->data[i]) 3470 break; 3471 if (i == data_len) 3472 return rte_flow_error_set(error, ENOTSUP, 3473 RTE_FLOW_ERROR_TYPE_ITEM, item, 3474 "Can't match on Geneve option data and mask 0"); 3475 /* Check data mask supported. */ 3476 for (i = data_max_supported; i < data_len ; i++) 3477 if (mask->data[i]) 3478 return rte_flow_error_set(error, ENOTSUP, 3479 RTE_FLOW_ERROR_TYPE_ITEM, item, 3480 "Data mask is of unsupported size"); 3481 } 3482 /* Check GENEVE option is supported in NIC. */ 3483 if (!hca_attr->geneve_tlv_opt) 3484 return rte_flow_error_set 3485 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item, 3486 "Geneve TLV opt not supported"); 3487 /* Check if we already have geneve option with different type/class. */ 3488 rte_spinlock_lock(&sh->geneve_tlv_opt_sl); 3489 geneve_opt_resource = sh->geneve_tlv_option_resource; 3490 if (geneve_opt_resource != NULL) 3491 if (geneve_opt_resource->option_class != spec->option_class || 3492 geneve_opt_resource->option_type != spec->option_type || 3493 geneve_opt_resource->length != spec->option_len) { 3494 rte_spinlock_unlock(&sh->geneve_tlv_opt_sl); 3495 return rte_flow_error_set(error, ENOTSUP, 3496 RTE_FLOW_ERROR_TYPE_ITEM, item, 3497 "Only one Geneve TLV option supported"); 3498 } 3499 rte_spinlock_unlock(&sh->geneve_tlv_opt_sl); 3500 return 0; 3501 } 3502 3503 /** 3504 * Validate MPLS item. 3505 * 3506 * @param[in] dev 3507 * Pointer to the rte_eth_dev structure. 3508 * @param[in] item 3509 * Item specification. 3510 * @param[in] item_flags 3511 * Bit-fields that holds the items detected until now. 3512 * @param[in] prev_layer 3513 * The protocol layer indicated in previous item. 3514 * @param[out] error 3515 * Pointer to error structure. 3516 * 3517 * @return 3518 * 0 on success, a negative errno value otherwise and rte_errno is set. 3519 */ 3520 int 3521 mlx5_flow_validate_item_mpls(struct rte_eth_dev *dev __rte_unused, 3522 const struct rte_flow_item *item __rte_unused, 3523 uint64_t item_flags __rte_unused, 3524 uint64_t prev_layer __rte_unused, 3525 struct rte_flow_error *error) 3526 { 3527 #ifdef HAVE_IBV_DEVICE_MPLS_SUPPORT 3528 const struct rte_flow_item_mpls *mask = item->mask; 3529 struct mlx5_priv *priv = dev->data->dev_private; 3530 int ret; 3531 3532 if (!priv->sh->dev_cap.mpls_en) 3533 return rte_flow_error_set(error, ENOTSUP, 3534 RTE_FLOW_ERROR_TYPE_ITEM, item, 3535 "MPLS not supported or" 3536 " disabled in firmware" 3537 " configuration."); 3538 /* MPLS over UDP, GRE is allowed */ 3539 if (!(prev_layer & (MLX5_FLOW_LAYER_OUTER_L4_UDP | 3540 MLX5_FLOW_LAYER_GRE | 3541 MLX5_FLOW_LAYER_GRE_KEY))) 3542 return rte_flow_error_set(error, EINVAL, 3543 RTE_FLOW_ERROR_TYPE_ITEM, item, 3544 "protocol filtering not compatible" 3545 " with MPLS layer"); 3546 /* Multi-tunnel isn't allowed but MPLS over GRE is an exception. */ 3547 if ((item_flags & MLX5_FLOW_LAYER_TUNNEL) && 3548 !(item_flags & MLX5_FLOW_LAYER_GRE)) 3549 return rte_flow_error_set(error, ENOTSUP, 3550 RTE_FLOW_ERROR_TYPE_ITEM, item, 3551 "multiple tunnel layers not" 3552 " supported"); 3553 if (!mask) 3554 mask = &rte_flow_item_mpls_mask; 3555 ret = mlx5_flow_item_acceptable 3556 (item, (const uint8_t *)mask, 3557 (const uint8_t *)&rte_flow_item_mpls_mask, 3558 sizeof(struct rte_flow_item_mpls), 3559 MLX5_ITEM_RANGE_NOT_ACCEPTED, error); 3560 if (ret < 0) 3561 return ret; 3562 return 0; 3563 #else 3564 return rte_flow_error_set(error, ENOTSUP, 3565 RTE_FLOW_ERROR_TYPE_ITEM, item, 3566 "MPLS is not supported by Verbs, please" 3567 " update."); 3568 #endif 3569 } 3570 3571 /** 3572 * Validate NVGRE item. 3573 * 3574 * @param[in] item 3575 * Item specification. 3576 * @param[in] item_flags 3577 * Bit flags to mark detected items. 3578 * @param[in] target_protocol 3579 * The next protocol in the previous item. 3580 * @param[out] error 3581 * Pointer to error structure. 3582 * 3583 * @return 3584 * 0 on success, a negative errno value otherwise and rte_errno is set. 3585 */ 3586 int 3587 mlx5_flow_validate_item_nvgre(const struct rte_flow_item *item, 3588 uint64_t item_flags, 3589 uint8_t target_protocol, 3590 struct rte_flow_error *error) 3591 { 3592 const struct rte_flow_item_nvgre *mask = item->mask; 3593 int ret; 3594 3595 if (target_protocol != 0xff && target_protocol != IPPROTO_GRE) 3596 return rte_flow_error_set(error, EINVAL, 3597 RTE_FLOW_ERROR_TYPE_ITEM, item, 3598 "protocol filtering not compatible" 3599 " with this GRE layer"); 3600 if (item_flags & MLX5_FLOW_LAYER_TUNNEL) 3601 return rte_flow_error_set(error, ENOTSUP, 3602 RTE_FLOW_ERROR_TYPE_ITEM, item, 3603 "multiple tunnel layers not" 3604 " supported"); 3605 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L3)) 3606 return rte_flow_error_set(error, ENOTSUP, 3607 RTE_FLOW_ERROR_TYPE_ITEM, item, 3608 "L3 Layer is missing"); 3609 if (!mask) 3610 mask = &rte_flow_item_nvgre_mask; 3611 ret = mlx5_flow_item_acceptable 3612 (item, (const uint8_t *)mask, 3613 (const uint8_t *)&rte_flow_item_nvgre_mask, 3614 sizeof(struct rte_flow_item_nvgre), 3615 MLX5_ITEM_RANGE_NOT_ACCEPTED, error); 3616 if (ret < 0) 3617 return ret; 3618 return 0; 3619 } 3620 3621 /** 3622 * Validate eCPRI item. 3623 * 3624 * @param[in] item 3625 * Item specification. 3626 * @param[in] item_flags 3627 * Bit-fields that holds the items detected until now. 3628 * @param[in] last_item 3629 * Previous validated item in the pattern items. 3630 * @param[in] ether_type 3631 * Type in the ethernet layer header (including dot1q). 3632 * @param[in] acc_mask 3633 * Acceptable mask, if NULL default internal default mask 3634 * will be used to check whether item fields are supported. 3635 * @param[out] error 3636 * Pointer to error structure. 3637 * 3638 * @return 3639 * 0 on success, a negative errno value otherwise and rte_errno is set. 3640 */ 3641 int 3642 mlx5_flow_validate_item_ecpri(const struct rte_flow_item *item, 3643 uint64_t item_flags, 3644 uint64_t last_item, 3645 uint16_t ether_type, 3646 const struct rte_flow_item_ecpri *acc_mask, 3647 struct rte_flow_error *error) 3648 { 3649 const struct rte_flow_item_ecpri *mask = item->mask; 3650 const struct rte_flow_item_ecpri nic_mask = { 3651 .hdr = { 3652 .common = { 3653 .u32 = 3654 RTE_BE32(((const struct rte_ecpri_common_hdr) { 3655 .type = 0xFF, 3656 }).u32), 3657 }, 3658 .dummy[0] = 0xFFFFFFFF, 3659 }, 3660 }; 3661 const uint64_t outer_l2_vlan = (MLX5_FLOW_LAYER_OUTER_L2 | 3662 MLX5_FLOW_LAYER_OUTER_VLAN); 3663 struct rte_flow_item_ecpri mask_lo; 3664 3665 if (!(last_item & outer_l2_vlan) && 3666 last_item != MLX5_FLOW_LAYER_OUTER_L4_UDP) 3667 return rte_flow_error_set(error, EINVAL, 3668 RTE_FLOW_ERROR_TYPE_ITEM, item, 3669 "eCPRI can only follow L2/VLAN layer or UDP layer"); 3670 if ((last_item & outer_l2_vlan) && ether_type && 3671 ether_type != RTE_ETHER_TYPE_ECPRI) 3672 return rte_flow_error_set(error, EINVAL, 3673 RTE_FLOW_ERROR_TYPE_ITEM, item, 3674 "eCPRI cannot follow L2/VLAN layer which ether type is not 0xAEFE"); 3675 if (item_flags & MLX5_FLOW_LAYER_TUNNEL) 3676 return rte_flow_error_set(error, EINVAL, 3677 RTE_FLOW_ERROR_TYPE_ITEM, item, 3678 "eCPRI with tunnel is not supported right now"); 3679 if (item_flags & MLX5_FLOW_LAYER_OUTER_L3) 3680 return rte_flow_error_set(error, ENOTSUP, 3681 RTE_FLOW_ERROR_TYPE_ITEM, item, 3682 "multiple L3 layers not supported"); 3683 else if (item_flags & MLX5_FLOW_LAYER_OUTER_L4_TCP) 3684 return rte_flow_error_set(error, EINVAL, 3685 RTE_FLOW_ERROR_TYPE_ITEM, item, 3686 "eCPRI cannot coexist with a TCP layer"); 3687 /* In specification, eCPRI could be over UDP layer. */ 3688 else if (item_flags & MLX5_FLOW_LAYER_OUTER_L4_UDP) 3689 return rte_flow_error_set(error, EINVAL, 3690 RTE_FLOW_ERROR_TYPE_ITEM, item, 3691 "eCPRI over UDP layer is not yet supported right now"); 3692 /* Mask for type field in common header could be zero. */ 3693 if (!mask) 3694 mask = &rte_flow_item_ecpri_mask; 3695 mask_lo.hdr.common.u32 = rte_be_to_cpu_32(mask->hdr.common.u32); 3696 /* Input mask is in big-endian format. */ 3697 if (mask_lo.hdr.common.type != 0 && mask_lo.hdr.common.type != 0xff) 3698 return rte_flow_error_set(error, EINVAL, 3699 RTE_FLOW_ERROR_TYPE_ITEM_MASK, mask, 3700 "partial mask is not supported for protocol"); 3701 else if (mask_lo.hdr.common.type == 0 && mask->hdr.dummy[0] != 0) 3702 return rte_flow_error_set(error, EINVAL, 3703 RTE_FLOW_ERROR_TYPE_ITEM_MASK, mask, 3704 "message header mask must be after a type mask"); 3705 return mlx5_flow_item_acceptable(item, (const uint8_t *)mask, 3706 acc_mask ? (const uint8_t *)acc_mask 3707 : (const uint8_t *)&nic_mask, 3708 sizeof(struct rte_flow_item_ecpri), 3709 MLX5_ITEM_RANGE_NOT_ACCEPTED, error); 3710 } 3711 3712 static int 3713 flow_null_validate(struct rte_eth_dev *dev __rte_unused, 3714 const struct rte_flow_attr *attr __rte_unused, 3715 const struct rte_flow_item items[] __rte_unused, 3716 const struct rte_flow_action actions[] __rte_unused, 3717 bool external __rte_unused, 3718 int hairpin __rte_unused, 3719 struct rte_flow_error *error) 3720 { 3721 return rte_flow_error_set(error, ENOTSUP, 3722 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, NULL); 3723 } 3724 3725 static struct mlx5_flow * 3726 flow_null_prepare(struct rte_eth_dev *dev __rte_unused, 3727 const struct rte_flow_attr *attr __rte_unused, 3728 const struct rte_flow_item items[] __rte_unused, 3729 const struct rte_flow_action actions[] __rte_unused, 3730 struct rte_flow_error *error) 3731 { 3732 rte_flow_error_set(error, ENOTSUP, 3733 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, NULL); 3734 return NULL; 3735 } 3736 3737 static int 3738 flow_null_translate(struct rte_eth_dev *dev __rte_unused, 3739 struct mlx5_flow *dev_flow __rte_unused, 3740 const struct rte_flow_attr *attr __rte_unused, 3741 const struct rte_flow_item items[] __rte_unused, 3742 const struct rte_flow_action actions[] __rte_unused, 3743 struct rte_flow_error *error) 3744 { 3745 return rte_flow_error_set(error, ENOTSUP, 3746 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, NULL); 3747 } 3748 3749 static int 3750 flow_null_apply(struct rte_eth_dev *dev __rte_unused, 3751 struct rte_flow *flow __rte_unused, 3752 struct rte_flow_error *error) 3753 { 3754 return rte_flow_error_set(error, ENOTSUP, 3755 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, NULL); 3756 } 3757 3758 static void 3759 flow_null_remove(struct rte_eth_dev *dev __rte_unused, 3760 struct rte_flow *flow __rte_unused) 3761 { 3762 } 3763 3764 static void 3765 flow_null_destroy(struct rte_eth_dev *dev __rte_unused, 3766 struct rte_flow *flow __rte_unused) 3767 { 3768 } 3769 3770 static int 3771 flow_null_query(struct rte_eth_dev *dev __rte_unused, 3772 struct rte_flow *flow __rte_unused, 3773 const struct rte_flow_action *actions __rte_unused, 3774 void *data __rte_unused, 3775 struct rte_flow_error *error) 3776 { 3777 return rte_flow_error_set(error, ENOTSUP, 3778 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, NULL); 3779 } 3780 3781 static int 3782 flow_null_sync_domain(struct rte_eth_dev *dev __rte_unused, 3783 uint32_t domains __rte_unused, 3784 uint32_t flags __rte_unused) 3785 { 3786 return 0; 3787 } 3788 3789 /* Void driver to protect from null pointer reference. */ 3790 const struct mlx5_flow_driver_ops mlx5_flow_null_drv_ops = { 3791 .validate = flow_null_validate, 3792 .prepare = flow_null_prepare, 3793 .translate = flow_null_translate, 3794 .apply = flow_null_apply, 3795 .remove = flow_null_remove, 3796 .destroy = flow_null_destroy, 3797 .query = flow_null_query, 3798 .sync_domain = flow_null_sync_domain, 3799 }; 3800 3801 /** 3802 * Select flow driver type according to flow attributes and device 3803 * configuration. 3804 * 3805 * @param[in] dev 3806 * Pointer to the dev structure. 3807 * @param[in] attr 3808 * Pointer to the flow attributes. 3809 * 3810 * @return 3811 * flow driver type, MLX5_FLOW_TYPE_MAX otherwise. 3812 */ 3813 static enum mlx5_flow_drv_type 3814 flow_get_drv_type(struct rte_eth_dev *dev, const struct rte_flow_attr *attr) 3815 { 3816 struct mlx5_priv *priv = dev->data->dev_private; 3817 /* The OS can determine first a specific flow type (DV, VERBS) */ 3818 enum mlx5_flow_drv_type type = mlx5_flow_os_get_type(); 3819 3820 if (type != MLX5_FLOW_TYPE_MAX) 3821 return type; 3822 /* 3823 * Currently when dv_flow_en == 2, only HW steering engine is 3824 * supported. New engines can also be chosen here if ready. 3825 */ 3826 if (priv->sh->config.dv_flow_en == 2) 3827 return MLX5_FLOW_TYPE_HW; 3828 if (!attr) 3829 return MLX5_FLOW_TYPE_MIN; 3830 /* If no OS specific type - continue with DV/VERBS selection */ 3831 if (attr->transfer && priv->sh->config.dv_esw_en) 3832 type = MLX5_FLOW_TYPE_DV; 3833 if (!attr->transfer) 3834 type = priv->sh->config.dv_flow_en ? MLX5_FLOW_TYPE_DV : 3835 MLX5_FLOW_TYPE_VERBS; 3836 return type; 3837 } 3838 3839 #define flow_get_drv_ops(type) flow_drv_ops[type] 3840 3841 /** 3842 * Flow driver validation API. This abstracts calling driver specific functions. 3843 * The type of flow driver is determined according to flow attributes. 3844 * 3845 * @param[in] dev 3846 * Pointer to the dev structure. 3847 * @param[in] attr 3848 * Pointer to the flow attributes. 3849 * @param[in] items 3850 * Pointer to the list of items. 3851 * @param[in] actions 3852 * Pointer to the list of actions. 3853 * @param[in] external 3854 * This flow rule is created by request external to PMD. 3855 * @param[in] hairpin 3856 * Number of hairpin TX actions, 0 means classic flow. 3857 * @param[out] error 3858 * Pointer to the error structure. 3859 * 3860 * @return 3861 * 0 on success, a negative errno value otherwise and rte_errno is set. 3862 */ 3863 static inline int 3864 flow_drv_validate(struct rte_eth_dev *dev, 3865 const struct rte_flow_attr *attr, 3866 const struct rte_flow_item items[], 3867 const struct rte_flow_action actions[], 3868 bool external, int hairpin, struct rte_flow_error *error) 3869 { 3870 const struct mlx5_flow_driver_ops *fops; 3871 enum mlx5_flow_drv_type type = flow_get_drv_type(dev, attr); 3872 3873 fops = flow_get_drv_ops(type); 3874 return fops->validate(dev, attr, items, actions, external, 3875 hairpin, error); 3876 } 3877 3878 /** 3879 * Flow driver preparation API. This abstracts calling driver specific 3880 * functions. Parent flow (rte_flow) should have driver type (drv_type). It 3881 * calculates the size of memory required for device flow, allocates the memory, 3882 * initializes the device flow and returns the pointer. 3883 * 3884 * @note 3885 * This function initializes device flow structure such as dv or verbs in 3886 * struct mlx5_flow. However, it is caller's responsibility to initialize the 3887 * rest. For example, adding returning device flow to flow->dev_flow list and 3888 * setting backward reference to the flow should be done out of this function. 3889 * layers field is not filled either. 3890 * 3891 * @param[in] dev 3892 * Pointer to the dev structure. 3893 * @param[in] attr 3894 * Pointer to the flow attributes. 3895 * @param[in] items 3896 * Pointer to the list of items. 3897 * @param[in] actions 3898 * Pointer to the list of actions. 3899 * @param[in] flow_idx 3900 * This memory pool index to the flow. 3901 * @param[out] error 3902 * Pointer to the error structure. 3903 * 3904 * @return 3905 * Pointer to device flow on success, otherwise NULL and rte_errno is set. 3906 */ 3907 static inline struct mlx5_flow * 3908 flow_drv_prepare(struct rte_eth_dev *dev, 3909 const struct rte_flow *flow, 3910 const struct rte_flow_attr *attr, 3911 const struct rte_flow_item items[], 3912 const struct rte_flow_action actions[], 3913 uint32_t flow_idx, 3914 struct rte_flow_error *error) 3915 { 3916 const struct mlx5_flow_driver_ops *fops; 3917 enum mlx5_flow_drv_type type = flow->drv_type; 3918 struct mlx5_flow *mlx5_flow = NULL; 3919 3920 MLX5_ASSERT(type > MLX5_FLOW_TYPE_MIN && type < MLX5_FLOW_TYPE_MAX); 3921 fops = flow_get_drv_ops(type); 3922 mlx5_flow = fops->prepare(dev, attr, items, actions, error); 3923 if (mlx5_flow) 3924 mlx5_flow->flow_idx = flow_idx; 3925 return mlx5_flow; 3926 } 3927 3928 /** 3929 * Flow driver translation API. This abstracts calling driver specific 3930 * functions. Parent flow (rte_flow) should have driver type (drv_type). It 3931 * translates a generic flow into a driver flow. flow_drv_prepare() must 3932 * precede. 3933 * 3934 * @note 3935 * dev_flow->layers could be filled as a result of parsing during translation 3936 * if needed by flow_drv_apply(). dev_flow->flow->actions can also be filled 3937 * if necessary. As a flow can have multiple dev_flows by RSS flow expansion, 3938 * flow->actions could be overwritten even though all the expanded dev_flows 3939 * have the same actions. 3940 * 3941 * @param[in] dev 3942 * Pointer to the rte dev structure. 3943 * @param[in, out] dev_flow 3944 * Pointer to the mlx5 flow. 3945 * @param[in] attr 3946 * Pointer to the flow attributes. 3947 * @param[in] items 3948 * Pointer to the list of items. 3949 * @param[in] actions 3950 * Pointer to the list of actions. 3951 * @param[out] error 3952 * Pointer to the error structure. 3953 * 3954 * @return 3955 * 0 on success, a negative errno value otherwise and rte_errno is set. 3956 */ 3957 static inline int 3958 flow_drv_translate(struct rte_eth_dev *dev, struct mlx5_flow *dev_flow, 3959 const struct rte_flow_attr *attr, 3960 const struct rte_flow_item items[], 3961 const struct rte_flow_action actions[], 3962 struct rte_flow_error *error) 3963 { 3964 const struct mlx5_flow_driver_ops *fops; 3965 enum mlx5_flow_drv_type type = dev_flow->flow->drv_type; 3966 3967 MLX5_ASSERT(type > MLX5_FLOW_TYPE_MIN && type < MLX5_FLOW_TYPE_MAX); 3968 fops = flow_get_drv_ops(type); 3969 return fops->translate(dev, dev_flow, attr, items, actions, error); 3970 } 3971 3972 /** 3973 * Flow driver apply API. This abstracts calling driver specific functions. 3974 * Parent flow (rte_flow) should have driver type (drv_type). It applies 3975 * translated driver flows on to device. flow_drv_translate() must precede. 3976 * 3977 * @param[in] dev 3978 * Pointer to Ethernet device structure. 3979 * @param[in, out] flow 3980 * Pointer to flow structure. 3981 * @param[out] error 3982 * Pointer to error structure. 3983 * 3984 * @return 3985 * 0 on success, a negative errno value otherwise and rte_errno is set. 3986 */ 3987 static inline int 3988 flow_drv_apply(struct rte_eth_dev *dev, struct rte_flow *flow, 3989 struct rte_flow_error *error) 3990 { 3991 const struct mlx5_flow_driver_ops *fops; 3992 enum mlx5_flow_drv_type type = flow->drv_type; 3993 3994 MLX5_ASSERT(type > MLX5_FLOW_TYPE_MIN && type < MLX5_FLOW_TYPE_MAX); 3995 fops = flow_get_drv_ops(type); 3996 return fops->apply(dev, flow, error); 3997 } 3998 3999 /** 4000 * Flow driver destroy API. This abstracts calling driver specific functions. 4001 * Parent flow (rte_flow) should have driver type (drv_type). It removes a flow 4002 * on device and releases resources of the flow. 4003 * 4004 * @param[in] dev 4005 * Pointer to Ethernet device. 4006 * @param[in, out] flow 4007 * Pointer to flow structure. 4008 */ 4009 static inline void 4010 flow_drv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow) 4011 { 4012 const struct mlx5_flow_driver_ops *fops; 4013 enum mlx5_flow_drv_type type = flow->drv_type; 4014 4015 MLX5_ASSERT(type > MLX5_FLOW_TYPE_MIN && type < MLX5_FLOW_TYPE_MAX); 4016 fops = flow_get_drv_ops(type); 4017 fops->destroy(dev, flow); 4018 } 4019 4020 /** 4021 * Flow driver find RSS policy tbl API. This abstracts calling driver 4022 * specific functions. Parent flow (rte_flow) should have driver 4023 * type (drv_type). It will find the RSS policy table that has the rss_desc. 4024 * 4025 * @param[in] dev 4026 * Pointer to Ethernet device. 4027 * @param[in, out] flow 4028 * Pointer to flow structure. 4029 * @param[in] policy 4030 * Pointer to meter policy table. 4031 * @param[in] rss_desc 4032 * Pointer to rss_desc 4033 */ 4034 static struct mlx5_flow_meter_sub_policy * 4035 flow_drv_meter_sub_policy_rss_prepare(struct rte_eth_dev *dev, 4036 struct rte_flow *flow, 4037 struct mlx5_flow_meter_policy *policy, 4038 struct mlx5_flow_rss_desc *rss_desc[MLX5_MTR_RTE_COLORS]) 4039 { 4040 const struct mlx5_flow_driver_ops *fops; 4041 enum mlx5_flow_drv_type type = flow->drv_type; 4042 4043 MLX5_ASSERT(type > MLX5_FLOW_TYPE_MIN && type < MLX5_FLOW_TYPE_MAX); 4044 fops = flow_get_drv_ops(type); 4045 return fops->meter_sub_policy_rss_prepare(dev, policy, rss_desc); 4046 } 4047 4048 /** 4049 * Flow driver color tag rule API. This abstracts calling driver 4050 * specific functions. Parent flow (rte_flow) should have driver 4051 * type (drv_type). It will create the color tag rules in hierarchy meter. 4052 * 4053 * @param[in] dev 4054 * Pointer to Ethernet device. 4055 * @param[in, out] flow 4056 * Pointer to flow structure. 4057 * @param[in] fm 4058 * Pointer to flow meter structure. 4059 * @param[in] src_port 4060 * The src port this extra rule should use. 4061 * @param[in] item 4062 * The src port id match item. 4063 * @param[out] error 4064 * Pointer to error structure. 4065 */ 4066 static int 4067 flow_drv_mtr_hierarchy_rule_create(struct rte_eth_dev *dev, 4068 struct rte_flow *flow, 4069 struct mlx5_flow_meter_info *fm, 4070 int32_t src_port, 4071 const struct rte_flow_item *item, 4072 struct rte_flow_error *error) 4073 { 4074 const struct mlx5_flow_driver_ops *fops; 4075 enum mlx5_flow_drv_type type = flow->drv_type; 4076 4077 MLX5_ASSERT(type > MLX5_FLOW_TYPE_MIN && type < MLX5_FLOW_TYPE_MAX); 4078 fops = flow_get_drv_ops(type); 4079 return fops->meter_hierarchy_rule_create(dev, fm, 4080 src_port, item, error); 4081 } 4082 4083 /** 4084 * Get RSS action from the action list. 4085 * 4086 * @param[in] dev 4087 * Pointer to Ethernet device. 4088 * @param[in] actions 4089 * Pointer to the list of actions. 4090 * @param[in] flow 4091 * Parent flow structure pointer. 4092 * 4093 * @return 4094 * Pointer to the RSS action if exist, else return NULL. 4095 */ 4096 static const struct rte_flow_action_rss* 4097 flow_get_rss_action(struct rte_eth_dev *dev, 4098 const struct rte_flow_action actions[]) 4099 { 4100 struct mlx5_priv *priv = dev->data->dev_private; 4101 const struct rte_flow_action_rss *rss = NULL; 4102 struct mlx5_meter_policy_action_container *acg; 4103 struct mlx5_meter_policy_action_container *acy; 4104 4105 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) { 4106 switch (actions->type) { 4107 case RTE_FLOW_ACTION_TYPE_RSS: 4108 rss = actions->conf; 4109 break; 4110 case RTE_FLOW_ACTION_TYPE_SAMPLE: 4111 { 4112 const struct rte_flow_action_sample *sample = 4113 actions->conf; 4114 const struct rte_flow_action *act = sample->actions; 4115 for (; act->type != RTE_FLOW_ACTION_TYPE_END; act++) 4116 if (act->type == RTE_FLOW_ACTION_TYPE_RSS) 4117 rss = act->conf; 4118 break; 4119 } 4120 case RTE_FLOW_ACTION_TYPE_METER: 4121 { 4122 uint32_t mtr_idx; 4123 struct mlx5_flow_meter_info *fm; 4124 struct mlx5_flow_meter_policy *policy; 4125 const struct rte_flow_action_meter *mtr = actions->conf; 4126 4127 fm = mlx5_flow_meter_find(priv, mtr->mtr_id, &mtr_idx); 4128 if (fm && !fm->def_policy) { 4129 policy = mlx5_flow_meter_policy_find(dev, 4130 fm->policy_id, NULL); 4131 MLX5_ASSERT(policy); 4132 if (policy->is_hierarchy) { 4133 policy = 4134 mlx5_flow_meter_hierarchy_get_final_policy(dev, 4135 policy); 4136 if (!policy) 4137 return NULL; 4138 } 4139 if (policy->is_rss) { 4140 acg = 4141 &policy->act_cnt[RTE_COLOR_GREEN]; 4142 acy = 4143 &policy->act_cnt[RTE_COLOR_YELLOW]; 4144 if (acg->fate_action == 4145 MLX5_FLOW_FATE_SHARED_RSS) 4146 rss = acg->rss->conf; 4147 else if (acy->fate_action == 4148 MLX5_FLOW_FATE_SHARED_RSS) 4149 rss = acy->rss->conf; 4150 } 4151 } 4152 break; 4153 } 4154 default: 4155 break; 4156 } 4157 } 4158 return rss; 4159 } 4160 4161 /** 4162 * Get ASO age action by index. 4163 * 4164 * @param[in] dev 4165 * Pointer to the Ethernet device structure. 4166 * @param[in] age_idx 4167 * Index to the ASO age action. 4168 * 4169 * @return 4170 * The specified ASO age action. 4171 */ 4172 struct mlx5_aso_age_action* 4173 flow_aso_age_get_by_idx(struct rte_eth_dev *dev, uint32_t age_idx) 4174 { 4175 uint16_t pool_idx = age_idx & UINT16_MAX; 4176 uint16_t offset = (age_idx >> 16) & UINT16_MAX; 4177 struct mlx5_priv *priv = dev->data->dev_private; 4178 struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng; 4179 struct mlx5_aso_age_pool *pool; 4180 4181 rte_rwlock_read_lock(&mng->resize_rwl); 4182 pool = mng->pools[pool_idx]; 4183 rte_rwlock_read_unlock(&mng->resize_rwl); 4184 return &pool->actions[offset - 1]; 4185 } 4186 4187 /* maps indirect action to translated direct in some actions array */ 4188 struct mlx5_translated_action_handle { 4189 struct rte_flow_action_handle *action; /**< Indirect action handle. */ 4190 int index; /**< Index in related array of rte_flow_action. */ 4191 }; 4192 4193 /** 4194 * Translates actions of type RTE_FLOW_ACTION_TYPE_INDIRECT to related 4195 * direct action if translation possible. 4196 * This functionality used to run same execution path for both direct and 4197 * indirect actions on flow create. All necessary preparations for indirect 4198 * action handling should be performed on *handle* actions list returned 4199 * from this call. 4200 * 4201 * @param[in] dev 4202 * Pointer to Ethernet device. 4203 * @param[in] actions 4204 * List of actions to translate. 4205 * @param[out] handle 4206 * List to store translated indirect action object handles. 4207 * @param[in, out] indir_n 4208 * Size of *handle* array. On return should be updated with number of 4209 * indirect actions retrieved from the *actions* list. 4210 * @param[out] translated_actions 4211 * List of actions where all indirect actions were translated to direct 4212 * if possible. NULL if no translation took place. 4213 * @param[out] error 4214 * Pointer to the error structure. 4215 * 4216 * @return 4217 * 0 on success, a negative errno value otherwise and rte_errno is set. 4218 */ 4219 static int 4220 flow_action_handles_translate(struct rte_eth_dev *dev, 4221 const struct rte_flow_action actions[], 4222 struct mlx5_translated_action_handle *handle, 4223 int *indir_n, 4224 struct rte_flow_action **translated_actions, 4225 struct rte_flow_error *error) 4226 { 4227 struct mlx5_priv *priv = dev->data->dev_private; 4228 struct rte_flow_action *translated = NULL; 4229 size_t actions_size; 4230 int n; 4231 int copied_n = 0; 4232 struct mlx5_translated_action_handle *handle_end = NULL; 4233 4234 for (n = 0; actions[n].type != RTE_FLOW_ACTION_TYPE_END; n++) { 4235 if (actions[n].type != RTE_FLOW_ACTION_TYPE_INDIRECT) 4236 continue; 4237 if (copied_n == *indir_n) { 4238 return rte_flow_error_set 4239 (error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION_NUM, 4240 NULL, "too many shared actions"); 4241 } 4242 rte_memcpy(&handle[copied_n].action, &actions[n].conf, 4243 sizeof(actions[n].conf)); 4244 handle[copied_n].index = n; 4245 copied_n++; 4246 } 4247 n++; 4248 *indir_n = copied_n; 4249 if (!copied_n) 4250 return 0; 4251 actions_size = sizeof(struct rte_flow_action) * n; 4252 translated = mlx5_malloc(MLX5_MEM_ZERO, actions_size, 0, SOCKET_ID_ANY); 4253 if (!translated) { 4254 rte_errno = ENOMEM; 4255 return -ENOMEM; 4256 } 4257 memcpy(translated, actions, actions_size); 4258 for (handle_end = handle + copied_n; handle < handle_end; handle++) { 4259 struct mlx5_shared_action_rss *shared_rss; 4260 uint32_t act_idx = (uint32_t)(uintptr_t)handle->action; 4261 uint32_t type = act_idx >> MLX5_INDIRECT_ACTION_TYPE_OFFSET; 4262 uint32_t idx = act_idx & 4263 ((1u << MLX5_INDIRECT_ACTION_TYPE_OFFSET) - 1); 4264 4265 switch (type) { 4266 case MLX5_INDIRECT_ACTION_TYPE_RSS: 4267 shared_rss = mlx5_ipool_get 4268 (priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], idx); 4269 translated[handle->index].type = 4270 RTE_FLOW_ACTION_TYPE_RSS; 4271 translated[handle->index].conf = 4272 &shared_rss->origin; 4273 break; 4274 case MLX5_INDIRECT_ACTION_TYPE_COUNT: 4275 translated[handle->index].type = 4276 (enum rte_flow_action_type) 4277 MLX5_RTE_FLOW_ACTION_TYPE_COUNT; 4278 translated[handle->index].conf = (void *)(uintptr_t)idx; 4279 break; 4280 case MLX5_INDIRECT_ACTION_TYPE_METER_MARK: 4281 translated[handle->index].type = 4282 (enum rte_flow_action_type) 4283 MLX5_RTE_FLOW_ACTION_TYPE_METER_MARK; 4284 translated[handle->index].conf = (void *)(uintptr_t)idx; 4285 break; 4286 case MLX5_INDIRECT_ACTION_TYPE_AGE: 4287 if (priv->sh->flow_hit_aso_en) { 4288 translated[handle->index].type = 4289 (enum rte_flow_action_type) 4290 MLX5_RTE_FLOW_ACTION_TYPE_AGE; 4291 translated[handle->index].conf = 4292 (void *)(uintptr_t)idx; 4293 break; 4294 } 4295 /* Fall-through */ 4296 case MLX5_INDIRECT_ACTION_TYPE_CT: 4297 if (priv->sh->ct_aso_en) { 4298 translated[handle->index].type = 4299 RTE_FLOW_ACTION_TYPE_CONNTRACK; 4300 translated[handle->index].conf = 4301 (void *)(uintptr_t)idx; 4302 break; 4303 } 4304 /* Fall-through */ 4305 default: 4306 mlx5_free(translated); 4307 return rte_flow_error_set 4308 (error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION, 4309 NULL, "invalid indirect action type"); 4310 } 4311 } 4312 *translated_actions = translated; 4313 return 0; 4314 } 4315 4316 /** 4317 * Get Shared RSS action from the action list. 4318 * 4319 * @param[in] dev 4320 * Pointer to Ethernet device. 4321 * @param[in] shared 4322 * Pointer to the list of actions. 4323 * @param[in] shared_n 4324 * Actions list length. 4325 * 4326 * @return 4327 * The MLX5 RSS action ID if exists, otherwise return 0. 4328 */ 4329 static uint32_t 4330 flow_get_shared_rss_action(struct rte_eth_dev *dev, 4331 struct mlx5_translated_action_handle *handle, 4332 int shared_n) 4333 { 4334 struct mlx5_translated_action_handle *handle_end; 4335 struct mlx5_priv *priv = dev->data->dev_private; 4336 struct mlx5_shared_action_rss *shared_rss; 4337 4338 4339 for (handle_end = handle + shared_n; handle < handle_end; handle++) { 4340 uint32_t act_idx = (uint32_t)(uintptr_t)handle->action; 4341 uint32_t type = act_idx >> MLX5_INDIRECT_ACTION_TYPE_OFFSET; 4342 uint32_t idx = act_idx & 4343 ((1u << MLX5_INDIRECT_ACTION_TYPE_OFFSET) - 1); 4344 switch (type) { 4345 case MLX5_INDIRECT_ACTION_TYPE_RSS: 4346 shared_rss = mlx5_ipool_get 4347 (priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], 4348 idx); 4349 __atomic_add_fetch(&shared_rss->refcnt, 1, 4350 __ATOMIC_RELAXED); 4351 return idx; 4352 default: 4353 break; 4354 } 4355 } 4356 return 0; 4357 } 4358 4359 static unsigned int 4360 find_graph_root(uint32_t rss_level) 4361 { 4362 return rss_level < 2 ? MLX5_EXPANSION_ROOT : 4363 MLX5_EXPANSION_ROOT_OUTER; 4364 } 4365 4366 /** 4367 * Get layer flags from the prefix flow. 4368 * 4369 * Some flows may be split to several subflows, the prefix subflow gets the 4370 * match items and the suffix sub flow gets the actions. 4371 * Some actions need the user defined match item flags to get the detail for 4372 * the action. 4373 * This function helps the suffix flow to get the item layer flags from prefix 4374 * subflow. 4375 * 4376 * @param[in] dev_flow 4377 * Pointer the created prefix subflow. 4378 * 4379 * @return 4380 * The layers get from prefix subflow. 4381 */ 4382 static inline uint64_t 4383 flow_get_prefix_layer_flags(struct mlx5_flow *dev_flow) 4384 { 4385 uint64_t layers = 0; 4386 4387 /* 4388 * Layers bits could be localization, but usually the compiler will 4389 * help to do the optimization work for source code. 4390 * If no decap actions, use the layers directly. 4391 */ 4392 if (!(dev_flow->act_flags & MLX5_FLOW_ACTION_DECAP)) 4393 return dev_flow->handle->layers; 4394 /* Convert L3 layers with decap action. */ 4395 if (dev_flow->handle->layers & MLX5_FLOW_LAYER_INNER_L3_IPV4) 4396 layers |= MLX5_FLOW_LAYER_OUTER_L3_IPV4; 4397 else if (dev_flow->handle->layers & MLX5_FLOW_LAYER_INNER_L3_IPV6) 4398 layers |= MLX5_FLOW_LAYER_OUTER_L3_IPV6; 4399 /* Convert L4 layers with decap action. */ 4400 if (dev_flow->handle->layers & MLX5_FLOW_LAYER_INNER_L4_TCP) 4401 layers |= MLX5_FLOW_LAYER_OUTER_L4_TCP; 4402 else if (dev_flow->handle->layers & MLX5_FLOW_LAYER_INNER_L4_UDP) 4403 layers |= MLX5_FLOW_LAYER_OUTER_L4_UDP; 4404 return layers; 4405 } 4406 4407 /** 4408 * Get metadata split action information. 4409 * 4410 * @param[in] actions 4411 * Pointer to the list of actions. 4412 * @param[out] qrss 4413 * Pointer to the return pointer. 4414 * @param[out] qrss_type 4415 * Pointer to the action type to return. RTE_FLOW_ACTION_TYPE_END is returned 4416 * if no QUEUE/RSS is found. 4417 * @param[out] encap_idx 4418 * Pointer to the index of the encap action if exists, otherwise the last 4419 * action index. 4420 * 4421 * @return 4422 * Total number of actions. 4423 */ 4424 static int 4425 flow_parse_metadata_split_actions_info(const struct rte_flow_action actions[], 4426 const struct rte_flow_action **qrss, 4427 int *encap_idx) 4428 { 4429 const struct rte_flow_action_raw_encap *raw_encap; 4430 int actions_n = 0; 4431 int raw_decap_idx = -1; 4432 4433 *encap_idx = -1; 4434 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) { 4435 switch (actions->type) { 4436 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP: 4437 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP: 4438 *encap_idx = actions_n; 4439 break; 4440 case RTE_FLOW_ACTION_TYPE_RAW_DECAP: 4441 raw_decap_idx = actions_n; 4442 break; 4443 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP: 4444 raw_encap = actions->conf; 4445 if (raw_encap->size > MLX5_ENCAPSULATION_DECISION_SIZE) 4446 *encap_idx = raw_decap_idx != -1 ? 4447 raw_decap_idx : actions_n; 4448 break; 4449 case RTE_FLOW_ACTION_TYPE_QUEUE: 4450 case RTE_FLOW_ACTION_TYPE_RSS: 4451 *qrss = actions; 4452 break; 4453 default: 4454 break; 4455 } 4456 actions_n++; 4457 } 4458 if (*encap_idx == -1) 4459 *encap_idx = actions_n; 4460 /* Count RTE_FLOW_ACTION_TYPE_END. */ 4461 return actions_n + 1; 4462 } 4463 4464 /** 4465 * Check if the action will change packet. 4466 * 4467 * @param dev 4468 * Pointer to Ethernet device. 4469 * @param[in] type 4470 * action type. 4471 * 4472 * @return 4473 * true if action will change packet, false otherwise. 4474 */ 4475 static bool flow_check_modify_action_type(struct rte_eth_dev *dev, 4476 enum rte_flow_action_type type) 4477 { 4478 struct mlx5_priv *priv = dev->data->dev_private; 4479 4480 switch (type) { 4481 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC: 4482 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST: 4483 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC: 4484 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST: 4485 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC: 4486 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST: 4487 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC: 4488 case RTE_FLOW_ACTION_TYPE_SET_TP_DST: 4489 case RTE_FLOW_ACTION_TYPE_DEC_TTL: 4490 case RTE_FLOW_ACTION_TYPE_SET_TTL: 4491 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ: 4492 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ: 4493 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK: 4494 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK: 4495 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP: 4496 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP: 4497 case RTE_FLOW_ACTION_TYPE_SET_META: 4498 case RTE_FLOW_ACTION_TYPE_SET_TAG: 4499 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN: 4500 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN: 4501 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID: 4502 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP: 4503 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP: 4504 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP: 4505 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP: 4506 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP: 4507 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP: 4508 case RTE_FLOW_ACTION_TYPE_RAW_DECAP: 4509 case RTE_FLOW_ACTION_TYPE_MODIFY_FIELD: 4510 return true; 4511 case RTE_FLOW_ACTION_TYPE_FLAG: 4512 case RTE_FLOW_ACTION_TYPE_MARK: 4513 if (priv->sh->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY && 4514 priv->sh->config.dv_xmeta_en != MLX5_XMETA_MODE_META32_HWS) 4515 return true; 4516 else 4517 return false; 4518 default: 4519 return false; 4520 } 4521 } 4522 4523 /** 4524 * Check meter action from the action list. 4525 * 4526 * @param dev 4527 * Pointer to Ethernet device. 4528 * @param[in] actions 4529 * Pointer to the list of actions. 4530 * @param[out] has_mtr 4531 * Pointer to the meter exist flag. 4532 * @param[out] has_modify 4533 * Pointer to the flag showing there's packet change action. 4534 * @param[out] meter_id 4535 * Pointer to the meter id. 4536 * 4537 * @return 4538 * Total number of actions. 4539 */ 4540 static int 4541 flow_check_meter_action(struct rte_eth_dev *dev, 4542 const struct rte_flow_action actions[], 4543 bool *has_mtr, bool *has_modify, uint32_t *meter_id) 4544 { 4545 const struct rte_flow_action_meter *mtr = NULL; 4546 int actions_n = 0; 4547 4548 MLX5_ASSERT(has_mtr); 4549 *has_mtr = false; 4550 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) { 4551 switch (actions->type) { 4552 case RTE_FLOW_ACTION_TYPE_METER: 4553 mtr = actions->conf; 4554 *meter_id = mtr->mtr_id; 4555 *has_mtr = true; 4556 break; 4557 default: 4558 break; 4559 } 4560 if (!*has_mtr) 4561 *has_modify |= flow_check_modify_action_type(dev, 4562 actions->type); 4563 actions_n++; 4564 } 4565 /* Count RTE_FLOW_ACTION_TYPE_END. */ 4566 return actions_n + 1; 4567 } 4568 4569 /** 4570 * Check if the flow should be split due to hairpin. 4571 * The reason for the split is that in current HW we can't 4572 * support encap and push-vlan on Rx, so if a flow contains 4573 * these actions we move it to Tx. 4574 * 4575 * @param dev 4576 * Pointer to Ethernet device. 4577 * @param[in] attr 4578 * Flow rule attributes. 4579 * @param[in] actions 4580 * Associated actions (list terminated by the END action). 4581 * 4582 * @return 4583 * > 0 the number of actions and the flow should be split, 4584 * 0 when no split required. 4585 */ 4586 static int 4587 flow_check_hairpin_split(struct rte_eth_dev *dev, 4588 const struct rte_flow_attr *attr, 4589 const struct rte_flow_action actions[]) 4590 { 4591 int queue_action = 0; 4592 int action_n = 0; 4593 int split = 0; 4594 const struct rte_flow_action_queue *queue; 4595 const struct rte_flow_action_rss *rss; 4596 const struct rte_flow_action_raw_encap *raw_encap; 4597 const struct rte_eth_hairpin_conf *conf; 4598 4599 if (!attr->ingress) 4600 return 0; 4601 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) { 4602 switch (actions->type) { 4603 case RTE_FLOW_ACTION_TYPE_QUEUE: 4604 queue = actions->conf; 4605 if (queue == NULL) 4606 return 0; 4607 conf = mlx5_rxq_get_hairpin_conf(dev, queue->index); 4608 if (conf == NULL || conf->tx_explicit != 0) 4609 return 0; 4610 queue_action = 1; 4611 action_n++; 4612 break; 4613 case RTE_FLOW_ACTION_TYPE_RSS: 4614 rss = actions->conf; 4615 if (rss == NULL || rss->queue_num == 0) 4616 return 0; 4617 conf = mlx5_rxq_get_hairpin_conf(dev, rss->queue[0]); 4618 if (conf == NULL || conf->tx_explicit != 0) 4619 return 0; 4620 queue_action = 1; 4621 action_n++; 4622 break; 4623 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP: 4624 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP: 4625 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN: 4626 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID: 4627 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP: 4628 split++; 4629 action_n++; 4630 break; 4631 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP: 4632 raw_encap = actions->conf; 4633 if (raw_encap->size > MLX5_ENCAPSULATION_DECISION_SIZE) 4634 split++; 4635 action_n++; 4636 break; 4637 default: 4638 action_n++; 4639 break; 4640 } 4641 } 4642 if (split && queue_action) 4643 return action_n; 4644 return 0; 4645 } 4646 4647 /* Declare flow create/destroy prototype in advance. */ 4648 static uint32_t 4649 flow_list_create(struct rte_eth_dev *dev, enum mlx5_flow_type type, 4650 const struct rte_flow_attr *attr, 4651 const struct rte_flow_item items[], 4652 const struct rte_flow_action actions[], 4653 bool external, struct rte_flow_error *error); 4654 4655 static void 4656 flow_list_destroy(struct rte_eth_dev *dev, enum mlx5_flow_type type, 4657 uint32_t flow_idx); 4658 4659 int 4660 flow_dv_mreg_match_cb(void *tool_ctx __rte_unused, 4661 struct mlx5_list_entry *entry, void *cb_ctx) 4662 { 4663 struct mlx5_flow_cb_ctx *ctx = cb_ctx; 4664 struct mlx5_flow_mreg_copy_resource *mcp_res = 4665 container_of(entry, typeof(*mcp_res), hlist_ent); 4666 4667 return mcp_res->mark_id != *(uint32_t *)(ctx->data); 4668 } 4669 4670 struct mlx5_list_entry * 4671 flow_dv_mreg_create_cb(void *tool_ctx, void *cb_ctx) 4672 { 4673 struct rte_eth_dev *dev = tool_ctx; 4674 struct mlx5_priv *priv = dev->data->dev_private; 4675 struct mlx5_flow_cb_ctx *ctx = cb_ctx; 4676 struct mlx5_flow_mreg_copy_resource *mcp_res; 4677 struct rte_flow_error *error = ctx->error; 4678 uint32_t idx = 0; 4679 int ret; 4680 uint32_t mark_id = *(uint32_t *)(ctx->data); 4681 struct rte_flow_attr attr = { 4682 .group = MLX5_FLOW_MREG_CP_TABLE_GROUP, 4683 .ingress = 1, 4684 }; 4685 struct mlx5_rte_flow_item_tag tag_spec = { 4686 .data = mark_id, 4687 }; 4688 struct rte_flow_item items[] = { 4689 [1] = { .type = RTE_FLOW_ITEM_TYPE_END, }, 4690 }; 4691 struct rte_flow_action_mark ftag = { 4692 .id = mark_id, 4693 }; 4694 struct mlx5_flow_action_copy_mreg cp_mreg = { 4695 .dst = REG_B, 4696 .src = REG_NON, 4697 }; 4698 struct rte_flow_action_jump jump = { 4699 .group = MLX5_FLOW_MREG_ACT_TABLE_GROUP, 4700 }; 4701 struct rte_flow_action actions[] = { 4702 [3] = { .type = RTE_FLOW_ACTION_TYPE_END, }, 4703 }; 4704 4705 /* Fill the register fields in the flow. */ 4706 ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error); 4707 if (ret < 0) 4708 return NULL; 4709 tag_spec.id = ret; 4710 ret = mlx5_flow_get_reg_id(dev, MLX5_METADATA_RX, 0, error); 4711 if (ret < 0) 4712 return NULL; 4713 cp_mreg.src = ret; 4714 /* Provide the full width of FLAG specific value. */ 4715 if (mark_id == (priv->sh->dv_regc0_mask & MLX5_FLOW_MARK_DEFAULT)) 4716 tag_spec.data = MLX5_FLOW_MARK_DEFAULT; 4717 /* Build a new flow. */ 4718 if (mark_id != MLX5_DEFAULT_COPY_ID) { 4719 items[0] = (struct rte_flow_item){ 4720 .type = (enum rte_flow_item_type) 4721 MLX5_RTE_FLOW_ITEM_TYPE_TAG, 4722 .spec = &tag_spec, 4723 }; 4724 items[1] = (struct rte_flow_item){ 4725 .type = RTE_FLOW_ITEM_TYPE_END, 4726 }; 4727 actions[0] = (struct rte_flow_action){ 4728 .type = (enum rte_flow_action_type) 4729 MLX5_RTE_FLOW_ACTION_TYPE_MARK, 4730 .conf = &ftag, 4731 }; 4732 actions[1] = (struct rte_flow_action){ 4733 .type = (enum rte_flow_action_type) 4734 MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG, 4735 .conf = &cp_mreg, 4736 }; 4737 actions[2] = (struct rte_flow_action){ 4738 .type = RTE_FLOW_ACTION_TYPE_JUMP, 4739 .conf = &jump, 4740 }; 4741 actions[3] = (struct rte_flow_action){ 4742 .type = RTE_FLOW_ACTION_TYPE_END, 4743 }; 4744 } else { 4745 /* Default rule, wildcard match. */ 4746 attr.priority = MLX5_FLOW_LOWEST_PRIO_INDICATOR; 4747 items[0] = (struct rte_flow_item){ 4748 .type = RTE_FLOW_ITEM_TYPE_END, 4749 }; 4750 actions[0] = (struct rte_flow_action){ 4751 .type = (enum rte_flow_action_type) 4752 MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG, 4753 .conf = &cp_mreg, 4754 }; 4755 actions[1] = (struct rte_flow_action){ 4756 .type = RTE_FLOW_ACTION_TYPE_JUMP, 4757 .conf = &jump, 4758 }; 4759 actions[2] = (struct rte_flow_action){ 4760 .type = RTE_FLOW_ACTION_TYPE_END, 4761 }; 4762 } 4763 /* Build a new entry. */ 4764 mcp_res = mlx5_ipool_zmalloc(priv->sh->ipool[MLX5_IPOOL_MCP], &idx); 4765 if (!mcp_res) { 4766 rte_errno = ENOMEM; 4767 return NULL; 4768 } 4769 mcp_res->idx = idx; 4770 mcp_res->mark_id = mark_id; 4771 /* 4772 * The copy Flows are not included in any list. There 4773 * ones are referenced from other Flows and can not 4774 * be applied, removed, deleted in arbitrary order 4775 * by list traversing. 4776 */ 4777 mcp_res->rix_flow = flow_list_create(dev, MLX5_FLOW_TYPE_MCP, 4778 &attr, items, actions, false, error); 4779 if (!mcp_res->rix_flow) { 4780 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_MCP], idx); 4781 return NULL; 4782 } 4783 return &mcp_res->hlist_ent; 4784 } 4785 4786 struct mlx5_list_entry * 4787 flow_dv_mreg_clone_cb(void *tool_ctx, struct mlx5_list_entry *oentry, 4788 void *cb_ctx __rte_unused) 4789 { 4790 struct rte_eth_dev *dev = tool_ctx; 4791 struct mlx5_priv *priv = dev->data->dev_private; 4792 struct mlx5_flow_mreg_copy_resource *mcp_res; 4793 uint32_t idx = 0; 4794 4795 mcp_res = mlx5_ipool_malloc(priv->sh->ipool[MLX5_IPOOL_MCP], &idx); 4796 if (!mcp_res) { 4797 rte_errno = ENOMEM; 4798 return NULL; 4799 } 4800 memcpy(mcp_res, oentry, sizeof(*mcp_res)); 4801 mcp_res->idx = idx; 4802 return &mcp_res->hlist_ent; 4803 } 4804 4805 void 4806 flow_dv_mreg_clone_free_cb(void *tool_ctx, struct mlx5_list_entry *entry) 4807 { 4808 struct mlx5_flow_mreg_copy_resource *mcp_res = 4809 container_of(entry, typeof(*mcp_res), hlist_ent); 4810 struct rte_eth_dev *dev = tool_ctx; 4811 struct mlx5_priv *priv = dev->data->dev_private; 4812 4813 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_MCP], mcp_res->idx); 4814 } 4815 4816 /** 4817 * Add a flow of copying flow metadata registers in RX_CP_TBL. 4818 * 4819 * As mark_id is unique, if there's already a registered flow for the mark_id, 4820 * return by increasing the reference counter of the resource. Otherwise, create 4821 * the resource (mcp_res) and flow. 4822 * 4823 * Flow looks like, 4824 * - If ingress port is ANY and reg_c[1] is mark_id, 4825 * flow_tag := mark_id, reg_b := reg_c[0] and jump to RX_ACT_TBL. 4826 * 4827 * For default flow (zero mark_id), flow is like, 4828 * - If ingress port is ANY, 4829 * reg_b := reg_c[0] and jump to RX_ACT_TBL. 4830 * 4831 * @param dev 4832 * Pointer to Ethernet device. 4833 * @param mark_id 4834 * ID of MARK action, zero means default flow for META. 4835 * @param[out] error 4836 * Perform verbose error reporting if not NULL. 4837 * 4838 * @return 4839 * Associated resource on success, NULL otherwise and rte_errno is set. 4840 */ 4841 static struct mlx5_flow_mreg_copy_resource * 4842 flow_mreg_add_copy_action(struct rte_eth_dev *dev, uint32_t mark_id, 4843 struct rte_flow_error *error) 4844 { 4845 struct mlx5_priv *priv = dev->data->dev_private; 4846 struct mlx5_list_entry *entry; 4847 struct mlx5_flow_cb_ctx ctx = { 4848 .dev = dev, 4849 .error = error, 4850 .data = &mark_id, 4851 }; 4852 4853 /* Check if already registered. */ 4854 MLX5_ASSERT(priv->mreg_cp_tbl); 4855 entry = mlx5_hlist_register(priv->mreg_cp_tbl, mark_id, &ctx); 4856 if (!entry) 4857 return NULL; 4858 return container_of(entry, struct mlx5_flow_mreg_copy_resource, 4859 hlist_ent); 4860 } 4861 4862 void 4863 flow_dv_mreg_remove_cb(void *tool_ctx, struct mlx5_list_entry *entry) 4864 { 4865 struct mlx5_flow_mreg_copy_resource *mcp_res = 4866 container_of(entry, typeof(*mcp_res), hlist_ent); 4867 struct rte_eth_dev *dev = tool_ctx; 4868 struct mlx5_priv *priv = dev->data->dev_private; 4869 4870 MLX5_ASSERT(mcp_res->rix_flow); 4871 flow_list_destroy(dev, MLX5_FLOW_TYPE_MCP, mcp_res->rix_flow); 4872 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_MCP], mcp_res->idx); 4873 } 4874 4875 /** 4876 * Release flow in RX_CP_TBL. 4877 * 4878 * @param dev 4879 * Pointer to Ethernet device. 4880 * @flow 4881 * Parent flow for wich copying is provided. 4882 */ 4883 static void 4884 flow_mreg_del_copy_action(struct rte_eth_dev *dev, 4885 struct rte_flow *flow) 4886 { 4887 struct mlx5_flow_mreg_copy_resource *mcp_res; 4888 struct mlx5_priv *priv = dev->data->dev_private; 4889 4890 if (!flow->rix_mreg_copy) 4891 return; 4892 mcp_res = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_MCP], 4893 flow->rix_mreg_copy); 4894 if (!mcp_res || !priv->mreg_cp_tbl) 4895 return; 4896 MLX5_ASSERT(mcp_res->rix_flow); 4897 mlx5_hlist_unregister(priv->mreg_cp_tbl, &mcp_res->hlist_ent); 4898 flow->rix_mreg_copy = 0; 4899 } 4900 4901 /** 4902 * Remove the default copy action from RX_CP_TBL. 4903 * 4904 * This functions is called in the mlx5_dev_start(). No thread safe 4905 * is guaranteed. 4906 * 4907 * @param dev 4908 * Pointer to Ethernet device. 4909 */ 4910 static void 4911 flow_mreg_del_default_copy_action(struct rte_eth_dev *dev) 4912 { 4913 struct mlx5_list_entry *entry; 4914 struct mlx5_priv *priv = dev->data->dev_private; 4915 struct mlx5_flow_cb_ctx ctx; 4916 uint32_t mark_id; 4917 4918 /* Check if default flow is registered. */ 4919 if (!priv->mreg_cp_tbl) 4920 return; 4921 mark_id = MLX5_DEFAULT_COPY_ID; 4922 ctx.data = &mark_id; 4923 entry = mlx5_hlist_lookup(priv->mreg_cp_tbl, mark_id, &ctx); 4924 if (!entry) 4925 return; 4926 mlx5_hlist_unregister(priv->mreg_cp_tbl, entry); 4927 } 4928 4929 /** 4930 * Add the default copy action in in RX_CP_TBL. 4931 * 4932 * This functions is called in the mlx5_dev_start(). No thread safe 4933 * is guaranteed. 4934 * 4935 * @param dev 4936 * Pointer to Ethernet device. 4937 * @param[out] error 4938 * Perform verbose error reporting if not NULL. 4939 * 4940 * @return 4941 * 0 for success, negative value otherwise and rte_errno is set. 4942 */ 4943 static int 4944 flow_mreg_add_default_copy_action(struct rte_eth_dev *dev, 4945 struct rte_flow_error *error) 4946 { 4947 struct mlx5_priv *priv = dev->data->dev_private; 4948 struct mlx5_flow_mreg_copy_resource *mcp_res; 4949 struct mlx5_flow_cb_ctx ctx; 4950 uint32_t mark_id; 4951 4952 /* Check whether extensive metadata feature is engaged. */ 4953 if (!priv->sh->config.dv_flow_en || 4954 priv->sh->config.dv_xmeta_en == MLX5_XMETA_MODE_LEGACY || 4955 !mlx5_flow_ext_mreg_supported(dev) || 4956 !priv->sh->dv_regc0_mask) 4957 return 0; 4958 /* 4959 * Add default mreg copy flow may be called multiple time, but 4960 * only be called once in stop. Avoid register it twice. 4961 */ 4962 mark_id = MLX5_DEFAULT_COPY_ID; 4963 ctx.data = &mark_id; 4964 if (mlx5_hlist_lookup(priv->mreg_cp_tbl, mark_id, &ctx)) 4965 return 0; 4966 mcp_res = flow_mreg_add_copy_action(dev, mark_id, error); 4967 if (!mcp_res) 4968 return -rte_errno; 4969 return 0; 4970 } 4971 4972 /** 4973 * Add a flow of copying flow metadata registers in RX_CP_TBL. 4974 * 4975 * All the flow having Q/RSS action should be split by 4976 * flow_mreg_split_qrss_prep() to pass by RX_CP_TBL. A flow in the RX_CP_TBL 4977 * performs the following, 4978 * - CQE->flow_tag := reg_c[1] (MARK) 4979 * - CQE->flow_table_metadata (reg_b) := reg_c[0] (META) 4980 * As CQE's flow_tag is not a register, it can't be simply copied from reg_c[1] 4981 * but there should be a flow per each MARK ID set by MARK action. 4982 * 4983 * For the aforementioned reason, if there's a MARK action in flow's action 4984 * list, a corresponding flow should be added to the RX_CP_TBL in order to copy 4985 * the MARK ID to CQE's flow_tag like, 4986 * - If reg_c[1] is mark_id, 4987 * flow_tag := mark_id, reg_b := reg_c[0] and jump to RX_ACT_TBL. 4988 * 4989 * For SET_META action which stores value in reg_c[0], as the destination is 4990 * also a flow metadata register (reg_b), adding a default flow is enough. Zero 4991 * MARK ID means the default flow. The default flow looks like, 4992 * - For all flow, reg_b := reg_c[0] and jump to RX_ACT_TBL. 4993 * 4994 * @param dev 4995 * Pointer to Ethernet device. 4996 * @param flow 4997 * Pointer to flow structure. 4998 * @param[in] actions 4999 * Pointer to the list of actions. 5000 * @param[out] error 5001 * Perform verbose error reporting if not NULL. 5002 * 5003 * @return 5004 * 0 on success, negative value otherwise and rte_errno is set. 5005 */ 5006 static int 5007 flow_mreg_update_copy_table(struct rte_eth_dev *dev, 5008 struct rte_flow *flow, 5009 const struct rte_flow_action *actions, 5010 struct rte_flow_error *error) 5011 { 5012 struct mlx5_priv *priv = dev->data->dev_private; 5013 struct mlx5_sh_config *config = &priv->sh->config; 5014 struct mlx5_flow_mreg_copy_resource *mcp_res; 5015 const struct rte_flow_action_mark *mark; 5016 5017 /* Check whether extensive metadata feature is engaged. */ 5018 if (!config->dv_flow_en || 5019 config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY || 5020 !mlx5_flow_ext_mreg_supported(dev) || 5021 !priv->sh->dv_regc0_mask) 5022 return 0; 5023 /* Find MARK action. */ 5024 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) { 5025 switch (actions->type) { 5026 case RTE_FLOW_ACTION_TYPE_FLAG: 5027 mcp_res = flow_mreg_add_copy_action 5028 (dev, MLX5_FLOW_MARK_DEFAULT, error); 5029 if (!mcp_res) 5030 return -rte_errno; 5031 flow->rix_mreg_copy = mcp_res->idx; 5032 return 0; 5033 case RTE_FLOW_ACTION_TYPE_MARK: 5034 mark = (const struct rte_flow_action_mark *) 5035 actions->conf; 5036 mcp_res = 5037 flow_mreg_add_copy_action(dev, mark->id, error); 5038 if (!mcp_res) 5039 return -rte_errno; 5040 flow->rix_mreg_copy = mcp_res->idx; 5041 return 0; 5042 default: 5043 break; 5044 } 5045 } 5046 return 0; 5047 } 5048 5049 #define MLX5_MAX_SPLIT_ACTIONS 24 5050 #define MLX5_MAX_SPLIT_ITEMS 24 5051 5052 /** 5053 * Split the hairpin flow. 5054 * Since HW can't support encap and push-vlan on Rx, we move these 5055 * actions to Tx. 5056 * If the count action is after the encap then we also 5057 * move the count action. in this case the count will also measure 5058 * the outer bytes. 5059 * 5060 * @param dev 5061 * Pointer to Ethernet device. 5062 * @param[in] actions 5063 * Associated actions (list terminated by the END action). 5064 * @param[out] actions_rx 5065 * Rx flow actions. 5066 * @param[out] actions_tx 5067 * Tx flow actions.. 5068 * @param[out] pattern_tx 5069 * The pattern items for the Tx flow. 5070 * @param[out] flow_id 5071 * The flow ID connected to this flow. 5072 * 5073 * @return 5074 * 0 on success. 5075 */ 5076 static int 5077 flow_hairpin_split(struct rte_eth_dev *dev, 5078 const struct rte_flow_action actions[], 5079 struct rte_flow_action actions_rx[], 5080 struct rte_flow_action actions_tx[], 5081 struct rte_flow_item pattern_tx[], 5082 uint32_t flow_id) 5083 { 5084 const struct rte_flow_action_raw_encap *raw_encap; 5085 const struct rte_flow_action_raw_decap *raw_decap; 5086 struct mlx5_rte_flow_action_set_tag *set_tag; 5087 struct rte_flow_action *tag_action; 5088 struct mlx5_rte_flow_item_tag *tag_item; 5089 struct rte_flow_item *item; 5090 char *addr; 5091 int encap = 0; 5092 5093 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) { 5094 switch (actions->type) { 5095 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP: 5096 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP: 5097 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN: 5098 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID: 5099 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP: 5100 rte_memcpy(actions_tx, actions, 5101 sizeof(struct rte_flow_action)); 5102 actions_tx++; 5103 break; 5104 case RTE_FLOW_ACTION_TYPE_COUNT: 5105 if (encap) { 5106 rte_memcpy(actions_tx, actions, 5107 sizeof(struct rte_flow_action)); 5108 actions_tx++; 5109 } else { 5110 rte_memcpy(actions_rx, actions, 5111 sizeof(struct rte_flow_action)); 5112 actions_rx++; 5113 } 5114 break; 5115 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP: 5116 raw_encap = actions->conf; 5117 if (raw_encap->size > MLX5_ENCAPSULATION_DECISION_SIZE) { 5118 memcpy(actions_tx, actions, 5119 sizeof(struct rte_flow_action)); 5120 actions_tx++; 5121 encap = 1; 5122 } else { 5123 rte_memcpy(actions_rx, actions, 5124 sizeof(struct rte_flow_action)); 5125 actions_rx++; 5126 } 5127 break; 5128 case RTE_FLOW_ACTION_TYPE_RAW_DECAP: 5129 raw_decap = actions->conf; 5130 if (raw_decap->size < MLX5_ENCAPSULATION_DECISION_SIZE) { 5131 memcpy(actions_tx, actions, 5132 sizeof(struct rte_flow_action)); 5133 actions_tx++; 5134 } else { 5135 rte_memcpy(actions_rx, actions, 5136 sizeof(struct rte_flow_action)); 5137 actions_rx++; 5138 } 5139 break; 5140 default: 5141 rte_memcpy(actions_rx, actions, 5142 sizeof(struct rte_flow_action)); 5143 actions_rx++; 5144 break; 5145 } 5146 } 5147 /* Add set meta action and end action for the Rx flow. */ 5148 tag_action = actions_rx; 5149 tag_action->type = (enum rte_flow_action_type) 5150 MLX5_RTE_FLOW_ACTION_TYPE_TAG; 5151 actions_rx++; 5152 rte_memcpy(actions_rx, actions, sizeof(struct rte_flow_action)); 5153 actions_rx++; 5154 set_tag = (void *)actions_rx; 5155 *set_tag = (struct mlx5_rte_flow_action_set_tag) { 5156 .id = mlx5_flow_get_reg_id(dev, MLX5_HAIRPIN_RX, 0, NULL), 5157 .data = flow_id, 5158 }; 5159 MLX5_ASSERT(set_tag->id > REG_NON); 5160 tag_action->conf = set_tag; 5161 /* Create Tx item list. */ 5162 rte_memcpy(actions_tx, actions, sizeof(struct rte_flow_action)); 5163 addr = (void *)&pattern_tx[2]; 5164 item = pattern_tx; 5165 item->type = (enum rte_flow_item_type) 5166 MLX5_RTE_FLOW_ITEM_TYPE_TAG; 5167 tag_item = (void *)addr; 5168 tag_item->data = flow_id; 5169 tag_item->id = mlx5_flow_get_reg_id(dev, MLX5_HAIRPIN_TX, 0, NULL); 5170 MLX5_ASSERT(set_tag->id > REG_NON); 5171 item->spec = tag_item; 5172 addr += sizeof(struct mlx5_rte_flow_item_tag); 5173 tag_item = (void *)addr; 5174 tag_item->data = UINT32_MAX; 5175 tag_item->id = UINT16_MAX; 5176 item->mask = tag_item; 5177 item->last = NULL; 5178 item++; 5179 item->type = RTE_FLOW_ITEM_TYPE_END; 5180 return 0; 5181 } 5182 5183 /** 5184 * The last stage of splitting chain, just creates the subflow 5185 * without any modification. 5186 * 5187 * @param[in] dev 5188 * Pointer to Ethernet device. 5189 * @param[in] flow 5190 * Parent flow structure pointer. 5191 * @param[in, out] sub_flow 5192 * Pointer to return the created subflow, may be NULL. 5193 * @param[in] attr 5194 * Flow rule attributes. 5195 * @param[in] items 5196 * Pattern specification (list terminated by the END pattern item). 5197 * @param[in] actions 5198 * Associated actions (list terminated by the END action). 5199 * @param[in] flow_split_info 5200 * Pointer to flow split info structure. 5201 * @param[out] error 5202 * Perform verbose error reporting if not NULL. 5203 * @return 5204 * 0 on success, negative value otherwise 5205 */ 5206 static int 5207 flow_create_split_inner(struct rte_eth_dev *dev, 5208 struct rte_flow *flow, 5209 struct mlx5_flow **sub_flow, 5210 const struct rte_flow_attr *attr, 5211 const struct rte_flow_item items[], 5212 const struct rte_flow_action actions[], 5213 struct mlx5_flow_split_info *flow_split_info, 5214 struct rte_flow_error *error) 5215 { 5216 struct mlx5_flow *dev_flow; 5217 struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace(); 5218 5219 dev_flow = flow_drv_prepare(dev, flow, attr, items, actions, 5220 flow_split_info->flow_idx, error); 5221 if (!dev_flow) 5222 return -rte_errno; 5223 dev_flow->flow = flow; 5224 dev_flow->external = flow_split_info->external; 5225 dev_flow->skip_scale = flow_split_info->skip_scale; 5226 /* Subflow object was created, we must include one in the list. */ 5227 SILIST_INSERT(&flow->dev_handles, dev_flow->handle_idx, 5228 dev_flow->handle, next); 5229 /* 5230 * If dev_flow is as one of the suffix flow, some actions in suffix 5231 * flow may need some user defined item layer flags, and pass the 5232 * Metadata rxq mark flag to suffix flow as well. 5233 */ 5234 if (flow_split_info->prefix_layers) 5235 dev_flow->handle->layers = flow_split_info->prefix_layers; 5236 if (flow_split_info->prefix_mark) { 5237 MLX5_ASSERT(wks); 5238 wks->mark = 1; 5239 } 5240 if (sub_flow) 5241 *sub_flow = dev_flow; 5242 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 5243 dev_flow->dv.table_id = flow_split_info->table_id; 5244 #endif 5245 return flow_drv_translate(dev, dev_flow, attr, items, actions, error); 5246 } 5247 5248 /** 5249 * Get the sub policy of a meter. 5250 * 5251 * @param[in] dev 5252 * Pointer to Ethernet device. 5253 * @param[in] flow 5254 * Parent flow structure pointer. 5255 * @param wks 5256 * Pointer to thread flow work space. 5257 * @param[in] attr 5258 * Flow rule attributes. 5259 * @param[in] items 5260 * Pattern specification (list terminated by the END pattern item). 5261 * @param[out] error 5262 * Perform verbose error reporting if not NULL. 5263 * 5264 * @return 5265 * Pointer to the meter sub policy, NULL otherwise and rte_errno is set. 5266 */ 5267 static struct mlx5_flow_meter_sub_policy * 5268 get_meter_sub_policy(struct rte_eth_dev *dev, 5269 struct rte_flow *flow, 5270 struct mlx5_flow_workspace *wks, 5271 const struct rte_flow_attr *attr, 5272 const struct rte_flow_item items[], 5273 struct rte_flow_error *error) 5274 { 5275 struct mlx5_flow_meter_policy *policy; 5276 struct mlx5_flow_meter_policy *final_policy; 5277 struct mlx5_flow_meter_sub_policy *sub_policy = NULL; 5278 5279 policy = wks->policy; 5280 final_policy = policy->is_hierarchy ? wks->final_policy : policy; 5281 if (final_policy->is_rss || final_policy->is_queue) { 5282 struct mlx5_flow_rss_desc rss_desc_v[MLX5_MTR_RTE_COLORS]; 5283 struct mlx5_flow_rss_desc *rss_desc[MLX5_MTR_RTE_COLORS] = {0}; 5284 uint32_t i; 5285 5286 /* 5287 * This is a tmp dev_flow, 5288 * no need to register any matcher for it in translate. 5289 */ 5290 wks->skip_matcher_reg = 1; 5291 for (i = 0; i < MLX5_MTR_RTE_COLORS; i++) { 5292 struct mlx5_flow dev_flow = {0}; 5293 struct mlx5_flow_handle dev_handle = { {0} }; 5294 uint8_t fate = final_policy->act_cnt[i].fate_action; 5295 5296 if (fate == MLX5_FLOW_FATE_SHARED_RSS) { 5297 const struct rte_flow_action_rss *rss_act = 5298 final_policy->act_cnt[i].rss->conf; 5299 struct rte_flow_action rss_actions[2] = { 5300 [0] = { 5301 .type = RTE_FLOW_ACTION_TYPE_RSS, 5302 .conf = rss_act, 5303 }, 5304 [1] = { 5305 .type = RTE_FLOW_ACTION_TYPE_END, 5306 .conf = NULL, 5307 } 5308 }; 5309 5310 dev_flow.handle = &dev_handle; 5311 dev_flow.ingress = attr->ingress; 5312 dev_flow.flow = flow; 5313 dev_flow.external = 0; 5314 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 5315 dev_flow.dv.transfer = attr->transfer; 5316 #endif 5317 /** 5318 * Translate RSS action to get rss hash fields. 5319 */ 5320 if (flow_drv_translate(dev, &dev_flow, attr, 5321 items, rss_actions, error)) 5322 goto exit; 5323 rss_desc_v[i] = wks->rss_desc; 5324 rss_desc_v[i].key_len = MLX5_RSS_HASH_KEY_LEN; 5325 rss_desc_v[i].hash_fields = 5326 dev_flow.hash_fields; 5327 rss_desc_v[i].queue_num = 5328 rss_desc_v[i].hash_fields ? 5329 rss_desc_v[i].queue_num : 1; 5330 rss_desc_v[i].tunnel = 5331 !!(dev_flow.handle->layers & 5332 MLX5_FLOW_LAYER_TUNNEL); 5333 /* Use the RSS queues in the containers. */ 5334 rss_desc_v[i].queue = 5335 (uint16_t *)(uintptr_t)rss_act->queue; 5336 rss_desc[i] = &rss_desc_v[i]; 5337 } else if (fate == MLX5_FLOW_FATE_QUEUE) { 5338 /* This is queue action. */ 5339 rss_desc_v[i] = wks->rss_desc; 5340 rss_desc_v[i].key_len = 0; 5341 rss_desc_v[i].hash_fields = 0; 5342 rss_desc_v[i].queue = 5343 &final_policy->act_cnt[i].queue; 5344 rss_desc_v[i].queue_num = 1; 5345 rss_desc[i] = &rss_desc_v[i]; 5346 } else { 5347 rss_desc[i] = NULL; 5348 } 5349 } 5350 sub_policy = flow_drv_meter_sub_policy_rss_prepare(dev, 5351 flow, policy, rss_desc); 5352 } else { 5353 enum mlx5_meter_domain mtr_domain = 5354 attr->transfer ? MLX5_MTR_DOMAIN_TRANSFER : 5355 (attr->egress ? MLX5_MTR_DOMAIN_EGRESS : 5356 MLX5_MTR_DOMAIN_INGRESS); 5357 sub_policy = policy->sub_policys[mtr_domain][0]; 5358 } 5359 if (!sub_policy) 5360 rte_flow_error_set(error, EINVAL, 5361 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, 5362 "Failed to get meter sub-policy."); 5363 exit: 5364 return sub_policy; 5365 } 5366 5367 /** 5368 * Split the meter flow. 5369 * 5370 * As meter flow will split to three sub flow, other than meter 5371 * action, the other actions make sense to only meter accepts 5372 * the packet. If it need to be dropped, no other additional 5373 * actions should be take. 5374 * 5375 * One kind of special action which decapsulates the L3 tunnel 5376 * header will be in the prefix sub flow, as not to take the 5377 * L3 tunnel header into account. 5378 * 5379 * @param[in] dev 5380 * Pointer to Ethernet device. 5381 * @param[in] flow 5382 * Parent flow structure pointer. 5383 * @param wks 5384 * Pointer to thread flow work space. 5385 * @param[in] attr 5386 * Flow rule attributes. 5387 * @param[in] items 5388 * Pattern specification (list terminated by the END pattern item). 5389 * @param[out] sfx_items 5390 * Suffix flow match items (list terminated by the END pattern item). 5391 * @param[in] actions 5392 * Associated actions (list terminated by the END action). 5393 * @param[out] actions_sfx 5394 * Suffix flow actions. 5395 * @param[out] actions_pre 5396 * Prefix flow actions. 5397 * @param[out] mtr_flow_id 5398 * Pointer to meter flow id. 5399 * @param[out] error 5400 * Perform verbose error reporting if not NULL. 5401 * 5402 * @return 5403 * 0 on success, a negative errno value otherwise and rte_errno is set. 5404 */ 5405 static int 5406 flow_meter_split_prep(struct rte_eth_dev *dev, 5407 struct rte_flow *flow, 5408 struct mlx5_flow_workspace *wks, 5409 const struct rte_flow_attr *attr, 5410 const struct rte_flow_item items[], 5411 struct rte_flow_item sfx_items[], 5412 const struct rte_flow_action actions[], 5413 struct rte_flow_action actions_sfx[], 5414 struct rte_flow_action actions_pre[], 5415 uint32_t *mtr_flow_id, 5416 struct rte_flow_error *error) 5417 { 5418 struct mlx5_priv *priv = dev->data->dev_private; 5419 struct mlx5_flow_meter_info *fm = wks->fm; 5420 struct rte_flow_action *tag_action = NULL; 5421 struct rte_flow_item *tag_item; 5422 struct mlx5_rte_flow_action_set_tag *set_tag; 5423 const struct rte_flow_action_raw_encap *raw_encap; 5424 const struct rte_flow_action_raw_decap *raw_decap; 5425 struct mlx5_rte_flow_item_tag *tag_item_spec; 5426 struct mlx5_rte_flow_item_tag *tag_item_mask; 5427 uint32_t tag_id = 0; 5428 struct rte_flow_item *vlan_item_dst = NULL; 5429 const struct rte_flow_item *vlan_item_src = NULL; 5430 const struct rte_flow_item *orig_items = items; 5431 struct rte_flow_action *hw_mtr_action; 5432 struct rte_flow_action *action_pre_head = NULL; 5433 uint16_t flow_src_port = priv->representor_id; 5434 bool mtr_first; 5435 uint8_t mtr_id_offset = priv->mtr_reg_share ? MLX5_MTR_COLOR_BITS : 0; 5436 uint8_t mtr_reg_bits = priv->mtr_reg_share ? 5437 MLX5_MTR_IDLE_BITS_IN_COLOR_REG : MLX5_REG_BITS; 5438 uint32_t flow_id = 0; 5439 uint32_t flow_id_reversed = 0; 5440 uint8_t flow_id_bits = 0; 5441 bool after_meter = false; 5442 int shift; 5443 5444 /* Prepare the suffix subflow items. */ 5445 tag_item = sfx_items++; 5446 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) { 5447 int item_type = items->type; 5448 5449 switch (item_type) { 5450 case RTE_FLOW_ITEM_TYPE_PORT_ID: 5451 case RTE_FLOW_ITEM_TYPE_REPRESENTED_PORT: 5452 if (mlx5_flow_get_item_vport_id(dev, items, &flow_src_port, NULL, error)) 5453 return -rte_errno; 5454 if (!fm->def_policy && wks->policy->is_hierarchy && 5455 flow_src_port != priv->representor_id) { 5456 if (flow_drv_mtr_hierarchy_rule_create(dev, 5457 flow, fm, 5458 flow_src_port, 5459 items, 5460 error)) 5461 return -rte_errno; 5462 } 5463 memcpy(sfx_items, items, sizeof(*sfx_items)); 5464 sfx_items++; 5465 break; 5466 case RTE_FLOW_ITEM_TYPE_PORT_REPRESENTOR: 5467 flow_src_port = 0; 5468 memcpy(sfx_items, items, sizeof(*sfx_items)); 5469 sfx_items++; 5470 break; 5471 case RTE_FLOW_ITEM_TYPE_VLAN: 5472 /* Determine if copy vlan item below. */ 5473 vlan_item_src = items; 5474 vlan_item_dst = sfx_items++; 5475 vlan_item_dst->type = RTE_FLOW_ITEM_TYPE_VOID; 5476 break; 5477 default: 5478 break; 5479 } 5480 } 5481 sfx_items->type = RTE_FLOW_ITEM_TYPE_END; 5482 sfx_items++; 5483 mtr_first = priv->sh->meter_aso_en && 5484 (attr->egress || (attr->transfer && flow_src_port != UINT16_MAX)); 5485 /* For ASO meter, meter must be before tag in TX direction. */ 5486 if (mtr_first) { 5487 action_pre_head = actions_pre++; 5488 /* Leave space for tag action. */ 5489 tag_action = actions_pre++; 5490 } 5491 /* Prepare the actions for prefix and suffix flow. */ 5492 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) { 5493 struct rte_flow_action *action_cur = NULL; 5494 5495 switch (actions->type) { 5496 case RTE_FLOW_ACTION_TYPE_METER: 5497 if (mtr_first) { 5498 action_cur = action_pre_head; 5499 } else { 5500 /* Leave space for tag action. */ 5501 tag_action = actions_pre++; 5502 action_cur = actions_pre++; 5503 } 5504 after_meter = true; 5505 break; 5506 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP: 5507 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP: 5508 action_cur = actions_pre++; 5509 break; 5510 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP: 5511 raw_encap = actions->conf; 5512 if (raw_encap->size < MLX5_ENCAPSULATION_DECISION_SIZE) 5513 action_cur = actions_pre++; 5514 break; 5515 case RTE_FLOW_ACTION_TYPE_RAW_DECAP: 5516 raw_decap = actions->conf; 5517 if (raw_decap->size > MLX5_ENCAPSULATION_DECISION_SIZE) 5518 action_cur = actions_pre++; 5519 break; 5520 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN: 5521 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID: 5522 if (vlan_item_dst && vlan_item_src) { 5523 memcpy(vlan_item_dst, vlan_item_src, 5524 sizeof(*vlan_item_dst)); 5525 /* 5526 * Convert to internal match item, it is used 5527 * for vlan push and set vid. 5528 */ 5529 vlan_item_dst->type = (enum rte_flow_item_type) 5530 MLX5_RTE_FLOW_ITEM_TYPE_VLAN; 5531 } 5532 break; 5533 case RTE_FLOW_ACTION_TYPE_COUNT: 5534 if (fm->def_policy) 5535 action_cur = after_meter ? 5536 actions_sfx++ : actions_pre++; 5537 break; 5538 default: 5539 break; 5540 } 5541 if (!action_cur) 5542 action_cur = (fm->def_policy) ? 5543 actions_sfx++ : actions_pre++; 5544 memcpy(action_cur, actions, sizeof(struct rte_flow_action)); 5545 } 5546 /* Add end action to the actions. */ 5547 actions_sfx->type = RTE_FLOW_ACTION_TYPE_END; 5548 if (priv->sh->meter_aso_en) { 5549 /** 5550 * For ASO meter, need to add an extra jump action explicitly, 5551 * to jump from meter to policer table. 5552 */ 5553 struct mlx5_flow_meter_sub_policy *sub_policy; 5554 struct mlx5_flow_tbl_data_entry *tbl_data; 5555 5556 if (!fm->def_policy) { 5557 sub_policy = get_meter_sub_policy(dev, flow, wks, 5558 attr, orig_items, 5559 error); 5560 if (!sub_policy) 5561 return -rte_errno; 5562 } else { 5563 enum mlx5_meter_domain mtr_domain = 5564 attr->transfer ? MLX5_MTR_DOMAIN_TRANSFER : 5565 (attr->egress ? MLX5_MTR_DOMAIN_EGRESS : 5566 MLX5_MTR_DOMAIN_INGRESS); 5567 5568 sub_policy = 5569 &priv->sh->mtrmng->def_policy[mtr_domain]->sub_policy; 5570 } 5571 tbl_data = container_of(sub_policy->tbl_rsc, 5572 struct mlx5_flow_tbl_data_entry, tbl); 5573 hw_mtr_action = actions_pre++; 5574 hw_mtr_action->type = (enum rte_flow_action_type) 5575 MLX5_RTE_FLOW_ACTION_TYPE_JUMP; 5576 hw_mtr_action->conf = tbl_data->jump.action; 5577 } 5578 actions_pre->type = RTE_FLOW_ACTION_TYPE_END; 5579 actions_pre++; 5580 if (!tag_action) 5581 return rte_flow_error_set(error, ENOMEM, 5582 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, 5583 NULL, "No tag action space."); 5584 if (!mtr_flow_id) { 5585 tag_action->type = RTE_FLOW_ACTION_TYPE_VOID; 5586 goto exit; 5587 } 5588 /* Only default-policy Meter creates mtr flow id. */ 5589 if (fm->def_policy) { 5590 mlx5_ipool_malloc(fm->flow_ipool, &tag_id); 5591 if (!tag_id) 5592 return rte_flow_error_set(error, ENOMEM, 5593 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, 5594 "Failed to allocate meter flow id."); 5595 flow_id = tag_id - 1; 5596 flow_id_bits = (!flow_id) ? 1 : 5597 (MLX5_REG_BITS - __builtin_clz(flow_id)); 5598 if ((flow_id_bits + priv->sh->mtrmng->max_mtr_bits) > 5599 mtr_reg_bits) { 5600 mlx5_ipool_free(fm->flow_ipool, tag_id); 5601 return rte_flow_error_set(error, EINVAL, 5602 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, 5603 "Meter flow id exceeds max limit."); 5604 } 5605 if (flow_id_bits > priv->sh->mtrmng->max_mtr_flow_bits) 5606 priv->sh->mtrmng->max_mtr_flow_bits = flow_id_bits; 5607 } 5608 /* Build tag actions and items for meter_id/meter flow_id. */ 5609 set_tag = (struct mlx5_rte_flow_action_set_tag *)actions_pre; 5610 tag_item_spec = (struct mlx5_rte_flow_item_tag *)sfx_items; 5611 tag_item_mask = tag_item_spec + 1; 5612 /* Both flow_id and meter_id share the same register. */ 5613 *set_tag = (struct mlx5_rte_flow_action_set_tag) { 5614 .id = (enum modify_reg)mlx5_flow_get_reg_id(dev, MLX5_MTR_ID, 5615 0, error), 5616 .offset = mtr_id_offset, 5617 .length = mtr_reg_bits, 5618 .data = flow->meter, 5619 }; 5620 /* 5621 * The color Reg bits used by flow_id are growing from 5622 * msb to lsb, so must do bit reverse for flow_id val in RegC. 5623 */ 5624 for (shift = 0; shift < flow_id_bits; shift++) 5625 flow_id_reversed = (flow_id_reversed << 1) | 5626 ((flow_id >> shift) & 0x1); 5627 set_tag->data |= 5628 flow_id_reversed << (mtr_reg_bits - flow_id_bits); 5629 tag_item_spec->id = set_tag->id; 5630 tag_item_spec->data = set_tag->data << mtr_id_offset; 5631 tag_item_mask->data = UINT32_MAX << mtr_id_offset; 5632 tag_action->type = (enum rte_flow_action_type) 5633 MLX5_RTE_FLOW_ACTION_TYPE_TAG; 5634 tag_action->conf = set_tag; 5635 tag_item->type = (enum rte_flow_item_type) 5636 MLX5_RTE_FLOW_ITEM_TYPE_TAG; 5637 tag_item->spec = tag_item_spec; 5638 tag_item->last = NULL; 5639 tag_item->mask = tag_item_mask; 5640 exit: 5641 if (mtr_flow_id) 5642 *mtr_flow_id = tag_id; 5643 return 0; 5644 } 5645 5646 /** 5647 * Split action list having QUEUE/RSS for metadata register copy. 5648 * 5649 * Once Q/RSS action is detected in user's action list, the flow action 5650 * should be split in order to copy metadata registers, which will happen in 5651 * RX_CP_TBL like, 5652 * - CQE->flow_tag := reg_c[1] (MARK) 5653 * - CQE->flow_table_metadata (reg_b) := reg_c[0] (META) 5654 * The Q/RSS action will be performed on RX_ACT_TBL after passing by RX_CP_TBL. 5655 * This is because the last action of each flow must be a terminal action 5656 * (QUEUE, RSS or DROP). 5657 * 5658 * Flow ID must be allocated to identify actions in the RX_ACT_TBL and it is 5659 * stored and kept in the mlx5_flow structure per each sub_flow. 5660 * 5661 * The Q/RSS action is replaced with, 5662 * - SET_TAG, setting the allocated flow ID to reg_c[2]. 5663 * And the following JUMP action is added at the end, 5664 * - JUMP, to RX_CP_TBL. 5665 * 5666 * A flow to perform remained Q/RSS action will be created in RX_ACT_TBL by 5667 * flow_create_split_metadata() routine. The flow will look like, 5668 * - If flow ID matches (reg_c[2]), perform Q/RSS. 5669 * 5670 * @param dev 5671 * Pointer to Ethernet device. 5672 * @param[out] split_actions 5673 * Pointer to store split actions to jump to CP_TBL. 5674 * @param[in] actions 5675 * Pointer to the list of original flow actions. 5676 * @param[in] qrss 5677 * Pointer to the Q/RSS action. 5678 * @param[in] actions_n 5679 * Number of original actions. 5680 * @param[in] mtr_sfx 5681 * Check if it is in meter suffix table. 5682 * @param[out] error 5683 * Perform verbose error reporting if not NULL. 5684 * 5685 * @return 5686 * non-zero unique flow_id on success, otherwise 0 and 5687 * error/rte_error are set. 5688 */ 5689 static uint32_t 5690 flow_mreg_split_qrss_prep(struct rte_eth_dev *dev, 5691 struct rte_flow_action *split_actions, 5692 const struct rte_flow_action *actions, 5693 const struct rte_flow_action *qrss, 5694 int actions_n, int mtr_sfx, 5695 struct rte_flow_error *error) 5696 { 5697 struct mlx5_priv *priv = dev->data->dev_private; 5698 struct mlx5_rte_flow_action_set_tag *set_tag; 5699 struct rte_flow_action_jump *jump; 5700 const int qrss_idx = qrss - actions; 5701 uint32_t flow_id = 0; 5702 int ret = 0; 5703 5704 /* 5705 * Given actions will be split 5706 * - Replace QUEUE/RSS action with SET_TAG to set flow ID. 5707 * - Add jump to mreg CP_TBL. 5708 * As a result, there will be one more action. 5709 */ 5710 memcpy(split_actions, actions, sizeof(*split_actions) * actions_n); 5711 /* Count MLX5_RTE_FLOW_ACTION_TYPE_TAG. */ 5712 ++actions_n; 5713 set_tag = (void *)(split_actions + actions_n); 5714 /* 5715 * If we are not the meter suffix flow, add the tag action. 5716 * Since meter suffix flow already has the tag added. 5717 */ 5718 if (!mtr_sfx) { 5719 /* 5720 * Allocate the new subflow ID. This one is unique within 5721 * device and not shared with representors. Otherwise, 5722 * we would have to resolve multi-thread access synch 5723 * issue. Each flow on the shared device is appended 5724 * with source vport identifier, so the resulting 5725 * flows will be unique in the shared (by master and 5726 * representors) domain even if they have coinciding 5727 * IDs. 5728 */ 5729 mlx5_ipool_malloc(priv->sh->ipool 5730 [MLX5_IPOOL_RSS_EXPANTION_FLOW_ID], &flow_id); 5731 if (!flow_id) 5732 return rte_flow_error_set(error, ENOMEM, 5733 RTE_FLOW_ERROR_TYPE_ACTION, 5734 NULL, "can't allocate id " 5735 "for split Q/RSS subflow"); 5736 /* Internal SET_TAG action to set flow ID. */ 5737 *set_tag = (struct mlx5_rte_flow_action_set_tag){ 5738 .data = flow_id, 5739 }; 5740 ret = mlx5_flow_get_reg_id(dev, MLX5_COPY_MARK, 0, error); 5741 if (ret < 0) 5742 return ret; 5743 set_tag->id = ret; 5744 /* Construct new actions array. */ 5745 /* Replace QUEUE/RSS action. */ 5746 split_actions[qrss_idx] = (struct rte_flow_action){ 5747 .type = (enum rte_flow_action_type) 5748 MLX5_RTE_FLOW_ACTION_TYPE_TAG, 5749 .conf = set_tag, 5750 }; 5751 } else { 5752 /* 5753 * If we are the suffix flow of meter, tag already exist. 5754 * Set the QUEUE/RSS action to void. 5755 */ 5756 split_actions[qrss_idx].type = RTE_FLOW_ACTION_TYPE_VOID; 5757 } 5758 /* JUMP action to jump to mreg copy table (CP_TBL). */ 5759 jump = (void *)(set_tag + 1); 5760 *jump = (struct rte_flow_action_jump){ 5761 .group = MLX5_FLOW_MREG_CP_TABLE_GROUP, 5762 }; 5763 split_actions[actions_n - 2] = (struct rte_flow_action){ 5764 .type = RTE_FLOW_ACTION_TYPE_JUMP, 5765 .conf = jump, 5766 }; 5767 split_actions[actions_n - 1] = (struct rte_flow_action){ 5768 .type = RTE_FLOW_ACTION_TYPE_END, 5769 }; 5770 return flow_id; 5771 } 5772 5773 /** 5774 * Extend the given action list for Tx metadata copy. 5775 * 5776 * Copy the given action list to the ext_actions and add flow metadata register 5777 * copy action in order to copy reg_a set by WQE to reg_c[0]. 5778 * 5779 * @param[out] ext_actions 5780 * Pointer to the extended action list. 5781 * @param[in] actions 5782 * Pointer to the list of actions. 5783 * @param[in] actions_n 5784 * Number of actions in the list. 5785 * @param[out] error 5786 * Perform verbose error reporting if not NULL. 5787 * @param[in] encap_idx 5788 * The encap action index. 5789 * 5790 * @return 5791 * 0 on success, negative value otherwise 5792 */ 5793 static int 5794 flow_mreg_tx_copy_prep(struct rte_eth_dev *dev, 5795 struct rte_flow_action *ext_actions, 5796 const struct rte_flow_action *actions, 5797 int actions_n, struct rte_flow_error *error, 5798 int encap_idx) 5799 { 5800 struct mlx5_flow_action_copy_mreg *cp_mreg = 5801 (struct mlx5_flow_action_copy_mreg *) 5802 (ext_actions + actions_n + 1); 5803 int ret; 5804 5805 ret = mlx5_flow_get_reg_id(dev, MLX5_METADATA_RX, 0, error); 5806 if (ret < 0) 5807 return ret; 5808 cp_mreg->dst = ret; 5809 ret = mlx5_flow_get_reg_id(dev, MLX5_METADATA_TX, 0, error); 5810 if (ret < 0) 5811 return ret; 5812 cp_mreg->src = ret; 5813 if (encap_idx != 0) 5814 memcpy(ext_actions, actions, sizeof(*ext_actions) * encap_idx); 5815 if (encap_idx == actions_n - 1) { 5816 ext_actions[actions_n - 1] = (struct rte_flow_action){ 5817 .type = (enum rte_flow_action_type) 5818 MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG, 5819 .conf = cp_mreg, 5820 }; 5821 ext_actions[actions_n] = (struct rte_flow_action){ 5822 .type = RTE_FLOW_ACTION_TYPE_END, 5823 }; 5824 } else { 5825 ext_actions[encap_idx] = (struct rte_flow_action){ 5826 .type = (enum rte_flow_action_type) 5827 MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG, 5828 .conf = cp_mreg, 5829 }; 5830 memcpy(ext_actions + encap_idx + 1, actions + encap_idx, 5831 sizeof(*ext_actions) * (actions_n - encap_idx)); 5832 } 5833 return 0; 5834 } 5835 5836 /** 5837 * Check the match action from the action list. 5838 * 5839 * @param[in] actions 5840 * Pointer to the list of actions. 5841 * @param[in] attr 5842 * Flow rule attributes. 5843 * @param[in] action 5844 * The action to be check if exist. 5845 * @param[out] match_action_pos 5846 * Pointer to the position of the matched action if exists, otherwise is -1. 5847 * @param[out] qrss_action_pos 5848 * Pointer to the position of the Queue/RSS action if exists, otherwise is -1. 5849 * @param[out] modify_after_mirror 5850 * Pointer to the flag of modify action after FDB mirroring. 5851 * 5852 * @return 5853 * > 0 the total number of actions. 5854 * 0 if not found match action in action list. 5855 */ 5856 static int 5857 flow_check_match_action(const struct rte_flow_action actions[], 5858 const struct rte_flow_attr *attr, 5859 enum rte_flow_action_type action, 5860 int *match_action_pos, int *qrss_action_pos, 5861 int *modify_after_mirror) 5862 { 5863 const struct rte_flow_action_sample *sample; 5864 const struct rte_flow_action_raw_decap *decap; 5865 int actions_n = 0; 5866 uint32_t ratio = 0; 5867 int sub_type = 0; 5868 int flag = 0; 5869 int fdb_mirror = 0; 5870 5871 *match_action_pos = -1; 5872 *qrss_action_pos = -1; 5873 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) { 5874 if (actions->type == action) { 5875 flag = 1; 5876 *match_action_pos = actions_n; 5877 } 5878 switch (actions->type) { 5879 case RTE_FLOW_ACTION_TYPE_QUEUE: 5880 case RTE_FLOW_ACTION_TYPE_RSS: 5881 *qrss_action_pos = actions_n; 5882 break; 5883 case RTE_FLOW_ACTION_TYPE_SAMPLE: 5884 sample = actions->conf; 5885 ratio = sample->ratio; 5886 sub_type = ((const struct rte_flow_action *) 5887 (sample->actions))->type; 5888 if (ratio == 1 && attr->transfer && 5889 sub_type != RTE_FLOW_ACTION_TYPE_END) 5890 fdb_mirror = 1; 5891 break; 5892 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC: 5893 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST: 5894 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC: 5895 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST: 5896 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC: 5897 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST: 5898 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC: 5899 case RTE_FLOW_ACTION_TYPE_SET_TP_DST: 5900 case RTE_FLOW_ACTION_TYPE_DEC_TTL: 5901 case RTE_FLOW_ACTION_TYPE_SET_TTL: 5902 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ: 5903 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ: 5904 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK: 5905 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK: 5906 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP: 5907 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP: 5908 case RTE_FLOW_ACTION_TYPE_FLAG: 5909 case RTE_FLOW_ACTION_TYPE_MARK: 5910 case RTE_FLOW_ACTION_TYPE_SET_META: 5911 case RTE_FLOW_ACTION_TYPE_SET_TAG: 5912 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN: 5913 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN: 5914 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID: 5915 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP: 5916 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP: 5917 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP: 5918 case RTE_FLOW_ACTION_TYPE_MODIFY_FIELD: 5919 case RTE_FLOW_ACTION_TYPE_METER: 5920 if (fdb_mirror) 5921 *modify_after_mirror = 1; 5922 break; 5923 case RTE_FLOW_ACTION_TYPE_RAW_DECAP: 5924 decap = actions->conf; 5925 while ((++actions)->type == RTE_FLOW_ACTION_TYPE_VOID) 5926 ; 5927 actions_n++; 5928 if (actions->type == RTE_FLOW_ACTION_TYPE_RAW_ENCAP) { 5929 const struct rte_flow_action_raw_encap *encap = 5930 actions->conf; 5931 if (decap->size <= 5932 MLX5_ENCAPSULATION_DECISION_SIZE && 5933 encap->size > 5934 MLX5_ENCAPSULATION_DECISION_SIZE) 5935 /* L3 encap. */ 5936 break; 5937 } 5938 if (fdb_mirror) 5939 *modify_after_mirror = 1; 5940 break; 5941 default: 5942 break; 5943 } 5944 actions_n++; 5945 } 5946 if (flag && fdb_mirror && !*modify_after_mirror) { 5947 /* FDB mirroring uses the destination array to implement 5948 * instead of FLOW_SAMPLER object. 5949 */ 5950 if (sub_type != RTE_FLOW_ACTION_TYPE_END) 5951 flag = 0; 5952 } 5953 /* Count RTE_FLOW_ACTION_TYPE_END. */ 5954 return flag ? actions_n + 1 : 0; 5955 } 5956 5957 #define SAMPLE_SUFFIX_ITEM 3 5958 5959 /** 5960 * Split the sample flow. 5961 * 5962 * As sample flow will split to two sub flow, sample flow with 5963 * sample action, the other actions will move to new suffix flow. 5964 * 5965 * Also add unique tag id with tag action in the sample flow, 5966 * the same tag id will be as match in the suffix flow. 5967 * 5968 * @param dev 5969 * Pointer to Ethernet device. 5970 * @param[in] add_tag 5971 * Add extra tag action flag. 5972 * @param[out] sfx_items 5973 * Suffix flow match items (list terminated by the END pattern item). 5974 * @param[in] actions 5975 * Associated actions (list terminated by the END action). 5976 * @param[out] actions_sfx 5977 * Suffix flow actions. 5978 * @param[out] actions_pre 5979 * Prefix flow actions. 5980 * @param[in] actions_n 5981 * The total number of actions. 5982 * @param[in] sample_action_pos 5983 * The sample action position. 5984 * @param[in] qrss_action_pos 5985 * The Queue/RSS action position. 5986 * @param[in] jump_table 5987 * Add extra jump action flag. 5988 * @param[out] error 5989 * Perform verbose error reporting if not NULL. 5990 * 5991 * @return 5992 * 0 on success, or unique flow_id, a negative errno value 5993 * otherwise and rte_errno is set. 5994 */ 5995 static int 5996 flow_sample_split_prep(struct rte_eth_dev *dev, 5997 int add_tag, 5998 const struct rte_flow_item items[], 5999 struct rte_flow_item sfx_items[], 6000 const struct rte_flow_action actions[], 6001 struct rte_flow_action actions_sfx[], 6002 struct rte_flow_action actions_pre[], 6003 int actions_n, 6004 int sample_action_pos, 6005 int qrss_action_pos, 6006 int jump_table, 6007 struct rte_flow_error *error) 6008 { 6009 struct mlx5_priv *priv = dev->data->dev_private; 6010 struct mlx5_rte_flow_action_set_tag *set_tag; 6011 struct mlx5_rte_flow_item_tag *tag_spec; 6012 struct mlx5_rte_flow_item_tag *tag_mask; 6013 struct rte_flow_action_jump *jump_action; 6014 uint32_t tag_id = 0; 6015 int append_index = 0; 6016 int set_tag_idx = -1; 6017 int index; 6018 int ret; 6019 6020 if (sample_action_pos < 0) 6021 return rte_flow_error_set(error, EINVAL, 6022 RTE_FLOW_ERROR_TYPE_ACTION, 6023 NULL, "invalid position of sample " 6024 "action in list"); 6025 /* Prepare the actions for prefix and suffix flow. */ 6026 if (add_tag) { 6027 /* Update the new added tag action index preceding 6028 * the PUSH_VLAN or ENCAP action. 6029 */ 6030 const struct rte_flow_action_raw_encap *raw_encap; 6031 const struct rte_flow_action *action = actions; 6032 int encap_idx; 6033 int action_idx = 0; 6034 int raw_decap_idx = -1; 6035 int push_vlan_idx = -1; 6036 for (; action->type != RTE_FLOW_ACTION_TYPE_END; action++) { 6037 switch (action->type) { 6038 case RTE_FLOW_ACTION_TYPE_RAW_DECAP: 6039 raw_decap_idx = action_idx; 6040 break; 6041 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP: 6042 raw_encap = action->conf; 6043 if (raw_encap->size > 6044 MLX5_ENCAPSULATION_DECISION_SIZE) { 6045 encap_idx = raw_decap_idx != -1 ? 6046 raw_decap_idx : action_idx; 6047 if (encap_idx < sample_action_pos && 6048 push_vlan_idx == -1) 6049 set_tag_idx = encap_idx; 6050 } 6051 break; 6052 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP: 6053 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP: 6054 encap_idx = action_idx; 6055 if (encap_idx < sample_action_pos && 6056 push_vlan_idx == -1) 6057 set_tag_idx = encap_idx; 6058 break; 6059 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN: 6060 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID: 6061 if (action_idx < sample_action_pos && 6062 push_vlan_idx == -1) { 6063 set_tag_idx = action_idx; 6064 push_vlan_idx = action_idx; 6065 } 6066 break; 6067 default: 6068 break; 6069 } 6070 action_idx++; 6071 } 6072 } 6073 /* Prepare the actions for prefix and suffix flow. */ 6074 if (qrss_action_pos >= 0 && qrss_action_pos < sample_action_pos) { 6075 index = qrss_action_pos; 6076 /* Put the preceding the Queue/RSS action into prefix flow. */ 6077 if (index != 0) 6078 memcpy(actions_pre, actions, 6079 sizeof(struct rte_flow_action) * index); 6080 /* Put others preceding the sample action into prefix flow. */ 6081 if (sample_action_pos > index + 1) 6082 memcpy(actions_pre + index, actions + index + 1, 6083 sizeof(struct rte_flow_action) * 6084 (sample_action_pos - index - 1)); 6085 index = sample_action_pos - 1; 6086 /* Put Queue/RSS action into Suffix flow. */ 6087 memcpy(actions_sfx, actions + qrss_action_pos, 6088 sizeof(struct rte_flow_action)); 6089 actions_sfx++; 6090 } else if (add_tag && set_tag_idx >= 0) { 6091 if (set_tag_idx > 0) 6092 memcpy(actions_pre, actions, 6093 sizeof(struct rte_flow_action) * set_tag_idx); 6094 memcpy(actions_pre + set_tag_idx + 1, actions + set_tag_idx, 6095 sizeof(struct rte_flow_action) * 6096 (sample_action_pos - set_tag_idx)); 6097 index = sample_action_pos; 6098 } else { 6099 index = sample_action_pos; 6100 if (index != 0) 6101 memcpy(actions_pre, actions, 6102 sizeof(struct rte_flow_action) * index); 6103 } 6104 /* For CX5, add an extra tag action for NIC-RX and E-Switch ingress. 6105 * For CX6DX and above, metadata registers Cx preserve their value, 6106 * add an extra tag action for NIC-RX and E-Switch Domain. 6107 */ 6108 if (add_tag) { 6109 /* Prepare the prefix tag action. */ 6110 append_index++; 6111 set_tag = (void *)(actions_pre + actions_n + append_index); 6112 ret = mlx5_flow_get_reg_id(dev, MLX5_SAMPLE_ID, 0, error); 6113 /* Trust VF/SF on CX5 not supported meter so that the reserved 6114 * metadata regC is REG_NON, back to use application tag 6115 * index 0. 6116 */ 6117 if (unlikely(ret == REG_NON)) 6118 ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, 0, error); 6119 if (ret < 0) 6120 return ret; 6121 mlx5_ipool_malloc(priv->sh->ipool 6122 [MLX5_IPOOL_RSS_EXPANTION_FLOW_ID], &tag_id); 6123 *set_tag = (struct mlx5_rte_flow_action_set_tag) { 6124 .id = ret, 6125 .data = tag_id, 6126 }; 6127 /* Prepare the suffix subflow items. */ 6128 tag_spec = (void *)(sfx_items + SAMPLE_SUFFIX_ITEM); 6129 tag_spec->data = tag_id; 6130 tag_spec->id = set_tag->id; 6131 tag_mask = tag_spec + 1; 6132 tag_mask->data = UINT32_MAX; 6133 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) { 6134 if (items->type == RTE_FLOW_ITEM_TYPE_PORT_ID || 6135 items->type == RTE_FLOW_ITEM_TYPE_PORT_REPRESENTOR || 6136 items->type == RTE_FLOW_ITEM_TYPE_REPRESENTED_PORT) { 6137 memcpy(sfx_items, items, sizeof(*sfx_items)); 6138 sfx_items++; 6139 break; 6140 } 6141 } 6142 sfx_items[0] = (struct rte_flow_item){ 6143 .type = (enum rte_flow_item_type) 6144 MLX5_RTE_FLOW_ITEM_TYPE_TAG, 6145 .spec = tag_spec, 6146 .last = NULL, 6147 .mask = tag_mask, 6148 }; 6149 sfx_items[1] = (struct rte_flow_item){ 6150 .type = (enum rte_flow_item_type) 6151 RTE_FLOW_ITEM_TYPE_END, 6152 }; 6153 /* Prepare the tag action in prefix subflow. */ 6154 set_tag_idx = (set_tag_idx == -1) ? index : set_tag_idx; 6155 actions_pre[set_tag_idx] = 6156 (struct rte_flow_action){ 6157 .type = (enum rte_flow_action_type) 6158 MLX5_RTE_FLOW_ACTION_TYPE_TAG, 6159 .conf = set_tag, 6160 }; 6161 /* Update next sample position due to add one tag action */ 6162 index += 1; 6163 } 6164 /* Copy the sample action into prefix flow. */ 6165 memcpy(actions_pre + index, actions + sample_action_pos, 6166 sizeof(struct rte_flow_action)); 6167 index += 1; 6168 /* For the modify action after the sample action in E-Switch mirroring, 6169 * Add the extra jump action in prefix subflow and jump into the next 6170 * table, then do the modify action in the new table. 6171 */ 6172 if (jump_table) { 6173 /* Prepare the prefix jump action. */ 6174 append_index++; 6175 jump_action = (void *)(actions_pre + actions_n + append_index); 6176 jump_action->group = jump_table; 6177 actions_pre[index++] = 6178 (struct rte_flow_action){ 6179 .type = (enum rte_flow_action_type) 6180 RTE_FLOW_ACTION_TYPE_JUMP, 6181 .conf = jump_action, 6182 }; 6183 } 6184 actions_pre[index] = (struct rte_flow_action){ 6185 .type = (enum rte_flow_action_type) 6186 RTE_FLOW_ACTION_TYPE_END, 6187 }; 6188 /* Put the actions after sample into Suffix flow. */ 6189 memcpy(actions_sfx, actions + sample_action_pos + 1, 6190 sizeof(struct rte_flow_action) * 6191 (actions_n - sample_action_pos - 1)); 6192 return tag_id; 6193 } 6194 6195 /** 6196 * The splitting for metadata feature. 6197 * 6198 * - Q/RSS action on NIC Rx should be split in order to pass by 6199 * the mreg copy table (RX_CP_TBL) and then it jumps to the 6200 * action table (RX_ACT_TBL) which has the split Q/RSS action. 6201 * 6202 * - All the actions on NIC Tx should have a mreg copy action to 6203 * copy reg_a from WQE to reg_c[0]. 6204 * 6205 * @param dev 6206 * Pointer to Ethernet device. 6207 * @param[in] flow 6208 * Parent flow structure pointer. 6209 * @param[in] attr 6210 * Flow rule attributes. 6211 * @param[in] items 6212 * Pattern specification (list terminated by the END pattern item). 6213 * @param[in] actions 6214 * Associated actions (list terminated by the END action). 6215 * @param[in] flow_split_info 6216 * Pointer to flow split info structure. 6217 * @param[out] error 6218 * Perform verbose error reporting if not NULL. 6219 * @return 6220 * 0 on success, negative value otherwise 6221 */ 6222 static int 6223 flow_create_split_metadata(struct rte_eth_dev *dev, 6224 struct rte_flow *flow, 6225 const struct rte_flow_attr *attr, 6226 const struct rte_flow_item items[], 6227 const struct rte_flow_action actions[], 6228 struct mlx5_flow_split_info *flow_split_info, 6229 struct rte_flow_error *error) 6230 { 6231 struct mlx5_priv *priv = dev->data->dev_private; 6232 struct mlx5_sh_config *config = &priv->sh->config; 6233 const struct rte_flow_action *qrss = NULL; 6234 struct rte_flow_action *ext_actions = NULL; 6235 struct mlx5_flow *dev_flow = NULL; 6236 uint32_t qrss_id = 0; 6237 int mtr_sfx = 0; 6238 size_t act_size; 6239 int actions_n; 6240 int encap_idx; 6241 int ret; 6242 6243 /* Check whether extensive metadata feature is engaged. */ 6244 if (!config->dv_flow_en || 6245 config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY || 6246 !mlx5_flow_ext_mreg_supported(dev)) 6247 return flow_create_split_inner(dev, flow, NULL, attr, items, 6248 actions, flow_split_info, error); 6249 actions_n = flow_parse_metadata_split_actions_info(actions, &qrss, 6250 &encap_idx); 6251 if (qrss) { 6252 /* Exclude hairpin flows from splitting. */ 6253 if (qrss->type == RTE_FLOW_ACTION_TYPE_QUEUE) { 6254 const struct rte_flow_action_queue *queue; 6255 6256 queue = qrss->conf; 6257 if (mlx5_rxq_is_hairpin(dev, queue->index)) 6258 qrss = NULL; 6259 } else if (qrss->type == RTE_FLOW_ACTION_TYPE_RSS) { 6260 const struct rte_flow_action_rss *rss; 6261 6262 rss = qrss->conf; 6263 if (mlx5_rxq_is_hairpin(dev, rss->queue[0])) 6264 qrss = NULL; 6265 } 6266 } 6267 if (qrss) { 6268 /* Check if it is in meter suffix table. */ 6269 mtr_sfx = attr->group == 6270 ((attr->transfer && priv->fdb_def_rule) ? 6271 (MLX5_FLOW_TABLE_LEVEL_METER - 1) : 6272 MLX5_FLOW_TABLE_LEVEL_METER); 6273 /* 6274 * Q/RSS action on NIC Rx should be split in order to pass by 6275 * the mreg copy table (RX_CP_TBL) and then it jumps to the 6276 * action table (RX_ACT_TBL) which has the split Q/RSS action. 6277 */ 6278 act_size = sizeof(struct rte_flow_action) * (actions_n + 1) + 6279 sizeof(struct rte_flow_action_set_tag) + 6280 sizeof(struct rte_flow_action_jump); 6281 ext_actions = mlx5_malloc(MLX5_MEM_ZERO, act_size, 0, 6282 SOCKET_ID_ANY); 6283 if (!ext_actions) 6284 return rte_flow_error_set(error, ENOMEM, 6285 RTE_FLOW_ERROR_TYPE_ACTION, 6286 NULL, "no memory to split " 6287 "metadata flow"); 6288 /* 6289 * Create the new actions list with removed Q/RSS action 6290 * and appended set tag and jump to register copy table 6291 * (RX_CP_TBL). We should preallocate unique tag ID here 6292 * in advance, because it is needed for set tag action. 6293 */ 6294 qrss_id = flow_mreg_split_qrss_prep(dev, ext_actions, actions, 6295 qrss, actions_n, 6296 mtr_sfx, error); 6297 if (!mtr_sfx && !qrss_id) { 6298 ret = -rte_errno; 6299 goto exit; 6300 } 6301 } else if (attr->egress) { 6302 /* 6303 * All the actions on NIC Tx should have a metadata register 6304 * copy action to copy reg_a from WQE to reg_c[meta] 6305 */ 6306 act_size = sizeof(struct rte_flow_action) * (actions_n + 1) + 6307 sizeof(struct mlx5_flow_action_copy_mreg); 6308 ext_actions = mlx5_malloc(MLX5_MEM_ZERO, act_size, 0, 6309 SOCKET_ID_ANY); 6310 if (!ext_actions) 6311 return rte_flow_error_set(error, ENOMEM, 6312 RTE_FLOW_ERROR_TYPE_ACTION, 6313 NULL, "no memory to split " 6314 "metadata flow"); 6315 /* Create the action list appended with copy register. */ 6316 ret = flow_mreg_tx_copy_prep(dev, ext_actions, actions, 6317 actions_n, error, encap_idx); 6318 if (ret < 0) 6319 goto exit; 6320 } 6321 /* Add the unmodified original or prefix subflow. */ 6322 ret = flow_create_split_inner(dev, flow, &dev_flow, attr, 6323 items, ext_actions ? ext_actions : 6324 actions, flow_split_info, error); 6325 if (ret < 0) 6326 goto exit; 6327 MLX5_ASSERT(dev_flow); 6328 if (qrss) { 6329 const struct rte_flow_attr q_attr = { 6330 .group = MLX5_FLOW_MREG_ACT_TABLE_GROUP, 6331 .ingress = 1, 6332 }; 6333 /* Internal PMD action to set register. */ 6334 struct mlx5_rte_flow_item_tag q_tag_spec = { 6335 .data = qrss_id, 6336 .id = REG_NON, 6337 }; 6338 struct rte_flow_item q_items[] = { 6339 { 6340 .type = (enum rte_flow_item_type) 6341 MLX5_RTE_FLOW_ITEM_TYPE_TAG, 6342 .spec = &q_tag_spec, 6343 .last = NULL, 6344 .mask = NULL, 6345 }, 6346 { 6347 .type = RTE_FLOW_ITEM_TYPE_END, 6348 }, 6349 }; 6350 struct rte_flow_action q_actions[] = { 6351 { 6352 .type = qrss->type, 6353 .conf = qrss->conf, 6354 }, 6355 { 6356 .type = RTE_FLOW_ACTION_TYPE_END, 6357 }, 6358 }; 6359 uint64_t layers = flow_get_prefix_layer_flags(dev_flow); 6360 6361 /* 6362 * Configure the tag item only if there is no meter subflow. 6363 * Since tag is already marked in the meter suffix subflow 6364 * we can just use the meter suffix items as is. 6365 */ 6366 if (qrss_id) { 6367 /* Not meter subflow. */ 6368 MLX5_ASSERT(!mtr_sfx); 6369 /* 6370 * Put unique id in prefix flow due to it is destroyed 6371 * after suffix flow and id will be freed after there 6372 * is no actual flows with this id and identifier 6373 * reallocation becomes possible (for example, for 6374 * other flows in other threads). 6375 */ 6376 dev_flow->handle->split_flow_id = qrss_id; 6377 ret = mlx5_flow_get_reg_id(dev, MLX5_COPY_MARK, 0, 6378 error); 6379 if (ret < 0) 6380 goto exit; 6381 q_tag_spec.id = ret; 6382 } 6383 dev_flow = NULL; 6384 /* Add suffix subflow to execute Q/RSS. */ 6385 flow_split_info->prefix_layers = layers; 6386 flow_split_info->prefix_mark = 0; 6387 flow_split_info->table_id = 0; 6388 ret = flow_create_split_inner(dev, flow, &dev_flow, 6389 &q_attr, mtr_sfx ? items : 6390 q_items, q_actions, 6391 flow_split_info, error); 6392 if (ret < 0) 6393 goto exit; 6394 /* qrss ID should be freed if failed. */ 6395 qrss_id = 0; 6396 MLX5_ASSERT(dev_flow); 6397 } 6398 6399 exit: 6400 /* 6401 * We do not destroy the partially created sub_flows in case of error. 6402 * These ones are included into parent flow list and will be destroyed 6403 * by flow_drv_destroy. 6404 */ 6405 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_RSS_EXPANTION_FLOW_ID], 6406 qrss_id); 6407 mlx5_free(ext_actions); 6408 return ret; 6409 } 6410 6411 /** 6412 * Create meter internal drop flow with the original pattern. 6413 * 6414 * @param dev 6415 * Pointer to Ethernet device. 6416 * @param[in] flow 6417 * Parent flow structure pointer. 6418 * @param[in] attr 6419 * Flow rule attributes. 6420 * @param[in] items 6421 * Pattern specification (list terminated by the END pattern item). 6422 * @param[in] flow_split_info 6423 * Pointer to flow split info structure. 6424 * @param[in] fm 6425 * Pointer to flow meter structure. 6426 * @param[out] error 6427 * Perform verbose error reporting if not NULL. 6428 * @return 6429 * 0 on success, negative value otherwise 6430 */ 6431 static uint32_t 6432 flow_meter_create_drop_flow_with_org_pattern(struct rte_eth_dev *dev, 6433 struct rte_flow *flow, 6434 const struct rte_flow_attr *attr, 6435 const struct rte_flow_item items[], 6436 struct mlx5_flow_split_info *flow_split_info, 6437 struct mlx5_flow_meter_info *fm, 6438 struct rte_flow_error *error) 6439 { 6440 struct mlx5_flow *dev_flow = NULL; 6441 struct rte_flow_attr drop_attr = *attr; 6442 struct rte_flow_action drop_actions[3]; 6443 struct mlx5_flow_split_info drop_split_info = *flow_split_info; 6444 6445 MLX5_ASSERT(fm->drop_cnt); 6446 drop_actions[0].type = 6447 (enum rte_flow_action_type)MLX5_RTE_FLOW_ACTION_TYPE_COUNT; 6448 drop_actions[0].conf = (void *)(uintptr_t)fm->drop_cnt; 6449 drop_actions[1].type = RTE_FLOW_ACTION_TYPE_DROP; 6450 drop_actions[1].conf = NULL; 6451 drop_actions[2].type = RTE_FLOW_ACTION_TYPE_END; 6452 drop_actions[2].conf = NULL; 6453 drop_split_info.external = false; 6454 drop_split_info.skip_scale |= 1 << MLX5_SCALE_FLOW_GROUP_BIT; 6455 drop_split_info.table_id = MLX5_MTR_TABLE_ID_DROP; 6456 drop_attr.group = MLX5_FLOW_TABLE_LEVEL_METER; 6457 return flow_create_split_inner(dev, flow, &dev_flow, 6458 &drop_attr, items, drop_actions, 6459 &drop_split_info, error); 6460 } 6461 6462 /** 6463 * The splitting for meter feature. 6464 * 6465 * - The meter flow will be split to two flows as prefix and 6466 * suffix flow. The packets make sense only it pass the prefix 6467 * meter action. 6468 * 6469 * - Reg_C_5 is used for the packet to match betweend prefix and 6470 * suffix flow. 6471 * 6472 * @param dev 6473 * Pointer to Ethernet device. 6474 * @param[in] flow 6475 * Parent flow structure pointer. 6476 * @param[in] attr 6477 * Flow rule attributes. 6478 * @param[in] items 6479 * Pattern specification (list terminated by the END pattern item). 6480 * @param[in] actions 6481 * Associated actions (list terminated by the END action). 6482 * @param[in] flow_split_info 6483 * Pointer to flow split info structure. 6484 * @param[out] error 6485 * Perform verbose error reporting if not NULL. 6486 * @return 6487 * 0 on success, negative value otherwise 6488 */ 6489 static int 6490 flow_create_split_meter(struct rte_eth_dev *dev, 6491 struct rte_flow *flow, 6492 const struct rte_flow_attr *attr, 6493 const struct rte_flow_item items[], 6494 const struct rte_flow_action actions[], 6495 struct mlx5_flow_split_info *flow_split_info, 6496 struct rte_flow_error *error) 6497 { 6498 struct mlx5_priv *priv = dev->data->dev_private; 6499 struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace(); 6500 struct rte_flow_action *sfx_actions = NULL; 6501 struct rte_flow_action *pre_actions = NULL; 6502 struct rte_flow_item *sfx_items = NULL; 6503 struct mlx5_flow *dev_flow = NULL; 6504 struct rte_flow_attr sfx_attr = *attr; 6505 struct mlx5_flow_meter_info *fm = NULL; 6506 uint8_t skip_scale_restore; 6507 bool has_mtr = false; 6508 bool has_modify = false; 6509 bool set_mtr_reg = true; 6510 bool is_mtr_hierarchy = false; 6511 uint32_t meter_id = 0; 6512 uint32_t mtr_idx = 0; 6513 uint32_t mtr_flow_id = 0; 6514 size_t act_size; 6515 size_t item_size; 6516 int actions_n = 0; 6517 int ret = 0; 6518 6519 if (priv->mtr_en) 6520 actions_n = flow_check_meter_action(dev, actions, &has_mtr, 6521 &has_modify, &meter_id); 6522 if (has_mtr) { 6523 if (flow->meter) { 6524 fm = flow_dv_meter_find_by_idx(priv, flow->meter); 6525 if (!fm) 6526 return rte_flow_error_set(error, EINVAL, 6527 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, 6528 NULL, "Meter not found."); 6529 } else { 6530 fm = mlx5_flow_meter_find(priv, meter_id, &mtr_idx); 6531 if (!fm) 6532 return rte_flow_error_set(error, EINVAL, 6533 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, 6534 NULL, "Meter not found."); 6535 ret = mlx5_flow_meter_attach(priv, fm, 6536 &sfx_attr, error); 6537 if (ret) 6538 return -rte_errno; 6539 flow->meter = mtr_idx; 6540 } 6541 MLX5_ASSERT(wks); 6542 wks->fm = fm; 6543 if (!fm->def_policy) { 6544 wks->policy = mlx5_flow_meter_policy_find(dev, 6545 fm->policy_id, 6546 NULL); 6547 MLX5_ASSERT(wks->policy); 6548 if (wks->policy->mark) 6549 wks->mark = 1; 6550 if (wks->policy->is_hierarchy) { 6551 wks->final_policy = 6552 mlx5_flow_meter_hierarchy_get_final_policy(dev, 6553 wks->policy); 6554 if (!wks->final_policy) 6555 return rte_flow_error_set(error, 6556 EINVAL, 6557 RTE_FLOW_ERROR_TYPE_ACTION, NULL, 6558 "Failed to find terminal policy of hierarchy."); 6559 is_mtr_hierarchy = true; 6560 } 6561 } 6562 /* 6563 * If it isn't default-policy Meter, and 6564 * 1. Not meter hierarchy and there's no action in flow to change 6565 * packet (modify/encap/decap etc.), OR 6566 * 2. No drop count needed for this meter. 6567 * Then no need to use regC to save meter id anymore. 6568 */ 6569 if (!fm->def_policy && ((!has_modify && !is_mtr_hierarchy) || !fm->drop_cnt)) 6570 set_mtr_reg = false; 6571 /* Prefix actions: meter, decap, encap, tag, jump, end, cnt. */ 6572 #define METER_PREFIX_ACTION 7 6573 act_size = (sizeof(struct rte_flow_action) * 6574 (actions_n + METER_PREFIX_ACTION)) + 6575 sizeof(struct mlx5_rte_flow_action_set_tag); 6576 /* Suffix items: tag, vlan, port id, end. */ 6577 #define METER_SUFFIX_ITEM 4 6578 item_size = sizeof(struct rte_flow_item) * METER_SUFFIX_ITEM + 6579 sizeof(struct mlx5_rte_flow_item_tag) * 2; 6580 sfx_actions = mlx5_malloc(MLX5_MEM_ZERO, (act_size + item_size), 6581 0, SOCKET_ID_ANY); 6582 if (!sfx_actions) 6583 return rte_flow_error_set(error, ENOMEM, 6584 RTE_FLOW_ERROR_TYPE_ACTION, 6585 NULL, "no memory to split " 6586 "meter flow"); 6587 sfx_items = (struct rte_flow_item *)((char *)sfx_actions + 6588 act_size); 6589 /* There's no suffix flow for meter of non-default policy. */ 6590 if (!fm->def_policy) 6591 pre_actions = sfx_actions + 1; 6592 else 6593 pre_actions = sfx_actions + actions_n; 6594 ret = flow_meter_split_prep(dev, flow, wks, &sfx_attr, 6595 items, sfx_items, actions, 6596 sfx_actions, pre_actions, 6597 (set_mtr_reg ? &mtr_flow_id : NULL), 6598 error); 6599 if (ret) { 6600 ret = -rte_errno; 6601 goto exit; 6602 } 6603 /* Add the prefix subflow. */ 6604 skip_scale_restore = flow_split_info->skip_scale; 6605 flow_split_info->skip_scale |= 6606 1 << MLX5_SCALE_JUMP_FLOW_GROUP_BIT; 6607 ret = flow_create_split_inner(dev, flow, &dev_flow, 6608 attr, items, pre_actions, 6609 flow_split_info, error); 6610 flow_split_info->skip_scale = skip_scale_restore; 6611 if (ret) { 6612 if (mtr_flow_id) 6613 mlx5_ipool_free(fm->flow_ipool, mtr_flow_id); 6614 ret = -rte_errno; 6615 goto exit; 6616 } 6617 if (mtr_flow_id) { 6618 dev_flow->handle->split_flow_id = mtr_flow_id; 6619 dev_flow->handle->is_meter_flow_id = 1; 6620 } 6621 if (!fm->def_policy) { 6622 if (!set_mtr_reg && fm->drop_cnt) 6623 ret = 6624 flow_meter_create_drop_flow_with_org_pattern(dev, flow, 6625 &sfx_attr, items, 6626 flow_split_info, 6627 fm, error); 6628 goto exit; 6629 } 6630 /* Setting the sfx group atrr. */ 6631 sfx_attr.group = sfx_attr.transfer ? 6632 (MLX5_FLOW_TABLE_LEVEL_METER - 1) : 6633 MLX5_FLOW_TABLE_LEVEL_METER; 6634 flow_split_info->prefix_layers = 6635 flow_get_prefix_layer_flags(dev_flow); 6636 flow_split_info->prefix_mark |= wks->mark; 6637 flow_split_info->table_id = MLX5_MTR_TABLE_ID_SUFFIX; 6638 } 6639 /* Add the prefix subflow. */ 6640 ret = flow_create_split_metadata(dev, flow, 6641 &sfx_attr, sfx_items ? 6642 sfx_items : items, 6643 sfx_actions ? sfx_actions : actions, 6644 flow_split_info, error); 6645 exit: 6646 if (sfx_actions) 6647 mlx5_free(sfx_actions); 6648 return ret; 6649 } 6650 6651 /** 6652 * The splitting for sample feature. 6653 * 6654 * Once Sample action is detected in the action list, the flow actions should 6655 * be split into prefix sub flow and suffix sub flow. 6656 * 6657 * The original items remain in the prefix sub flow, all actions preceding the 6658 * sample action and the sample action itself will be copied to the prefix 6659 * sub flow, the actions following the sample action will be copied to the 6660 * suffix sub flow, Queue action always be located in the suffix sub flow. 6661 * 6662 * In order to make the packet from prefix sub flow matches with suffix sub 6663 * flow, an extra tag action be added into prefix sub flow, and the suffix sub 6664 * flow uses tag item with the unique flow id. 6665 * 6666 * @param dev 6667 * Pointer to Ethernet device. 6668 * @param[in] flow 6669 * Parent flow structure pointer. 6670 * @param[in] attr 6671 * Flow rule attributes. 6672 * @param[in] items 6673 * Pattern specification (list terminated by the END pattern item). 6674 * @param[in] actions 6675 * Associated actions (list terminated by the END action). 6676 * @param[in] flow_split_info 6677 * Pointer to flow split info structure. 6678 * @param[out] error 6679 * Perform verbose error reporting if not NULL. 6680 * @return 6681 * 0 on success, negative value otherwise 6682 */ 6683 static int 6684 flow_create_split_sample(struct rte_eth_dev *dev, 6685 struct rte_flow *flow, 6686 const struct rte_flow_attr *attr, 6687 const struct rte_flow_item items[], 6688 const struct rte_flow_action actions[], 6689 struct mlx5_flow_split_info *flow_split_info, 6690 struct rte_flow_error *error) 6691 { 6692 struct mlx5_priv *priv = dev->data->dev_private; 6693 struct rte_flow_action *sfx_actions = NULL; 6694 struct rte_flow_action *pre_actions = NULL; 6695 struct rte_flow_item *sfx_items = NULL; 6696 struct mlx5_flow *dev_flow = NULL; 6697 struct rte_flow_attr sfx_attr = *attr; 6698 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 6699 struct mlx5_flow_dv_sample_resource *sample_res; 6700 struct mlx5_flow_tbl_data_entry *sfx_tbl_data; 6701 struct mlx5_flow_tbl_resource *sfx_tbl; 6702 struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace(); 6703 #endif 6704 size_t act_size; 6705 size_t item_size; 6706 uint32_t fdb_tx = 0; 6707 int32_t tag_id = 0; 6708 int actions_n = 0; 6709 int sample_action_pos; 6710 int qrss_action_pos; 6711 int add_tag = 0; 6712 int modify_after_mirror = 0; 6713 uint16_t jump_table = 0; 6714 const uint32_t next_ft_step = 1; 6715 int ret = 0; 6716 struct mlx5_priv *item_port_priv = NULL; 6717 const struct rte_flow_item *item; 6718 6719 if (priv->sampler_en) 6720 actions_n = flow_check_match_action(actions, attr, 6721 RTE_FLOW_ACTION_TYPE_SAMPLE, 6722 &sample_action_pos, &qrss_action_pos, 6723 &modify_after_mirror); 6724 if (actions_n) { 6725 /* The prefix actions must includes sample, tag, end. */ 6726 act_size = sizeof(struct rte_flow_action) * (actions_n * 2 + 1) 6727 + sizeof(struct mlx5_rte_flow_action_set_tag); 6728 item_size = sizeof(struct rte_flow_item) * SAMPLE_SUFFIX_ITEM + 6729 sizeof(struct mlx5_rte_flow_item_tag) * 2; 6730 sfx_actions = mlx5_malloc(MLX5_MEM_ZERO, (act_size + 6731 item_size), 0, SOCKET_ID_ANY); 6732 if (!sfx_actions) 6733 return rte_flow_error_set(error, ENOMEM, 6734 RTE_FLOW_ERROR_TYPE_ACTION, 6735 NULL, "no memory to split " 6736 "sample flow"); 6737 for (item = items; item->type != RTE_FLOW_ITEM_TYPE_END; item++) { 6738 if (item->type == RTE_FLOW_ITEM_TYPE_PORT_ID) { 6739 const struct rte_flow_item_port_id *spec; 6740 6741 spec = (const struct rte_flow_item_port_id *)item->spec; 6742 if (spec) 6743 item_port_priv = 6744 mlx5_port_to_eswitch_info(spec->id, true); 6745 break; 6746 } else if (item->type == RTE_FLOW_ITEM_TYPE_REPRESENTED_PORT) { 6747 const struct rte_flow_item_ethdev *spec; 6748 6749 spec = (const struct rte_flow_item_ethdev *)item->spec; 6750 if (spec) 6751 item_port_priv = 6752 mlx5_port_to_eswitch_info(spec->port_id, true); 6753 break; 6754 } else if (item->type == RTE_FLOW_ITEM_TYPE_PORT_REPRESENTOR) { 6755 const struct rte_flow_item_ethdev *spec; 6756 6757 spec = (const struct rte_flow_item_ethdev *)item->spec; 6758 if (spec) 6759 item_port_priv = 6760 mlx5_port_to_eswitch_info(spec->port_id, true); 6761 break; 6762 } 6763 } 6764 /* The representor_id is UINT16_MAX for uplink. */ 6765 fdb_tx = (attr->transfer && 6766 flow_source_vport_representor(priv, item_port_priv)); 6767 /* 6768 * When reg_c_preserve is set, metadata registers Cx preserve 6769 * their value even through packet duplication. 6770 */ 6771 add_tag = (!fdb_tx || 6772 priv->sh->cdev->config.hca_attr.reg_c_preserve); 6773 if (add_tag) 6774 sfx_items = (struct rte_flow_item *)((char *)sfx_actions 6775 + act_size); 6776 if (modify_after_mirror) 6777 jump_table = attr->group * MLX5_FLOW_TABLE_FACTOR + 6778 next_ft_step; 6779 pre_actions = sfx_actions + actions_n; 6780 tag_id = flow_sample_split_prep(dev, add_tag, items, sfx_items, 6781 actions, sfx_actions, 6782 pre_actions, actions_n, 6783 sample_action_pos, 6784 qrss_action_pos, jump_table, 6785 error); 6786 if (tag_id < 0 || (add_tag && !tag_id)) { 6787 ret = -rte_errno; 6788 goto exit; 6789 } 6790 if (modify_after_mirror) 6791 flow_split_info->skip_scale = 6792 1 << MLX5_SCALE_JUMP_FLOW_GROUP_BIT; 6793 /* Add the prefix subflow. */ 6794 ret = flow_create_split_inner(dev, flow, &dev_flow, attr, 6795 items, pre_actions, 6796 flow_split_info, error); 6797 if (ret) { 6798 ret = -rte_errno; 6799 goto exit; 6800 } 6801 dev_flow->handle->split_flow_id = tag_id; 6802 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 6803 if (!modify_after_mirror) { 6804 /* Set the sfx group attr. */ 6805 sample_res = (struct mlx5_flow_dv_sample_resource *) 6806 dev_flow->dv.sample_res; 6807 sfx_tbl = (struct mlx5_flow_tbl_resource *) 6808 sample_res->normal_path_tbl; 6809 sfx_tbl_data = container_of(sfx_tbl, 6810 struct mlx5_flow_tbl_data_entry, 6811 tbl); 6812 sfx_attr.group = sfx_attr.transfer ? 6813 (sfx_tbl_data->level - 1) : sfx_tbl_data->level; 6814 } else { 6815 MLX5_ASSERT(attr->transfer); 6816 sfx_attr.group = jump_table; 6817 } 6818 flow_split_info->prefix_layers = 6819 flow_get_prefix_layer_flags(dev_flow); 6820 MLX5_ASSERT(wks); 6821 flow_split_info->prefix_mark |= wks->mark; 6822 /* Suffix group level already be scaled with factor, set 6823 * MLX5_SCALE_FLOW_GROUP_BIT of skip_scale to 1 to avoid scale 6824 * again in translation. 6825 */ 6826 flow_split_info->skip_scale = 1 << MLX5_SCALE_FLOW_GROUP_BIT; 6827 #endif 6828 } 6829 /* Add the suffix subflow. */ 6830 ret = flow_create_split_meter(dev, flow, &sfx_attr, 6831 sfx_items ? sfx_items : items, 6832 sfx_actions ? sfx_actions : actions, 6833 flow_split_info, error); 6834 exit: 6835 if (sfx_actions) 6836 mlx5_free(sfx_actions); 6837 return ret; 6838 } 6839 6840 /** 6841 * Split the flow to subflow set. The splitters might be linked 6842 * in the chain, like this: 6843 * flow_create_split_outer() calls: 6844 * flow_create_split_meter() calls: 6845 * flow_create_split_metadata(meter_subflow_0) calls: 6846 * flow_create_split_inner(metadata_subflow_0) 6847 * flow_create_split_inner(metadata_subflow_1) 6848 * flow_create_split_inner(metadata_subflow_2) 6849 * flow_create_split_metadata(meter_subflow_1) calls: 6850 * flow_create_split_inner(metadata_subflow_0) 6851 * flow_create_split_inner(metadata_subflow_1) 6852 * flow_create_split_inner(metadata_subflow_2) 6853 * 6854 * This provide flexible way to add new levels of flow splitting. 6855 * The all of successfully created subflows are included to the 6856 * parent flow dev_flow list. 6857 * 6858 * @param dev 6859 * Pointer to Ethernet device. 6860 * @param[in] flow 6861 * Parent flow structure pointer. 6862 * @param[in] attr 6863 * Flow rule attributes. 6864 * @param[in] items 6865 * Pattern specification (list terminated by the END pattern item). 6866 * @param[in] actions 6867 * Associated actions (list terminated by the END action). 6868 * @param[in] flow_split_info 6869 * Pointer to flow split info structure. 6870 * @param[out] error 6871 * Perform verbose error reporting if not NULL. 6872 * @return 6873 * 0 on success, negative value otherwise 6874 */ 6875 static int 6876 flow_create_split_outer(struct rte_eth_dev *dev, 6877 struct rte_flow *flow, 6878 const struct rte_flow_attr *attr, 6879 const struct rte_flow_item items[], 6880 const struct rte_flow_action actions[], 6881 struct mlx5_flow_split_info *flow_split_info, 6882 struct rte_flow_error *error) 6883 { 6884 int ret; 6885 6886 ret = flow_create_split_sample(dev, flow, attr, items, 6887 actions, flow_split_info, error); 6888 MLX5_ASSERT(ret <= 0); 6889 return ret; 6890 } 6891 6892 static inline struct mlx5_flow_tunnel * 6893 flow_tunnel_from_rule(const struct mlx5_flow *flow) 6894 { 6895 struct mlx5_flow_tunnel *tunnel; 6896 6897 #pragma GCC diagnostic push 6898 #pragma GCC diagnostic ignored "-Wcast-qual" 6899 tunnel = (typeof(tunnel))flow->tunnel; 6900 #pragma GCC diagnostic pop 6901 6902 return tunnel; 6903 } 6904 6905 /** 6906 * Adjust flow RSS workspace if needed. 6907 * 6908 * @param wks 6909 * Pointer to thread flow work space. 6910 * @param rss_desc 6911 * Pointer to RSS descriptor. 6912 * @param[in] nrssq_num 6913 * New RSS queue number. 6914 * 6915 * @return 6916 * 0 on success, -1 otherwise and rte_errno is set. 6917 */ 6918 static int 6919 flow_rss_workspace_adjust(struct mlx5_flow_workspace *wks, 6920 struct mlx5_flow_rss_desc *rss_desc, 6921 uint32_t nrssq_num) 6922 { 6923 if (likely(nrssq_num <= wks->rssq_num)) 6924 return 0; 6925 rss_desc->queue = realloc(rss_desc->queue, 6926 sizeof(*rss_desc->queue) * RTE_ALIGN(nrssq_num, 2)); 6927 if (!rss_desc->queue) { 6928 rte_errno = ENOMEM; 6929 return -1; 6930 } 6931 wks->rssq_num = RTE_ALIGN(nrssq_num, 2); 6932 return 0; 6933 } 6934 6935 /** 6936 * Create a flow and add it to @p list. 6937 * 6938 * @param dev 6939 * Pointer to Ethernet device. 6940 * @param list 6941 * Pointer to a TAILQ flow list. If this parameter NULL, 6942 * no list insertion occurred, flow is just created, 6943 * this is caller's responsibility to track the 6944 * created flow. 6945 * @param[in] attr 6946 * Flow rule attributes. 6947 * @param[in] items 6948 * Pattern specification (list terminated by the END pattern item). 6949 * @param[in] actions 6950 * Associated actions (list terminated by the END action). 6951 * @param[in] external 6952 * This flow rule is created by request external to PMD. 6953 * @param[out] error 6954 * Perform verbose error reporting if not NULL. 6955 * 6956 * @return 6957 * A flow index on success, 0 otherwise and rte_errno is set. 6958 */ 6959 static uint32_t 6960 flow_list_create(struct rte_eth_dev *dev, enum mlx5_flow_type type, 6961 const struct rte_flow_attr *attr, 6962 const struct rte_flow_item items[], 6963 const struct rte_flow_action original_actions[], 6964 bool external, struct rte_flow_error *error) 6965 { 6966 struct mlx5_priv *priv = dev->data->dev_private; 6967 struct rte_flow *flow = NULL; 6968 struct mlx5_flow *dev_flow; 6969 const struct rte_flow_action_rss *rss = NULL; 6970 struct mlx5_translated_action_handle 6971 indir_actions[MLX5_MAX_INDIRECT_ACTIONS]; 6972 int indir_actions_n = MLX5_MAX_INDIRECT_ACTIONS; 6973 union { 6974 struct mlx5_flow_expand_rss buf; 6975 uint8_t buffer[8192]; 6976 } expand_buffer; 6977 union { 6978 struct rte_flow_action actions[MLX5_MAX_SPLIT_ACTIONS]; 6979 uint8_t buffer[2048]; 6980 } actions_rx; 6981 union { 6982 struct rte_flow_action actions[MLX5_MAX_SPLIT_ACTIONS]; 6983 uint8_t buffer[2048]; 6984 } actions_hairpin_tx; 6985 union { 6986 struct rte_flow_item items[MLX5_MAX_SPLIT_ITEMS]; 6987 uint8_t buffer[2048]; 6988 } items_tx; 6989 struct mlx5_rte_flow_item_sq sq_specs[RTE_MAX_QUEUES_PER_PORT]; 6990 struct mlx5_flow_expand_rss *buf = &expand_buffer.buf; 6991 struct mlx5_flow_rss_desc *rss_desc; 6992 const struct rte_flow_action *p_actions_rx; 6993 uint32_t i; 6994 uint32_t idx = 0; 6995 int hairpin_flow; 6996 struct rte_flow_attr attr_tx = { .priority = 0 }; 6997 const struct rte_flow_action *actions; 6998 struct rte_flow_action *translated_actions = NULL; 6999 struct mlx5_flow_tunnel *tunnel; 7000 struct tunnel_default_miss_ctx default_miss_ctx = { 0, }; 7001 struct mlx5_flow_workspace *wks = mlx5_flow_push_thread_workspace(); 7002 struct mlx5_flow_split_info flow_split_info = { 7003 .external = !!external, 7004 .skip_scale = 0, 7005 .flow_idx = 0, 7006 .prefix_mark = 0, 7007 .prefix_layers = 0, 7008 .table_id = 0 7009 }; 7010 int ret; 7011 7012 MLX5_ASSERT(wks); 7013 rss_desc = &wks->rss_desc; 7014 ret = flow_action_handles_translate(dev, original_actions, 7015 indir_actions, 7016 &indir_actions_n, 7017 &translated_actions, error); 7018 if (ret < 0) { 7019 MLX5_ASSERT(translated_actions == NULL); 7020 return 0; 7021 } 7022 actions = translated_actions ? translated_actions : original_actions; 7023 p_actions_rx = actions; 7024 hairpin_flow = flow_check_hairpin_split(dev, attr, actions); 7025 ret = flow_drv_validate(dev, attr, items, p_actions_rx, 7026 external, hairpin_flow, error); 7027 if (ret < 0) 7028 goto error_before_hairpin_split; 7029 flow = mlx5_ipool_zmalloc(priv->flows[type], &idx); 7030 if (!flow) { 7031 rte_errno = ENOMEM; 7032 goto error_before_hairpin_split; 7033 } 7034 if (hairpin_flow > 0) { 7035 if (hairpin_flow > MLX5_MAX_SPLIT_ACTIONS) { 7036 rte_errno = EINVAL; 7037 goto error_before_hairpin_split; 7038 } 7039 flow_hairpin_split(dev, actions, actions_rx.actions, 7040 actions_hairpin_tx.actions, items_tx.items, 7041 idx); 7042 p_actions_rx = actions_rx.actions; 7043 } 7044 flow_split_info.flow_idx = idx; 7045 flow->drv_type = flow_get_drv_type(dev, attr); 7046 MLX5_ASSERT(flow->drv_type > MLX5_FLOW_TYPE_MIN && 7047 flow->drv_type < MLX5_FLOW_TYPE_MAX); 7048 memset(rss_desc, 0, offsetof(struct mlx5_flow_rss_desc, queue)); 7049 /* RSS Action only works on NIC RX domain */ 7050 if (attr->ingress) 7051 rss = flow_get_rss_action(dev, p_actions_rx); 7052 if (rss) { 7053 if (flow_rss_workspace_adjust(wks, rss_desc, rss->queue_num)) 7054 return 0; 7055 /* 7056 * The following information is required by 7057 * mlx5_flow_hashfields_adjust() in advance. 7058 */ 7059 rss_desc->level = rss->level; 7060 /* RSS type 0 indicates default RSS type (RTE_ETH_RSS_IP). */ 7061 rss_desc->types = !rss->types ? RTE_ETH_RSS_IP : rss->types; 7062 } 7063 flow->dev_handles = 0; 7064 if (rss && rss->types) { 7065 unsigned int graph_root; 7066 7067 graph_root = find_graph_root(rss->level); 7068 ret = mlx5_flow_expand_rss(buf, sizeof(expand_buffer.buffer), 7069 items, rss->types, 7070 mlx5_support_expansion, graph_root); 7071 MLX5_ASSERT(ret > 0 && 7072 (unsigned int)ret < sizeof(expand_buffer.buffer)); 7073 if (rte_log_can_log(mlx5_logtype, RTE_LOG_DEBUG)) { 7074 for (i = 0; i < buf->entries; ++i) 7075 mlx5_dbg__print_pattern(buf->entry[i].pattern); 7076 } 7077 } else { 7078 ret = mlx5_flow_expand_sqn((struct mlx5_flow_expand_sqn *)buf, 7079 sizeof(expand_buffer.buffer), 7080 items, sq_specs); 7081 if (ret) { 7082 rte_flow_error_set(error, ENOMEM, RTE_FLOW_ERROR_TYPE_HANDLE, 7083 NULL, "not enough memory for rte_flow"); 7084 goto error; 7085 } 7086 if (buf->entries == 0) { 7087 buf->entries = 1; 7088 buf->entry[0].pattern = (void *)(uintptr_t)items; 7089 } 7090 } 7091 rss_desc->shared_rss = flow_get_shared_rss_action(dev, indir_actions, 7092 indir_actions_n); 7093 for (i = 0; i < buf->entries; ++i) { 7094 /* Initialize flow split data. */ 7095 flow_split_info.prefix_layers = 0; 7096 flow_split_info.prefix_mark = 0; 7097 flow_split_info.skip_scale = 0; 7098 /* 7099 * The splitter may create multiple dev_flows, 7100 * depending on configuration. In the simplest 7101 * case it just creates unmodified original flow. 7102 */ 7103 ret = flow_create_split_outer(dev, flow, attr, 7104 buf->entry[i].pattern, 7105 p_actions_rx, &flow_split_info, 7106 error); 7107 if (ret < 0) 7108 goto error; 7109 if (is_flow_tunnel_steer_rule(wks->flows[0].tof_type)) { 7110 ret = flow_tunnel_add_default_miss(dev, flow, attr, 7111 p_actions_rx, 7112 idx, 7113 wks->flows[0].tunnel, 7114 &default_miss_ctx, 7115 error); 7116 if (ret < 0) { 7117 mlx5_free(default_miss_ctx.queue); 7118 goto error; 7119 } 7120 } 7121 } 7122 /* Create the tx flow. */ 7123 if (hairpin_flow) { 7124 attr_tx.group = MLX5_HAIRPIN_TX_TABLE; 7125 attr_tx.ingress = 0; 7126 attr_tx.egress = 1; 7127 dev_flow = flow_drv_prepare(dev, flow, &attr_tx, items_tx.items, 7128 actions_hairpin_tx.actions, 7129 idx, error); 7130 if (!dev_flow) 7131 goto error; 7132 dev_flow->flow = flow; 7133 dev_flow->external = 0; 7134 SILIST_INSERT(&flow->dev_handles, dev_flow->handle_idx, 7135 dev_flow->handle, next); 7136 ret = flow_drv_translate(dev, dev_flow, &attr_tx, 7137 items_tx.items, 7138 actions_hairpin_tx.actions, error); 7139 if (ret < 0) 7140 goto error; 7141 } 7142 /* 7143 * Update the metadata register copy table. If extensive 7144 * metadata feature is enabled and registers are supported 7145 * we might create the extra rte_flow for each unique 7146 * MARK/FLAG action ID. 7147 * 7148 * The table is updated for ingress and transfer flows only, because 7149 * the egress Flows belong to the different device and 7150 * copy table should be updated in peer NIC Rx domain. 7151 */ 7152 if ((attr->ingress || attr->transfer) && 7153 (external || attr->group != MLX5_FLOW_MREG_CP_TABLE_GROUP)) { 7154 ret = flow_mreg_update_copy_table(dev, flow, actions, error); 7155 if (ret) 7156 goto error; 7157 } 7158 /* 7159 * If the flow is external (from application) OR device is started, 7160 * OR mreg discover, then apply immediately. 7161 */ 7162 if (external || dev->data->dev_started || 7163 (attr->group == MLX5_FLOW_MREG_CP_TABLE_GROUP && 7164 attr->priority == MLX5_FLOW_LOWEST_PRIO_INDICATOR)) { 7165 ret = flow_drv_apply(dev, flow, error); 7166 if (ret < 0) 7167 goto error; 7168 } 7169 flow->type = type; 7170 flow_rxq_flags_set(dev, flow); 7171 rte_free(translated_actions); 7172 tunnel = flow_tunnel_from_rule(wks->flows); 7173 if (tunnel) { 7174 flow->tunnel = 1; 7175 flow->tunnel_id = tunnel->tunnel_id; 7176 __atomic_add_fetch(&tunnel->refctn, 1, __ATOMIC_RELAXED); 7177 mlx5_free(default_miss_ctx.queue); 7178 } 7179 mlx5_flow_pop_thread_workspace(); 7180 return idx; 7181 error: 7182 MLX5_ASSERT(flow); 7183 ret = rte_errno; /* Save rte_errno before cleanup. */ 7184 flow_mreg_del_copy_action(dev, flow); 7185 flow_drv_destroy(dev, flow); 7186 if (rss_desc->shared_rss) 7187 __atomic_sub_fetch(&((struct mlx5_shared_action_rss *) 7188 mlx5_ipool_get 7189 (priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], 7190 rss_desc->shared_rss))->refcnt, 1, __ATOMIC_RELAXED); 7191 mlx5_ipool_free(priv->flows[type], idx); 7192 rte_errno = ret; /* Restore rte_errno. */ 7193 ret = rte_errno; 7194 rte_errno = ret; 7195 error_before_hairpin_split: 7196 mlx5_flow_pop_thread_workspace(); 7197 rte_free(translated_actions); 7198 return 0; 7199 } 7200 7201 /** 7202 * Create a dedicated flow rule on e-switch table 0 (root table), to direct all 7203 * incoming packets to table 1. 7204 * 7205 * Other flow rules, requested for group n, will be created in 7206 * e-switch table n+1. 7207 * Jump action to e-switch group n will be created to group n+1. 7208 * 7209 * Used when working in switchdev mode, to utilise advantages of table 1 7210 * and above. 7211 * 7212 * @param dev 7213 * Pointer to Ethernet device. 7214 * 7215 * @return 7216 * Pointer to flow on success, NULL otherwise and rte_errno is set. 7217 */ 7218 struct rte_flow * 7219 mlx5_flow_create_esw_table_zero_flow(struct rte_eth_dev *dev) 7220 { 7221 const struct rte_flow_attr attr = { 7222 .group = 0, 7223 .priority = 0, 7224 .ingress = 0, 7225 .egress = 0, 7226 .transfer = 1, 7227 }; 7228 const struct rte_flow_item pattern = { 7229 .type = RTE_FLOW_ITEM_TYPE_END, 7230 }; 7231 struct rte_flow_action_jump jump = { 7232 .group = 1, 7233 }; 7234 const struct rte_flow_action actions[] = { 7235 { 7236 .type = RTE_FLOW_ACTION_TYPE_JUMP, 7237 .conf = &jump, 7238 }, 7239 { 7240 .type = RTE_FLOW_ACTION_TYPE_END, 7241 }, 7242 }; 7243 struct rte_flow_error error; 7244 7245 return (void *)(uintptr_t)flow_list_create(dev, MLX5_FLOW_TYPE_CTL, 7246 &attr, &pattern, 7247 actions, false, &error); 7248 } 7249 7250 /** 7251 * Create a dedicated flow rule on e-switch table 1, matches ESW manager 7252 * and sq number, directs all packets to peer vport. 7253 * 7254 * @param dev 7255 * Pointer to Ethernet device. 7256 * @param sq_num 7257 * SQ number. 7258 * 7259 * @return 7260 * Flow ID on success, 0 otherwise and rte_errno is set. 7261 */ 7262 uint32_t 7263 mlx5_flow_create_devx_sq_miss_flow(struct rte_eth_dev *dev, uint32_t sq_num) 7264 { 7265 struct rte_flow_attr attr = { 7266 .group = 0, 7267 .priority = MLX5_FLOW_LOWEST_PRIO_INDICATOR, 7268 .ingress = 0, 7269 .egress = 0, 7270 .transfer = 1, 7271 }; 7272 struct rte_flow_item_port_id port_spec = { 7273 .id = MLX5_PORT_ESW_MGR, 7274 }; 7275 struct mlx5_rte_flow_item_sq sq_spec = { 7276 .queue = sq_num, 7277 }; 7278 struct rte_flow_item pattern[] = { 7279 { 7280 .type = RTE_FLOW_ITEM_TYPE_PORT_ID, 7281 .spec = &port_spec, 7282 }, 7283 { 7284 .type = (enum rte_flow_item_type) 7285 MLX5_RTE_FLOW_ITEM_TYPE_SQ, 7286 .spec = &sq_spec, 7287 }, 7288 { 7289 .type = RTE_FLOW_ITEM_TYPE_END, 7290 }, 7291 }; 7292 struct rte_flow_action_jump jump = { 7293 .group = 1, 7294 }; 7295 struct rte_flow_action_port_id port = { 7296 .id = dev->data->port_id, 7297 }; 7298 struct rte_flow_action actions[] = { 7299 { 7300 .type = RTE_FLOW_ACTION_TYPE_JUMP, 7301 .conf = &jump, 7302 }, 7303 { 7304 .type = RTE_FLOW_ACTION_TYPE_END, 7305 }, 7306 }; 7307 struct rte_flow_error error; 7308 7309 /* 7310 * Creates group 0, highest priority jump flow. 7311 * Matches txq to bypass kernel packets. 7312 */ 7313 if (flow_list_create(dev, MLX5_FLOW_TYPE_CTL, &attr, pattern, actions, 7314 false, &error) == 0) 7315 return 0; 7316 /* Create group 1, lowest priority redirect flow for txq. */ 7317 attr.group = 1; 7318 actions[0].conf = &port; 7319 actions[0].type = RTE_FLOW_ACTION_TYPE_PORT_ID; 7320 return flow_list_create(dev, MLX5_FLOW_TYPE_CTL, &attr, pattern, 7321 actions, false, &error); 7322 } 7323 7324 /** 7325 * Validate a flow supported by the NIC. 7326 * 7327 * @see rte_flow_validate() 7328 * @see rte_flow_ops 7329 */ 7330 int 7331 mlx5_flow_validate(struct rte_eth_dev *dev, 7332 const struct rte_flow_attr *attr, 7333 const struct rte_flow_item items[], 7334 const struct rte_flow_action original_actions[], 7335 struct rte_flow_error *error) 7336 { 7337 int hairpin_flow; 7338 struct mlx5_translated_action_handle 7339 indir_actions[MLX5_MAX_INDIRECT_ACTIONS]; 7340 int indir_actions_n = MLX5_MAX_INDIRECT_ACTIONS; 7341 const struct rte_flow_action *actions; 7342 struct rte_flow_action *translated_actions = NULL; 7343 int ret = flow_action_handles_translate(dev, original_actions, 7344 indir_actions, 7345 &indir_actions_n, 7346 &translated_actions, error); 7347 7348 if (ret) 7349 return ret; 7350 actions = translated_actions ? translated_actions : original_actions; 7351 hairpin_flow = flow_check_hairpin_split(dev, attr, actions); 7352 ret = flow_drv_validate(dev, attr, items, actions, 7353 true, hairpin_flow, error); 7354 rte_free(translated_actions); 7355 return ret; 7356 } 7357 7358 /** 7359 * Create a flow. 7360 * 7361 * @see rte_flow_create() 7362 * @see rte_flow_ops 7363 */ 7364 struct rte_flow * 7365 mlx5_flow_create(struct rte_eth_dev *dev, 7366 const struct rte_flow_attr *attr, 7367 const struct rte_flow_item items[], 7368 const struct rte_flow_action actions[], 7369 struct rte_flow_error *error) 7370 { 7371 struct mlx5_priv *priv = dev->data->dev_private; 7372 7373 if (priv->sh->config.dv_flow_en == 2) { 7374 rte_flow_error_set(error, ENOTSUP, 7375 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, 7376 NULL, 7377 "Flow non-Q creation not supported"); 7378 return NULL; 7379 } 7380 /* 7381 * If the device is not started yet, it is not allowed to created a 7382 * flow from application. PMD default flows and traffic control flows 7383 * are not affected. 7384 */ 7385 if (unlikely(!dev->data->dev_started)) { 7386 DRV_LOG(DEBUG, "port %u is not started when " 7387 "inserting a flow", dev->data->port_id); 7388 rte_flow_error_set(error, ENODEV, 7389 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, 7390 NULL, 7391 "port not started"); 7392 return NULL; 7393 } 7394 7395 return (void *)(uintptr_t)flow_list_create(dev, MLX5_FLOW_TYPE_GEN, 7396 attr, items, actions, 7397 true, error); 7398 } 7399 7400 /** 7401 * Destroy a flow in a list. 7402 * 7403 * @param dev 7404 * Pointer to Ethernet device. 7405 * @param[in] flow_idx 7406 * Index of flow to destroy. 7407 */ 7408 static void 7409 flow_list_destroy(struct rte_eth_dev *dev, enum mlx5_flow_type type, 7410 uint32_t flow_idx) 7411 { 7412 struct mlx5_priv *priv = dev->data->dev_private; 7413 struct rte_flow *flow = mlx5_ipool_get(priv->flows[type], flow_idx); 7414 7415 if (!flow) 7416 return; 7417 MLX5_ASSERT(flow->type == type); 7418 /* 7419 * Update RX queue flags only if port is started, otherwise it is 7420 * already clean. 7421 */ 7422 if (dev->data->dev_started) 7423 flow_rxq_flags_trim(dev, flow); 7424 flow_drv_destroy(dev, flow); 7425 if (flow->tunnel) { 7426 struct mlx5_flow_tunnel *tunnel; 7427 7428 tunnel = mlx5_find_tunnel_id(dev, flow->tunnel_id); 7429 RTE_VERIFY(tunnel); 7430 if (!__atomic_sub_fetch(&tunnel->refctn, 1, __ATOMIC_RELAXED)) 7431 mlx5_flow_tunnel_free(dev, tunnel); 7432 } 7433 flow_mreg_del_copy_action(dev, flow); 7434 mlx5_ipool_free(priv->flows[type], flow_idx); 7435 } 7436 7437 /** 7438 * Destroy all flows. 7439 * 7440 * @param dev 7441 * Pointer to Ethernet device. 7442 * @param type 7443 * Flow type to be flushed. 7444 * @param active 7445 * If flushing is called actively. 7446 */ 7447 void 7448 mlx5_flow_list_flush(struct rte_eth_dev *dev, enum mlx5_flow_type type, 7449 bool active) 7450 { 7451 struct mlx5_priv *priv = dev->data->dev_private; 7452 uint32_t num_flushed = 0, fidx = 1; 7453 struct rte_flow *flow; 7454 7455 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 7456 if (priv->sh->config.dv_flow_en == 2 && 7457 type == MLX5_FLOW_TYPE_GEN) { 7458 flow_hw_q_flow_flush(dev, NULL); 7459 return; 7460 } 7461 #endif 7462 7463 MLX5_IPOOL_FOREACH(priv->flows[type], fidx, flow) { 7464 flow_list_destroy(dev, type, fidx); 7465 num_flushed++; 7466 } 7467 if (active) { 7468 DRV_LOG(INFO, "port %u: %u flows flushed before stopping", 7469 dev->data->port_id, num_flushed); 7470 } 7471 } 7472 7473 /** 7474 * Stop all default actions for flows. 7475 * 7476 * @param dev 7477 * Pointer to Ethernet device. 7478 */ 7479 void 7480 mlx5_flow_stop_default(struct rte_eth_dev *dev) 7481 { 7482 flow_mreg_del_default_copy_action(dev); 7483 flow_rxq_flags_clear(dev); 7484 } 7485 7486 /** 7487 * Start all default actions for flows. 7488 * 7489 * @param dev 7490 * Pointer to Ethernet device. 7491 * @return 7492 * 0 on success, a negative errno value otherwise and rte_errno is set. 7493 */ 7494 int 7495 mlx5_flow_start_default(struct rte_eth_dev *dev) 7496 { 7497 struct rte_flow_error error; 7498 7499 /* Make sure default copy action (reg_c[0] -> reg_b) is created. */ 7500 return flow_mreg_add_default_copy_action(dev, &error); 7501 } 7502 7503 /** 7504 * Release key of thread specific flow workspace data. 7505 */ 7506 void 7507 flow_release_workspace(void *data) 7508 { 7509 struct mlx5_flow_workspace *wks = data; 7510 struct mlx5_flow_workspace *next; 7511 7512 while (wks) { 7513 next = wks->next; 7514 free(wks->rss_desc.queue); 7515 free(wks); 7516 wks = next; 7517 } 7518 } 7519 7520 /** 7521 * Get thread specific current flow workspace. 7522 * 7523 * @return pointer to thread specific flow workspace data, NULL on error. 7524 */ 7525 struct mlx5_flow_workspace* 7526 mlx5_flow_get_thread_workspace(void) 7527 { 7528 struct mlx5_flow_workspace *data; 7529 7530 data = mlx5_flow_os_get_specific_workspace(); 7531 MLX5_ASSERT(data && data->inuse); 7532 if (!data || !data->inuse) 7533 DRV_LOG(ERR, "flow workspace not initialized."); 7534 return data; 7535 } 7536 7537 /** 7538 * Allocate and init new flow workspace. 7539 * 7540 * @return pointer to flow workspace data, NULL on error. 7541 */ 7542 static struct mlx5_flow_workspace* 7543 flow_alloc_thread_workspace(void) 7544 { 7545 struct mlx5_flow_workspace *data = calloc(1, sizeof(*data)); 7546 7547 if (!data) { 7548 DRV_LOG(ERR, "Failed to allocate flow workspace " 7549 "memory."); 7550 return NULL; 7551 } 7552 data->rss_desc.queue = calloc(1, 7553 sizeof(uint16_t) * MLX5_RSSQ_DEFAULT_NUM); 7554 if (!data->rss_desc.queue) 7555 goto err; 7556 data->rssq_num = MLX5_RSSQ_DEFAULT_NUM; 7557 return data; 7558 err: 7559 free(data->rss_desc.queue); 7560 free(data); 7561 return NULL; 7562 } 7563 7564 /** 7565 * Get new thread specific flow workspace. 7566 * 7567 * If current workspace inuse, create new one and set as current. 7568 * 7569 * @return pointer to thread specific flow workspace data, NULL on error. 7570 */ 7571 struct mlx5_flow_workspace* 7572 mlx5_flow_push_thread_workspace(void) 7573 { 7574 struct mlx5_flow_workspace *curr; 7575 struct mlx5_flow_workspace *data; 7576 7577 curr = mlx5_flow_os_get_specific_workspace(); 7578 if (!curr) { 7579 data = flow_alloc_thread_workspace(); 7580 if (!data) 7581 return NULL; 7582 } else if (!curr->inuse) { 7583 data = curr; 7584 } else if (curr->next) { 7585 data = curr->next; 7586 } else { 7587 data = flow_alloc_thread_workspace(); 7588 if (!data) 7589 return NULL; 7590 curr->next = data; 7591 data->prev = curr; 7592 } 7593 data->inuse = 1; 7594 data->flow_idx = 0; 7595 /* Set as current workspace */ 7596 if (mlx5_flow_os_set_specific_workspace(data)) 7597 DRV_LOG(ERR, "Failed to set flow workspace to thread."); 7598 return data; 7599 } 7600 7601 /** 7602 * Close current thread specific flow workspace. 7603 * 7604 * If previous workspace available, set it as current. 7605 * 7606 * @return pointer to thread specific flow workspace data, NULL on error. 7607 */ 7608 void 7609 mlx5_flow_pop_thread_workspace(void) 7610 { 7611 struct mlx5_flow_workspace *data = mlx5_flow_get_thread_workspace(); 7612 7613 if (!data) 7614 return; 7615 if (!data->inuse) { 7616 DRV_LOG(ERR, "Failed to close unused flow workspace."); 7617 return; 7618 } 7619 data->inuse = 0; 7620 if (!data->prev) 7621 return; 7622 if (mlx5_flow_os_set_specific_workspace(data->prev)) 7623 DRV_LOG(ERR, "Failed to set flow workspace to thread."); 7624 } 7625 7626 /** 7627 * Verify the flow list is empty 7628 * 7629 * @param dev 7630 * Pointer to Ethernet device. 7631 * 7632 * @return the number of flows not released. 7633 */ 7634 int 7635 mlx5_flow_verify(struct rte_eth_dev *dev __rte_unused) 7636 { 7637 struct mlx5_priv *priv = dev->data->dev_private; 7638 struct rte_flow *flow; 7639 uint32_t idx = 0; 7640 int ret = 0, i; 7641 7642 for (i = 0; i < MLX5_FLOW_TYPE_MAXI; i++) { 7643 MLX5_IPOOL_FOREACH(priv->flows[i], idx, flow) { 7644 DRV_LOG(DEBUG, "port %u flow %p still referenced", 7645 dev->data->port_id, (void *)flow); 7646 ret++; 7647 } 7648 } 7649 return ret; 7650 } 7651 7652 /** 7653 * Enable default hairpin egress flow. 7654 * 7655 * @param dev 7656 * Pointer to Ethernet device. 7657 * @param sq_num 7658 * The SQ hw number. 7659 * 7660 * @return 7661 * 0 on success, a negative errno value otherwise and rte_errno is set. 7662 */ 7663 int 7664 mlx5_ctrl_flow_source_queue(struct rte_eth_dev *dev, 7665 uint32_t sq_num) 7666 { 7667 const struct rte_flow_attr attr = { 7668 .egress = 1, 7669 .priority = 0, 7670 }; 7671 struct mlx5_rte_flow_item_sq queue_spec = { 7672 .queue = sq_num, 7673 }; 7674 struct mlx5_rte_flow_item_sq queue_mask = { 7675 .queue = UINT32_MAX, 7676 }; 7677 struct rte_flow_item items[] = { 7678 { 7679 .type = (enum rte_flow_item_type) 7680 MLX5_RTE_FLOW_ITEM_TYPE_SQ, 7681 .spec = &queue_spec, 7682 .last = NULL, 7683 .mask = &queue_mask, 7684 }, 7685 { 7686 .type = RTE_FLOW_ITEM_TYPE_END, 7687 }, 7688 }; 7689 struct rte_flow_action_jump jump = { 7690 .group = MLX5_HAIRPIN_TX_TABLE, 7691 }; 7692 struct rte_flow_action actions[2]; 7693 uint32_t flow_idx; 7694 struct rte_flow_error error; 7695 7696 actions[0].type = RTE_FLOW_ACTION_TYPE_JUMP; 7697 actions[0].conf = &jump; 7698 actions[1].type = RTE_FLOW_ACTION_TYPE_END; 7699 flow_idx = flow_list_create(dev, MLX5_FLOW_TYPE_CTL, 7700 &attr, items, actions, false, &error); 7701 if (!flow_idx) { 7702 DRV_LOG(DEBUG, 7703 "Failed to create ctrl flow: rte_errno(%d)," 7704 " type(%d), message(%s)", 7705 rte_errno, error.type, 7706 error.message ? error.message : " (no stated reason)"); 7707 return -rte_errno; 7708 } 7709 return 0; 7710 } 7711 7712 /** 7713 * Enable a control flow configured from the control plane. 7714 * 7715 * @param dev 7716 * Pointer to Ethernet device. 7717 * @param eth_spec 7718 * An Ethernet flow spec to apply. 7719 * @param eth_mask 7720 * An Ethernet flow mask to apply. 7721 * @param vlan_spec 7722 * A VLAN flow spec to apply. 7723 * @param vlan_mask 7724 * A VLAN flow mask to apply. 7725 * 7726 * @return 7727 * 0 on success, a negative errno value otherwise and rte_errno is set. 7728 */ 7729 int 7730 mlx5_ctrl_flow_vlan(struct rte_eth_dev *dev, 7731 struct rte_flow_item_eth *eth_spec, 7732 struct rte_flow_item_eth *eth_mask, 7733 struct rte_flow_item_vlan *vlan_spec, 7734 struct rte_flow_item_vlan *vlan_mask) 7735 { 7736 struct mlx5_priv *priv = dev->data->dev_private; 7737 const struct rte_flow_attr attr = { 7738 .ingress = 1, 7739 .priority = MLX5_FLOW_LOWEST_PRIO_INDICATOR, 7740 }; 7741 struct rte_flow_item items[] = { 7742 { 7743 .type = RTE_FLOW_ITEM_TYPE_ETH, 7744 .spec = eth_spec, 7745 .last = NULL, 7746 .mask = eth_mask, 7747 }, 7748 { 7749 .type = (vlan_spec) ? RTE_FLOW_ITEM_TYPE_VLAN : 7750 RTE_FLOW_ITEM_TYPE_END, 7751 .spec = vlan_spec, 7752 .last = NULL, 7753 .mask = vlan_mask, 7754 }, 7755 { 7756 .type = RTE_FLOW_ITEM_TYPE_END, 7757 }, 7758 }; 7759 uint16_t queue[priv->reta_idx_n]; 7760 struct rte_flow_action_rss action_rss = { 7761 .func = RTE_ETH_HASH_FUNCTION_DEFAULT, 7762 .level = 0, 7763 .types = priv->rss_conf.rss_hf, 7764 .key_len = priv->rss_conf.rss_key_len, 7765 .queue_num = priv->reta_idx_n, 7766 .key = priv->rss_conf.rss_key, 7767 .queue = queue, 7768 }; 7769 struct rte_flow_action actions[] = { 7770 { 7771 .type = RTE_FLOW_ACTION_TYPE_RSS, 7772 .conf = &action_rss, 7773 }, 7774 { 7775 .type = RTE_FLOW_ACTION_TYPE_END, 7776 }, 7777 }; 7778 uint32_t flow_idx; 7779 struct rte_flow_error error; 7780 unsigned int i; 7781 7782 if (!priv->reta_idx_n || !priv->rxqs_n) { 7783 return 0; 7784 } 7785 if (!(dev->data->dev_conf.rxmode.mq_mode & RTE_ETH_MQ_RX_RSS_FLAG)) 7786 action_rss.types = 0; 7787 for (i = 0; i != priv->reta_idx_n; ++i) 7788 queue[i] = (*priv->reta_idx)[i]; 7789 flow_idx = flow_list_create(dev, MLX5_FLOW_TYPE_CTL, 7790 &attr, items, actions, false, &error); 7791 if (!flow_idx) 7792 return -rte_errno; 7793 return 0; 7794 } 7795 7796 /** 7797 * Enable a flow control configured from the control plane. 7798 * 7799 * @param dev 7800 * Pointer to Ethernet device. 7801 * @param eth_spec 7802 * An Ethernet flow spec to apply. 7803 * @param eth_mask 7804 * An Ethernet flow mask to apply. 7805 * 7806 * @return 7807 * 0 on success, a negative errno value otherwise and rte_errno is set. 7808 */ 7809 int 7810 mlx5_ctrl_flow(struct rte_eth_dev *dev, 7811 struct rte_flow_item_eth *eth_spec, 7812 struct rte_flow_item_eth *eth_mask) 7813 { 7814 return mlx5_ctrl_flow_vlan(dev, eth_spec, eth_mask, NULL, NULL); 7815 } 7816 7817 /** 7818 * Create default miss flow rule matching lacp traffic 7819 * 7820 * @param dev 7821 * Pointer to Ethernet device. 7822 * @param eth_spec 7823 * An Ethernet flow spec to apply. 7824 * 7825 * @return 7826 * 0 on success, a negative errno value otherwise and rte_errno is set. 7827 */ 7828 int 7829 mlx5_flow_lacp_miss(struct rte_eth_dev *dev) 7830 { 7831 /* 7832 * The LACP matching is done by only using ether type since using 7833 * a multicast dst mac causes kernel to give low priority to this flow. 7834 */ 7835 static const struct rte_flow_item_eth lacp_spec = { 7836 .type = RTE_BE16(0x8809), 7837 }; 7838 static const struct rte_flow_item_eth lacp_mask = { 7839 .type = 0xffff, 7840 }; 7841 const struct rte_flow_attr attr = { 7842 .ingress = 1, 7843 }; 7844 struct rte_flow_item items[] = { 7845 { 7846 .type = RTE_FLOW_ITEM_TYPE_ETH, 7847 .spec = &lacp_spec, 7848 .mask = &lacp_mask, 7849 }, 7850 { 7851 .type = RTE_FLOW_ITEM_TYPE_END, 7852 }, 7853 }; 7854 struct rte_flow_action actions[] = { 7855 { 7856 .type = (enum rte_flow_action_type) 7857 MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS, 7858 }, 7859 { 7860 .type = RTE_FLOW_ACTION_TYPE_END, 7861 }, 7862 }; 7863 struct rte_flow_error error; 7864 uint32_t flow_idx = flow_list_create(dev, MLX5_FLOW_TYPE_CTL, 7865 &attr, items, actions, 7866 false, &error); 7867 7868 if (!flow_idx) 7869 return -rte_errno; 7870 return 0; 7871 } 7872 7873 /** 7874 * Destroy a flow. 7875 * 7876 * @see rte_flow_destroy() 7877 * @see rte_flow_ops 7878 */ 7879 int 7880 mlx5_flow_destroy(struct rte_eth_dev *dev, 7881 struct rte_flow *flow, 7882 struct rte_flow_error *error __rte_unused) 7883 { 7884 struct mlx5_priv *priv = dev->data->dev_private; 7885 7886 if (priv->sh->config.dv_flow_en == 2) 7887 return rte_flow_error_set(error, ENOTSUP, 7888 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, 7889 NULL, 7890 "Flow non-Q destruction not supported"); 7891 flow_list_destroy(dev, MLX5_FLOW_TYPE_GEN, 7892 (uintptr_t)(void *)flow); 7893 return 0; 7894 } 7895 7896 /** 7897 * Destroy all flows. 7898 * 7899 * @see rte_flow_flush() 7900 * @see rte_flow_ops 7901 */ 7902 int 7903 mlx5_flow_flush(struct rte_eth_dev *dev, 7904 struct rte_flow_error *error __rte_unused) 7905 { 7906 mlx5_flow_list_flush(dev, MLX5_FLOW_TYPE_GEN, false); 7907 return 0; 7908 } 7909 7910 /** 7911 * Isolated mode. 7912 * 7913 * @see rte_flow_isolate() 7914 * @see rte_flow_ops 7915 */ 7916 int 7917 mlx5_flow_isolate(struct rte_eth_dev *dev, 7918 int enable, 7919 struct rte_flow_error *error) 7920 { 7921 struct mlx5_priv *priv = dev->data->dev_private; 7922 7923 if (dev->data->dev_started) { 7924 rte_flow_error_set(error, EBUSY, 7925 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, 7926 NULL, 7927 "port must be stopped first"); 7928 return -rte_errno; 7929 } 7930 priv->isolated = !!enable; 7931 if (enable) 7932 dev->dev_ops = &mlx5_dev_ops_isolate; 7933 else 7934 dev->dev_ops = &mlx5_dev_ops; 7935 7936 dev->rx_descriptor_status = mlx5_rx_descriptor_status; 7937 dev->tx_descriptor_status = mlx5_tx_descriptor_status; 7938 7939 return 0; 7940 } 7941 7942 /** 7943 * Query a flow. 7944 * 7945 * @see rte_flow_query() 7946 * @see rte_flow_ops 7947 */ 7948 static int 7949 flow_drv_query(struct rte_eth_dev *dev, 7950 struct rte_flow *eflow, 7951 const struct rte_flow_action *actions, 7952 void *data, 7953 struct rte_flow_error *error) 7954 { 7955 struct mlx5_priv *priv = dev->data->dev_private; 7956 const struct mlx5_flow_driver_ops *fops; 7957 struct rte_flow *flow = NULL; 7958 enum mlx5_flow_drv_type ftype = MLX5_FLOW_TYPE_MIN; 7959 7960 if (priv->sh->config.dv_flow_en == 2) { 7961 #ifdef HAVE_MLX5_HWS_SUPPORT 7962 flow = eflow; 7963 ftype = MLX5_FLOW_TYPE_HW; 7964 #endif 7965 } else { 7966 flow = (struct rte_flow *)mlx5_ipool_get(priv->flows[MLX5_FLOW_TYPE_GEN], 7967 (uintptr_t)(void *)eflow); 7968 } 7969 if (!flow) { 7970 return rte_flow_error_set(error, ENOENT, 7971 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, 7972 NULL, 7973 "invalid flow handle"); 7974 } 7975 if (ftype == MLX5_FLOW_TYPE_MIN) 7976 ftype = flow->drv_type; 7977 MLX5_ASSERT(ftype > MLX5_FLOW_TYPE_MIN && ftype < MLX5_FLOW_TYPE_MAX); 7978 fops = flow_get_drv_ops(ftype); 7979 7980 return fops->query(dev, flow, actions, data, error); 7981 } 7982 7983 /** 7984 * Query a flow. 7985 * 7986 * @see rte_flow_query() 7987 * @see rte_flow_ops 7988 */ 7989 int 7990 mlx5_flow_query(struct rte_eth_dev *dev, 7991 struct rte_flow *flow, 7992 const struct rte_flow_action *actions, 7993 void *data, 7994 struct rte_flow_error *error) 7995 { 7996 int ret; 7997 7998 ret = flow_drv_query(dev, flow, actions, data, 7999 error); 8000 if (ret < 0) 8001 return ret; 8002 return 0; 8003 } 8004 8005 /** 8006 * Get rte_flow callbacks. 8007 * 8008 * @param dev 8009 * Pointer to Ethernet device structure. 8010 * @param ops 8011 * Pointer to operation-specific structure. 8012 * 8013 * @return 0 8014 */ 8015 int 8016 mlx5_flow_ops_get(struct rte_eth_dev *dev __rte_unused, 8017 const struct rte_flow_ops **ops) 8018 { 8019 *ops = &mlx5_flow_ops; 8020 return 0; 8021 } 8022 8023 /** 8024 * Validate meter policy actions. 8025 * Dispatcher for action type specific validation. 8026 * 8027 * @param[in] dev 8028 * Pointer to the Ethernet device structure. 8029 * @param[in] action 8030 * The meter policy action object to validate. 8031 * @param[in] attr 8032 * Attributes of flow to determine steering domain. 8033 * @param[out] is_rss 8034 * Is RSS or not. 8035 * @param[out] domain_bitmap 8036 * Domain bitmap. 8037 * @param[out] is_def_policy 8038 * Is default policy or not. 8039 * @param[out] error 8040 * Perform verbose error reporting if not NULL. Initialized in case of 8041 * error only. 8042 * 8043 * @return 8044 * 0 on success, otherwise negative errno value. 8045 */ 8046 int 8047 mlx5_flow_validate_mtr_acts(struct rte_eth_dev *dev, 8048 const struct rte_flow_action *actions[RTE_COLORS], 8049 struct rte_flow_attr *attr, 8050 bool *is_rss, 8051 uint8_t *domain_bitmap, 8052 uint8_t *policy_mode, 8053 struct rte_mtr_error *error) 8054 { 8055 const struct mlx5_flow_driver_ops *fops; 8056 8057 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_DV); 8058 return fops->validate_mtr_acts(dev, actions, attr, is_rss, 8059 domain_bitmap, policy_mode, error); 8060 } 8061 8062 /** 8063 * Destroy the meter table set. 8064 * 8065 * @param[in] dev 8066 * Pointer to Ethernet device. 8067 * @param[in] mtr_policy 8068 * Meter policy struct. 8069 */ 8070 void 8071 mlx5_flow_destroy_mtr_acts(struct rte_eth_dev *dev, 8072 struct mlx5_flow_meter_policy *mtr_policy) 8073 { 8074 const struct mlx5_flow_driver_ops *fops; 8075 8076 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_DV); 8077 fops->destroy_mtr_acts(dev, mtr_policy); 8078 } 8079 8080 /** 8081 * Create policy action, lock free, 8082 * (mutex should be acquired by caller). 8083 * Dispatcher for action type specific call. 8084 * 8085 * @param[in] dev 8086 * Pointer to the Ethernet device structure. 8087 * @param[in] mtr_policy 8088 * Meter policy struct. 8089 * @param[in] action 8090 * Action specification used to create meter actions. 8091 * @param[in] attr 8092 * Flow rule attributes. 8093 * @param[out] error 8094 * Perform verbose error reporting if not NULL. Initialized in case of 8095 * error only. 8096 * 8097 * @return 8098 * 0 on success, otherwise negative errno value. 8099 */ 8100 int 8101 mlx5_flow_create_mtr_acts(struct rte_eth_dev *dev, 8102 struct mlx5_flow_meter_policy *mtr_policy, 8103 const struct rte_flow_action *actions[RTE_COLORS], 8104 struct rte_flow_attr *attr, 8105 struct rte_mtr_error *error) 8106 { 8107 const struct mlx5_flow_driver_ops *fops; 8108 8109 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_DV); 8110 return fops->create_mtr_acts(dev, mtr_policy, actions, attr, error); 8111 } 8112 8113 /** 8114 * Create policy rules, lock free, 8115 * (mutex should be acquired by caller). 8116 * Dispatcher for action type specific call. 8117 * 8118 * @param[in] dev 8119 * Pointer to the Ethernet device structure. 8120 * @param[in] mtr_policy 8121 * Meter policy struct. 8122 * 8123 * @return 8124 * 0 on success, -1 otherwise. 8125 */ 8126 int 8127 mlx5_flow_create_policy_rules(struct rte_eth_dev *dev, 8128 struct mlx5_flow_meter_policy *mtr_policy) 8129 { 8130 const struct mlx5_flow_driver_ops *fops; 8131 8132 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_DV); 8133 return fops->create_policy_rules(dev, mtr_policy); 8134 } 8135 8136 /** 8137 * Destroy policy rules, lock free, 8138 * (mutex should be acquired by caller). 8139 * Dispatcher for action type specific call. 8140 * 8141 * @param[in] dev 8142 * Pointer to the Ethernet device structure. 8143 * @param[in] mtr_policy 8144 * Meter policy struct. 8145 */ 8146 void 8147 mlx5_flow_destroy_policy_rules(struct rte_eth_dev *dev, 8148 struct mlx5_flow_meter_policy *mtr_policy) 8149 { 8150 const struct mlx5_flow_driver_ops *fops; 8151 8152 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_DV); 8153 fops->destroy_policy_rules(dev, mtr_policy); 8154 } 8155 8156 /** 8157 * Destroy the default policy table set. 8158 * 8159 * @param[in] dev 8160 * Pointer to Ethernet device. 8161 */ 8162 void 8163 mlx5_flow_destroy_def_policy(struct rte_eth_dev *dev) 8164 { 8165 const struct mlx5_flow_driver_ops *fops; 8166 8167 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_DV); 8168 fops->destroy_def_policy(dev); 8169 } 8170 8171 /** 8172 * Destroy the default policy table set. 8173 * 8174 * @param[in] dev 8175 * Pointer to Ethernet device. 8176 * 8177 * @return 8178 * 0 on success, -1 otherwise. 8179 */ 8180 int 8181 mlx5_flow_create_def_policy(struct rte_eth_dev *dev) 8182 { 8183 const struct mlx5_flow_driver_ops *fops; 8184 8185 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_DV); 8186 return fops->create_def_policy(dev); 8187 } 8188 8189 /** 8190 * Create the needed meter and suffix tables. 8191 * 8192 * @param[in] dev 8193 * Pointer to Ethernet device. 8194 * 8195 * @return 8196 * 0 on success, -1 otherwise. 8197 */ 8198 int 8199 mlx5_flow_create_mtr_tbls(struct rte_eth_dev *dev, 8200 struct mlx5_flow_meter_info *fm, 8201 uint32_t mtr_idx, 8202 uint8_t domain_bitmap) 8203 { 8204 const struct mlx5_flow_driver_ops *fops; 8205 8206 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_DV); 8207 return fops->create_mtr_tbls(dev, fm, mtr_idx, domain_bitmap); 8208 } 8209 8210 /** 8211 * Destroy the meter table set. 8212 * 8213 * @param[in] dev 8214 * Pointer to Ethernet device. 8215 * @param[in] tbl 8216 * Pointer to the meter table set. 8217 */ 8218 void 8219 mlx5_flow_destroy_mtr_tbls(struct rte_eth_dev *dev, 8220 struct mlx5_flow_meter_info *fm) 8221 { 8222 const struct mlx5_flow_driver_ops *fops; 8223 8224 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_DV); 8225 fops->destroy_mtr_tbls(dev, fm); 8226 } 8227 8228 /** 8229 * Destroy the global meter drop table. 8230 * 8231 * @param[in] dev 8232 * Pointer to Ethernet device. 8233 */ 8234 void 8235 mlx5_flow_destroy_mtr_drop_tbls(struct rte_eth_dev *dev) 8236 { 8237 const struct mlx5_flow_driver_ops *fops; 8238 8239 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_DV); 8240 fops->destroy_mtr_drop_tbls(dev); 8241 } 8242 8243 /** 8244 * Destroy the sub policy table with RX queue. 8245 * 8246 * @param[in] dev 8247 * Pointer to Ethernet device. 8248 * @param[in] mtr_policy 8249 * Pointer to meter policy table. 8250 */ 8251 void 8252 mlx5_flow_destroy_sub_policy_with_rxq(struct rte_eth_dev *dev, 8253 struct mlx5_flow_meter_policy *mtr_policy) 8254 { 8255 const struct mlx5_flow_driver_ops *fops; 8256 8257 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_DV); 8258 fops->destroy_sub_policy_with_rxq(dev, mtr_policy); 8259 } 8260 8261 /** 8262 * Allocate the needed aso flow meter id. 8263 * 8264 * @param[in] dev 8265 * Pointer to Ethernet device. 8266 * 8267 * @return 8268 * Index to aso flow meter on success, NULL otherwise. 8269 */ 8270 uint32_t 8271 mlx5_flow_mtr_alloc(struct rte_eth_dev *dev) 8272 { 8273 const struct mlx5_flow_driver_ops *fops; 8274 8275 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_DV); 8276 return fops->create_meter(dev); 8277 } 8278 8279 /** 8280 * Free the aso flow meter id. 8281 * 8282 * @param[in] dev 8283 * Pointer to Ethernet device. 8284 * @param[in] mtr_idx 8285 * Index to aso flow meter to be free. 8286 * 8287 * @return 8288 * 0 on success. 8289 */ 8290 void 8291 mlx5_flow_mtr_free(struct rte_eth_dev *dev, uint32_t mtr_idx) 8292 { 8293 const struct mlx5_flow_driver_ops *fops; 8294 8295 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_DV); 8296 fops->free_meter(dev, mtr_idx); 8297 } 8298 8299 /** 8300 * Allocate a counter. 8301 * 8302 * @param[in] dev 8303 * Pointer to Ethernet device structure. 8304 * 8305 * @return 8306 * Index to allocated counter on success, 0 otherwise. 8307 */ 8308 uint32_t 8309 mlx5_counter_alloc(struct rte_eth_dev *dev) 8310 { 8311 const struct mlx5_flow_driver_ops *fops; 8312 struct rte_flow_attr attr = { .transfer = 0 }; 8313 8314 if (flow_get_drv_type(dev, &attr) == MLX5_FLOW_TYPE_DV) { 8315 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_DV); 8316 return fops->counter_alloc(dev); 8317 } 8318 DRV_LOG(ERR, 8319 "port %u counter allocate is not supported.", 8320 dev->data->port_id); 8321 return 0; 8322 } 8323 8324 /** 8325 * Free a counter. 8326 * 8327 * @param[in] dev 8328 * Pointer to Ethernet device structure. 8329 * @param[in] cnt 8330 * Index to counter to be free. 8331 */ 8332 void 8333 mlx5_counter_free(struct rte_eth_dev *dev, uint32_t cnt) 8334 { 8335 const struct mlx5_flow_driver_ops *fops; 8336 struct rte_flow_attr attr = { .transfer = 0 }; 8337 8338 if (flow_get_drv_type(dev, &attr) == MLX5_FLOW_TYPE_DV) { 8339 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_DV); 8340 fops->counter_free(dev, cnt); 8341 return; 8342 } 8343 DRV_LOG(ERR, 8344 "port %u counter free is not supported.", 8345 dev->data->port_id); 8346 } 8347 8348 /** 8349 * Query counter statistics. 8350 * 8351 * @param[in] dev 8352 * Pointer to Ethernet device structure. 8353 * @param[in] cnt 8354 * Index to counter to query. 8355 * @param[in] clear 8356 * Set to clear counter statistics. 8357 * @param[out] pkts 8358 * The counter hits packets number to save. 8359 * @param[out] bytes 8360 * The counter hits bytes number to save. 8361 * 8362 * @return 8363 * 0 on success, a negative errno value otherwise. 8364 */ 8365 int 8366 mlx5_counter_query(struct rte_eth_dev *dev, uint32_t cnt, 8367 bool clear, uint64_t *pkts, uint64_t *bytes, void **action) 8368 { 8369 const struct mlx5_flow_driver_ops *fops; 8370 struct rte_flow_attr attr = { .transfer = 0 }; 8371 8372 if (flow_get_drv_type(dev, &attr) == MLX5_FLOW_TYPE_DV) { 8373 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_DV); 8374 return fops->counter_query(dev, cnt, clear, pkts, 8375 bytes, action); 8376 } 8377 DRV_LOG(ERR, 8378 "port %u counter query is not supported.", 8379 dev->data->port_id); 8380 return -ENOTSUP; 8381 } 8382 8383 /** 8384 * Get information about HWS pre-configurable resources. 8385 * 8386 * @param[in] dev 8387 * Pointer to the rte_eth_dev structure. 8388 * @param[out] port_info 8389 * Pointer to port information. 8390 * @param[out] queue_info 8391 * Pointer to queue information. 8392 * @param[out] error 8393 * Pointer to error structure. 8394 * 8395 * @return 8396 * 0 on success, a negative errno value otherwise and rte_errno is set. 8397 */ 8398 static int 8399 mlx5_flow_info_get(struct rte_eth_dev *dev, 8400 struct rte_flow_port_info *port_info, 8401 struct rte_flow_queue_info *queue_info, 8402 struct rte_flow_error *error) 8403 { 8404 const struct mlx5_flow_driver_ops *fops; 8405 struct rte_flow_attr attr = {0}; 8406 8407 if (flow_get_drv_type(dev, &attr) != MLX5_FLOW_TYPE_HW) 8408 return rte_flow_error_set(error, ENOTSUP, 8409 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, 8410 NULL, 8411 "info get with incorrect steering mode"); 8412 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_HW); 8413 return fops->info_get(dev, port_info, queue_info, error); 8414 } 8415 8416 /** 8417 * Configure port HWS resources. 8418 * 8419 * @param[in] dev 8420 * Pointer to the rte_eth_dev structure. 8421 * @param[in] port_attr 8422 * Port configuration attributes. 8423 * @param[in] nb_queue 8424 * Number of queue. 8425 * @param[in] queue_attr 8426 * Array that holds attributes for each flow queue. 8427 * @param[out] error 8428 * Pointer to error structure. 8429 * 8430 * @return 8431 * 0 on success, a negative errno value otherwise and rte_errno is set. 8432 */ 8433 static int 8434 mlx5_flow_port_configure(struct rte_eth_dev *dev, 8435 const struct rte_flow_port_attr *port_attr, 8436 uint16_t nb_queue, 8437 const struct rte_flow_queue_attr *queue_attr[], 8438 struct rte_flow_error *error) 8439 { 8440 const struct mlx5_flow_driver_ops *fops; 8441 struct rte_flow_attr attr = {0}; 8442 8443 if (flow_get_drv_type(dev, &attr) != MLX5_FLOW_TYPE_HW) 8444 return rte_flow_error_set(error, ENOTSUP, 8445 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, 8446 NULL, 8447 "port configure with incorrect steering mode"); 8448 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_HW); 8449 return fops->configure(dev, port_attr, nb_queue, queue_attr, error); 8450 } 8451 8452 /** 8453 * Validate item template. 8454 * 8455 * @param[in] dev 8456 * Pointer to the rte_eth_dev structure. 8457 * @param[in] attr 8458 * Pointer to the item template attributes. 8459 * @param[in] items 8460 * The template item pattern. 8461 * @param[out] error 8462 * Pointer to error structure. 8463 * 8464 * @return 8465 * 0 on success, a negative errno value otherwise and rte_errno is set. 8466 */ 8467 int 8468 mlx5_flow_pattern_validate(struct rte_eth_dev *dev, 8469 const struct rte_flow_pattern_template_attr *attr, 8470 const struct rte_flow_item items[], 8471 struct rte_flow_error *error) 8472 { 8473 const struct mlx5_flow_driver_ops *fops; 8474 struct rte_flow_attr fattr = {0}; 8475 8476 if (flow_get_drv_type(dev, &fattr) != MLX5_FLOW_TYPE_HW) { 8477 rte_flow_error_set(error, ENOTSUP, 8478 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, 8479 "pattern validate with incorrect steering mode"); 8480 return -ENOTSUP; 8481 } 8482 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_HW); 8483 return fops->pattern_validate(dev, attr, items, error); 8484 } 8485 8486 /** 8487 * Create flow item template. 8488 * 8489 * @param[in] dev 8490 * Pointer to the rte_eth_dev structure. 8491 * @param[in] attr 8492 * Pointer to the item template attributes. 8493 * @param[in] items 8494 * The template item pattern. 8495 * @param[out] error 8496 * Pointer to error structure. 8497 * 8498 * @return 8499 * 0 on success, a negative errno value otherwise and rte_errno is set. 8500 */ 8501 static struct rte_flow_pattern_template * 8502 mlx5_flow_pattern_template_create(struct rte_eth_dev *dev, 8503 const struct rte_flow_pattern_template_attr *attr, 8504 const struct rte_flow_item items[], 8505 struct rte_flow_error *error) 8506 { 8507 const struct mlx5_flow_driver_ops *fops; 8508 struct rte_flow_attr fattr = {0}; 8509 8510 if (flow_get_drv_type(dev, &fattr) != MLX5_FLOW_TYPE_HW) { 8511 rte_flow_error_set(error, ENOTSUP, 8512 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, 8513 NULL, 8514 "pattern create with incorrect steering mode"); 8515 return NULL; 8516 } 8517 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_HW); 8518 return fops->pattern_template_create(dev, attr, items, error); 8519 } 8520 8521 /** 8522 * Destroy flow item template. 8523 * 8524 * @param[in] dev 8525 * Pointer to the rte_eth_dev structure. 8526 * @param[in] template 8527 * Pointer to the item template to be destroyed. 8528 * @param[out] error 8529 * Pointer to error structure. 8530 * 8531 * @return 8532 * 0 on success, a negative errno value otherwise and rte_errno is set. 8533 */ 8534 static int 8535 mlx5_flow_pattern_template_destroy(struct rte_eth_dev *dev, 8536 struct rte_flow_pattern_template *template, 8537 struct rte_flow_error *error) 8538 { 8539 const struct mlx5_flow_driver_ops *fops; 8540 struct rte_flow_attr attr = {0}; 8541 8542 if (flow_get_drv_type(dev, &attr) != MLX5_FLOW_TYPE_HW) 8543 return rte_flow_error_set(error, ENOTSUP, 8544 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, 8545 NULL, 8546 "pattern destroy with incorrect steering mode"); 8547 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_HW); 8548 return fops->pattern_template_destroy(dev, template, error); 8549 } 8550 8551 /** 8552 * Validate flow actions template. 8553 * 8554 * @param[in] dev 8555 * Pointer to the rte_eth_dev structure. 8556 * @param[in] attr 8557 * Pointer to the action template attributes. 8558 * @param[in] actions 8559 * Associated actions (list terminated by the END action). 8560 * @param[in] masks 8561 * List of actions that marks which of the action's member is constant. 8562 * @param[out] error 8563 * Pointer to error structure. 8564 * 8565 * @return 8566 * 0 on success, a negative errno value otherwise and rte_errno is set. 8567 */ 8568 int 8569 mlx5_flow_actions_validate(struct rte_eth_dev *dev, 8570 const struct rte_flow_actions_template_attr *attr, 8571 const struct rte_flow_action actions[], 8572 const struct rte_flow_action masks[], 8573 struct rte_flow_error *error) 8574 { 8575 const struct mlx5_flow_driver_ops *fops; 8576 struct rte_flow_attr fattr = {0}; 8577 8578 if (flow_get_drv_type(dev, &fattr) != MLX5_FLOW_TYPE_HW) { 8579 rte_flow_error_set(error, ENOTSUP, 8580 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, 8581 "actions validate with incorrect steering mode"); 8582 return -ENOTSUP; 8583 } 8584 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_HW); 8585 return fops->actions_validate(dev, attr, actions, masks, error); 8586 } 8587 8588 /** 8589 * Create flow item template. 8590 * 8591 * @param[in] dev 8592 * Pointer to the rte_eth_dev structure. 8593 * @param[in] attr 8594 * Pointer to the action template attributes. 8595 * @param[in] actions 8596 * Associated actions (list terminated by the END action). 8597 * @param[in] masks 8598 * List of actions that marks which of the action's member is constant. 8599 * @param[out] error 8600 * Pointer to error structure. 8601 * 8602 * @return 8603 * 0 on success, a negative errno value otherwise and rte_errno is set. 8604 */ 8605 static struct rte_flow_actions_template * 8606 mlx5_flow_actions_template_create(struct rte_eth_dev *dev, 8607 const struct rte_flow_actions_template_attr *attr, 8608 const struct rte_flow_action actions[], 8609 const struct rte_flow_action masks[], 8610 struct rte_flow_error *error) 8611 { 8612 const struct mlx5_flow_driver_ops *fops; 8613 struct rte_flow_attr fattr = {0}; 8614 8615 if (flow_get_drv_type(dev, &fattr) != MLX5_FLOW_TYPE_HW) { 8616 rte_flow_error_set(error, ENOTSUP, 8617 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, 8618 NULL, 8619 "action create with incorrect steering mode"); 8620 return NULL; 8621 } 8622 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_HW); 8623 return fops->actions_template_create(dev, attr, actions, masks, error); 8624 } 8625 8626 /** 8627 * Destroy flow action template. 8628 * 8629 * @param[in] dev 8630 * Pointer to the rte_eth_dev structure. 8631 * @param[in] template 8632 * Pointer to the action template to be destroyed. 8633 * @param[out] error 8634 * Pointer to error structure. 8635 * 8636 * @return 8637 * 0 on success, a negative errno value otherwise and rte_errno is set. 8638 */ 8639 static int 8640 mlx5_flow_actions_template_destroy(struct rte_eth_dev *dev, 8641 struct rte_flow_actions_template *template, 8642 struct rte_flow_error *error) 8643 { 8644 const struct mlx5_flow_driver_ops *fops; 8645 struct rte_flow_attr attr = {0}; 8646 8647 if (flow_get_drv_type(dev, &attr) != MLX5_FLOW_TYPE_HW) 8648 return rte_flow_error_set(error, ENOTSUP, 8649 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, 8650 NULL, 8651 "action destroy with incorrect steering mode"); 8652 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_HW); 8653 return fops->actions_template_destroy(dev, template, error); 8654 } 8655 8656 /** 8657 * Create flow table. 8658 * 8659 * @param[in] dev 8660 * Pointer to the rte_eth_dev structure. 8661 * @param[in] attr 8662 * Pointer to the table attributes. 8663 * @param[in] item_templates 8664 * Item template array to be binded to the table. 8665 * @param[in] nb_item_templates 8666 * Number of item template. 8667 * @param[in] action_templates 8668 * Action template array to be binded to the table. 8669 * @param[in] nb_action_templates 8670 * Number of action template. 8671 * @param[out] error 8672 * Pointer to error structure. 8673 * 8674 * @return 8675 * Table on success, NULL otherwise and rte_errno is set. 8676 */ 8677 static struct rte_flow_template_table * 8678 mlx5_flow_table_create(struct rte_eth_dev *dev, 8679 const struct rte_flow_template_table_attr *attr, 8680 struct rte_flow_pattern_template *item_templates[], 8681 uint8_t nb_item_templates, 8682 struct rte_flow_actions_template *action_templates[], 8683 uint8_t nb_action_templates, 8684 struct rte_flow_error *error) 8685 { 8686 const struct mlx5_flow_driver_ops *fops; 8687 struct rte_flow_attr fattr = {0}; 8688 8689 if (flow_get_drv_type(dev, &fattr) != MLX5_FLOW_TYPE_HW) { 8690 rte_flow_error_set(error, ENOTSUP, 8691 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, 8692 NULL, 8693 "table create with incorrect steering mode"); 8694 return NULL; 8695 } 8696 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_HW); 8697 return fops->template_table_create(dev, 8698 attr, 8699 item_templates, 8700 nb_item_templates, 8701 action_templates, 8702 nb_action_templates, 8703 error); 8704 } 8705 8706 /** 8707 * PMD destroy flow table. 8708 * 8709 * @param[in] dev 8710 * Pointer to the rte_eth_dev structure. 8711 * @param[in] table 8712 * Pointer to the table to be destroyed. 8713 * @param[out] error 8714 * Pointer to error structure. 8715 * 8716 * @return 8717 * 0 on success, a negative errno value otherwise and rte_errno is set. 8718 */ 8719 static int 8720 mlx5_flow_table_destroy(struct rte_eth_dev *dev, 8721 struct rte_flow_template_table *table, 8722 struct rte_flow_error *error) 8723 { 8724 const struct mlx5_flow_driver_ops *fops; 8725 struct rte_flow_attr attr = {0}; 8726 8727 if (flow_get_drv_type(dev, &attr) != MLX5_FLOW_TYPE_HW) 8728 return rte_flow_error_set(error, ENOTSUP, 8729 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, 8730 NULL, 8731 "table destroy with incorrect steering mode"); 8732 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_HW); 8733 return fops->template_table_destroy(dev, table, error); 8734 } 8735 8736 /** 8737 * Enqueue flow creation. 8738 * 8739 * @param[in] dev 8740 * Pointer to the rte_eth_dev structure. 8741 * @param[in] queue_id 8742 * The queue to create the flow. 8743 * @param[in] attr 8744 * Pointer to the flow operation attributes. 8745 * @param[in] items 8746 * Items with flow spec value. 8747 * @param[in] pattern_template_index 8748 * The item pattern flow follows from the table. 8749 * @param[in] actions 8750 * Action with flow spec value. 8751 * @param[in] action_template_index 8752 * The action pattern flow follows from the table. 8753 * @param[in] user_data 8754 * Pointer to the user_data. 8755 * @param[out] error 8756 * Pointer to error structure. 8757 * 8758 * @return 8759 * Flow pointer on success, NULL otherwise and rte_errno is set. 8760 */ 8761 static struct rte_flow * 8762 mlx5_flow_async_flow_create(struct rte_eth_dev *dev, 8763 uint32_t queue_id, 8764 const struct rte_flow_op_attr *attr, 8765 struct rte_flow_template_table *table, 8766 const struct rte_flow_item items[], 8767 uint8_t pattern_template_index, 8768 const struct rte_flow_action actions[], 8769 uint8_t action_template_index, 8770 void *user_data, 8771 struct rte_flow_error *error) 8772 { 8773 const struct mlx5_flow_driver_ops *fops; 8774 struct rte_flow_attr fattr = {0}; 8775 8776 if (flow_get_drv_type(dev, &fattr) != MLX5_FLOW_TYPE_HW) { 8777 rte_flow_error_set(error, ENOTSUP, 8778 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, 8779 NULL, 8780 "flow_q create with incorrect steering mode"); 8781 return NULL; 8782 } 8783 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_HW); 8784 return fops->async_flow_create(dev, queue_id, attr, table, 8785 items, pattern_template_index, 8786 actions, action_template_index, 8787 user_data, error); 8788 } 8789 8790 /** 8791 * Enqueue flow destruction. 8792 * 8793 * @param[in] dev 8794 * Pointer to the rte_eth_dev structure. 8795 * @param[in] queue 8796 * The queue to destroy the flow. 8797 * @param[in] attr 8798 * Pointer to the flow operation attributes. 8799 * @param[in] flow 8800 * Pointer to the flow to be destroyed. 8801 * @param[in] user_data 8802 * Pointer to the user_data. 8803 * @param[out] error 8804 * Pointer to error structure. 8805 * 8806 * @return 8807 * 0 on success, negative value otherwise and rte_errno is set. 8808 */ 8809 static int 8810 mlx5_flow_async_flow_destroy(struct rte_eth_dev *dev, 8811 uint32_t queue, 8812 const struct rte_flow_op_attr *attr, 8813 struct rte_flow *flow, 8814 void *user_data, 8815 struct rte_flow_error *error) 8816 { 8817 const struct mlx5_flow_driver_ops *fops; 8818 struct rte_flow_attr fattr = {0}; 8819 8820 if (flow_get_drv_type(dev, &fattr) != MLX5_FLOW_TYPE_HW) 8821 return rte_flow_error_set(error, ENOTSUP, 8822 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, 8823 NULL, 8824 "flow_q destroy with incorrect steering mode"); 8825 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_HW); 8826 return fops->async_flow_destroy(dev, queue, attr, flow, 8827 user_data, error); 8828 } 8829 8830 /** 8831 * Pull the enqueued flows. 8832 * 8833 * @param[in] dev 8834 * Pointer to the rte_eth_dev structure. 8835 * @param[in] queue 8836 * The queue to pull the result. 8837 * @param[in/out] res 8838 * Array to save the results. 8839 * @param[in] n_res 8840 * Available result with the array. 8841 * @param[out] error 8842 * Pointer to error structure. 8843 * 8844 * @return 8845 * Result number on success, negative value otherwise and rte_errno is set. 8846 */ 8847 static int 8848 mlx5_flow_pull(struct rte_eth_dev *dev, 8849 uint32_t queue, 8850 struct rte_flow_op_result res[], 8851 uint16_t n_res, 8852 struct rte_flow_error *error) 8853 { 8854 const struct mlx5_flow_driver_ops *fops; 8855 struct rte_flow_attr attr = {0}; 8856 8857 if (flow_get_drv_type(dev, &attr) != MLX5_FLOW_TYPE_HW) 8858 return rte_flow_error_set(error, ENOTSUP, 8859 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, 8860 NULL, 8861 "flow_q pull with incorrect steering mode"); 8862 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_HW); 8863 return fops->pull(dev, queue, res, n_res, error); 8864 } 8865 8866 /** 8867 * Push the enqueued flows. 8868 * 8869 * @param[in] dev 8870 * Pointer to the rte_eth_dev structure. 8871 * @param[in] queue 8872 * The queue to push the flows. 8873 * @param[out] error 8874 * Pointer to error structure. 8875 * 8876 * @return 8877 * 0 on success, negative value otherwise and rte_errno is set. 8878 */ 8879 static int 8880 mlx5_flow_push(struct rte_eth_dev *dev, 8881 uint32_t queue, 8882 struct rte_flow_error *error) 8883 { 8884 const struct mlx5_flow_driver_ops *fops; 8885 struct rte_flow_attr attr = {0}; 8886 8887 if (flow_get_drv_type(dev, &attr) != MLX5_FLOW_TYPE_HW) 8888 return rte_flow_error_set(error, ENOTSUP, 8889 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, 8890 NULL, 8891 "flow_q push with incorrect steering mode"); 8892 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_HW); 8893 return fops->push(dev, queue, error); 8894 } 8895 8896 /** 8897 * Create shared action. 8898 * 8899 * @param[in] dev 8900 * Pointer to the rte_eth_dev structure. 8901 * @param[in] queue 8902 * Which queue to be used.. 8903 * @param[in] attr 8904 * Operation attribute. 8905 * @param[in] conf 8906 * Indirect action configuration. 8907 * @param[in] action 8908 * rte_flow action detail. 8909 * @param[in] user_data 8910 * Pointer to the user_data. 8911 * @param[out] error 8912 * Pointer to error structure. 8913 * 8914 * @return 8915 * Action handle on success, NULL otherwise and rte_errno is set. 8916 */ 8917 static struct rte_flow_action_handle * 8918 mlx5_flow_async_action_handle_create(struct rte_eth_dev *dev, uint32_t queue, 8919 const struct rte_flow_op_attr *attr, 8920 const struct rte_flow_indir_action_conf *conf, 8921 const struct rte_flow_action *action, 8922 void *user_data, 8923 struct rte_flow_error *error) 8924 { 8925 const struct mlx5_flow_driver_ops *fops = 8926 flow_get_drv_ops(MLX5_FLOW_TYPE_HW); 8927 8928 return fops->async_action_create(dev, queue, attr, conf, action, 8929 user_data, error); 8930 } 8931 8932 /** 8933 * Update shared action. 8934 * 8935 * @param[in] dev 8936 * Pointer to the rte_eth_dev structure. 8937 * @param[in] queue 8938 * Which queue to be used.. 8939 * @param[in] attr 8940 * Operation attribute. 8941 * @param[in] handle 8942 * Action handle to be updated. 8943 * @param[in] update 8944 * Update value. 8945 * @param[in] user_data 8946 * Pointer to the user_data. 8947 * @param[out] error 8948 * Pointer to error structure. 8949 * 8950 * @return 8951 * 0 on success, negative value otherwise and rte_errno is set. 8952 */ 8953 static int 8954 mlx5_flow_async_action_handle_update(struct rte_eth_dev *dev, uint32_t queue, 8955 const struct rte_flow_op_attr *attr, 8956 struct rte_flow_action_handle *handle, 8957 const void *update, 8958 void *user_data, 8959 struct rte_flow_error *error) 8960 { 8961 const struct mlx5_flow_driver_ops *fops = 8962 flow_get_drv_ops(MLX5_FLOW_TYPE_HW); 8963 8964 return fops->async_action_update(dev, queue, attr, handle, 8965 update, user_data, error); 8966 } 8967 8968 /** 8969 * Query shared action. 8970 * 8971 * @param[in] dev 8972 * Pointer to the rte_eth_dev structure. 8973 * @param[in] queue 8974 * Which queue to be used.. 8975 * @param[in] attr 8976 * Operation attribute. 8977 * @param[in] handle 8978 * Action handle to be updated. 8979 * @param[in] data 8980 * Pointer query result data. 8981 * @param[in] user_data 8982 * Pointer to the user_data. 8983 * @param[out] error 8984 * Pointer to error structure. 8985 * 8986 * @return 8987 * 0 on success, negative value otherwise and rte_errno is set. 8988 */ 8989 static int 8990 mlx5_flow_async_action_handle_query(struct rte_eth_dev *dev, uint32_t queue, 8991 const struct rte_flow_op_attr *attr, 8992 const struct rte_flow_action_handle *handle, 8993 void *data, 8994 void *user_data, 8995 struct rte_flow_error *error) 8996 { 8997 const struct mlx5_flow_driver_ops *fops = 8998 flow_get_drv_ops(MLX5_FLOW_TYPE_HW); 8999 9000 return fops->async_action_query(dev, queue, attr, handle, 9001 data, user_data, error); 9002 } 9003 9004 /** 9005 * Destroy shared action. 9006 * 9007 * @param[in] dev 9008 * Pointer to the rte_eth_dev structure. 9009 * @param[in] queue 9010 * Which queue to be used.. 9011 * @param[in] attr 9012 * Operation attribute. 9013 * @param[in] handle 9014 * Action handle to be destroyed. 9015 * @param[in] user_data 9016 * Pointer to the user_data. 9017 * @param[out] error 9018 * Pointer to error structure. 9019 * 9020 * @return 9021 * 0 on success, negative value otherwise and rte_errno is set. 9022 */ 9023 static int 9024 mlx5_flow_async_action_handle_destroy(struct rte_eth_dev *dev, uint32_t queue, 9025 const struct rte_flow_op_attr *attr, 9026 struct rte_flow_action_handle *handle, 9027 void *user_data, 9028 struct rte_flow_error *error) 9029 { 9030 const struct mlx5_flow_driver_ops *fops = 9031 flow_get_drv_ops(MLX5_FLOW_TYPE_HW); 9032 9033 return fops->async_action_destroy(dev, queue, attr, handle, 9034 user_data, error); 9035 } 9036 9037 /** 9038 * Allocate a new memory for the counter values wrapped by all the needed 9039 * management. 9040 * 9041 * @param[in] sh 9042 * Pointer to mlx5_dev_ctx_shared object. 9043 * 9044 * @return 9045 * 0 on success, a negative errno value otherwise. 9046 */ 9047 static int 9048 mlx5_flow_create_counter_stat_mem_mng(struct mlx5_dev_ctx_shared *sh) 9049 { 9050 struct mlx5_counter_stats_mem_mng *mem_mng; 9051 volatile struct flow_counter_stats *raw_data; 9052 int raws_n = MLX5_CNT_MR_ALLOC_BULK + MLX5_MAX_PENDING_QUERIES; 9053 int size = (sizeof(struct flow_counter_stats) * 9054 MLX5_COUNTERS_PER_POOL + 9055 sizeof(struct mlx5_counter_stats_raw)) * raws_n + 9056 sizeof(struct mlx5_counter_stats_mem_mng); 9057 size_t pgsize = rte_mem_page_size(); 9058 uint8_t *mem; 9059 int ret; 9060 int i; 9061 9062 if (pgsize == (size_t)-1) { 9063 DRV_LOG(ERR, "Failed to get mem page size"); 9064 rte_errno = ENOMEM; 9065 return -ENOMEM; 9066 } 9067 mem = mlx5_malloc(MLX5_MEM_ZERO, size, pgsize, SOCKET_ID_ANY); 9068 if (!mem) { 9069 rte_errno = ENOMEM; 9070 return -ENOMEM; 9071 } 9072 mem_mng = (struct mlx5_counter_stats_mem_mng *)(mem + size) - 1; 9073 size = sizeof(*raw_data) * MLX5_COUNTERS_PER_POOL * raws_n; 9074 ret = mlx5_os_wrapped_mkey_create(sh->cdev->ctx, sh->cdev->pd, 9075 sh->cdev->pdn, mem, size, 9076 &mem_mng->wm); 9077 if (ret) { 9078 rte_errno = errno; 9079 mlx5_free(mem); 9080 return -rte_errno; 9081 } 9082 mem_mng->raws = (struct mlx5_counter_stats_raw *)(mem + size); 9083 raw_data = (volatile struct flow_counter_stats *)mem; 9084 for (i = 0; i < raws_n; ++i) { 9085 mem_mng->raws[i].mem_mng = mem_mng; 9086 mem_mng->raws[i].data = raw_data + i * MLX5_COUNTERS_PER_POOL; 9087 } 9088 for (i = 0; i < MLX5_MAX_PENDING_QUERIES; ++i) 9089 LIST_INSERT_HEAD(&sh->sws_cmng.free_stat_raws, 9090 mem_mng->raws + MLX5_CNT_MR_ALLOC_BULK + i, 9091 next); 9092 LIST_INSERT_HEAD(&sh->sws_cmng.mem_mngs, mem_mng, next); 9093 sh->sws_cmng.mem_mng = mem_mng; 9094 return 0; 9095 } 9096 9097 /** 9098 * Set the statistic memory to the new counter pool. 9099 * 9100 * @param[in] sh 9101 * Pointer to mlx5_dev_ctx_shared object. 9102 * @param[in] pool 9103 * Pointer to the pool to set the statistic memory. 9104 * 9105 * @return 9106 * 0 on success, a negative errno value otherwise. 9107 */ 9108 static int 9109 mlx5_flow_set_counter_stat_mem(struct mlx5_dev_ctx_shared *sh, 9110 struct mlx5_flow_counter_pool *pool) 9111 { 9112 struct mlx5_flow_counter_mng *cmng = &sh->sws_cmng; 9113 /* Resize statistic memory once used out. */ 9114 if (!(pool->index % MLX5_CNT_MR_ALLOC_BULK) && 9115 mlx5_flow_create_counter_stat_mem_mng(sh)) { 9116 DRV_LOG(ERR, "Cannot resize counter stat mem."); 9117 return -1; 9118 } 9119 rte_spinlock_lock(&pool->sl); 9120 pool->raw = cmng->mem_mng->raws + pool->index % MLX5_CNT_MR_ALLOC_BULK; 9121 rte_spinlock_unlock(&pool->sl); 9122 pool->raw_hw = NULL; 9123 return 0; 9124 } 9125 9126 #define MLX5_POOL_QUERY_FREQ_US 1000000 9127 9128 /** 9129 * Set the periodic procedure for triggering asynchronous batch queries for all 9130 * the counter pools. 9131 * 9132 * @param[in] sh 9133 * Pointer to mlx5_dev_ctx_shared object. 9134 */ 9135 void 9136 mlx5_set_query_alarm(struct mlx5_dev_ctx_shared *sh) 9137 { 9138 uint32_t pools_n, us; 9139 9140 pools_n = __atomic_load_n(&sh->sws_cmng.n_valid, __ATOMIC_RELAXED); 9141 us = MLX5_POOL_QUERY_FREQ_US / pools_n; 9142 DRV_LOG(DEBUG, "Set alarm for %u pools each %u us", pools_n, us); 9143 if (rte_eal_alarm_set(us, mlx5_flow_query_alarm, sh)) { 9144 sh->sws_cmng.query_thread_on = 0; 9145 DRV_LOG(ERR, "Cannot reinitialize query alarm"); 9146 } else { 9147 sh->sws_cmng.query_thread_on = 1; 9148 } 9149 } 9150 9151 /** 9152 * The periodic procedure for triggering asynchronous batch queries for all the 9153 * counter pools. This function is probably called by the host thread. 9154 * 9155 * @param[in] arg 9156 * The parameter for the alarm process. 9157 */ 9158 void 9159 mlx5_flow_query_alarm(void *arg) 9160 { 9161 struct mlx5_dev_ctx_shared *sh = arg; 9162 struct mlx5_flow_counter_mng *cmng = &sh->sws_cmng; 9163 uint16_t pool_index = cmng->pool_index; 9164 struct mlx5_flow_counter_pool *pool; 9165 uint16_t n_valid; 9166 int ret; 9167 9168 if (cmng->pending_queries >= MLX5_MAX_PENDING_QUERIES) 9169 goto set_alarm; 9170 rte_spinlock_lock(&cmng->pool_update_sl); 9171 pool = cmng->pools[pool_index]; 9172 n_valid = cmng->n_valid; 9173 rte_spinlock_unlock(&cmng->pool_update_sl); 9174 /* Set the statistic memory to the new created pool. */ 9175 if ((!pool->raw && mlx5_flow_set_counter_stat_mem(sh, pool))) 9176 goto set_alarm; 9177 if (pool->raw_hw) 9178 /* There is a pool query in progress. */ 9179 goto set_alarm; 9180 pool->raw_hw = LIST_FIRST(&cmng->free_stat_raws); 9181 if (!pool->raw_hw) 9182 /* No free counter statistics raw memory. */ 9183 goto set_alarm; 9184 /* 9185 * Identify the counters released between query trigger and query 9186 * handle more efficiently. The counter released in this gap period 9187 * should wait for a new round of query as the new arrived packets 9188 * will not be taken into account. 9189 */ 9190 pool->query_gen++; 9191 ret = mlx5_devx_cmd_flow_counter_query(pool->min_dcs, 0, 9192 MLX5_COUNTERS_PER_POOL, 9193 NULL, NULL, 9194 pool->raw_hw->mem_mng->wm.lkey, 9195 (void *)(uintptr_t) 9196 pool->raw_hw->data, 9197 sh->devx_comp, 9198 (uint64_t)(uintptr_t)pool); 9199 if (ret) { 9200 DRV_LOG(ERR, "Failed to trigger asynchronous query for dcs ID" 9201 " %d", pool->min_dcs->id); 9202 pool->raw_hw = NULL; 9203 goto set_alarm; 9204 } 9205 LIST_REMOVE(pool->raw_hw, next); 9206 cmng->pending_queries++; 9207 pool_index++; 9208 if (pool_index >= n_valid) 9209 pool_index = 0; 9210 set_alarm: 9211 cmng->pool_index = pool_index; 9212 mlx5_set_query_alarm(sh); 9213 } 9214 9215 /** 9216 * Check and callback event for new aged flow in the counter pool 9217 * 9218 * @param[in] sh 9219 * Pointer to mlx5_dev_ctx_shared object. 9220 * @param[in] pool 9221 * Pointer to Current counter pool. 9222 */ 9223 static void 9224 mlx5_flow_aging_check(struct mlx5_dev_ctx_shared *sh, 9225 struct mlx5_flow_counter_pool *pool) 9226 { 9227 struct mlx5_priv *priv; 9228 struct mlx5_flow_counter *cnt; 9229 struct mlx5_age_info *age_info; 9230 struct mlx5_age_param *age_param; 9231 struct mlx5_counter_stats_raw *cur = pool->raw_hw; 9232 struct mlx5_counter_stats_raw *prev = pool->raw; 9233 const uint64_t curr_time = MLX5_CURR_TIME_SEC; 9234 const uint32_t time_delta = curr_time - pool->time_of_last_age_check; 9235 uint16_t expected = AGE_CANDIDATE; 9236 uint32_t i; 9237 9238 pool->time_of_last_age_check = curr_time; 9239 for (i = 0; i < MLX5_COUNTERS_PER_POOL; ++i) { 9240 cnt = MLX5_POOL_GET_CNT(pool, i); 9241 age_param = MLX5_CNT_TO_AGE(cnt); 9242 if (__atomic_load_n(&age_param->state, 9243 __ATOMIC_RELAXED) != AGE_CANDIDATE) 9244 continue; 9245 if (cur->data[i].hits != prev->data[i].hits) { 9246 __atomic_store_n(&age_param->sec_since_last_hit, 0, 9247 __ATOMIC_RELAXED); 9248 continue; 9249 } 9250 if (__atomic_add_fetch(&age_param->sec_since_last_hit, 9251 time_delta, 9252 __ATOMIC_RELAXED) <= age_param->timeout) 9253 continue; 9254 /** 9255 * Hold the lock first, or if between the 9256 * state AGE_TMOUT and tailq operation the 9257 * release happened, the release procedure 9258 * may delete a non-existent tailq node. 9259 */ 9260 priv = rte_eth_devices[age_param->port_id].data->dev_private; 9261 age_info = GET_PORT_AGE_INFO(priv); 9262 rte_spinlock_lock(&age_info->aged_sl); 9263 if (__atomic_compare_exchange_n(&age_param->state, &expected, 9264 AGE_TMOUT, false, 9265 __ATOMIC_RELAXED, 9266 __ATOMIC_RELAXED)) { 9267 TAILQ_INSERT_TAIL(&age_info->aged_counters, cnt, next); 9268 MLX5_AGE_SET(age_info, MLX5_AGE_EVENT_NEW); 9269 } 9270 rte_spinlock_unlock(&age_info->aged_sl); 9271 } 9272 mlx5_age_event_prepare(sh); 9273 } 9274 9275 /** 9276 * Handler for the HW respond about ready values from an asynchronous batch 9277 * query. This function is probably called by the host thread. 9278 * 9279 * @param[in] sh 9280 * The pointer to the shared device context. 9281 * @param[in] async_id 9282 * The Devx async ID. 9283 * @param[in] status 9284 * The status of the completion. 9285 */ 9286 void 9287 mlx5_flow_async_pool_query_handle(struct mlx5_dev_ctx_shared *sh, 9288 uint64_t async_id, int status) 9289 { 9290 struct mlx5_flow_counter_pool *pool = 9291 (struct mlx5_flow_counter_pool *)(uintptr_t)async_id; 9292 struct mlx5_counter_stats_raw *raw_to_free; 9293 uint8_t query_gen = pool->query_gen ^ 1; 9294 struct mlx5_flow_counter_mng *cmng = &sh->sws_cmng; 9295 enum mlx5_counter_type cnt_type = 9296 pool->is_aged ? MLX5_COUNTER_TYPE_AGE : 9297 MLX5_COUNTER_TYPE_ORIGIN; 9298 9299 if (unlikely(status)) { 9300 raw_to_free = pool->raw_hw; 9301 } else { 9302 raw_to_free = pool->raw; 9303 if (pool->is_aged) 9304 mlx5_flow_aging_check(sh, pool); 9305 rte_spinlock_lock(&pool->sl); 9306 pool->raw = pool->raw_hw; 9307 rte_spinlock_unlock(&pool->sl); 9308 /* Be sure the new raw counters data is updated in memory. */ 9309 rte_io_wmb(); 9310 if (!TAILQ_EMPTY(&pool->counters[query_gen])) { 9311 rte_spinlock_lock(&cmng->csl[cnt_type]); 9312 TAILQ_CONCAT(&cmng->counters[cnt_type], 9313 &pool->counters[query_gen], next); 9314 rte_spinlock_unlock(&cmng->csl[cnt_type]); 9315 } 9316 } 9317 LIST_INSERT_HEAD(&sh->sws_cmng.free_stat_raws, raw_to_free, next); 9318 pool->raw_hw = NULL; 9319 sh->sws_cmng.pending_queries--; 9320 } 9321 9322 static int 9323 flow_group_to_table(uint32_t port_id, uint32_t group, uint32_t *table, 9324 const struct flow_grp_info *grp_info, 9325 struct rte_flow_error *error) 9326 { 9327 if (grp_info->transfer && grp_info->external && 9328 grp_info->fdb_def_rule) { 9329 if (group == UINT32_MAX) 9330 return rte_flow_error_set 9331 (error, EINVAL, 9332 RTE_FLOW_ERROR_TYPE_ATTR_GROUP, 9333 NULL, 9334 "group index not supported"); 9335 *table = group + 1; 9336 } else { 9337 *table = group; 9338 } 9339 DRV_LOG(DEBUG, "port %u group=%#x table=%#x", port_id, group, *table); 9340 return 0; 9341 } 9342 9343 /** 9344 * Translate the rte_flow group index to HW table value. 9345 * 9346 * If tunnel offload is disabled, all group ids converted to flow table 9347 * id using the standard method. 9348 * If tunnel offload is enabled, group id can be converted using the 9349 * standard or tunnel conversion method. Group conversion method 9350 * selection depends on flags in `grp_info` parameter: 9351 * - Internal (grp_info.external == 0) groups conversion uses the 9352 * standard method. 9353 * - Group ids in JUMP action converted with the tunnel conversion. 9354 * - Group id in rule attribute conversion depends on a rule type and 9355 * group id value: 9356 * ** non zero group attributes converted with the tunnel method 9357 * ** zero group attribute in non-tunnel rule is converted using the 9358 * standard method - there's only one root table 9359 * ** zero group attribute in steer tunnel rule is converted with the 9360 * standard method - single root table 9361 * ** zero group attribute in match tunnel rule is a special OvS 9362 * case: that value is used for portability reasons. That group 9363 * id is converted with the tunnel conversion method. 9364 * 9365 * @param[in] dev 9366 * Port device 9367 * @param[in] tunnel 9368 * PMD tunnel offload object 9369 * @param[in] group 9370 * rte_flow group index value. 9371 * @param[out] table 9372 * HW table value. 9373 * @param[in] grp_info 9374 * flags used for conversion 9375 * @param[out] error 9376 * Pointer to error structure. 9377 * 9378 * @return 9379 * 0 on success, a negative errno value otherwise and rte_errno is set. 9380 */ 9381 int 9382 mlx5_flow_group_to_table(struct rte_eth_dev *dev, 9383 const struct mlx5_flow_tunnel *tunnel, 9384 uint32_t group, uint32_t *table, 9385 const struct flow_grp_info *grp_info, 9386 struct rte_flow_error *error) 9387 { 9388 int ret; 9389 bool standard_translation; 9390 9391 if (!grp_info->skip_scale && grp_info->external && 9392 group < MLX5_MAX_TABLES_EXTERNAL) 9393 group *= MLX5_FLOW_TABLE_FACTOR; 9394 if (is_tunnel_offload_active(dev)) { 9395 standard_translation = !grp_info->external || 9396 grp_info->std_tbl_fix; 9397 } else { 9398 standard_translation = true; 9399 } 9400 DRV_LOG(DEBUG, 9401 "port %u group=%u transfer=%d external=%d fdb_def_rule=%d translate=%s", 9402 dev->data->port_id, group, grp_info->transfer, 9403 grp_info->external, grp_info->fdb_def_rule, 9404 standard_translation ? "STANDARD" : "TUNNEL"); 9405 if (standard_translation) 9406 ret = flow_group_to_table(dev->data->port_id, group, table, 9407 grp_info, error); 9408 else 9409 ret = tunnel_flow_group_to_flow_table(dev, tunnel, group, 9410 table, error); 9411 9412 return ret; 9413 } 9414 9415 /** 9416 * Discover availability of metadata reg_c's. 9417 * 9418 * Iteratively use test flows to check availability. 9419 * 9420 * @param[in] dev 9421 * Pointer to the Ethernet device structure. 9422 * 9423 * @return 9424 * 0 on success, a negative errno value otherwise and rte_errno is set. 9425 */ 9426 int 9427 mlx5_flow_discover_mreg_c(struct rte_eth_dev *dev) 9428 { 9429 struct mlx5_priv *priv = dev->data->dev_private; 9430 enum modify_reg idx; 9431 int n = 0; 9432 9433 /* reg_c[0] and reg_c[1] are reserved. */ 9434 priv->sh->flow_mreg_c[n++] = REG_C_0; 9435 priv->sh->flow_mreg_c[n++] = REG_C_1; 9436 /* Discover availability of other reg_c's. */ 9437 for (idx = REG_C_2; idx <= REG_C_7; ++idx) { 9438 struct rte_flow_attr attr = { 9439 .group = MLX5_FLOW_MREG_CP_TABLE_GROUP, 9440 .priority = MLX5_FLOW_LOWEST_PRIO_INDICATOR, 9441 .ingress = 1, 9442 }; 9443 struct rte_flow_item items[] = { 9444 [0] = { 9445 .type = RTE_FLOW_ITEM_TYPE_END, 9446 }, 9447 }; 9448 struct rte_flow_action actions[] = { 9449 [0] = { 9450 .type = (enum rte_flow_action_type) 9451 MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG, 9452 .conf = &(struct mlx5_flow_action_copy_mreg){ 9453 .src = REG_C_1, 9454 .dst = idx, 9455 }, 9456 }, 9457 [1] = { 9458 .type = RTE_FLOW_ACTION_TYPE_JUMP, 9459 .conf = &(struct rte_flow_action_jump){ 9460 .group = MLX5_FLOW_MREG_ACT_TABLE_GROUP, 9461 }, 9462 }, 9463 [2] = { 9464 .type = RTE_FLOW_ACTION_TYPE_END, 9465 }, 9466 }; 9467 uint32_t flow_idx; 9468 struct rte_flow *flow; 9469 struct rte_flow_error error; 9470 9471 if (!priv->sh->config.dv_flow_en) 9472 break; 9473 /* Create internal flow, validation skips copy action. */ 9474 flow_idx = flow_list_create(dev, MLX5_FLOW_TYPE_GEN, &attr, 9475 items, actions, false, &error); 9476 flow = mlx5_ipool_get(priv->flows[MLX5_FLOW_TYPE_GEN], 9477 flow_idx); 9478 if (!flow) 9479 continue; 9480 priv->sh->flow_mreg_c[n++] = idx; 9481 flow_list_destroy(dev, MLX5_FLOW_TYPE_GEN, flow_idx); 9482 } 9483 for (; n < MLX5_MREG_C_NUM; ++n) 9484 priv->sh->flow_mreg_c[n] = REG_NON; 9485 priv->sh->metadata_regc_check_flag = 1; 9486 return 0; 9487 } 9488 9489 int 9490 save_dump_file(const uint8_t *data, uint32_t size, 9491 uint32_t type, uint64_t id, void *arg, FILE *file) 9492 { 9493 char line[BUF_SIZE]; 9494 uint32_t out = 0; 9495 uint32_t k; 9496 uint32_t actions_num; 9497 struct rte_flow_query_count *count; 9498 9499 memset(line, 0, BUF_SIZE); 9500 switch (type) { 9501 case DR_DUMP_REC_TYPE_PMD_MODIFY_HDR: 9502 actions_num = *(uint32_t *)(arg); 9503 out += snprintf(line + out, BUF_SIZE - out, "%d,0x%" PRIx64 ",%d,", 9504 type, id, actions_num); 9505 break; 9506 case DR_DUMP_REC_TYPE_PMD_PKT_REFORMAT: 9507 out += snprintf(line + out, BUF_SIZE - out, "%d,0x%" PRIx64 ",", 9508 type, id); 9509 break; 9510 case DR_DUMP_REC_TYPE_PMD_COUNTER: 9511 count = (struct rte_flow_query_count *)arg; 9512 fprintf(file, 9513 "%d,0x%" PRIx64 ",%" PRIu64 ",%" PRIu64 "\n", 9514 type, id, count->hits, count->bytes); 9515 return 0; 9516 default: 9517 return -1; 9518 } 9519 9520 for (k = 0; k < size; k++) { 9521 /* Make sure we do not overrun the line buffer length. */ 9522 if (out >= BUF_SIZE - 4) { 9523 line[out] = '\0'; 9524 break; 9525 } 9526 out += snprintf(line + out, BUF_SIZE - out, "%02x", 9527 (data[k]) & 0xff); 9528 } 9529 fprintf(file, "%s\n", line); 9530 return 0; 9531 } 9532 9533 int 9534 mlx5_flow_query_counter(struct rte_eth_dev *dev, struct rte_flow *flow, 9535 struct rte_flow_query_count *count, struct rte_flow_error *error) 9536 { 9537 struct rte_flow_action action[2]; 9538 enum mlx5_flow_drv_type ftype; 9539 const struct mlx5_flow_driver_ops *fops; 9540 9541 if (!flow) { 9542 return rte_flow_error_set(error, ENOENT, 9543 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, 9544 NULL, 9545 "invalid flow handle"); 9546 } 9547 action[0].type = RTE_FLOW_ACTION_TYPE_COUNT; 9548 action[1].type = RTE_FLOW_ACTION_TYPE_END; 9549 if (flow->counter) { 9550 memset(count, 0, sizeof(struct rte_flow_query_count)); 9551 ftype = (enum mlx5_flow_drv_type)(flow->drv_type); 9552 MLX5_ASSERT(ftype > MLX5_FLOW_TYPE_MIN && 9553 ftype < MLX5_FLOW_TYPE_MAX); 9554 fops = flow_get_drv_ops(ftype); 9555 return fops->query(dev, flow, action, count, error); 9556 } 9557 return -1; 9558 } 9559 9560 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 9561 /** 9562 * Dump flow ipool data to file 9563 * 9564 * @param[in] dev 9565 * The pointer to Ethernet device. 9566 * @param[in] file 9567 * A pointer to a file for output. 9568 * @param[out] error 9569 * Perform verbose error reporting if not NULL. PMDs initialize this 9570 * structure in case of error only. 9571 * @return 9572 * 0 on success, a negative value otherwise. 9573 */ 9574 int 9575 mlx5_flow_dev_dump_ipool(struct rte_eth_dev *dev, 9576 struct rte_flow *flow, FILE *file, 9577 struct rte_flow_error *error) 9578 { 9579 struct mlx5_priv *priv = dev->data->dev_private; 9580 struct mlx5_flow_dv_modify_hdr_resource *modify_hdr; 9581 struct mlx5_flow_dv_encap_decap_resource *encap_decap; 9582 uint32_t handle_idx; 9583 struct mlx5_flow_handle *dh; 9584 struct rte_flow_query_count count; 9585 uint32_t actions_num; 9586 const uint8_t *data; 9587 size_t size; 9588 uint64_t id; 9589 uint32_t type; 9590 void *action = NULL; 9591 9592 if (!flow) { 9593 return rte_flow_error_set(error, ENOENT, 9594 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, 9595 NULL, 9596 "invalid flow handle"); 9597 } 9598 handle_idx = flow->dev_handles; 9599 /* query counter */ 9600 if (flow->counter && 9601 (!mlx5_counter_query(dev, flow->counter, false, 9602 &count.hits, &count.bytes, &action)) && action) { 9603 id = (uint64_t)(uintptr_t)action; 9604 type = DR_DUMP_REC_TYPE_PMD_COUNTER; 9605 save_dump_file(NULL, 0, type, 9606 id, (void *)&count, file); 9607 } 9608 9609 while (handle_idx) { 9610 dh = mlx5_ipool_get(priv->sh->ipool 9611 [MLX5_IPOOL_MLX5_FLOW], handle_idx); 9612 if (!dh) 9613 continue; 9614 handle_idx = dh->next.next; 9615 9616 /* Get modify_hdr and encap_decap buf from ipools. */ 9617 encap_decap = NULL; 9618 modify_hdr = dh->dvh.modify_hdr; 9619 9620 if (dh->dvh.rix_encap_decap) { 9621 encap_decap = mlx5_ipool_get(priv->sh->ipool 9622 [MLX5_IPOOL_DECAP_ENCAP], 9623 dh->dvh.rix_encap_decap); 9624 } 9625 if (modify_hdr) { 9626 data = (const uint8_t *)modify_hdr->actions; 9627 size = (size_t)(modify_hdr->actions_num) * 8; 9628 id = (uint64_t)(uintptr_t)modify_hdr->action; 9629 actions_num = modify_hdr->actions_num; 9630 type = DR_DUMP_REC_TYPE_PMD_MODIFY_HDR; 9631 save_dump_file(data, size, type, id, 9632 (void *)(&actions_num), file); 9633 } 9634 if (encap_decap) { 9635 data = encap_decap->buf; 9636 size = encap_decap->size; 9637 id = (uint64_t)(uintptr_t)encap_decap->action; 9638 type = DR_DUMP_REC_TYPE_PMD_PKT_REFORMAT; 9639 save_dump_file(data, size, type, 9640 id, NULL, file); 9641 } 9642 } 9643 return 0; 9644 } 9645 9646 /** 9647 * Dump all flow's encap_decap/modify_hdr/counter data to file 9648 * 9649 * @param[in] dev 9650 * The pointer to Ethernet device. 9651 * @param[in] file 9652 * A pointer to a file for output. 9653 * @param[out] error 9654 * Perform verbose error reporting if not NULL. PMDs initialize this 9655 * structure in case of error only. 9656 * @return 9657 * 0 on success, a negative value otherwise. 9658 */ 9659 static int 9660 mlx5_flow_dev_dump_sh_all(struct rte_eth_dev *dev, 9661 FILE *file, struct rte_flow_error *error __rte_unused) 9662 { 9663 struct mlx5_priv *priv = dev->data->dev_private; 9664 struct mlx5_dev_ctx_shared *sh = priv->sh; 9665 struct mlx5_hlist *h; 9666 struct mlx5_flow_dv_modify_hdr_resource *modify_hdr; 9667 struct mlx5_flow_dv_encap_decap_resource *encap_decap; 9668 struct rte_flow_query_count count; 9669 uint32_t actions_num; 9670 const uint8_t *data; 9671 size_t size; 9672 uint64_t id; 9673 uint32_t type; 9674 uint32_t i; 9675 uint32_t j; 9676 struct mlx5_list_inconst *l_inconst; 9677 struct mlx5_list_entry *e; 9678 int lcore_index; 9679 struct mlx5_flow_counter_mng *cmng = &priv->sh->sws_cmng; 9680 uint32_t max; 9681 void *action; 9682 9683 /* encap_decap hlist is lcore_share, get global core cache. */ 9684 i = MLX5_LIST_GLOBAL; 9685 h = sh->encaps_decaps; 9686 if (h) { 9687 for (j = 0; j <= h->mask; j++) { 9688 l_inconst = &h->buckets[j].l; 9689 if (!l_inconst || !l_inconst->cache[i]) 9690 continue; 9691 9692 e = LIST_FIRST(&l_inconst->cache[i]->h); 9693 while (e) { 9694 encap_decap = 9695 (struct mlx5_flow_dv_encap_decap_resource *)e; 9696 data = encap_decap->buf; 9697 size = encap_decap->size; 9698 id = (uint64_t)(uintptr_t)encap_decap->action; 9699 type = DR_DUMP_REC_TYPE_PMD_PKT_REFORMAT; 9700 save_dump_file(data, size, type, 9701 id, NULL, file); 9702 e = LIST_NEXT(e, next); 9703 } 9704 } 9705 } 9706 9707 /* get modify_hdr */ 9708 h = sh->modify_cmds; 9709 if (h) { 9710 lcore_index = rte_lcore_index(rte_lcore_id()); 9711 if (unlikely(lcore_index == -1)) { 9712 lcore_index = MLX5_LIST_NLCORE; 9713 rte_spinlock_lock(&h->l_const.lcore_lock); 9714 } 9715 i = lcore_index; 9716 9717 for (j = 0; j <= h->mask; j++) { 9718 l_inconst = &h->buckets[j].l; 9719 if (!l_inconst || !l_inconst->cache[i]) 9720 continue; 9721 9722 e = LIST_FIRST(&l_inconst->cache[i]->h); 9723 while (e) { 9724 modify_hdr = 9725 (struct mlx5_flow_dv_modify_hdr_resource *)e; 9726 data = (const uint8_t *)modify_hdr->actions; 9727 size = (size_t)(modify_hdr->actions_num) * 8; 9728 actions_num = modify_hdr->actions_num; 9729 id = (uint64_t)(uintptr_t)modify_hdr->action; 9730 type = DR_DUMP_REC_TYPE_PMD_MODIFY_HDR; 9731 save_dump_file(data, size, type, id, 9732 (void *)(&actions_num), file); 9733 e = LIST_NEXT(e, next); 9734 } 9735 } 9736 9737 if (unlikely(lcore_index == MLX5_LIST_NLCORE)) 9738 rte_spinlock_unlock(&h->l_const.lcore_lock); 9739 } 9740 9741 /* get counter */ 9742 MLX5_ASSERT(cmng->n_valid <= MLX5_COUNTER_POOLS_MAX_NUM); 9743 max = MLX5_COUNTERS_PER_POOL * cmng->n_valid; 9744 for (j = 1; j <= max; j++) { 9745 action = NULL; 9746 if ((!mlx5_counter_query(dev, j, false, &count.hits, 9747 &count.bytes, &action)) && action) { 9748 id = (uint64_t)(uintptr_t)action; 9749 type = DR_DUMP_REC_TYPE_PMD_COUNTER; 9750 save_dump_file(NULL, 0, type, 9751 id, (void *)&count, file); 9752 } 9753 } 9754 return 0; 9755 } 9756 #endif 9757 9758 /** 9759 * Dump flow raw hw data to file 9760 * 9761 * @param[in] dev 9762 * The pointer to Ethernet device. 9763 * @param[in] file 9764 * A pointer to a file for output. 9765 * @param[out] error 9766 * Perform verbose error reporting if not NULL. PMDs initialize this 9767 * structure in case of error only. 9768 * @return 9769 * 0 on success, a negative value otherwise. 9770 */ 9771 int 9772 mlx5_flow_dev_dump(struct rte_eth_dev *dev, struct rte_flow *flow_idx, 9773 FILE *file, 9774 struct rte_flow_error *error __rte_unused) 9775 { 9776 struct mlx5_priv *priv = dev->data->dev_private; 9777 struct mlx5_dev_ctx_shared *sh = priv->sh; 9778 uint32_t handle_idx; 9779 int ret; 9780 struct mlx5_flow_handle *dh; 9781 struct rte_flow *flow; 9782 9783 if (!sh->config.dv_flow_en) { 9784 if (fputs("device dv flow disabled\n", file) <= 0) 9785 return -errno; 9786 return -ENOTSUP; 9787 } 9788 9789 /* dump all */ 9790 if (!flow_idx) { 9791 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 9792 if (mlx5_flow_dev_dump_sh_all(dev, file, error)) 9793 return -EINVAL; 9794 #endif 9795 return mlx5_devx_cmd_flow_dump(sh->fdb_domain, 9796 sh->rx_domain, 9797 sh->tx_domain, file); 9798 } 9799 /* dump one */ 9800 flow = mlx5_ipool_get(priv->flows[MLX5_FLOW_TYPE_GEN], 9801 (uintptr_t)(void *)flow_idx); 9802 if (!flow) 9803 return -EINVAL; 9804 9805 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 9806 mlx5_flow_dev_dump_ipool(dev, flow, file, error); 9807 #endif 9808 handle_idx = flow->dev_handles; 9809 while (handle_idx) { 9810 dh = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW], 9811 handle_idx); 9812 if (!dh) 9813 return -ENOENT; 9814 if (dh->drv_flow) { 9815 ret = mlx5_devx_cmd_flow_single_dump(dh->drv_flow, 9816 file); 9817 if (ret) 9818 return -ENOENT; 9819 } 9820 handle_idx = dh->next.next; 9821 } 9822 return 0; 9823 } 9824 9825 /** 9826 * Get aged-out flows. 9827 * 9828 * @param[in] dev 9829 * Pointer to the Ethernet device structure. 9830 * @param[in] context 9831 * The address of an array of pointers to the aged-out flows contexts. 9832 * @param[in] nb_countexts 9833 * The length of context array pointers. 9834 * @param[out] error 9835 * Perform verbose error reporting if not NULL. Initialized in case of 9836 * error only. 9837 * 9838 * @return 9839 * how many contexts get in success, otherwise negative errno value. 9840 * if nb_contexts is 0, return the amount of all aged contexts. 9841 * if nb_contexts is not 0 , return the amount of aged flows reported 9842 * in the context array. 9843 */ 9844 int 9845 mlx5_flow_get_aged_flows(struct rte_eth_dev *dev, void **contexts, 9846 uint32_t nb_contexts, struct rte_flow_error *error) 9847 { 9848 const struct mlx5_flow_driver_ops *fops; 9849 struct rte_flow_attr attr = { .transfer = 0 }; 9850 enum mlx5_flow_drv_type type = flow_get_drv_type(dev, &attr); 9851 9852 if (type == MLX5_FLOW_TYPE_DV || type == MLX5_FLOW_TYPE_HW) { 9853 fops = flow_get_drv_ops(type); 9854 return fops->get_aged_flows(dev, contexts, nb_contexts, error); 9855 } 9856 DRV_LOG(ERR, "port %u get aged flows is not supported.", 9857 dev->data->port_id); 9858 return -ENOTSUP; 9859 } 9860 9861 /** 9862 * Get aged-out flows per HWS queue. 9863 * 9864 * @param[in] dev 9865 * Pointer to the Ethernet device structure. 9866 * @param[in] queue_id 9867 * Flow queue to query. 9868 * @param[in] context 9869 * The address of an array of pointers to the aged-out flows contexts. 9870 * @param[in] nb_countexts 9871 * The length of context array pointers. 9872 * @param[out] error 9873 * Perform verbose error reporting if not NULL. Initialized in case of 9874 * error only. 9875 * 9876 * @return 9877 * how many contexts get in success, otherwise negative errno value. 9878 * if nb_contexts is 0, return the amount of all aged contexts. 9879 * if nb_contexts is not 0 , return the amount of aged flows reported 9880 * in the context array. 9881 */ 9882 int 9883 mlx5_flow_get_q_aged_flows(struct rte_eth_dev *dev, uint32_t queue_id, 9884 void **contexts, uint32_t nb_contexts, 9885 struct rte_flow_error *error) 9886 { 9887 const struct mlx5_flow_driver_ops *fops; 9888 struct rte_flow_attr attr = { 0 }; 9889 9890 if (flow_get_drv_type(dev, &attr) == MLX5_FLOW_TYPE_HW) { 9891 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_HW); 9892 return fops->get_q_aged_flows(dev, queue_id, contexts, 9893 nb_contexts, error); 9894 } 9895 DRV_LOG(ERR, "port %u queue %u get aged flows is not supported.", 9896 dev->data->port_id, queue_id); 9897 return rte_flow_error_set(error, ENOTSUP, 9898 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, 9899 "get Q aged flows with incorrect steering mode"); 9900 } 9901 9902 /* Wrapper for driver action_validate op callback */ 9903 static int 9904 flow_drv_action_validate(struct rte_eth_dev *dev, 9905 const struct rte_flow_indir_action_conf *conf, 9906 const struct rte_flow_action *action, 9907 const struct mlx5_flow_driver_ops *fops, 9908 struct rte_flow_error *error) 9909 { 9910 static const char err_msg[] = "indirect action validation unsupported"; 9911 9912 if (!fops->action_validate) { 9913 DRV_LOG(ERR, "port %u %s.", dev->data->port_id, err_msg); 9914 rte_flow_error_set(error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION, 9915 NULL, err_msg); 9916 return -rte_errno; 9917 } 9918 return fops->action_validate(dev, conf, action, error); 9919 } 9920 9921 /** 9922 * Destroys the shared action by handle. 9923 * 9924 * @param dev 9925 * Pointer to Ethernet device structure. 9926 * @param[in] handle 9927 * Handle for the indirect action object to be destroyed. 9928 * @param[out] error 9929 * Perform verbose error reporting if not NULL. PMDs initialize this 9930 * structure in case of error only. 9931 * 9932 * @return 9933 * 0 on success, a negative errno value otherwise and rte_errno is set. 9934 * 9935 * @note: wrapper for driver action_create op callback. 9936 */ 9937 static int 9938 mlx5_action_handle_destroy(struct rte_eth_dev *dev, 9939 struct rte_flow_action_handle *handle, 9940 struct rte_flow_error *error) 9941 { 9942 static const char err_msg[] = "indirect action destruction unsupported"; 9943 struct rte_flow_attr attr = { .transfer = 0 }; 9944 const struct mlx5_flow_driver_ops *fops = 9945 flow_get_drv_ops(flow_get_drv_type(dev, &attr)); 9946 9947 if (!fops->action_destroy) { 9948 DRV_LOG(ERR, "port %u %s.", dev->data->port_id, err_msg); 9949 rte_flow_error_set(error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION, 9950 NULL, err_msg); 9951 return -rte_errno; 9952 } 9953 return fops->action_destroy(dev, handle, error); 9954 } 9955 9956 /* Wrapper for driver action_destroy op callback */ 9957 static int 9958 flow_drv_action_update(struct rte_eth_dev *dev, 9959 struct rte_flow_action_handle *handle, 9960 const void *update, 9961 const struct mlx5_flow_driver_ops *fops, 9962 struct rte_flow_error *error) 9963 { 9964 static const char err_msg[] = "indirect action update unsupported"; 9965 9966 if (!fops->action_update) { 9967 DRV_LOG(ERR, "port %u %s.", dev->data->port_id, err_msg); 9968 rte_flow_error_set(error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION, 9969 NULL, err_msg); 9970 return -rte_errno; 9971 } 9972 return fops->action_update(dev, handle, update, error); 9973 } 9974 9975 /* Wrapper for driver action_destroy op callback */ 9976 static int 9977 flow_drv_action_query(struct rte_eth_dev *dev, 9978 const struct rte_flow_action_handle *handle, 9979 void *data, 9980 const struct mlx5_flow_driver_ops *fops, 9981 struct rte_flow_error *error) 9982 { 9983 static const char err_msg[] = "indirect action query unsupported"; 9984 9985 if (!fops->action_query) { 9986 DRV_LOG(ERR, "port %u %s.", dev->data->port_id, err_msg); 9987 rte_flow_error_set(error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION, 9988 NULL, err_msg); 9989 return -rte_errno; 9990 } 9991 return fops->action_query(dev, handle, data, error); 9992 } 9993 9994 /** 9995 * Create indirect action for reuse in multiple flow rules. 9996 * 9997 * @param dev 9998 * Pointer to Ethernet device structure. 9999 * @param conf 10000 * Pointer to indirect action object configuration. 10001 * @param[in] action 10002 * Action configuration for indirect action object creation. 10003 * @param[out] error 10004 * Perform verbose error reporting if not NULL. PMDs initialize this 10005 * structure in case of error only. 10006 * @return 10007 * A valid handle in case of success, NULL otherwise and rte_errno is set. 10008 */ 10009 static struct rte_flow_action_handle * 10010 mlx5_action_handle_create(struct rte_eth_dev *dev, 10011 const struct rte_flow_indir_action_conf *conf, 10012 const struct rte_flow_action *action, 10013 struct rte_flow_error *error) 10014 { 10015 static const char err_msg[] = "indirect action creation unsupported"; 10016 struct rte_flow_attr attr = { .transfer = 0 }; 10017 const struct mlx5_flow_driver_ops *fops = 10018 flow_get_drv_ops(flow_get_drv_type(dev, &attr)); 10019 10020 if (flow_drv_action_validate(dev, conf, action, fops, error)) 10021 return NULL; 10022 if (!fops->action_create) { 10023 DRV_LOG(ERR, "port %u %s.", dev->data->port_id, err_msg); 10024 rte_flow_error_set(error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION, 10025 NULL, err_msg); 10026 return NULL; 10027 } 10028 return fops->action_create(dev, conf, action, error); 10029 } 10030 10031 /** 10032 * Updates inplace the indirect action configuration pointed by *handle* 10033 * with the configuration provided as *update* argument. 10034 * The update of the indirect action configuration effects all flow rules 10035 * reusing the action via handle. 10036 * 10037 * @param dev 10038 * Pointer to Ethernet device structure. 10039 * @param[in] handle 10040 * Handle for the indirect action to be updated. 10041 * @param[in] update 10042 * Action specification used to modify the action pointed by handle. 10043 * *update* could be of same type with the action pointed by the *handle* 10044 * handle argument, or some other structures like a wrapper, depending on 10045 * the indirect action type. 10046 * @param[out] error 10047 * Perform verbose error reporting if not NULL. PMDs initialize this 10048 * structure in case of error only. 10049 * 10050 * @return 10051 * 0 on success, a negative errno value otherwise and rte_errno is set. 10052 */ 10053 static int 10054 mlx5_action_handle_update(struct rte_eth_dev *dev, 10055 struct rte_flow_action_handle *handle, 10056 const void *update, 10057 struct rte_flow_error *error) 10058 { 10059 struct rte_flow_attr attr = { .transfer = 0 }; 10060 const struct mlx5_flow_driver_ops *fops = 10061 flow_get_drv_ops(flow_get_drv_type(dev, &attr)); 10062 int ret; 10063 10064 ret = flow_drv_action_validate(dev, NULL, 10065 (const struct rte_flow_action *)update, fops, error); 10066 if (ret) 10067 return ret; 10068 return flow_drv_action_update(dev, handle, update, fops, 10069 error); 10070 } 10071 10072 /** 10073 * Query the indirect action by handle. 10074 * 10075 * This function allows retrieving action-specific data such as counters. 10076 * Data is gathered by special action which may be present/referenced in 10077 * more than one flow rule definition. 10078 * 10079 * see @RTE_FLOW_ACTION_TYPE_COUNT 10080 * 10081 * @param dev 10082 * Pointer to Ethernet device structure. 10083 * @param[in] handle 10084 * Handle for the indirect action to query. 10085 * @param[in, out] data 10086 * Pointer to storage for the associated query data type. 10087 * @param[out] error 10088 * Perform verbose error reporting if not NULL. PMDs initialize this 10089 * structure in case of error only. 10090 * 10091 * @return 10092 * 0 on success, a negative errno value otherwise and rte_errno is set. 10093 */ 10094 static int 10095 mlx5_action_handle_query(struct rte_eth_dev *dev, 10096 const struct rte_flow_action_handle *handle, 10097 void *data, 10098 struct rte_flow_error *error) 10099 { 10100 struct rte_flow_attr attr = { .transfer = 0 }; 10101 const struct mlx5_flow_driver_ops *fops = 10102 flow_get_drv_ops(flow_get_drv_type(dev, &attr)); 10103 10104 return flow_drv_action_query(dev, handle, data, fops, error); 10105 } 10106 10107 /** 10108 * Destroy all indirect actions (shared RSS). 10109 * 10110 * @param dev 10111 * Pointer to Ethernet device. 10112 * 10113 * @return 10114 * 0 on success, a negative errno value otherwise and rte_errno is set. 10115 */ 10116 int 10117 mlx5_action_handle_flush(struct rte_eth_dev *dev) 10118 { 10119 struct rte_flow_error error; 10120 struct mlx5_priv *priv = dev->data->dev_private; 10121 struct mlx5_shared_action_rss *shared_rss; 10122 int ret = 0; 10123 uint32_t idx; 10124 10125 ILIST_FOREACH(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], 10126 priv->rss_shared_actions, idx, shared_rss, next) { 10127 ret |= mlx5_action_handle_destroy(dev, 10128 (struct rte_flow_action_handle *)(uintptr_t)idx, &error); 10129 } 10130 return ret; 10131 } 10132 10133 /** 10134 * Validate existing indirect actions against current device configuration 10135 * and attach them to device resources. 10136 * 10137 * @param dev 10138 * Pointer to Ethernet device. 10139 * 10140 * @return 10141 * 0 on success, a negative errno value otherwise and rte_errno is set. 10142 */ 10143 int 10144 mlx5_action_handle_attach(struct rte_eth_dev *dev) 10145 { 10146 struct mlx5_priv *priv = dev->data->dev_private; 10147 int ret = 0; 10148 struct mlx5_ind_table_obj *ind_tbl, *ind_tbl_last; 10149 10150 LIST_FOREACH(ind_tbl, &priv->standalone_ind_tbls, next) { 10151 const char *message; 10152 uint32_t queue_idx; 10153 10154 ret = mlx5_validate_rss_queues(dev, ind_tbl->queues, 10155 ind_tbl->queues_n, 10156 &message, &queue_idx); 10157 if (ret != 0) { 10158 DRV_LOG(ERR, "Port %u cannot use queue %u in RSS: %s", 10159 dev->data->port_id, ind_tbl->queues[queue_idx], 10160 message); 10161 break; 10162 } 10163 } 10164 if (ret != 0) 10165 return ret; 10166 LIST_FOREACH(ind_tbl, &priv->standalone_ind_tbls, next) { 10167 ret = mlx5_ind_table_obj_attach(dev, ind_tbl); 10168 if (ret != 0) { 10169 DRV_LOG(ERR, "Port %u could not attach " 10170 "indirection table obj %p", 10171 dev->data->port_id, (void *)ind_tbl); 10172 goto error; 10173 } 10174 } 10175 10176 return 0; 10177 error: 10178 ind_tbl_last = ind_tbl; 10179 LIST_FOREACH(ind_tbl, &priv->standalone_ind_tbls, next) { 10180 if (ind_tbl == ind_tbl_last) 10181 break; 10182 if (mlx5_ind_table_obj_detach(dev, ind_tbl) != 0) 10183 DRV_LOG(CRIT, "Port %u could not detach " 10184 "indirection table obj %p on rollback", 10185 dev->data->port_id, (void *)ind_tbl); 10186 } 10187 return ret; 10188 } 10189 10190 /** 10191 * Detach indirect actions of the device from its resources. 10192 * 10193 * @param dev 10194 * Pointer to Ethernet device. 10195 * 10196 * @return 10197 * 0 on success, a negative errno value otherwise and rte_errno is set. 10198 */ 10199 int 10200 mlx5_action_handle_detach(struct rte_eth_dev *dev) 10201 { 10202 struct mlx5_priv *priv = dev->data->dev_private; 10203 int ret = 0; 10204 struct mlx5_ind_table_obj *ind_tbl, *ind_tbl_last; 10205 10206 LIST_FOREACH(ind_tbl, &priv->standalone_ind_tbls, next) { 10207 ret = mlx5_ind_table_obj_detach(dev, ind_tbl); 10208 if (ret != 0) { 10209 DRV_LOG(ERR, "Port %u could not detach " 10210 "indirection table obj %p", 10211 dev->data->port_id, (void *)ind_tbl); 10212 goto error; 10213 } 10214 } 10215 return 0; 10216 error: 10217 ind_tbl_last = ind_tbl; 10218 LIST_FOREACH(ind_tbl, &priv->standalone_ind_tbls, next) { 10219 if (ind_tbl == ind_tbl_last) 10220 break; 10221 if (mlx5_ind_table_obj_attach(dev, ind_tbl) != 0) 10222 DRV_LOG(CRIT, "Port %u could not attach " 10223 "indirection table obj %p on rollback", 10224 dev->data->port_id, (void *)ind_tbl); 10225 } 10226 return ret; 10227 } 10228 10229 #ifndef HAVE_MLX5DV_DR 10230 #define MLX5_DOMAIN_SYNC_FLOW ((1 << 0) | (1 << 1)) 10231 #else 10232 #define MLX5_DOMAIN_SYNC_FLOW \ 10233 (MLX5DV_DR_DOMAIN_SYNC_FLAGS_SW | MLX5DV_DR_DOMAIN_SYNC_FLAGS_HW) 10234 #endif 10235 10236 int rte_pmd_mlx5_sync_flow(uint16_t port_id, uint32_t domains) 10237 { 10238 struct rte_eth_dev *dev = &rte_eth_devices[port_id]; 10239 const struct mlx5_flow_driver_ops *fops; 10240 int ret; 10241 struct rte_flow_attr attr = { .transfer = 0 }; 10242 10243 fops = flow_get_drv_ops(flow_get_drv_type(dev, &attr)); 10244 ret = fops->sync_domain(dev, domains, MLX5_DOMAIN_SYNC_FLOW); 10245 if (ret > 0) 10246 ret = -ret; 10247 return ret; 10248 } 10249 10250 const struct mlx5_flow_tunnel * 10251 mlx5_get_tof(const struct rte_flow_item *item, 10252 const struct rte_flow_action *action, 10253 enum mlx5_tof_rule_type *rule_type) 10254 { 10255 for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) { 10256 if (item->type == (typeof(item->type)) 10257 MLX5_RTE_FLOW_ITEM_TYPE_TUNNEL) { 10258 *rule_type = MLX5_TUNNEL_OFFLOAD_MATCH_RULE; 10259 return flow_items_to_tunnel(item); 10260 } 10261 } 10262 for (; action->conf != RTE_FLOW_ACTION_TYPE_END; action++) { 10263 if (action->type == (typeof(action->type)) 10264 MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET) { 10265 *rule_type = MLX5_TUNNEL_OFFLOAD_SET_RULE; 10266 return flow_actions_to_tunnel(action); 10267 } 10268 } 10269 return NULL; 10270 } 10271 10272 /** 10273 * tunnel offload functionality is defined for DV environment only 10274 */ 10275 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 10276 __extension__ 10277 union tunnel_offload_mark { 10278 uint32_t val; 10279 struct { 10280 uint32_t app_reserve:8; 10281 uint32_t table_id:15; 10282 uint32_t transfer:1; 10283 uint32_t _unused_:8; 10284 }; 10285 }; 10286 10287 static bool 10288 mlx5_access_tunnel_offload_db 10289 (struct rte_eth_dev *dev, 10290 bool (*match)(struct rte_eth_dev *, 10291 struct mlx5_flow_tunnel *, const void *), 10292 void (*hit)(struct rte_eth_dev *, struct mlx5_flow_tunnel *, void *), 10293 void (*miss)(struct rte_eth_dev *, void *), 10294 void *ctx, bool lock_op); 10295 10296 static int 10297 flow_tunnel_add_default_miss(struct rte_eth_dev *dev, 10298 struct rte_flow *flow, 10299 const struct rte_flow_attr *attr, 10300 const struct rte_flow_action *app_actions, 10301 uint32_t flow_idx, 10302 const struct mlx5_flow_tunnel *tunnel, 10303 struct tunnel_default_miss_ctx *ctx, 10304 struct rte_flow_error *error) 10305 { 10306 struct mlx5_priv *priv = dev->data->dev_private; 10307 struct mlx5_flow *dev_flow; 10308 struct rte_flow_attr miss_attr = *attr; 10309 const struct rte_flow_item miss_items[2] = { 10310 { 10311 .type = RTE_FLOW_ITEM_TYPE_ETH, 10312 .spec = NULL, 10313 .last = NULL, 10314 .mask = NULL 10315 }, 10316 { 10317 .type = RTE_FLOW_ITEM_TYPE_END, 10318 .spec = NULL, 10319 .last = NULL, 10320 .mask = NULL 10321 } 10322 }; 10323 union tunnel_offload_mark mark_id; 10324 struct rte_flow_action_mark miss_mark; 10325 struct rte_flow_action miss_actions[3] = { 10326 [0] = { .type = RTE_FLOW_ACTION_TYPE_MARK, .conf = &miss_mark }, 10327 [2] = { .type = RTE_FLOW_ACTION_TYPE_END, .conf = NULL } 10328 }; 10329 const struct rte_flow_action_jump *jump_data; 10330 uint32_t i, flow_table = 0; /* prevent compilation warning */ 10331 struct flow_grp_info grp_info = { 10332 .external = 1, 10333 .transfer = attr->transfer, 10334 .fdb_def_rule = !!priv->fdb_def_rule, 10335 .std_tbl_fix = 0, 10336 }; 10337 int ret; 10338 10339 if (!attr->transfer) { 10340 uint32_t q_size; 10341 10342 miss_actions[1].type = RTE_FLOW_ACTION_TYPE_RSS; 10343 q_size = priv->reta_idx_n * sizeof(ctx->queue[0]); 10344 ctx->queue = mlx5_malloc(MLX5_MEM_SYS | MLX5_MEM_ZERO, q_size, 10345 0, SOCKET_ID_ANY); 10346 if (!ctx->queue) 10347 return rte_flow_error_set 10348 (error, ENOMEM, 10349 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 10350 NULL, "invalid default miss RSS"); 10351 ctx->action_rss.func = RTE_ETH_HASH_FUNCTION_DEFAULT, 10352 ctx->action_rss.level = 0, 10353 ctx->action_rss.types = priv->rss_conf.rss_hf, 10354 ctx->action_rss.key_len = priv->rss_conf.rss_key_len, 10355 ctx->action_rss.queue_num = priv->reta_idx_n, 10356 ctx->action_rss.key = priv->rss_conf.rss_key, 10357 ctx->action_rss.queue = ctx->queue; 10358 if (!priv->reta_idx_n || !priv->rxqs_n) 10359 return rte_flow_error_set 10360 (error, EINVAL, 10361 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 10362 NULL, "invalid port configuration"); 10363 if (!(dev->data->dev_conf.rxmode.mq_mode & RTE_ETH_MQ_RX_RSS_FLAG)) 10364 ctx->action_rss.types = 0; 10365 for (i = 0; i != priv->reta_idx_n; ++i) 10366 ctx->queue[i] = (*priv->reta_idx)[i]; 10367 } else { 10368 miss_actions[1].type = RTE_FLOW_ACTION_TYPE_JUMP; 10369 ctx->miss_jump.group = MLX5_TNL_MISS_FDB_JUMP_GRP; 10370 } 10371 miss_actions[1].conf = (typeof(miss_actions[1].conf))ctx->raw; 10372 for (; app_actions->type != RTE_FLOW_ACTION_TYPE_JUMP; app_actions++); 10373 jump_data = app_actions->conf; 10374 miss_attr.priority = MLX5_TNL_MISS_RULE_PRIORITY; 10375 miss_attr.group = jump_data->group; 10376 ret = mlx5_flow_group_to_table(dev, tunnel, jump_data->group, 10377 &flow_table, &grp_info, error); 10378 if (ret) 10379 return rte_flow_error_set(error, EINVAL, 10380 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 10381 NULL, "invalid tunnel id"); 10382 mark_id.app_reserve = 0; 10383 mark_id.table_id = tunnel_flow_tbl_to_id(flow_table); 10384 mark_id.transfer = !!attr->transfer; 10385 mark_id._unused_ = 0; 10386 miss_mark.id = mark_id.val; 10387 dev_flow = flow_drv_prepare(dev, flow, &miss_attr, 10388 miss_items, miss_actions, flow_idx, error); 10389 if (!dev_flow) 10390 return -rte_errno; 10391 dev_flow->flow = flow; 10392 dev_flow->external = true; 10393 dev_flow->tunnel = tunnel; 10394 dev_flow->tof_type = MLX5_TUNNEL_OFFLOAD_MISS_RULE; 10395 /* Subflow object was created, we must include one in the list. */ 10396 SILIST_INSERT(&flow->dev_handles, dev_flow->handle_idx, 10397 dev_flow->handle, next); 10398 DRV_LOG(DEBUG, 10399 "port %u tunnel type=%d id=%u miss rule priority=%u group=%u", 10400 dev->data->port_id, tunnel->app_tunnel.type, 10401 tunnel->tunnel_id, miss_attr.priority, miss_attr.group); 10402 ret = flow_drv_translate(dev, dev_flow, &miss_attr, miss_items, 10403 miss_actions, error); 10404 if (!ret) 10405 ret = flow_mreg_update_copy_table(dev, flow, miss_actions, 10406 error); 10407 10408 return ret; 10409 } 10410 10411 static const struct mlx5_flow_tbl_data_entry * 10412 tunnel_mark_decode(struct rte_eth_dev *dev, uint32_t mark) 10413 { 10414 struct mlx5_priv *priv = dev->data->dev_private; 10415 struct mlx5_dev_ctx_shared *sh = priv->sh; 10416 struct mlx5_list_entry *he; 10417 union tunnel_offload_mark mbits = { .val = mark }; 10418 union mlx5_flow_tbl_key table_key = { 10419 { 10420 .level = tunnel_id_to_flow_tbl(mbits.table_id), 10421 .id = 0, 10422 .reserved = 0, 10423 .dummy = 0, 10424 .is_fdb = !!mbits.transfer, 10425 .is_egress = 0, 10426 } 10427 }; 10428 struct mlx5_flow_cb_ctx ctx = { 10429 .data = &table_key.v64, 10430 }; 10431 10432 he = mlx5_hlist_lookup(sh->flow_tbls, table_key.v64, &ctx); 10433 return he ? 10434 container_of(he, struct mlx5_flow_tbl_data_entry, entry) : NULL; 10435 } 10436 10437 static void 10438 mlx5_flow_tunnel_grp2tbl_remove_cb(void *tool_ctx, 10439 struct mlx5_list_entry *entry) 10440 { 10441 struct mlx5_dev_ctx_shared *sh = tool_ctx; 10442 struct tunnel_tbl_entry *tte = container_of(entry, typeof(*tte), hash); 10443 10444 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_TNL_TBL_ID], 10445 tunnel_flow_tbl_to_id(tte->flow_table)); 10446 mlx5_free(tte); 10447 } 10448 10449 static int 10450 mlx5_flow_tunnel_grp2tbl_match_cb(void *tool_ctx __rte_unused, 10451 struct mlx5_list_entry *entry, void *cb_ctx) 10452 { 10453 struct mlx5_flow_cb_ctx *ctx = cb_ctx; 10454 union tunnel_tbl_key tbl = { 10455 .val = *(uint64_t *)(ctx->data), 10456 }; 10457 struct tunnel_tbl_entry *tte = container_of(entry, typeof(*tte), hash); 10458 10459 return tbl.tunnel_id != tte->tunnel_id || tbl.group != tte->group; 10460 } 10461 10462 static struct mlx5_list_entry * 10463 mlx5_flow_tunnel_grp2tbl_create_cb(void *tool_ctx, void *cb_ctx) 10464 { 10465 struct mlx5_dev_ctx_shared *sh = tool_ctx; 10466 struct mlx5_flow_cb_ctx *ctx = cb_ctx; 10467 struct tunnel_tbl_entry *tte; 10468 union tunnel_tbl_key tbl = { 10469 .val = *(uint64_t *)(ctx->data), 10470 }; 10471 10472 tte = mlx5_malloc(MLX5_MEM_SYS | MLX5_MEM_ZERO, 10473 sizeof(*tte), 0, 10474 SOCKET_ID_ANY); 10475 if (!tte) 10476 goto err; 10477 mlx5_ipool_malloc(sh->ipool[MLX5_IPOOL_TNL_TBL_ID], 10478 &tte->flow_table); 10479 if (tte->flow_table >= MLX5_MAX_TABLES) { 10480 DRV_LOG(ERR, "Tunnel TBL ID %d exceed max limit.", 10481 tte->flow_table); 10482 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_TNL_TBL_ID], 10483 tte->flow_table); 10484 goto err; 10485 } else if (!tte->flow_table) { 10486 goto err; 10487 } 10488 tte->flow_table = tunnel_id_to_flow_tbl(tte->flow_table); 10489 tte->tunnel_id = tbl.tunnel_id; 10490 tte->group = tbl.group; 10491 return &tte->hash; 10492 err: 10493 if (tte) 10494 mlx5_free(tte); 10495 return NULL; 10496 } 10497 10498 static struct mlx5_list_entry * 10499 mlx5_flow_tunnel_grp2tbl_clone_cb(void *tool_ctx __rte_unused, 10500 struct mlx5_list_entry *oentry, 10501 void *cb_ctx __rte_unused) 10502 { 10503 struct tunnel_tbl_entry *tte = mlx5_malloc(MLX5_MEM_SYS, sizeof(*tte), 10504 0, SOCKET_ID_ANY); 10505 10506 if (!tte) 10507 return NULL; 10508 memcpy(tte, oentry, sizeof(*tte)); 10509 return &tte->hash; 10510 } 10511 10512 static void 10513 mlx5_flow_tunnel_grp2tbl_clone_free_cb(void *tool_ctx __rte_unused, 10514 struct mlx5_list_entry *entry) 10515 { 10516 struct tunnel_tbl_entry *tte = container_of(entry, typeof(*tte), hash); 10517 10518 mlx5_free(tte); 10519 } 10520 10521 static uint32_t 10522 tunnel_flow_group_to_flow_table(struct rte_eth_dev *dev, 10523 const struct mlx5_flow_tunnel *tunnel, 10524 uint32_t group, uint32_t *table, 10525 struct rte_flow_error *error) 10526 { 10527 struct mlx5_list_entry *he; 10528 struct tunnel_tbl_entry *tte; 10529 union tunnel_tbl_key key = { 10530 .tunnel_id = tunnel ? tunnel->tunnel_id : 0, 10531 .group = group 10532 }; 10533 struct mlx5_flow_tunnel_hub *thub = mlx5_tunnel_hub(dev); 10534 struct mlx5_hlist *group_hash; 10535 struct mlx5_flow_cb_ctx ctx = { 10536 .data = &key.val, 10537 }; 10538 10539 group_hash = tunnel ? tunnel->groups : thub->groups; 10540 he = mlx5_hlist_register(group_hash, key.val, &ctx); 10541 if (!he) 10542 return rte_flow_error_set(error, EINVAL, 10543 RTE_FLOW_ERROR_TYPE_ATTR_GROUP, 10544 NULL, 10545 "tunnel group index not supported"); 10546 tte = container_of(he, typeof(*tte), hash); 10547 *table = tte->flow_table; 10548 DRV_LOG(DEBUG, "port %u tunnel %u group=%#x table=%#x", 10549 dev->data->port_id, key.tunnel_id, group, *table); 10550 return 0; 10551 } 10552 10553 static void 10554 mlx5_flow_tunnel_free(struct rte_eth_dev *dev, 10555 struct mlx5_flow_tunnel *tunnel) 10556 { 10557 struct mlx5_priv *priv = dev->data->dev_private; 10558 struct mlx5_indexed_pool *ipool; 10559 10560 DRV_LOG(DEBUG, "port %u release pmd tunnel id=0x%x", 10561 dev->data->port_id, tunnel->tunnel_id); 10562 LIST_REMOVE(tunnel, chain); 10563 mlx5_hlist_destroy(tunnel->groups); 10564 ipool = priv->sh->ipool[MLX5_IPOOL_TUNNEL_ID]; 10565 mlx5_ipool_free(ipool, tunnel->tunnel_id); 10566 } 10567 10568 static bool 10569 mlx5_access_tunnel_offload_db 10570 (struct rte_eth_dev *dev, 10571 bool (*match)(struct rte_eth_dev *, 10572 struct mlx5_flow_tunnel *, const void *), 10573 void (*hit)(struct rte_eth_dev *, struct mlx5_flow_tunnel *, void *), 10574 void (*miss)(struct rte_eth_dev *, void *), 10575 void *ctx, bool lock_op) 10576 { 10577 bool verdict = false; 10578 struct mlx5_flow_tunnel_hub *thub = mlx5_tunnel_hub(dev); 10579 struct mlx5_flow_tunnel *tunnel; 10580 10581 rte_spinlock_lock(&thub->sl); 10582 LIST_FOREACH(tunnel, &thub->tunnels, chain) { 10583 verdict = match(dev, tunnel, (const void *)ctx); 10584 if (verdict) 10585 break; 10586 } 10587 if (!lock_op) 10588 rte_spinlock_unlock(&thub->sl); 10589 if (verdict && hit) 10590 hit(dev, tunnel, ctx); 10591 if (!verdict && miss) 10592 miss(dev, ctx); 10593 if (lock_op) 10594 rte_spinlock_unlock(&thub->sl); 10595 10596 return verdict; 10597 } 10598 10599 struct tunnel_db_find_tunnel_id_ctx { 10600 uint32_t tunnel_id; 10601 struct mlx5_flow_tunnel *tunnel; 10602 }; 10603 10604 static bool 10605 find_tunnel_id_match(struct rte_eth_dev *dev, 10606 struct mlx5_flow_tunnel *tunnel, const void *x) 10607 { 10608 const struct tunnel_db_find_tunnel_id_ctx *ctx = x; 10609 10610 RTE_SET_USED(dev); 10611 return tunnel->tunnel_id == ctx->tunnel_id; 10612 } 10613 10614 static void 10615 find_tunnel_id_hit(struct rte_eth_dev *dev, 10616 struct mlx5_flow_tunnel *tunnel, void *x) 10617 { 10618 struct tunnel_db_find_tunnel_id_ctx *ctx = x; 10619 RTE_SET_USED(dev); 10620 ctx->tunnel = tunnel; 10621 } 10622 10623 static struct mlx5_flow_tunnel * 10624 mlx5_find_tunnel_id(struct rte_eth_dev *dev, uint32_t id) 10625 { 10626 struct tunnel_db_find_tunnel_id_ctx ctx = { 10627 .tunnel_id = id, 10628 }; 10629 10630 mlx5_access_tunnel_offload_db(dev, find_tunnel_id_match, 10631 find_tunnel_id_hit, NULL, &ctx, true); 10632 10633 return ctx.tunnel; 10634 } 10635 10636 static struct mlx5_flow_tunnel * 10637 mlx5_flow_tunnel_allocate(struct rte_eth_dev *dev, 10638 const struct rte_flow_tunnel *app_tunnel) 10639 { 10640 struct mlx5_priv *priv = dev->data->dev_private; 10641 struct mlx5_indexed_pool *ipool; 10642 struct mlx5_flow_tunnel *tunnel; 10643 uint32_t id; 10644 10645 ipool = priv->sh->ipool[MLX5_IPOOL_TUNNEL_ID]; 10646 tunnel = mlx5_ipool_zmalloc(ipool, &id); 10647 if (!tunnel) 10648 return NULL; 10649 if (id >= MLX5_MAX_TUNNELS) { 10650 mlx5_ipool_free(ipool, id); 10651 DRV_LOG(ERR, "Tunnel ID %d exceed max limit.", id); 10652 return NULL; 10653 } 10654 tunnel->groups = mlx5_hlist_create("tunnel groups", 64, false, true, 10655 priv->sh, 10656 mlx5_flow_tunnel_grp2tbl_create_cb, 10657 mlx5_flow_tunnel_grp2tbl_match_cb, 10658 mlx5_flow_tunnel_grp2tbl_remove_cb, 10659 mlx5_flow_tunnel_grp2tbl_clone_cb, 10660 mlx5_flow_tunnel_grp2tbl_clone_free_cb); 10661 if (!tunnel->groups) { 10662 mlx5_ipool_free(ipool, id); 10663 return NULL; 10664 } 10665 /* initiate new PMD tunnel */ 10666 memcpy(&tunnel->app_tunnel, app_tunnel, sizeof(*app_tunnel)); 10667 tunnel->tunnel_id = id; 10668 tunnel->action.type = (typeof(tunnel->action.type)) 10669 MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET; 10670 tunnel->action.conf = tunnel; 10671 tunnel->item.type = (typeof(tunnel->item.type)) 10672 MLX5_RTE_FLOW_ITEM_TYPE_TUNNEL; 10673 tunnel->item.spec = tunnel; 10674 tunnel->item.last = NULL; 10675 tunnel->item.mask = NULL; 10676 10677 DRV_LOG(DEBUG, "port %u new pmd tunnel id=0x%x", 10678 dev->data->port_id, tunnel->tunnel_id); 10679 10680 return tunnel; 10681 } 10682 10683 struct tunnel_db_get_tunnel_ctx { 10684 const struct rte_flow_tunnel *app_tunnel; 10685 struct mlx5_flow_tunnel *tunnel; 10686 }; 10687 10688 static bool get_tunnel_match(struct rte_eth_dev *dev, 10689 struct mlx5_flow_tunnel *tunnel, const void *x) 10690 { 10691 const struct tunnel_db_get_tunnel_ctx *ctx = x; 10692 10693 RTE_SET_USED(dev); 10694 return !memcmp(ctx->app_tunnel, &tunnel->app_tunnel, 10695 sizeof(*ctx->app_tunnel)); 10696 } 10697 10698 static void get_tunnel_hit(struct rte_eth_dev *dev, 10699 struct mlx5_flow_tunnel *tunnel, void *x) 10700 { 10701 /* called under tunnel spinlock protection */ 10702 struct tunnel_db_get_tunnel_ctx *ctx = x; 10703 10704 RTE_SET_USED(dev); 10705 tunnel->refctn++; 10706 ctx->tunnel = tunnel; 10707 } 10708 10709 static void get_tunnel_miss(struct rte_eth_dev *dev, void *x) 10710 { 10711 /* called under tunnel spinlock protection */ 10712 struct mlx5_flow_tunnel_hub *thub = mlx5_tunnel_hub(dev); 10713 struct tunnel_db_get_tunnel_ctx *ctx = x; 10714 10715 rte_spinlock_unlock(&thub->sl); 10716 ctx->tunnel = mlx5_flow_tunnel_allocate(dev, ctx->app_tunnel); 10717 rte_spinlock_lock(&thub->sl); 10718 if (ctx->tunnel) { 10719 ctx->tunnel->refctn = 1; 10720 LIST_INSERT_HEAD(&thub->tunnels, ctx->tunnel, chain); 10721 } 10722 } 10723 10724 10725 static int 10726 mlx5_get_flow_tunnel(struct rte_eth_dev *dev, 10727 const struct rte_flow_tunnel *app_tunnel, 10728 struct mlx5_flow_tunnel **tunnel) 10729 { 10730 struct tunnel_db_get_tunnel_ctx ctx = { 10731 .app_tunnel = app_tunnel, 10732 }; 10733 10734 mlx5_access_tunnel_offload_db(dev, get_tunnel_match, get_tunnel_hit, 10735 get_tunnel_miss, &ctx, true); 10736 *tunnel = ctx.tunnel; 10737 return ctx.tunnel ? 0 : -ENOMEM; 10738 } 10739 10740 void mlx5_release_tunnel_hub(struct mlx5_dev_ctx_shared *sh, uint16_t port_id) 10741 { 10742 struct mlx5_flow_tunnel_hub *thub = sh->tunnel_hub; 10743 10744 if (!thub) 10745 return; 10746 if (!LIST_EMPTY(&thub->tunnels)) 10747 DRV_LOG(WARNING, "port %u tunnels present", port_id); 10748 mlx5_hlist_destroy(thub->groups); 10749 mlx5_free(thub); 10750 } 10751 10752 int mlx5_alloc_tunnel_hub(struct mlx5_dev_ctx_shared *sh) 10753 { 10754 int err; 10755 struct mlx5_flow_tunnel_hub *thub; 10756 10757 thub = mlx5_malloc(MLX5_MEM_SYS | MLX5_MEM_ZERO, sizeof(*thub), 10758 0, SOCKET_ID_ANY); 10759 if (!thub) 10760 return -ENOMEM; 10761 LIST_INIT(&thub->tunnels); 10762 rte_spinlock_init(&thub->sl); 10763 thub->groups = mlx5_hlist_create("flow groups", 64, 10764 false, true, sh, 10765 mlx5_flow_tunnel_grp2tbl_create_cb, 10766 mlx5_flow_tunnel_grp2tbl_match_cb, 10767 mlx5_flow_tunnel_grp2tbl_remove_cb, 10768 mlx5_flow_tunnel_grp2tbl_clone_cb, 10769 mlx5_flow_tunnel_grp2tbl_clone_free_cb); 10770 if (!thub->groups) { 10771 err = -rte_errno; 10772 goto err; 10773 } 10774 sh->tunnel_hub = thub; 10775 10776 return 0; 10777 10778 err: 10779 if (thub->groups) 10780 mlx5_hlist_destroy(thub->groups); 10781 if (thub) 10782 mlx5_free(thub); 10783 return err; 10784 } 10785 10786 static inline int 10787 mlx5_flow_tunnel_validate(struct rte_eth_dev *dev, 10788 struct rte_flow_tunnel *tunnel, 10789 struct rte_flow_error *error) 10790 { 10791 struct mlx5_priv *priv = dev->data->dev_private; 10792 10793 if (!priv->sh->config.dv_flow_en) 10794 return rte_flow_error_set(error, ENOTSUP, 10795 RTE_FLOW_ERROR_TYPE_ACTION_CONF, NULL, 10796 "flow DV interface is off"); 10797 if (!is_tunnel_offload_active(dev)) 10798 return rte_flow_error_set(error, ENOTSUP, 10799 RTE_FLOW_ERROR_TYPE_ACTION_CONF, NULL, 10800 "tunnel offload was not activated"); 10801 if (!tunnel) 10802 return rte_flow_error_set(error, EINVAL, 10803 RTE_FLOW_ERROR_TYPE_ACTION_CONF, NULL, 10804 "no application tunnel"); 10805 switch (tunnel->type) { 10806 default: 10807 return rte_flow_error_set(error, EINVAL, 10808 RTE_FLOW_ERROR_TYPE_ACTION_CONF, NULL, 10809 "unsupported tunnel type"); 10810 case RTE_FLOW_ITEM_TYPE_VXLAN: 10811 case RTE_FLOW_ITEM_TYPE_GRE: 10812 case RTE_FLOW_ITEM_TYPE_NVGRE: 10813 case RTE_FLOW_ITEM_TYPE_GENEVE: 10814 break; 10815 } 10816 return 0; 10817 } 10818 10819 static int 10820 mlx5_flow_tunnel_decap_set(struct rte_eth_dev *dev, 10821 struct rte_flow_tunnel *app_tunnel, 10822 struct rte_flow_action **actions, 10823 uint32_t *num_of_actions, 10824 struct rte_flow_error *error) 10825 { 10826 struct mlx5_flow_tunnel *tunnel; 10827 int ret = mlx5_flow_tunnel_validate(dev, app_tunnel, error); 10828 10829 if (ret) 10830 return ret; 10831 ret = mlx5_get_flow_tunnel(dev, app_tunnel, &tunnel); 10832 if (ret < 0) { 10833 return rte_flow_error_set(error, ret, 10834 RTE_FLOW_ERROR_TYPE_ACTION_CONF, NULL, 10835 "failed to initialize pmd tunnel"); 10836 } 10837 *actions = &tunnel->action; 10838 *num_of_actions = 1; 10839 return 0; 10840 } 10841 10842 static int 10843 mlx5_flow_tunnel_match(struct rte_eth_dev *dev, 10844 struct rte_flow_tunnel *app_tunnel, 10845 struct rte_flow_item **items, 10846 uint32_t *num_of_items, 10847 struct rte_flow_error *error) 10848 { 10849 struct mlx5_flow_tunnel *tunnel; 10850 int ret = mlx5_flow_tunnel_validate(dev, app_tunnel, error); 10851 10852 if (ret) 10853 return ret; 10854 ret = mlx5_get_flow_tunnel(dev, app_tunnel, &tunnel); 10855 if (ret < 0) { 10856 return rte_flow_error_set(error, ret, 10857 RTE_FLOW_ERROR_TYPE_HANDLE, NULL, 10858 "failed to initialize pmd tunnel"); 10859 } 10860 *items = &tunnel->item; 10861 *num_of_items = 1; 10862 return 0; 10863 } 10864 10865 struct tunnel_db_element_release_ctx { 10866 struct rte_flow_item *items; 10867 struct rte_flow_action *actions; 10868 uint32_t num_elements; 10869 struct rte_flow_error *error; 10870 int ret; 10871 }; 10872 10873 static bool 10874 tunnel_element_release_match(struct rte_eth_dev *dev, 10875 struct mlx5_flow_tunnel *tunnel, const void *x) 10876 { 10877 const struct tunnel_db_element_release_ctx *ctx = x; 10878 10879 RTE_SET_USED(dev); 10880 if (ctx->num_elements != 1) 10881 return false; 10882 else if (ctx->items) 10883 return ctx->items == &tunnel->item; 10884 else if (ctx->actions) 10885 return ctx->actions == &tunnel->action; 10886 10887 return false; 10888 } 10889 10890 static void 10891 tunnel_element_release_hit(struct rte_eth_dev *dev, 10892 struct mlx5_flow_tunnel *tunnel, void *x) 10893 { 10894 struct tunnel_db_element_release_ctx *ctx = x; 10895 ctx->ret = 0; 10896 if (!__atomic_sub_fetch(&tunnel->refctn, 1, __ATOMIC_RELAXED)) 10897 mlx5_flow_tunnel_free(dev, tunnel); 10898 } 10899 10900 static void 10901 tunnel_element_release_miss(struct rte_eth_dev *dev, void *x) 10902 { 10903 struct tunnel_db_element_release_ctx *ctx = x; 10904 RTE_SET_USED(dev); 10905 ctx->ret = rte_flow_error_set(ctx->error, EINVAL, 10906 RTE_FLOW_ERROR_TYPE_HANDLE, NULL, 10907 "invalid argument"); 10908 } 10909 10910 static int 10911 mlx5_flow_tunnel_item_release(struct rte_eth_dev *dev, 10912 struct rte_flow_item *pmd_items, 10913 uint32_t num_items, struct rte_flow_error *err) 10914 { 10915 struct tunnel_db_element_release_ctx ctx = { 10916 .items = pmd_items, 10917 .actions = NULL, 10918 .num_elements = num_items, 10919 .error = err, 10920 }; 10921 10922 mlx5_access_tunnel_offload_db(dev, tunnel_element_release_match, 10923 tunnel_element_release_hit, 10924 tunnel_element_release_miss, &ctx, false); 10925 10926 return ctx.ret; 10927 } 10928 10929 static int 10930 mlx5_flow_tunnel_action_release(struct rte_eth_dev *dev, 10931 struct rte_flow_action *pmd_actions, 10932 uint32_t num_actions, struct rte_flow_error *err) 10933 { 10934 struct tunnel_db_element_release_ctx ctx = { 10935 .items = NULL, 10936 .actions = pmd_actions, 10937 .num_elements = num_actions, 10938 .error = err, 10939 }; 10940 10941 mlx5_access_tunnel_offload_db(dev, tunnel_element_release_match, 10942 tunnel_element_release_hit, 10943 tunnel_element_release_miss, &ctx, false); 10944 10945 return ctx.ret; 10946 } 10947 10948 static int 10949 mlx5_flow_tunnel_get_restore_info(struct rte_eth_dev *dev, 10950 struct rte_mbuf *m, 10951 struct rte_flow_restore_info *info, 10952 struct rte_flow_error *err) 10953 { 10954 uint64_t ol_flags = m->ol_flags; 10955 const struct mlx5_flow_tbl_data_entry *tble; 10956 const uint64_t mask = RTE_MBUF_F_RX_FDIR | RTE_MBUF_F_RX_FDIR_ID; 10957 10958 if (!is_tunnel_offload_active(dev)) { 10959 info->flags = 0; 10960 return 0; 10961 } 10962 10963 if ((ol_flags & mask) != mask) 10964 goto err; 10965 tble = tunnel_mark_decode(dev, m->hash.fdir.hi); 10966 if (!tble) { 10967 DRV_LOG(DEBUG, "port %u invalid miss tunnel mark %#x", 10968 dev->data->port_id, m->hash.fdir.hi); 10969 goto err; 10970 } 10971 MLX5_ASSERT(tble->tunnel); 10972 memcpy(&info->tunnel, &tble->tunnel->app_tunnel, sizeof(info->tunnel)); 10973 info->group_id = tble->group_id; 10974 info->flags = RTE_FLOW_RESTORE_INFO_TUNNEL | 10975 RTE_FLOW_RESTORE_INFO_GROUP_ID | 10976 RTE_FLOW_RESTORE_INFO_ENCAPSULATED; 10977 10978 return 0; 10979 10980 err: 10981 return rte_flow_error_set(err, EINVAL, 10982 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, 10983 "failed to get restore info"); 10984 } 10985 10986 #else /* HAVE_IBV_FLOW_DV_SUPPORT */ 10987 static int 10988 mlx5_flow_tunnel_decap_set(__rte_unused struct rte_eth_dev *dev, 10989 __rte_unused struct rte_flow_tunnel *app_tunnel, 10990 __rte_unused struct rte_flow_action **actions, 10991 __rte_unused uint32_t *num_of_actions, 10992 __rte_unused struct rte_flow_error *error) 10993 { 10994 return -ENOTSUP; 10995 } 10996 10997 static int 10998 mlx5_flow_tunnel_match(__rte_unused struct rte_eth_dev *dev, 10999 __rte_unused struct rte_flow_tunnel *app_tunnel, 11000 __rte_unused struct rte_flow_item **items, 11001 __rte_unused uint32_t *num_of_items, 11002 __rte_unused struct rte_flow_error *error) 11003 { 11004 return -ENOTSUP; 11005 } 11006 11007 static int 11008 mlx5_flow_tunnel_item_release(__rte_unused struct rte_eth_dev *dev, 11009 __rte_unused struct rte_flow_item *pmd_items, 11010 __rte_unused uint32_t num_items, 11011 __rte_unused struct rte_flow_error *err) 11012 { 11013 return -ENOTSUP; 11014 } 11015 11016 static int 11017 mlx5_flow_tunnel_action_release(__rte_unused struct rte_eth_dev *dev, 11018 __rte_unused struct rte_flow_action *pmd_action, 11019 __rte_unused uint32_t num_actions, 11020 __rte_unused struct rte_flow_error *err) 11021 { 11022 return -ENOTSUP; 11023 } 11024 11025 static int 11026 mlx5_flow_tunnel_get_restore_info(__rte_unused struct rte_eth_dev *dev, 11027 __rte_unused struct rte_mbuf *m, 11028 __rte_unused struct rte_flow_restore_info *i, 11029 __rte_unused struct rte_flow_error *err) 11030 { 11031 return -ENOTSUP; 11032 } 11033 11034 static int 11035 flow_tunnel_add_default_miss(__rte_unused struct rte_eth_dev *dev, 11036 __rte_unused struct rte_flow *flow, 11037 __rte_unused const struct rte_flow_attr *attr, 11038 __rte_unused const struct rte_flow_action *actions, 11039 __rte_unused uint32_t flow_idx, 11040 __rte_unused const struct mlx5_flow_tunnel *tunnel, 11041 __rte_unused struct tunnel_default_miss_ctx *ctx, 11042 __rte_unused struct rte_flow_error *error) 11043 { 11044 return -ENOTSUP; 11045 } 11046 11047 static struct mlx5_flow_tunnel * 11048 mlx5_find_tunnel_id(__rte_unused struct rte_eth_dev *dev, 11049 __rte_unused uint32_t id) 11050 { 11051 return NULL; 11052 } 11053 11054 static void 11055 mlx5_flow_tunnel_free(__rte_unused struct rte_eth_dev *dev, 11056 __rte_unused struct mlx5_flow_tunnel *tunnel) 11057 { 11058 } 11059 11060 static uint32_t 11061 tunnel_flow_group_to_flow_table(__rte_unused struct rte_eth_dev *dev, 11062 __rte_unused const struct mlx5_flow_tunnel *t, 11063 __rte_unused uint32_t group, 11064 __rte_unused uint32_t *table, 11065 struct rte_flow_error *error) 11066 { 11067 return rte_flow_error_set(error, ENOTSUP, 11068 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, 11069 "tunnel offload requires DV support"); 11070 } 11071 11072 void 11073 mlx5_release_tunnel_hub(__rte_unused struct mlx5_dev_ctx_shared *sh, 11074 __rte_unused uint16_t port_id) 11075 { 11076 } 11077 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */ 11078 11079 /* Flex flow item API */ 11080 static struct rte_flow_item_flex_handle * 11081 mlx5_flow_flex_item_create(struct rte_eth_dev *dev, 11082 const struct rte_flow_item_flex_conf *conf, 11083 struct rte_flow_error *error) 11084 { 11085 static const char err_msg[] = "flex item creation unsupported"; 11086 struct mlx5_priv *priv = dev->data->dev_private; 11087 struct rte_flow_attr attr = { .transfer = 0 }; 11088 const struct mlx5_flow_driver_ops *fops = 11089 flow_get_drv_ops(flow_get_drv_type(dev, &attr)); 11090 11091 if (!priv->pci_dev) { 11092 rte_flow_error_set(error, ENOTSUP, 11093 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, 11094 "create flex item on PF only"); 11095 return NULL; 11096 } 11097 switch (priv->pci_dev->id.device_id) { 11098 case PCI_DEVICE_ID_MELLANOX_CONNECTX6DXBF: 11099 case PCI_DEVICE_ID_MELLANOX_CONNECTX7BF: 11100 break; 11101 default: 11102 rte_flow_error_set(error, ENOTSUP, 11103 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, 11104 "flex item available on BlueField ports only"); 11105 return NULL; 11106 } 11107 if (!fops->item_create) { 11108 DRV_LOG(ERR, "port %u %s.", dev->data->port_id, err_msg); 11109 rte_flow_error_set(error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION, 11110 NULL, err_msg); 11111 return NULL; 11112 } 11113 return fops->item_create(dev, conf, error); 11114 } 11115 11116 static int 11117 mlx5_flow_flex_item_release(struct rte_eth_dev *dev, 11118 const struct rte_flow_item_flex_handle *handle, 11119 struct rte_flow_error *error) 11120 { 11121 static const char err_msg[] = "flex item release unsupported"; 11122 struct rte_flow_attr attr = { .transfer = 0 }; 11123 const struct mlx5_flow_driver_ops *fops = 11124 flow_get_drv_ops(flow_get_drv_type(dev, &attr)); 11125 11126 if (!fops->item_release) { 11127 DRV_LOG(ERR, "port %u %s.", dev->data->port_id, err_msg); 11128 rte_flow_error_set(error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION, 11129 NULL, err_msg); 11130 return -rte_errno; 11131 } 11132 return fops->item_release(dev, handle, error); 11133 } 11134 11135 static void 11136 mlx5_dbg__print_pattern(const struct rte_flow_item *item) 11137 { 11138 int ret; 11139 struct rte_flow_error error; 11140 11141 for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) { 11142 char *item_name; 11143 ret = rte_flow_conv(RTE_FLOW_CONV_OP_ITEM_NAME_PTR, &item_name, 11144 sizeof(item_name), 11145 (void *)(uintptr_t)item->type, &error); 11146 if (ret > 0) 11147 printf("%s ", item_name); 11148 else 11149 printf("%d\n", (int)item->type); 11150 } 11151 printf("END\n"); 11152 } 11153 11154 static int 11155 mlx5_flow_is_std_vxlan_port(const struct rte_flow_item *udp_item) 11156 { 11157 const struct rte_flow_item_udp *spec = udp_item->spec; 11158 const struct rte_flow_item_udp *mask = udp_item->mask; 11159 uint16_t udp_dport = 0; 11160 11161 if (spec != NULL) { 11162 if (!mask) 11163 mask = &rte_flow_item_udp_mask; 11164 udp_dport = rte_be_to_cpu_16(spec->hdr.dst_port & 11165 mask->hdr.dst_port); 11166 } 11167 return (!udp_dport || udp_dport == MLX5_UDP_PORT_VXLAN); 11168 } 11169 11170 static const struct mlx5_flow_expand_node * 11171 mlx5_flow_expand_rss_adjust_node(const struct rte_flow_item *pattern, 11172 unsigned int item_idx, 11173 const struct mlx5_flow_expand_node graph[], 11174 const struct mlx5_flow_expand_node *node) 11175 { 11176 const struct rte_flow_item *item = pattern + item_idx, *prev_item; 11177 11178 if (item->type == RTE_FLOW_ITEM_TYPE_VXLAN && 11179 node != NULL && 11180 node->type == RTE_FLOW_ITEM_TYPE_VXLAN) { 11181 /* 11182 * The expansion node is VXLAN and it is also the last 11183 * expandable item in the pattern, so need to continue 11184 * expansion of the inner tunnel. 11185 */ 11186 MLX5_ASSERT(item_idx > 0); 11187 prev_item = pattern + item_idx - 1; 11188 MLX5_ASSERT(prev_item->type == RTE_FLOW_ITEM_TYPE_UDP); 11189 if (mlx5_flow_is_std_vxlan_port(prev_item)) 11190 return &graph[MLX5_EXPANSION_STD_VXLAN]; 11191 return &graph[MLX5_EXPANSION_L3_VXLAN]; 11192 } 11193 return node; 11194 } 11195 11196 /* Map of Verbs to Flow priority with 8 Verbs priorities. */ 11197 static const uint32_t priority_map_3[][MLX5_PRIORITY_MAP_MAX] = { 11198 { 0, 1, 2 }, { 2, 3, 4 }, { 5, 6, 7 }, 11199 }; 11200 11201 /* Map of Verbs to Flow priority with 16 Verbs priorities. */ 11202 static const uint32_t priority_map_5[][MLX5_PRIORITY_MAP_MAX] = { 11203 { 0, 1, 2 }, { 3, 4, 5 }, { 6, 7, 8 }, 11204 { 9, 10, 11 }, { 12, 13, 14 }, 11205 }; 11206 11207 /** 11208 * Discover the number of available flow priorities. 11209 * 11210 * @param dev 11211 * Ethernet device. 11212 * 11213 * @return 11214 * On success, number of available flow priorities. 11215 * On failure, a negative errno-style code and rte_errno is set. 11216 */ 11217 int 11218 mlx5_flow_discover_priorities(struct rte_eth_dev *dev) 11219 { 11220 static const uint16_t vprio[] = {8, 16}; 11221 const struct mlx5_priv *priv = dev->data->dev_private; 11222 const struct mlx5_flow_driver_ops *fops; 11223 enum mlx5_flow_drv_type type; 11224 int ret; 11225 11226 type = mlx5_flow_os_get_type(); 11227 if (type == MLX5_FLOW_TYPE_MAX) { 11228 type = MLX5_FLOW_TYPE_VERBS; 11229 if (priv->sh->cdev->config.devx && priv->sh->config.dv_flow_en) 11230 type = MLX5_FLOW_TYPE_DV; 11231 } 11232 fops = flow_get_drv_ops(type); 11233 if (fops->discover_priorities == NULL) { 11234 DRV_LOG(ERR, "Priority discovery not supported"); 11235 rte_errno = ENOTSUP; 11236 return -rte_errno; 11237 } 11238 ret = fops->discover_priorities(dev, vprio, RTE_DIM(vprio)); 11239 if (ret < 0) 11240 return ret; 11241 switch (ret) { 11242 case 8: 11243 ret = RTE_DIM(priority_map_3); 11244 break; 11245 case 16: 11246 ret = RTE_DIM(priority_map_5); 11247 break; 11248 default: 11249 rte_errno = ENOTSUP; 11250 DRV_LOG(ERR, 11251 "port %u maximum priority: %d expected 8/16", 11252 dev->data->port_id, ret); 11253 return -rte_errno; 11254 } 11255 DRV_LOG(INFO, "port %u supported flow priorities:" 11256 " 0-%d for ingress or egress root table," 11257 " 0-%d for non-root table or transfer root table.", 11258 dev->data->port_id, ret - 2, 11259 MLX5_NON_ROOT_FLOW_MAX_PRIO - 1); 11260 return ret; 11261 } 11262 11263 /** 11264 * Adjust flow priority based on the highest layer and the request priority. 11265 * 11266 * @param[in] dev 11267 * Pointer to the Ethernet device structure. 11268 * @param[in] priority 11269 * The rule base priority. 11270 * @param[in] subpriority 11271 * The priority based on the items. 11272 * 11273 * @return 11274 * The new priority. 11275 */ 11276 uint32_t 11277 mlx5_flow_adjust_priority(struct rte_eth_dev *dev, int32_t priority, 11278 uint32_t subpriority) 11279 { 11280 uint32_t res = 0; 11281 struct mlx5_priv *priv = dev->data->dev_private; 11282 11283 switch (priv->sh->flow_max_priority) { 11284 case RTE_DIM(priority_map_3): 11285 res = priority_map_3[priority][subpriority]; 11286 break; 11287 case RTE_DIM(priority_map_5): 11288 res = priority_map_5[priority][subpriority]; 11289 break; 11290 } 11291 return res; 11292 } 11293 11294 /** 11295 * Get the priority for sending traffic to kernel table. 11296 * 11297 * @param[in] dev 11298 * Pointer to the Ethernet device structure. 11299 * 11300 * @return 11301 * On success: the value of priority for sending traffic to kernel table 11302 * On failure: -1 11303 */ 11304 uint32_t 11305 mlx5_get_send_to_kernel_priority(struct rte_eth_dev *dev) 11306 { 11307 struct mlx5_priv *priv = dev->data->dev_private; 11308 uint32_t res; 11309 11310 switch (priv->sh->flow_max_priority) { 11311 case RTE_DIM(priority_map_5): 11312 res = 15; 11313 break; 11314 case RTE_DIM(priority_map_3): 11315 res = 7; 11316 break; 11317 default: 11318 DRV_LOG(ERR, 11319 "port %u maximum priority: %d expected 8/16", 11320 dev->data->port_id, priv->sh->flow_max_priority); 11321 res = (uint32_t)-1; 11322 } 11323 return res; 11324 } 11325 11326 /** 11327 * Get the E-Switch Manager vport id. 11328 * 11329 * @param[in] dev 11330 * Pointer to the Ethernet device structure. 11331 * 11332 * @return 11333 * The vport id. 11334 */ 11335 int16_t mlx5_flow_get_esw_manager_vport_id(struct rte_eth_dev *dev) 11336 { 11337 struct mlx5_priv *priv = dev->data->dev_private; 11338 struct mlx5_common_device *cdev = priv->sh->cdev; 11339 11340 /* New FW exposes E-Switch Manager vport ID, can use it directly. */ 11341 if (cdev->config.hca_attr.esw_mgr_vport_id_valid) 11342 return (int16_t)cdev->config.hca_attr.esw_mgr_vport_id; 11343 11344 if (priv->pci_dev == NULL) 11345 return 0; 11346 switch (priv->pci_dev->id.device_id) { 11347 case PCI_DEVICE_ID_MELLANOX_CONNECTX5BF: 11348 case PCI_DEVICE_ID_MELLANOX_CONNECTX6DXBF: 11349 case PCI_DEVICE_ID_MELLANOX_CONNECTX7BF: 11350 /* 11351 * In old FW which doesn't expose the E-Switch Manager vport ID in the capability, 11352 * only the BF embedded CPUs control the E-Switch Manager port. Hence, 11353 * ECPF vport ID is selected and not the host port (0) in any BF case. 11354 */ 11355 return (int16_t)MLX5_ECPF_VPORT_ID; 11356 default: 11357 return MLX5_PF_VPORT_ID; 11358 } 11359 } 11360 11361 /** 11362 * Parse item to get the vport id. 11363 * 11364 * @param[in] dev 11365 * Pointer to the Ethernet device structure. 11366 * @param[in] item 11367 * The src port id match item. 11368 * @param[out] vport_id 11369 * Pointer to put the vport id. 11370 * @param[out] all_ports 11371 * Indicate if the item matches all ports. 11372 * @param[out] error 11373 * Pointer to error structure. 11374 * 11375 * @return 11376 * 0 on success, a negative errno value otherwise and rte_errno is set. 11377 */ 11378 int mlx5_flow_get_item_vport_id(struct rte_eth_dev *dev, 11379 const struct rte_flow_item *item, 11380 uint16_t *vport_id, 11381 bool *all_ports, 11382 struct rte_flow_error *error) 11383 { 11384 struct mlx5_priv *port_priv; 11385 const struct rte_flow_item_port_id *pid_v; 11386 uint32_t esw_mgr_port; 11387 11388 if (item->type != RTE_FLOW_ITEM_TYPE_PORT_ID && 11389 item->type != RTE_FLOW_ITEM_TYPE_REPRESENTED_PORT) 11390 return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ITEM_SPEC, 11391 NULL, "Incorrect item type."); 11392 pid_v = item->spec; 11393 if (!pid_v) { 11394 if (all_ports) 11395 *all_ports = (item->type == RTE_FLOW_ITEM_TYPE_REPRESENTED_PORT); 11396 return 0; 11397 } 11398 if (all_ports) 11399 *all_ports = false; 11400 esw_mgr_port = (item->type == RTE_FLOW_ITEM_TYPE_REPRESENTED_PORT) ? 11401 MLX5_REPRESENTED_PORT_ESW_MGR : MLX5_PORT_ESW_MGR; 11402 if (pid_v->id == esw_mgr_port) { 11403 *vport_id = mlx5_flow_get_esw_manager_vport_id(dev); 11404 } else { 11405 port_priv = mlx5_port_to_eswitch_info(pid_v->id, false); 11406 if (!port_priv) 11407 return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ITEM_SPEC, 11408 NULL, "Failed to get port info."); 11409 *vport_id = port_priv->representor_id; 11410 } 11411 11412 return 0; 11413 } 11414 11415 int 11416 mlx5_flow_pick_transfer_proxy(struct rte_eth_dev *dev, 11417 uint16_t *proxy_port_id, 11418 struct rte_flow_error *error) 11419 { 11420 const struct mlx5_priv *priv = dev->data->dev_private; 11421 uint16_t port_id; 11422 11423 if (!priv->sh->config.dv_esw_en) 11424 return rte_flow_error_set(error, EINVAL, 11425 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, 11426 NULL, 11427 "unable to provide a proxy port" 11428 " without E-Switch configured"); 11429 if (!priv->master && !priv->representor) 11430 return rte_flow_error_set(error, EINVAL, 11431 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, 11432 NULL, 11433 "unable to provide a proxy port" 11434 " for port which is not a master" 11435 " or a representor port"); 11436 if (priv->master) { 11437 *proxy_port_id = dev->data->port_id; 11438 return 0; 11439 } 11440 MLX5_ETH_FOREACH_DEV(port_id, dev->device) { 11441 const struct rte_eth_dev *port_dev = &rte_eth_devices[port_id]; 11442 const struct mlx5_priv *port_priv = port_dev->data->dev_private; 11443 11444 if (port_priv->master && 11445 port_priv->domain_id == priv->domain_id) { 11446 *proxy_port_id = port_id; 11447 return 0; 11448 } 11449 } 11450 return rte_flow_error_set(error, ENODEV, 11451 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, 11452 NULL, "unable to find a proxy port"); 11453 } 11454