1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2016 6WIND S.A. 3 * Copyright 2016 Mellanox Technologies, Ltd 4 */ 5 6 #include <netinet/in.h> 7 #include <sys/queue.h> 8 #include <stdalign.h> 9 #include <stdint.h> 10 #include <string.h> 11 #include <stdbool.h> 12 13 /* Verbs header. */ 14 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */ 15 #ifdef PEDANTIC 16 #pragma GCC diagnostic ignored "-Wpedantic" 17 #endif 18 #include <infiniband/verbs.h> 19 #ifdef PEDANTIC 20 #pragma GCC diagnostic error "-Wpedantic" 21 #endif 22 23 #include <rte_common.h> 24 #include <rte_ether.h> 25 #include <rte_ethdev_driver.h> 26 #include <rte_flow.h> 27 #include <rte_flow_driver.h> 28 #include <rte_malloc.h> 29 #include <rte_ip.h> 30 31 #include <mlx5_glue.h> 32 #include <mlx5_devx_cmds.h> 33 #include <mlx5_prm.h> 34 35 #include "mlx5_defs.h" 36 #include "mlx5.h" 37 #include "mlx5_flow.h" 38 #include "mlx5_rxtx.h" 39 40 /* Dev ops structure defined in mlx5.c */ 41 extern const struct eth_dev_ops mlx5_dev_ops; 42 extern const struct eth_dev_ops mlx5_dev_ops_isolate; 43 44 /** Device flow drivers. */ 45 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 46 extern const struct mlx5_flow_driver_ops mlx5_flow_dv_drv_ops; 47 #endif 48 extern const struct mlx5_flow_driver_ops mlx5_flow_verbs_drv_ops; 49 50 const struct mlx5_flow_driver_ops mlx5_flow_null_drv_ops; 51 52 const struct mlx5_flow_driver_ops *flow_drv_ops[] = { 53 [MLX5_FLOW_TYPE_MIN] = &mlx5_flow_null_drv_ops, 54 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 55 [MLX5_FLOW_TYPE_DV] = &mlx5_flow_dv_drv_ops, 56 #endif 57 [MLX5_FLOW_TYPE_VERBS] = &mlx5_flow_verbs_drv_ops, 58 [MLX5_FLOW_TYPE_MAX] = &mlx5_flow_null_drv_ops 59 }; 60 61 enum mlx5_expansion { 62 MLX5_EXPANSION_ROOT, 63 MLX5_EXPANSION_ROOT_OUTER, 64 MLX5_EXPANSION_ROOT_ETH_VLAN, 65 MLX5_EXPANSION_ROOT_OUTER_ETH_VLAN, 66 MLX5_EXPANSION_OUTER_ETH, 67 MLX5_EXPANSION_OUTER_ETH_VLAN, 68 MLX5_EXPANSION_OUTER_VLAN, 69 MLX5_EXPANSION_OUTER_IPV4, 70 MLX5_EXPANSION_OUTER_IPV4_UDP, 71 MLX5_EXPANSION_OUTER_IPV4_TCP, 72 MLX5_EXPANSION_OUTER_IPV6, 73 MLX5_EXPANSION_OUTER_IPV6_UDP, 74 MLX5_EXPANSION_OUTER_IPV6_TCP, 75 MLX5_EXPANSION_VXLAN, 76 MLX5_EXPANSION_VXLAN_GPE, 77 MLX5_EXPANSION_GRE, 78 MLX5_EXPANSION_MPLS, 79 MLX5_EXPANSION_ETH, 80 MLX5_EXPANSION_ETH_VLAN, 81 MLX5_EXPANSION_VLAN, 82 MLX5_EXPANSION_IPV4, 83 MLX5_EXPANSION_IPV4_UDP, 84 MLX5_EXPANSION_IPV4_TCP, 85 MLX5_EXPANSION_IPV6, 86 MLX5_EXPANSION_IPV6_UDP, 87 MLX5_EXPANSION_IPV6_TCP, 88 }; 89 90 /** Supported expansion of items. */ 91 static const struct rte_flow_expand_node mlx5_support_expansion[] = { 92 [MLX5_EXPANSION_ROOT] = { 93 .next = RTE_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_ETH, 94 MLX5_EXPANSION_IPV4, 95 MLX5_EXPANSION_IPV6), 96 .type = RTE_FLOW_ITEM_TYPE_END, 97 }, 98 [MLX5_EXPANSION_ROOT_OUTER] = { 99 .next = RTE_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_OUTER_ETH, 100 MLX5_EXPANSION_OUTER_IPV4, 101 MLX5_EXPANSION_OUTER_IPV6), 102 .type = RTE_FLOW_ITEM_TYPE_END, 103 }, 104 [MLX5_EXPANSION_ROOT_ETH_VLAN] = { 105 .next = RTE_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_ETH_VLAN), 106 .type = RTE_FLOW_ITEM_TYPE_END, 107 }, 108 [MLX5_EXPANSION_ROOT_OUTER_ETH_VLAN] = { 109 .next = RTE_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_OUTER_ETH_VLAN), 110 .type = RTE_FLOW_ITEM_TYPE_END, 111 }, 112 [MLX5_EXPANSION_OUTER_ETH] = { 113 .next = RTE_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_OUTER_IPV4, 114 MLX5_EXPANSION_OUTER_IPV6, 115 MLX5_EXPANSION_MPLS), 116 .type = RTE_FLOW_ITEM_TYPE_ETH, 117 .rss_types = 0, 118 }, 119 [MLX5_EXPANSION_OUTER_ETH_VLAN] = { 120 .next = RTE_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_OUTER_VLAN), 121 .type = RTE_FLOW_ITEM_TYPE_ETH, 122 .rss_types = 0, 123 }, 124 [MLX5_EXPANSION_OUTER_VLAN] = { 125 .next = RTE_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_OUTER_IPV4, 126 MLX5_EXPANSION_OUTER_IPV6), 127 .type = RTE_FLOW_ITEM_TYPE_VLAN, 128 }, 129 [MLX5_EXPANSION_OUTER_IPV4] = { 130 .next = RTE_FLOW_EXPAND_RSS_NEXT 131 (MLX5_EXPANSION_OUTER_IPV4_UDP, 132 MLX5_EXPANSION_OUTER_IPV4_TCP, 133 MLX5_EXPANSION_GRE, 134 MLX5_EXPANSION_IPV4, 135 MLX5_EXPANSION_IPV6), 136 .type = RTE_FLOW_ITEM_TYPE_IPV4, 137 .rss_types = ETH_RSS_IPV4 | ETH_RSS_FRAG_IPV4 | 138 ETH_RSS_NONFRAG_IPV4_OTHER, 139 }, 140 [MLX5_EXPANSION_OUTER_IPV4_UDP] = { 141 .next = RTE_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_VXLAN, 142 MLX5_EXPANSION_VXLAN_GPE), 143 .type = RTE_FLOW_ITEM_TYPE_UDP, 144 .rss_types = ETH_RSS_NONFRAG_IPV4_UDP, 145 }, 146 [MLX5_EXPANSION_OUTER_IPV4_TCP] = { 147 .type = RTE_FLOW_ITEM_TYPE_TCP, 148 .rss_types = ETH_RSS_NONFRAG_IPV4_TCP, 149 }, 150 [MLX5_EXPANSION_OUTER_IPV6] = { 151 .next = RTE_FLOW_EXPAND_RSS_NEXT 152 (MLX5_EXPANSION_OUTER_IPV6_UDP, 153 MLX5_EXPANSION_OUTER_IPV6_TCP, 154 MLX5_EXPANSION_IPV4, 155 MLX5_EXPANSION_IPV6), 156 .type = RTE_FLOW_ITEM_TYPE_IPV6, 157 .rss_types = ETH_RSS_IPV6 | ETH_RSS_FRAG_IPV6 | 158 ETH_RSS_NONFRAG_IPV6_OTHER, 159 }, 160 [MLX5_EXPANSION_OUTER_IPV6_UDP] = { 161 .next = RTE_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_VXLAN, 162 MLX5_EXPANSION_VXLAN_GPE), 163 .type = RTE_FLOW_ITEM_TYPE_UDP, 164 .rss_types = ETH_RSS_NONFRAG_IPV6_UDP, 165 }, 166 [MLX5_EXPANSION_OUTER_IPV6_TCP] = { 167 .type = RTE_FLOW_ITEM_TYPE_TCP, 168 .rss_types = ETH_RSS_NONFRAG_IPV6_TCP, 169 }, 170 [MLX5_EXPANSION_VXLAN] = { 171 .next = RTE_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_ETH, 172 MLX5_EXPANSION_IPV4, 173 MLX5_EXPANSION_IPV6), 174 .type = RTE_FLOW_ITEM_TYPE_VXLAN, 175 }, 176 [MLX5_EXPANSION_VXLAN_GPE] = { 177 .next = RTE_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_ETH, 178 MLX5_EXPANSION_IPV4, 179 MLX5_EXPANSION_IPV6), 180 .type = RTE_FLOW_ITEM_TYPE_VXLAN_GPE, 181 }, 182 [MLX5_EXPANSION_GRE] = { 183 .next = RTE_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_IPV4), 184 .type = RTE_FLOW_ITEM_TYPE_GRE, 185 }, 186 [MLX5_EXPANSION_MPLS] = { 187 .next = RTE_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_IPV4, 188 MLX5_EXPANSION_IPV6), 189 .type = RTE_FLOW_ITEM_TYPE_MPLS, 190 }, 191 [MLX5_EXPANSION_ETH] = { 192 .next = RTE_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_IPV4, 193 MLX5_EXPANSION_IPV6), 194 .type = RTE_FLOW_ITEM_TYPE_ETH, 195 }, 196 [MLX5_EXPANSION_ETH_VLAN] = { 197 .next = RTE_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_VLAN), 198 .type = RTE_FLOW_ITEM_TYPE_ETH, 199 }, 200 [MLX5_EXPANSION_VLAN] = { 201 .next = RTE_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_IPV4, 202 MLX5_EXPANSION_IPV6), 203 .type = RTE_FLOW_ITEM_TYPE_VLAN, 204 }, 205 [MLX5_EXPANSION_IPV4] = { 206 .next = RTE_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_IPV4_UDP, 207 MLX5_EXPANSION_IPV4_TCP), 208 .type = RTE_FLOW_ITEM_TYPE_IPV4, 209 .rss_types = ETH_RSS_IPV4 | ETH_RSS_FRAG_IPV4 | 210 ETH_RSS_NONFRAG_IPV4_OTHER, 211 }, 212 [MLX5_EXPANSION_IPV4_UDP] = { 213 .type = RTE_FLOW_ITEM_TYPE_UDP, 214 .rss_types = ETH_RSS_NONFRAG_IPV4_UDP, 215 }, 216 [MLX5_EXPANSION_IPV4_TCP] = { 217 .type = RTE_FLOW_ITEM_TYPE_TCP, 218 .rss_types = ETH_RSS_NONFRAG_IPV4_TCP, 219 }, 220 [MLX5_EXPANSION_IPV6] = { 221 .next = RTE_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_IPV6_UDP, 222 MLX5_EXPANSION_IPV6_TCP), 223 .type = RTE_FLOW_ITEM_TYPE_IPV6, 224 .rss_types = ETH_RSS_IPV6 | ETH_RSS_FRAG_IPV6 | 225 ETH_RSS_NONFRAG_IPV6_OTHER, 226 }, 227 [MLX5_EXPANSION_IPV6_UDP] = { 228 .type = RTE_FLOW_ITEM_TYPE_UDP, 229 .rss_types = ETH_RSS_NONFRAG_IPV6_UDP, 230 }, 231 [MLX5_EXPANSION_IPV6_TCP] = { 232 .type = RTE_FLOW_ITEM_TYPE_TCP, 233 .rss_types = ETH_RSS_NONFRAG_IPV6_TCP, 234 }, 235 }; 236 237 static const struct rte_flow_ops mlx5_flow_ops = { 238 .validate = mlx5_flow_validate, 239 .create = mlx5_flow_create, 240 .destroy = mlx5_flow_destroy, 241 .flush = mlx5_flow_flush, 242 .isolate = mlx5_flow_isolate, 243 .query = mlx5_flow_query, 244 .dev_dump = mlx5_flow_dev_dump, 245 }; 246 247 /* Convert FDIR request to Generic flow. */ 248 struct mlx5_fdir { 249 struct rte_flow_attr attr; 250 struct rte_flow_item items[4]; 251 struct rte_flow_item_eth l2; 252 struct rte_flow_item_eth l2_mask; 253 union { 254 struct rte_flow_item_ipv4 ipv4; 255 struct rte_flow_item_ipv6 ipv6; 256 } l3; 257 union { 258 struct rte_flow_item_ipv4 ipv4; 259 struct rte_flow_item_ipv6 ipv6; 260 } l3_mask; 261 union { 262 struct rte_flow_item_udp udp; 263 struct rte_flow_item_tcp tcp; 264 } l4; 265 union { 266 struct rte_flow_item_udp udp; 267 struct rte_flow_item_tcp tcp; 268 } l4_mask; 269 struct rte_flow_action actions[2]; 270 struct rte_flow_action_queue queue; 271 }; 272 273 /* Map of Verbs to Flow priority with 8 Verbs priorities. */ 274 static const uint32_t priority_map_3[][MLX5_PRIORITY_MAP_MAX] = { 275 { 0, 1, 2 }, { 2, 3, 4 }, { 5, 6, 7 }, 276 }; 277 278 /* Map of Verbs to Flow priority with 16 Verbs priorities. */ 279 static const uint32_t priority_map_5[][MLX5_PRIORITY_MAP_MAX] = { 280 { 0, 1, 2 }, { 3, 4, 5 }, { 6, 7, 8 }, 281 { 9, 10, 11 }, { 12, 13, 14 }, 282 }; 283 284 /* Tunnel information. */ 285 struct mlx5_flow_tunnel_info { 286 uint64_t tunnel; /**< Tunnel bit (see MLX5_FLOW_*). */ 287 uint32_t ptype; /**< Tunnel Ptype (see RTE_PTYPE_*). */ 288 }; 289 290 static struct mlx5_flow_tunnel_info tunnels_info[] = { 291 { 292 .tunnel = MLX5_FLOW_LAYER_VXLAN, 293 .ptype = RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_L4_UDP, 294 }, 295 { 296 .tunnel = MLX5_FLOW_LAYER_GENEVE, 297 .ptype = RTE_PTYPE_TUNNEL_GENEVE | RTE_PTYPE_L4_UDP, 298 }, 299 { 300 .tunnel = MLX5_FLOW_LAYER_VXLAN_GPE, 301 .ptype = RTE_PTYPE_TUNNEL_VXLAN_GPE | RTE_PTYPE_L4_UDP, 302 }, 303 { 304 .tunnel = MLX5_FLOW_LAYER_GRE, 305 .ptype = RTE_PTYPE_TUNNEL_GRE, 306 }, 307 { 308 .tunnel = MLX5_FLOW_LAYER_MPLS | MLX5_FLOW_LAYER_OUTER_L4_UDP, 309 .ptype = RTE_PTYPE_TUNNEL_MPLS_IN_UDP | RTE_PTYPE_L4_UDP, 310 }, 311 { 312 .tunnel = MLX5_FLOW_LAYER_MPLS, 313 .ptype = RTE_PTYPE_TUNNEL_MPLS_IN_GRE, 314 }, 315 { 316 .tunnel = MLX5_FLOW_LAYER_NVGRE, 317 .ptype = RTE_PTYPE_TUNNEL_NVGRE, 318 }, 319 { 320 .tunnel = MLX5_FLOW_LAYER_IPIP, 321 .ptype = RTE_PTYPE_TUNNEL_IP, 322 }, 323 { 324 .tunnel = MLX5_FLOW_LAYER_IPV6_ENCAP, 325 .ptype = RTE_PTYPE_TUNNEL_IP, 326 }, 327 { 328 .tunnel = MLX5_FLOW_LAYER_GTP, 329 .ptype = RTE_PTYPE_TUNNEL_GTPU, 330 }, 331 }; 332 333 /** 334 * Translate tag ID to register. 335 * 336 * @param[in] dev 337 * Pointer to the Ethernet device structure. 338 * @param[in] feature 339 * The feature that request the register. 340 * @param[in] id 341 * The request register ID. 342 * @param[out] error 343 * Error description in case of any. 344 * 345 * @return 346 * The request register on success, a negative errno 347 * value otherwise and rte_errno is set. 348 */ 349 int 350 mlx5_flow_get_reg_id(struct rte_eth_dev *dev, 351 enum mlx5_feature_name feature, 352 uint32_t id, 353 struct rte_flow_error *error) 354 { 355 struct mlx5_priv *priv = dev->data->dev_private; 356 struct mlx5_dev_config *config = &priv->config; 357 enum modify_reg start_reg; 358 bool skip_mtr_reg = false; 359 360 switch (feature) { 361 case MLX5_HAIRPIN_RX: 362 return REG_B; 363 case MLX5_HAIRPIN_TX: 364 return REG_A; 365 case MLX5_METADATA_RX: 366 switch (config->dv_xmeta_en) { 367 case MLX5_XMETA_MODE_LEGACY: 368 return REG_B; 369 case MLX5_XMETA_MODE_META16: 370 return REG_C_0; 371 case MLX5_XMETA_MODE_META32: 372 return REG_C_1; 373 } 374 break; 375 case MLX5_METADATA_TX: 376 return REG_A; 377 case MLX5_METADATA_FDB: 378 switch (config->dv_xmeta_en) { 379 case MLX5_XMETA_MODE_LEGACY: 380 return REG_NONE; 381 case MLX5_XMETA_MODE_META16: 382 return REG_C_0; 383 case MLX5_XMETA_MODE_META32: 384 return REG_C_1; 385 } 386 break; 387 case MLX5_FLOW_MARK: 388 switch (config->dv_xmeta_en) { 389 case MLX5_XMETA_MODE_LEGACY: 390 return REG_NONE; 391 case MLX5_XMETA_MODE_META16: 392 return REG_C_1; 393 case MLX5_XMETA_MODE_META32: 394 return REG_C_0; 395 } 396 break; 397 case MLX5_MTR_SFX: 398 /* 399 * If meter color and flow match share one register, flow match 400 * should use the meter color register for match. 401 */ 402 if (priv->mtr_reg_share) 403 return priv->mtr_color_reg; 404 else 405 return priv->mtr_color_reg != REG_C_2 ? REG_C_2 : 406 REG_C_3; 407 case MLX5_MTR_COLOR: 408 MLX5_ASSERT(priv->mtr_color_reg != REG_NONE); 409 return priv->mtr_color_reg; 410 case MLX5_COPY_MARK: 411 /* 412 * Metadata COPY_MARK register using is in meter suffix sub 413 * flow while with meter. It's safe to share the same register. 414 */ 415 return priv->mtr_color_reg != REG_C_2 ? REG_C_2 : REG_C_3; 416 case MLX5_APP_TAG: 417 /* 418 * If meter is enable, it will engage the register for color 419 * match and flow match. If meter color match is not using the 420 * REG_C_2, need to skip the REG_C_x be used by meter color 421 * match. 422 * If meter is disable, free to use all available registers. 423 */ 424 start_reg = priv->mtr_color_reg != REG_C_2 ? REG_C_2 : 425 (priv->mtr_reg_share ? REG_C_3 : REG_C_4); 426 skip_mtr_reg = !!(priv->mtr_en && start_reg == REG_C_2); 427 if (id > (REG_C_7 - start_reg)) 428 return rte_flow_error_set(error, EINVAL, 429 RTE_FLOW_ERROR_TYPE_ITEM, 430 NULL, "invalid tag id"); 431 if (config->flow_mreg_c[id + start_reg - REG_C_0] == REG_NONE) 432 return rte_flow_error_set(error, ENOTSUP, 433 RTE_FLOW_ERROR_TYPE_ITEM, 434 NULL, "unsupported tag id"); 435 /* 436 * This case means meter is using the REG_C_x great than 2. 437 * Take care not to conflict with meter color REG_C_x. 438 * If the available index REG_C_y >= REG_C_x, skip the 439 * color register. 440 */ 441 if (skip_mtr_reg && config->flow_mreg_c 442 [id + start_reg - REG_C_0] >= priv->mtr_color_reg) { 443 if (config->flow_mreg_c 444 [id + 1 + start_reg - REG_C_0] != REG_NONE) 445 return config->flow_mreg_c 446 [id + 1 + start_reg - REG_C_0]; 447 return rte_flow_error_set(error, ENOTSUP, 448 RTE_FLOW_ERROR_TYPE_ITEM, 449 NULL, "unsupported tag id"); 450 } 451 return config->flow_mreg_c[id + start_reg - REG_C_0]; 452 } 453 MLX5_ASSERT(false); 454 return rte_flow_error_set(error, EINVAL, 455 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, 456 NULL, "invalid feature name"); 457 } 458 459 /** 460 * Check extensive flow metadata register support. 461 * 462 * @param dev 463 * Pointer to rte_eth_dev structure. 464 * 465 * @return 466 * True if device supports extensive flow metadata register, otherwise false. 467 */ 468 bool 469 mlx5_flow_ext_mreg_supported(struct rte_eth_dev *dev) 470 { 471 struct mlx5_priv *priv = dev->data->dev_private; 472 struct mlx5_dev_config *config = &priv->config; 473 474 /* 475 * Having available reg_c can be regarded inclusively as supporting 476 * extensive flow metadata register, which could mean, 477 * - metadata register copy action by modify header. 478 * - 16 modify header actions is supported. 479 * - reg_c's are preserved across different domain (FDB and NIC) on 480 * packet loopback by flow lookup miss. 481 */ 482 return config->flow_mreg_c[2] != REG_NONE; 483 } 484 485 /** 486 * Discover the maximum number of priority available. 487 * 488 * @param[in] dev 489 * Pointer to the Ethernet device structure. 490 * 491 * @return 492 * number of supported flow priority on success, a negative errno 493 * value otherwise and rte_errno is set. 494 */ 495 int 496 mlx5_flow_discover_priorities(struct rte_eth_dev *dev) 497 { 498 struct mlx5_priv *priv = dev->data->dev_private; 499 struct { 500 struct ibv_flow_attr attr; 501 struct ibv_flow_spec_eth eth; 502 struct ibv_flow_spec_action_drop drop; 503 } flow_attr = { 504 .attr = { 505 .num_of_specs = 2, 506 .port = (uint8_t)priv->ibv_port, 507 }, 508 .eth = { 509 .type = IBV_FLOW_SPEC_ETH, 510 .size = sizeof(struct ibv_flow_spec_eth), 511 }, 512 .drop = { 513 .size = sizeof(struct ibv_flow_spec_action_drop), 514 .type = IBV_FLOW_SPEC_ACTION_DROP, 515 }, 516 }; 517 struct ibv_flow *flow; 518 struct mlx5_hrxq *drop = mlx5_hrxq_drop_new(dev); 519 uint16_t vprio[] = { 8, 16 }; 520 int i; 521 int priority = 0; 522 523 if (!drop) { 524 rte_errno = ENOTSUP; 525 return -rte_errno; 526 } 527 for (i = 0; i != RTE_DIM(vprio); i++) { 528 flow_attr.attr.priority = vprio[i] - 1; 529 flow = mlx5_glue->create_flow(drop->qp, &flow_attr.attr); 530 if (!flow) 531 break; 532 claim_zero(mlx5_glue->destroy_flow(flow)); 533 priority = vprio[i]; 534 } 535 mlx5_hrxq_drop_release(dev); 536 switch (priority) { 537 case 8: 538 priority = RTE_DIM(priority_map_3); 539 break; 540 case 16: 541 priority = RTE_DIM(priority_map_5); 542 break; 543 default: 544 rte_errno = ENOTSUP; 545 DRV_LOG(ERR, 546 "port %u verbs maximum priority: %d expected 8/16", 547 dev->data->port_id, priority); 548 return -rte_errno; 549 } 550 DRV_LOG(INFO, "port %u flow maximum priority: %d", 551 dev->data->port_id, priority); 552 return priority; 553 } 554 555 /** 556 * Adjust flow priority based on the highest layer and the request priority. 557 * 558 * @param[in] dev 559 * Pointer to the Ethernet device structure. 560 * @param[in] priority 561 * The rule base priority. 562 * @param[in] subpriority 563 * The priority based on the items. 564 * 565 * @return 566 * The new priority. 567 */ 568 uint32_t mlx5_flow_adjust_priority(struct rte_eth_dev *dev, int32_t priority, 569 uint32_t subpriority) 570 { 571 uint32_t res = 0; 572 struct mlx5_priv *priv = dev->data->dev_private; 573 574 switch (priv->config.flow_prio) { 575 case RTE_DIM(priority_map_3): 576 res = priority_map_3[priority][subpriority]; 577 break; 578 case RTE_DIM(priority_map_5): 579 res = priority_map_5[priority][subpriority]; 580 break; 581 } 582 return res; 583 } 584 585 /** 586 * Verify the @p item specifications (spec, last, mask) are compatible with the 587 * NIC capabilities. 588 * 589 * @param[in] item 590 * Item specification. 591 * @param[in] mask 592 * @p item->mask or flow default bit-masks. 593 * @param[in] nic_mask 594 * Bit-masks covering supported fields by the NIC to compare with user mask. 595 * @param[in] size 596 * Bit-masks size in bytes. 597 * @param[out] error 598 * Pointer to error structure. 599 * 600 * @return 601 * 0 on success, a negative errno value otherwise and rte_errno is set. 602 */ 603 int 604 mlx5_flow_item_acceptable(const struct rte_flow_item *item, 605 const uint8_t *mask, 606 const uint8_t *nic_mask, 607 unsigned int size, 608 struct rte_flow_error *error) 609 { 610 unsigned int i; 611 612 MLX5_ASSERT(nic_mask); 613 for (i = 0; i < size; ++i) 614 if ((nic_mask[i] | mask[i]) != nic_mask[i]) 615 return rte_flow_error_set(error, ENOTSUP, 616 RTE_FLOW_ERROR_TYPE_ITEM, 617 item, 618 "mask enables non supported" 619 " bits"); 620 if (!item->spec && (item->mask || item->last)) 621 return rte_flow_error_set(error, EINVAL, 622 RTE_FLOW_ERROR_TYPE_ITEM, item, 623 "mask/last without a spec is not" 624 " supported"); 625 if (item->spec && item->last) { 626 uint8_t spec[size]; 627 uint8_t last[size]; 628 unsigned int i; 629 int ret; 630 631 for (i = 0; i < size; ++i) { 632 spec[i] = ((const uint8_t *)item->spec)[i] & mask[i]; 633 last[i] = ((const uint8_t *)item->last)[i] & mask[i]; 634 } 635 ret = memcmp(spec, last, size); 636 if (ret != 0) 637 return rte_flow_error_set(error, EINVAL, 638 RTE_FLOW_ERROR_TYPE_ITEM, 639 item, 640 "range is not valid"); 641 } 642 return 0; 643 } 644 645 /** 646 * Adjust the hash fields according to the @p flow information. 647 * 648 * @param[in] dev_flow. 649 * Pointer to the mlx5_flow. 650 * @param[in] tunnel 651 * 1 when the hash field is for a tunnel item. 652 * @param[in] layer_types 653 * ETH_RSS_* types. 654 * @param[in] hash_fields 655 * Item hash fields. 656 * 657 * @return 658 * The hash fields that should be used. 659 */ 660 uint64_t 661 mlx5_flow_hashfields_adjust(struct mlx5_flow_rss_desc *rss_desc, 662 int tunnel __rte_unused, uint64_t layer_types, 663 uint64_t hash_fields) 664 { 665 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT 666 int rss_request_inner = rss_desc->level >= 2; 667 668 /* Check RSS hash level for tunnel. */ 669 if (tunnel && rss_request_inner) 670 hash_fields |= IBV_RX_HASH_INNER; 671 else if (tunnel || rss_request_inner) 672 return 0; 673 #endif 674 /* Check if requested layer matches RSS hash fields. */ 675 if (!(rss_desc->types & layer_types)) 676 return 0; 677 return hash_fields; 678 } 679 680 /** 681 * Lookup and set the ptype in the data Rx part. A single Ptype can be used, 682 * if several tunnel rules are used on this queue, the tunnel ptype will be 683 * cleared. 684 * 685 * @param rxq_ctrl 686 * Rx queue to update. 687 */ 688 static void 689 flow_rxq_tunnel_ptype_update(struct mlx5_rxq_ctrl *rxq_ctrl) 690 { 691 unsigned int i; 692 uint32_t tunnel_ptype = 0; 693 694 /* Look up for the ptype to use. */ 695 for (i = 0; i != MLX5_FLOW_TUNNEL; ++i) { 696 if (!rxq_ctrl->flow_tunnels_n[i]) 697 continue; 698 if (!tunnel_ptype) { 699 tunnel_ptype = tunnels_info[i].ptype; 700 } else { 701 tunnel_ptype = 0; 702 break; 703 } 704 } 705 rxq_ctrl->rxq.tunnel = tunnel_ptype; 706 } 707 708 /** 709 * Set the Rx queue flags (Mark/Flag and Tunnel Ptypes) according to the devive 710 * flow. 711 * 712 * @param[in] dev 713 * Pointer to the Ethernet device structure. 714 * @param[in] dev_handle 715 * Pointer to device flow handle structure. 716 */ 717 static void 718 flow_drv_rxq_flags_set(struct rte_eth_dev *dev, 719 struct mlx5_flow_handle *dev_handle) 720 { 721 struct mlx5_priv *priv = dev->data->dev_private; 722 const int mark = dev_handle->mark; 723 const int tunnel = !!(dev_handle->layers & MLX5_FLOW_LAYER_TUNNEL); 724 struct mlx5_hrxq *hrxq; 725 unsigned int i; 726 727 if (dev_handle->fate_action != MLX5_FLOW_FATE_QUEUE) 728 return; 729 hrxq = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_HRXQ], 730 dev_handle->rix_hrxq); 731 if (!hrxq) 732 return; 733 for (i = 0; i != hrxq->ind_table->queues_n; ++i) { 734 int idx = hrxq->ind_table->queues[i]; 735 struct mlx5_rxq_ctrl *rxq_ctrl = 736 container_of((*priv->rxqs)[idx], 737 struct mlx5_rxq_ctrl, rxq); 738 739 /* 740 * To support metadata register copy on Tx loopback, 741 * this must be always enabled (metadata may arive 742 * from other port - not from local flows only. 743 */ 744 if (priv->config.dv_flow_en && 745 priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY && 746 mlx5_flow_ext_mreg_supported(dev)) { 747 rxq_ctrl->rxq.mark = 1; 748 rxq_ctrl->flow_mark_n = 1; 749 } else if (mark) { 750 rxq_ctrl->rxq.mark = 1; 751 rxq_ctrl->flow_mark_n++; 752 } 753 if (tunnel) { 754 unsigned int j; 755 756 /* Increase the counter matching the flow. */ 757 for (j = 0; j != MLX5_FLOW_TUNNEL; ++j) { 758 if ((tunnels_info[j].tunnel & 759 dev_handle->layers) == 760 tunnels_info[j].tunnel) { 761 rxq_ctrl->flow_tunnels_n[j]++; 762 break; 763 } 764 } 765 flow_rxq_tunnel_ptype_update(rxq_ctrl); 766 } 767 } 768 } 769 770 /** 771 * Set the Rx queue flags (Mark/Flag and Tunnel Ptypes) for a flow 772 * 773 * @param[in] dev 774 * Pointer to the Ethernet device structure. 775 * @param[in] flow 776 * Pointer to flow structure. 777 */ 778 static void 779 flow_rxq_flags_set(struct rte_eth_dev *dev, struct rte_flow *flow) 780 { 781 struct mlx5_priv *priv = dev->data->dev_private; 782 uint32_t handle_idx; 783 struct mlx5_flow_handle *dev_handle; 784 785 SILIST_FOREACH(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW], flow->dev_handles, 786 handle_idx, dev_handle, next) 787 flow_drv_rxq_flags_set(dev, dev_handle); 788 } 789 790 /** 791 * Clear the Rx queue flags (Mark/Flag and Tunnel Ptype) associated with the 792 * device flow if no other flow uses it with the same kind of request. 793 * 794 * @param dev 795 * Pointer to Ethernet device. 796 * @param[in] dev_handle 797 * Pointer to the device flow handle structure. 798 */ 799 static void 800 flow_drv_rxq_flags_trim(struct rte_eth_dev *dev, 801 struct mlx5_flow_handle *dev_handle) 802 { 803 struct mlx5_priv *priv = dev->data->dev_private; 804 const int mark = dev_handle->mark; 805 const int tunnel = !!(dev_handle->layers & MLX5_FLOW_LAYER_TUNNEL); 806 struct mlx5_hrxq *hrxq; 807 unsigned int i; 808 809 if (dev_handle->fate_action != MLX5_FLOW_FATE_QUEUE) 810 return; 811 hrxq = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_HRXQ], 812 dev_handle->rix_hrxq); 813 if (!hrxq) 814 return; 815 MLX5_ASSERT(dev->data->dev_started); 816 for (i = 0; i != hrxq->ind_table->queues_n; ++i) { 817 int idx = hrxq->ind_table->queues[i]; 818 struct mlx5_rxq_ctrl *rxq_ctrl = 819 container_of((*priv->rxqs)[idx], 820 struct mlx5_rxq_ctrl, rxq); 821 822 if (priv->config.dv_flow_en && 823 priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY && 824 mlx5_flow_ext_mreg_supported(dev)) { 825 rxq_ctrl->rxq.mark = 1; 826 rxq_ctrl->flow_mark_n = 1; 827 } else if (mark) { 828 rxq_ctrl->flow_mark_n--; 829 rxq_ctrl->rxq.mark = !!rxq_ctrl->flow_mark_n; 830 } 831 if (tunnel) { 832 unsigned int j; 833 834 /* Decrease the counter matching the flow. */ 835 for (j = 0; j != MLX5_FLOW_TUNNEL; ++j) { 836 if ((tunnels_info[j].tunnel & 837 dev_handle->layers) == 838 tunnels_info[j].tunnel) { 839 rxq_ctrl->flow_tunnels_n[j]--; 840 break; 841 } 842 } 843 flow_rxq_tunnel_ptype_update(rxq_ctrl); 844 } 845 } 846 } 847 848 /** 849 * Clear the Rx queue flags (Mark/Flag and Tunnel Ptype) associated with the 850 * @p flow if no other flow uses it with the same kind of request. 851 * 852 * @param dev 853 * Pointer to Ethernet device. 854 * @param[in] flow 855 * Pointer to the flow. 856 */ 857 static void 858 flow_rxq_flags_trim(struct rte_eth_dev *dev, struct rte_flow *flow) 859 { 860 struct mlx5_priv *priv = dev->data->dev_private; 861 uint32_t handle_idx; 862 struct mlx5_flow_handle *dev_handle; 863 864 SILIST_FOREACH(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW], flow->dev_handles, 865 handle_idx, dev_handle, next) 866 flow_drv_rxq_flags_trim(dev, dev_handle); 867 } 868 869 /** 870 * Clear the Mark/Flag and Tunnel ptype information in all Rx queues. 871 * 872 * @param dev 873 * Pointer to Ethernet device. 874 */ 875 static void 876 flow_rxq_flags_clear(struct rte_eth_dev *dev) 877 { 878 struct mlx5_priv *priv = dev->data->dev_private; 879 unsigned int i; 880 881 for (i = 0; i != priv->rxqs_n; ++i) { 882 struct mlx5_rxq_ctrl *rxq_ctrl; 883 unsigned int j; 884 885 if (!(*priv->rxqs)[i]) 886 continue; 887 rxq_ctrl = container_of((*priv->rxqs)[i], 888 struct mlx5_rxq_ctrl, rxq); 889 rxq_ctrl->flow_mark_n = 0; 890 rxq_ctrl->rxq.mark = 0; 891 for (j = 0; j != MLX5_FLOW_TUNNEL; ++j) 892 rxq_ctrl->flow_tunnels_n[j] = 0; 893 rxq_ctrl->rxq.tunnel = 0; 894 } 895 } 896 897 /* 898 * return a pointer to the desired action in the list of actions. 899 * 900 * @param[in] actions 901 * The list of actions to search the action in. 902 * @param[in] action 903 * The action to find. 904 * 905 * @return 906 * Pointer to the action in the list, if found. NULL otherwise. 907 */ 908 const struct rte_flow_action * 909 mlx5_flow_find_action(const struct rte_flow_action *actions, 910 enum rte_flow_action_type action) 911 { 912 if (actions == NULL) 913 return NULL; 914 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) 915 if (actions->type == action) 916 return actions; 917 return NULL; 918 } 919 920 /* 921 * Validate the flag action. 922 * 923 * @param[in] action_flags 924 * Bit-fields that holds the actions detected until now. 925 * @param[in] attr 926 * Attributes of flow that includes this action. 927 * @param[out] error 928 * Pointer to error structure. 929 * 930 * @return 931 * 0 on success, a negative errno value otherwise and rte_errno is set. 932 */ 933 int 934 mlx5_flow_validate_action_flag(uint64_t action_flags, 935 const struct rte_flow_attr *attr, 936 struct rte_flow_error *error) 937 { 938 if (action_flags & MLX5_FLOW_ACTION_MARK) 939 return rte_flow_error_set(error, EINVAL, 940 RTE_FLOW_ERROR_TYPE_ACTION, NULL, 941 "can't mark and flag in same flow"); 942 if (action_flags & MLX5_FLOW_ACTION_FLAG) 943 return rte_flow_error_set(error, EINVAL, 944 RTE_FLOW_ERROR_TYPE_ACTION, NULL, 945 "can't have 2 flag" 946 " actions in same flow"); 947 if (attr->egress) 948 return rte_flow_error_set(error, ENOTSUP, 949 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, NULL, 950 "flag action not supported for " 951 "egress"); 952 return 0; 953 } 954 955 /* 956 * Validate the mark action. 957 * 958 * @param[in] action 959 * Pointer to the queue action. 960 * @param[in] action_flags 961 * Bit-fields that holds the actions detected until now. 962 * @param[in] attr 963 * Attributes of flow that includes this action. 964 * @param[out] error 965 * Pointer to error structure. 966 * 967 * @return 968 * 0 on success, a negative errno value otherwise and rte_errno is set. 969 */ 970 int 971 mlx5_flow_validate_action_mark(const struct rte_flow_action *action, 972 uint64_t action_flags, 973 const struct rte_flow_attr *attr, 974 struct rte_flow_error *error) 975 { 976 const struct rte_flow_action_mark *mark = action->conf; 977 978 if (!mark) 979 return rte_flow_error_set(error, EINVAL, 980 RTE_FLOW_ERROR_TYPE_ACTION, 981 action, 982 "configuration cannot be null"); 983 if (mark->id >= MLX5_FLOW_MARK_MAX) 984 return rte_flow_error_set(error, EINVAL, 985 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 986 &mark->id, 987 "mark id must in 0 <= id < " 988 RTE_STR(MLX5_FLOW_MARK_MAX)); 989 if (action_flags & MLX5_FLOW_ACTION_FLAG) 990 return rte_flow_error_set(error, EINVAL, 991 RTE_FLOW_ERROR_TYPE_ACTION, NULL, 992 "can't flag and mark in same flow"); 993 if (action_flags & MLX5_FLOW_ACTION_MARK) 994 return rte_flow_error_set(error, EINVAL, 995 RTE_FLOW_ERROR_TYPE_ACTION, NULL, 996 "can't have 2 mark actions in same" 997 " flow"); 998 if (attr->egress) 999 return rte_flow_error_set(error, ENOTSUP, 1000 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, NULL, 1001 "mark action not supported for " 1002 "egress"); 1003 return 0; 1004 } 1005 1006 /* 1007 * Validate the drop action. 1008 * 1009 * @param[in] action_flags 1010 * Bit-fields that holds the actions detected until now. 1011 * @param[in] attr 1012 * Attributes of flow that includes this action. 1013 * @param[out] error 1014 * Pointer to error structure. 1015 * 1016 * @return 1017 * 0 on success, a negative errno value otherwise and rte_errno is set. 1018 */ 1019 int 1020 mlx5_flow_validate_action_drop(uint64_t action_flags __rte_unused, 1021 const struct rte_flow_attr *attr, 1022 struct rte_flow_error *error) 1023 { 1024 if (attr->egress) 1025 return rte_flow_error_set(error, ENOTSUP, 1026 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, NULL, 1027 "drop action not supported for " 1028 "egress"); 1029 return 0; 1030 } 1031 1032 /* 1033 * Validate the queue action. 1034 * 1035 * @param[in] action 1036 * Pointer to the queue action. 1037 * @param[in] action_flags 1038 * Bit-fields that holds the actions detected until now. 1039 * @param[in] dev 1040 * Pointer to the Ethernet device structure. 1041 * @param[in] attr 1042 * Attributes of flow that includes this action. 1043 * @param[out] error 1044 * Pointer to error structure. 1045 * 1046 * @return 1047 * 0 on success, a negative errno value otherwise and rte_errno is set. 1048 */ 1049 int 1050 mlx5_flow_validate_action_queue(const struct rte_flow_action *action, 1051 uint64_t action_flags, 1052 struct rte_eth_dev *dev, 1053 const struct rte_flow_attr *attr, 1054 struct rte_flow_error *error) 1055 { 1056 struct mlx5_priv *priv = dev->data->dev_private; 1057 const struct rte_flow_action_queue *queue = action->conf; 1058 1059 if (action_flags & MLX5_FLOW_FATE_ACTIONS) 1060 return rte_flow_error_set(error, EINVAL, 1061 RTE_FLOW_ERROR_TYPE_ACTION, NULL, 1062 "can't have 2 fate actions in" 1063 " same flow"); 1064 if (!priv->rxqs_n) 1065 return rte_flow_error_set(error, EINVAL, 1066 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 1067 NULL, "No Rx queues configured"); 1068 if (queue->index >= priv->rxqs_n) 1069 return rte_flow_error_set(error, EINVAL, 1070 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 1071 &queue->index, 1072 "queue index out of range"); 1073 if (!(*priv->rxqs)[queue->index]) 1074 return rte_flow_error_set(error, EINVAL, 1075 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 1076 &queue->index, 1077 "queue is not configured"); 1078 if (attr->egress) 1079 return rte_flow_error_set(error, ENOTSUP, 1080 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, NULL, 1081 "queue action not supported for " 1082 "egress"); 1083 return 0; 1084 } 1085 1086 /* 1087 * Validate the rss action. 1088 * 1089 * @param[in] action 1090 * Pointer to the queue action. 1091 * @param[in] action_flags 1092 * Bit-fields that holds the actions detected until now. 1093 * @param[in] dev 1094 * Pointer to the Ethernet device structure. 1095 * @param[in] attr 1096 * Attributes of flow that includes this action. 1097 * @param[in] item_flags 1098 * Items that were detected. 1099 * @param[out] error 1100 * Pointer to error structure. 1101 * 1102 * @return 1103 * 0 on success, a negative errno value otherwise and rte_errno is set. 1104 */ 1105 int 1106 mlx5_flow_validate_action_rss(const struct rte_flow_action *action, 1107 uint64_t action_flags, 1108 struct rte_eth_dev *dev, 1109 const struct rte_flow_attr *attr, 1110 uint64_t item_flags, 1111 struct rte_flow_error *error) 1112 { 1113 struct mlx5_priv *priv = dev->data->dev_private; 1114 const struct rte_flow_action_rss *rss = action->conf; 1115 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL); 1116 unsigned int i; 1117 1118 if (action_flags & MLX5_FLOW_FATE_ACTIONS) 1119 return rte_flow_error_set(error, EINVAL, 1120 RTE_FLOW_ERROR_TYPE_ACTION, NULL, 1121 "can't have 2 fate actions" 1122 " in same flow"); 1123 if (rss->func != RTE_ETH_HASH_FUNCTION_DEFAULT && 1124 rss->func != RTE_ETH_HASH_FUNCTION_TOEPLITZ) 1125 return rte_flow_error_set(error, ENOTSUP, 1126 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 1127 &rss->func, 1128 "RSS hash function not supported"); 1129 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT 1130 if (rss->level > 2) 1131 #else 1132 if (rss->level > 1) 1133 #endif 1134 return rte_flow_error_set(error, ENOTSUP, 1135 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 1136 &rss->level, 1137 "tunnel RSS is not supported"); 1138 /* allow RSS key_len 0 in case of NULL (default) RSS key. */ 1139 if (rss->key_len == 0 && rss->key != NULL) 1140 return rte_flow_error_set(error, ENOTSUP, 1141 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 1142 &rss->key_len, 1143 "RSS hash key length 0"); 1144 if (rss->key_len > 0 && rss->key_len < MLX5_RSS_HASH_KEY_LEN) 1145 return rte_flow_error_set(error, ENOTSUP, 1146 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 1147 &rss->key_len, 1148 "RSS hash key too small"); 1149 if (rss->key_len > MLX5_RSS_HASH_KEY_LEN) 1150 return rte_flow_error_set(error, ENOTSUP, 1151 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 1152 &rss->key_len, 1153 "RSS hash key too large"); 1154 if (rss->queue_num > priv->config.ind_table_max_size) 1155 return rte_flow_error_set(error, ENOTSUP, 1156 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 1157 &rss->queue_num, 1158 "number of queues too large"); 1159 if (rss->types & MLX5_RSS_HF_MASK) 1160 return rte_flow_error_set(error, ENOTSUP, 1161 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 1162 &rss->types, 1163 "some RSS protocols are not" 1164 " supported"); 1165 if ((rss->types & (ETH_RSS_L3_SRC_ONLY | ETH_RSS_L3_DST_ONLY)) && 1166 !(rss->types & ETH_RSS_IP)) 1167 return rte_flow_error_set(error, EINVAL, 1168 RTE_FLOW_ERROR_TYPE_ACTION_CONF, NULL, 1169 "L3 partial RSS requested but L3 RSS" 1170 " type not specified"); 1171 if ((rss->types & (ETH_RSS_L4_SRC_ONLY | ETH_RSS_L4_DST_ONLY)) && 1172 !(rss->types & (ETH_RSS_UDP | ETH_RSS_TCP))) 1173 return rte_flow_error_set(error, EINVAL, 1174 RTE_FLOW_ERROR_TYPE_ACTION_CONF, NULL, 1175 "L4 partial RSS requested but L4 RSS" 1176 " type not specified"); 1177 if (!priv->rxqs_n) 1178 return rte_flow_error_set(error, EINVAL, 1179 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 1180 NULL, "No Rx queues configured"); 1181 if (!rss->queue_num) 1182 return rte_flow_error_set(error, EINVAL, 1183 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 1184 NULL, "No queues configured"); 1185 for (i = 0; i != rss->queue_num; ++i) { 1186 if (rss->queue[i] >= priv->rxqs_n) 1187 return rte_flow_error_set 1188 (error, EINVAL, 1189 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 1190 &rss->queue[i], "queue index out of range"); 1191 if (!(*priv->rxqs)[rss->queue[i]]) 1192 return rte_flow_error_set 1193 (error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION_CONF, 1194 &rss->queue[i], "queue is not configured"); 1195 } 1196 if (attr->egress) 1197 return rte_flow_error_set(error, ENOTSUP, 1198 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, NULL, 1199 "rss action not supported for " 1200 "egress"); 1201 if (rss->level > 1 && !tunnel) 1202 return rte_flow_error_set(error, EINVAL, 1203 RTE_FLOW_ERROR_TYPE_ACTION_CONF, NULL, 1204 "inner RSS is not supported for " 1205 "non-tunnel flows"); 1206 return 0; 1207 } 1208 1209 /* 1210 * Validate the count action. 1211 * 1212 * @param[in] dev 1213 * Pointer to the Ethernet device structure. 1214 * @param[in] attr 1215 * Attributes of flow that includes this action. 1216 * @param[out] error 1217 * Pointer to error structure. 1218 * 1219 * @return 1220 * 0 on success, a negative errno value otherwise and rte_errno is set. 1221 */ 1222 int 1223 mlx5_flow_validate_action_count(struct rte_eth_dev *dev __rte_unused, 1224 const struct rte_flow_attr *attr, 1225 struct rte_flow_error *error) 1226 { 1227 if (attr->egress) 1228 return rte_flow_error_set(error, ENOTSUP, 1229 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, NULL, 1230 "count action not supported for " 1231 "egress"); 1232 return 0; 1233 } 1234 1235 /** 1236 * Verify the @p attributes will be correctly understood by the NIC and store 1237 * them in the @p flow if everything is correct. 1238 * 1239 * @param[in] dev 1240 * Pointer to the Ethernet device structure. 1241 * @param[in] attributes 1242 * Pointer to flow attributes 1243 * @param[out] error 1244 * Pointer to error structure. 1245 * 1246 * @return 1247 * 0 on success, a negative errno value otherwise and rte_errno is set. 1248 */ 1249 int 1250 mlx5_flow_validate_attributes(struct rte_eth_dev *dev, 1251 const struct rte_flow_attr *attributes, 1252 struct rte_flow_error *error) 1253 { 1254 struct mlx5_priv *priv = dev->data->dev_private; 1255 uint32_t priority_max = priv->config.flow_prio - 1; 1256 1257 if (attributes->group) 1258 return rte_flow_error_set(error, ENOTSUP, 1259 RTE_FLOW_ERROR_TYPE_ATTR_GROUP, 1260 NULL, "groups is not supported"); 1261 if (attributes->priority != MLX5_FLOW_PRIO_RSVD && 1262 attributes->priority >= priority_max) 1263 return rte_flow_error_set(error, ENOTSUP, 1264 RTE_FLOW_ERROR_TYPE_ATTR_PRIORITY, 1265 NULL, "priority out of range"); 1266 if (attributes->egress) 1267 return rte_flow_error_set(error, ENOTSUP, 1268 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, NULL, 1269 "egress is not supported"); 1270 if (attributes->transfer && !priv->config.dv_esw_en) 1271 return rte_flow_error_set(error, ENOTSUP, 1272 RTE_FLOW_ERROR_TYPE_ATTR_TRANSFER, 1273 NULL, "transfer is not supported"); 1274 if (!attributes->ingress) 1275 return rte_flow_error_set(error, EINVAL, 1276 RTE_FLOW_ERROR_TYPE_ATTR_INGRESS, 1277 NULL, 1278 "ingress attribute is mandatory"); 1279 return 0; 1280 } 1281 1282 /** 1283 * Validate ICMP6 item. 1284 * 1285 * @param[in] item 1286 * Item specification. 1287 * @param[in] item_flags 1288 * Bit-fields that holds the items detected until now. 1289 * @param[out] error 1290 * Pointer to error structure. 1291 * 1292 * @return 1293 * 0 on success, a negative errno value otherwise and rte_errno is set. 1294 */ 1295 int 1296 mlx5_flow_validate_item_icmp6(const struct rte_flow_item *item, 1297 uint64_t item_flags, 1298 uint8_t target_protocol, 1299 struct rte_flow_error *error) 1300 { 1301 const struct rte_flow_item_icmp6 *mask = item->mask; 1302 const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL); 1303 const uint64_t l3m = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 : 1304 MLX5_FLOW_LAYER_OUTER_L3_IPV6; 1305 const uint64_t l4m = tunnel ? MLX5_FLOW_LAYER_INNER_L4 : 1306 MLX5_FLOW_LAYER_OUTER_L4; 1307 int ret; 1308 1309 if (target_protocol != 0xFF && target_protocol != IPPROTO_ICMPV6) 1310 return rte_flow_error_set(error, EINVAL, 1311 RTE_FLOW_ERROR_TYPE_ITEM, item, 1312 "protocol filtering not compatible" 1313 " with ICMP6 layer"); 1314 if (!(item_flags & l3m)) 1315 return rte_flow_error_set(error, EINVAL, 1316 RTE_FLOW_ERROR_TYPE_ITEM, item, 1317 "IPv6 is mandatory to filter on" 1318 " ICMP6"); 1319 if (item_flags & l4m) 1320 return rte_flow_error_set(error, EINVAL, 1321 RTE_FLOW_ERROR_TYPE_ITEM, item, 1322 "multiple L4 layers not supported"); 1323 if (!mask) 1324 mask = &rte_flow_item_icmp6_mask; 1325 ret = mlx5_flow_item_acceptable 1326 (item, (const uint8_t *)mask, 1327 (const uint8_t *)&rte_flow_item_icmp6_mask, 1328 sizeof(struct rte_flow_item_icmp6), error); 1329 if (ret < 0) 1330 return ret; 1331 return 0; 1332 } 1333 1334 /** 1335 * Validate ICMP item. 1336 * 1337 * @param[in] item 1338 * Item specification. 1339 * @param[in] item_flags 1340 * Bit-fields that holds the items detected until now. 1341 * @param[out] error 1342 * Pointer to error structure. 1343 * 1344 * @return 1345 * 0 on success, a negative errno value otherwise and rte_errno is set. 1346 */ 1347 int 1348 mlx5_flow_validate_item_icmp(const struct rte_flow_item *item, 1349 uint64_t item_flags, 1350 uint8_t target_protocol, 1351 struct rte_flow_error *error) 1352 { 1353 const struct rte_flow_item_icmp *mask = item->mask; 1354 const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL); 1355 const uint64_t l3m = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 : 1356 MLX5_FLOW_LAYER_OUTER_L3_IPV4; 1357 const uint64_t l4m = tunnel ? MLX5_FLOW_LAYER_INNER_L4 : 1358 MLX5_FLOW_LAYER_OUTER_L4; 1359 int ret; 1360 1361 if (target_protocol != 0xFF && target_protocol != IPPROTO_ICMP) 1362 return rte_flow_error_set(error, EINVAL, 1363 RTE_FLOW_ERROR_TYPE_ITEM, item, 1364 "protocol filtering not compatible" 1365 " with ICMP layer"); 1366 if (!(item_flags & l3m)) 1367 return rte_flow_error_set(error, EINVAL, 1368 RTE_FLOW_ERROR_TYPE_ITEM, item, 1369 "IPv4 is mandatory to filter" 1370 " on ICMP"); 1371 if (item_flags & l4m) 1372 return rte_flow_error_set(error, EINVAL, 1373 RTE_FLOW_ERROR_TYPE_ITEM, item, 1374 "multiple L4 layers not supported"); 1375 if (!mask) 1376 mask = &rte_flow_item_icmp_mask; 1377 ret = mlx5_flow_item_acceptable 1378 (item, (const uint8_t *)mask, 1379 (const uint8_t *)&rte_flow_item_icmp_mask, 1380 sizeof(struct rte_flow_item_icmp), error); 1381 if (ret < 0) 1382 return ret; 1383 return 0; 1384 } 1385 1386 /** 1387 * Validate Ethernet item. 1388 * 1389 * @param[in] item 1390 * Item specification. 1391 * @param[in] item_flags 1392 * Bit-fields that holds the items detected until now. 1393 * @param[out] error 1394 * Pointer to error structure. 1395 * 1396 * @return 1397 * 0 on success, a negative errno value otherwise and rte_errno is set. 1398 */ 1399 int 1400 mlx5_flow_validate_item_eth(const struct rte_flow_item *item, 1401 uint64_t item_flags, 1402 struct rte_flow_error *error) 1403 { 1404 const struct rte_flow_item_eth *mask = item->mask; 1405 const struct rte_flow_item_eth nic_mask = { 1406 .dst.addr_bytes = "\xff\xff\xff\xff\xff\xff", 1407 .src.addr_bytes = "\xff\xff\xff\xff\xff\xff", 1408 .type = RTE_BE16(0xffff), 1409 }; 1410 int ret; 1411 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL); 1412 const uint64_t ethm = tunnel ? MLX5_FLOW_LAYER_INNER_L2 : 1413 MLX5_FLOW_LAYER_OUTER_L2; 1414 1415 if (item_flags & ethm) 1416 return rte_flow_error_set(error, ENOTSUP, 1417 RTE_FLOW_ERROR_TYPE_ITEM, item, 1418 "multiple L2 layers not supported"); 1419 if ((!tunnel && (item_flags & MLX5_FLOW_LAYER_OUTER_L3)) || 1420 (tunnel && (item_flags & MLX5_FLOW_LAYER_INNER_L3))) 1421 return rte_flow_error_set(error, EINVAL, 1422 RTE_FLOW_ERROR_TYPE_ITEM, item, 1423 "L2 layer should not follow " 1424 "L3 layers"); 1425 if ((!tunnel && (item_flags & MLX5_FLOW_LAYER_OUTER_VLAN)) || 1426 (tunnel && (item_flags & MLX5_FLOW_LAYER_INNER_VLAN))) 1427 return rte_flow_error_set(error, EINVAL, 1428 RTE_FLOW_ERROR_TYPE_ITEM, item, 1429 "L2 layer should not follow VLAN"); 1430 if (!mask) 1431 mask = &rte_flow_item_eth_mask; 1432 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask, 1433 (const uint8_t *)&nic_mask, 1434 sizeof(struct rte_flow_item_eth), 1435 error); 1436 return ret; 1437 } 1438 1439 /** 1440 * Validate VLAN item. 1441 * 1442 * @param[in] item 1443 * Item specification. 1444 * @param[in] item_flags 1445 * Bit-fields that holds the items detected until now. 1446 * @param[in] dev 1447 * Ethernet device flow is being created on. 1448 * @param[out] error 1449 * Pointer to error structure. 1450 * 1451 * @return 1452 * 0 on success, a negative errno value otherwise and rte_errno is set. 1453 */ 1454 int 1455 mlx5_flow_validate_item_vlan(const struct rte_flow_item *item, 1456 uint64_t item_flags, 1457 struct rte_eth_dev *dev, 1458 struct rte_flow_error *error) 1459 { 1460 const struct rte_flow_item_vlan *spec = item->spec; 1461 const struct rte_flow_item_vlan *mask = item->mask; 1462 const struct rte_flow_item_vlan nic_mask = { 1463 .tci = RTE_BE16(UINT16_MAX), 1464 .inner_type = RTE_BE16(UINT16_MAX), 1465 }; 1466 uint16_t vlan_tag = 0; 1467 const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL); 1468 int ret; 1469 const uint64_t l34m = tunnel ? (MLX5_FLOW_LAYER_INNER_L3 | 1470 MLX5_FLOW_LAYER_INNER_L4) : 1471 (MLX5_FLOW_LAYER_OUTER_L3 | 1472 MLX5_FLOW_LAYER_OUTER_L4); 1473 const uint64_t vlanm = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN : 1474 MLX5_FLOW_LAYER_OUTER_VLAN; 1475 1476 if (item_flags & vlanm) 1477 return rte_flow_error_set(error, EINVAL, 1478 RTE_FLOW_ERROR_TYPE_ITEM, item, 1479 "multiple VLAN layers not supported"); 1480 else if ((item_flags & l34m) != 0) 1481 return rte_flow_error_set(error, EINVAL, 1482 RTE_FLOW_ERROR_TYPE_ITEM, item, 1483 "VLAN cannot follow L3/L4 layer"); 1484 if (!mask) 1485 mask = &rte_flow_item_vlan_mask; 1486 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask, 1487 (const uint8_t *)&nic_mask, 1488 sizeof(struct rte_flow_item_vlan), 1489 error); 1490 if (ret) 1491 return ret; 1492 if (!tunnel && mask->tci != RTE_BE16(0x0fff)) { 1493 struct mlx5_priv *priv = dev->data->dev_private; 1494 1495 if (priv->vmwa_context) { 1496 /* 1497 * Non-NULL context means we have a virtual machine 1498 * and SR-IOV enabled, we have to create VLAN interface 1499 * to make hypervisor to setup E-Switch vport 1500 * context correctly. We avoid creating the multiple 1501 * VLAN interfaces, so we cannot support VLAN tag mask. 1502 */ 1503 return rte_flow_error_set(error, EINVAL, 1504 RTE_FLOW_ERROR_TYPE_ITEM, 1505 item, 1506 "VLAN tag mask is not" 1507 " supported in virtual" 1508 " environment"); 1509 } 1510 } 1511 if (spec) { 1512 vlan_tag = spec->tci; 1513 vlan_tag &= mask->tci; 1514 } 1515 /* 1516 * From verbs perspective an empty VLAN is equivalent 1517 * to a packet without VLAN layer. 1518 */ 1519 if (!vlan_tag) 1520 return rte_flow_error_set(error, EINVAL, 1521 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, 1522 item->spec, 1523 "VLAN cannot be empty"); 1524 return 0; 1525 } 1526 1527 /** 1528 * Validate IPV4 item. 1529 * 1530 * @param[in] item 1531 * Item specification. 1532 * @param[in] item_flags 1533 * Bit-fields that holds the items detected until now. 1534 * @param[in] acc_mask 1535 * Acceptable mask, if NULL default internal default mask 1536 * will be used to check whether item fields are supported. 1537 * @param[out] error 1538 * Pointer to error structure. 1539 * 1540 * @return 1541 * 0 on success, a negative errno value otherwise and rte_errno is set. 1542 */ 1543 int 1544 mlx5_flow_validate_item_ipv4(const struct rte_flow_item *item, 1545 uint64_t item_flags, 1546 uint64_t last_item, 1547 uint16_t ether_type, 1548 const struct rte_flow_item_ipv4 *acc_mask, 1549 struct rte_flow_error *error) 1550 { 1551 const struct rte_flow_item_ipv4 *mask = item->mask; 1552 const struct rte_flow_item_ipv4 *spec = item->spec; 1553 const struct rte_flow_item_ipv4 nic_mask = { 1554 .hdr = { 1555 .src_addr = RTE_BE32(0xffffffff), 1556 .dst_addr = RTE_BE32(0xffffffff), 1557 .type_of_service = 0xff, 1558 .next_proto_id = 0xff, 1559 }, 1560 }; 1561 const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL); 1562 const uint64_t l3m = tunnel ? MLX5_FLOW_LAYER_INNER_L3 : 1563 MLX5_FLOW_LAYER_OUTER_L3; 1564 const uint64_t l4m = tunnel ? MLX5_FLOW_LAYER_INNER_L4 : 1565 MLX5_FLOW_LAYER_OUTER_L4; 1566 int ret; 1567 uint8_t next_proto = 0xFF; 1568 const uint64_t l2_vlan = (MLX5_FLOW_LAYER_L2 | 1569 MLX5_FLOW_LAYER_OUTER_VLAN | 1570 MLX5_FLOW_LAYER_INNER_VLAN); 1571 1572 if ((last_item & l2_vlan) && ether_type && 1573 ether_type != RTE_ETHER_TYPE_IPV4) 1574 return rte_flow_error_set(error, EINVAL, 1575 RTE_FLOW_ERROR_TYPE_ITEM, item, 1576 "IPv4 cannot follow L2/VLAN layer " 1577 "which ether type is not IPv4"); 1578 if (item_flags & MLX5_FLOW_LAYER_IPIP) { 1579 if (mask && spec) 1580 next_proto = mask->hdr.next_proto_id & 1581 spec->hdr.next_proto_id; 1582 if (next_proto == IPPROTO_IPIP || next_proto == IPPROTO_IPV6) 1583 return rte_flow_error_set(error, EINVAL, 1584 RTE_FLOW_ERROR_TYPE_ITEM, 1585 item, 1586 "multiple tunnel " 1587 "not supported"); 1588 } 1589 if (item_flags & MLX5_FLOW_LAYER_IPV6_ENCAP) 1590 return rte_flow_error_set(error, EINVAL, 1591 RTE_FLOW_ERROR_TYPE_ITEM, item, 1592 "wrong tunnel type - IPv6 specified " 1593 "but IPv4 item provided"); 1594 if (item_flags & l3m) 1595 return rte_flow_error_set(error, ENOTSUP, 1596 RTE_FLOW_ERROR_TYPE_ITEM, item, 1597 "multiple L3 layers not supported"); 1598 else if (item_flags & l4m) 1599 return rte_flow_error_set(error, EINVAL, 1600 RTE_FLOW_ERROR_TYPE_ITEM, item, 1601 "L3 cannot follow an L4 layer."); 1602 else if ((item_flags & MLX5_FLOW_LAYER_NVGRE) && 1603 !(item_flags & MLX5_FLOW_LAYER_INNER_L2)) 1604 return rte_flow_error_set(error, EINVAL, 1605 RTE_FLOW_ERROR_TYPE_ITEM, item, 1606 "L3 cannot follow an NVGRE layer."); 1607 if (!mask) 1608 mask = &rte_flow_item_ipv4_mask; 1609 else if (mask->hdr.next_proto_id != 0 && 1610 mask->hdr.next_proto_id != 0xff) 1611 return rte_flow_error_set(error, EINVAL, 1612 RTE_FLOW_ERROR_TYPE_ITEM_MASK, mask, 1613 "partial mask is not supported" 1614 " for protocol"); 1615 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask, 1616 acc_mask ? (const uint8_t *)acc_mask 1617 : (const uint8_t *)&nic_mask, 1618 sizeof(struct rte_flow_item_ipv4), 1619 error); 1620 if (ret < 0) 1621 return ret; 1622 return 0; 1623 } 1624 1625 /** 1626 * Validate IPV6 item. 1627 * 1628 * @param[in] item 1629 * Item specification. 1630 * @param[in] item_flags 1631 * Bit-fields that holds the items detected until now. 1632 * @param[in] acc_mask 1633 * Acceptable mask, if NULL default internal default mask 1634 * will be used to check whether item fields are supported. 1635 * @param[out] error 1636 * Pointer to error structure. 1637 * 1638 * @return 1639 * 0 on success, a negative errno value otherwise and rte_errno is set. 1640 */ 1641 int 1642 mlx5_flow_validate_item_ipv6(const struct rte_flow_item *item, 1643 uint64_t item_flags, 1644 uint64_t last_item, 1645 uint16_t ether_type, 1646 const struct rte_flow_item_ipv6 *acc_mask, 1647 struct rte_flow_error *error) 1648 { 1649 const struct rte_flow_item_ipv6 *mask = item->mask; 1650 const struct rte_flow_item_ipv6 *spec = item->spec; 1651 const struct rte_flow_item_ipv6 nic_mask = { 1652 .hdr = { 1653 .src_addr = 1654 "\xff\xff\xff\xff\xff\xff\xff\xff" 1655 "\xff\xff\xff\xff\xff\xff\xff\xff", 1656 .dst_addr = 1657 "\xff\xff\xff\xff\xff\xff\xff\xff" 1658 "\xff\xff\xff\xff\xff\xff\xff\xff", 1659 .vtc_flow = RTE_BE32(0xffffffff), 1660 .proto = 0xff, 1661 }, 1662 }; 1663 const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL); 1664 const uint64_t l3m = tunnel ? MLX5_FLOW_LAYER_INNER_L3 : 1665 MLX5_FLOW_LAYER_OUTER_L3; 1666 const uint64_t l4m = tunnel ? MLX5_FLOW_LAYER_INNER_L4 : 1667 MLX5_FLOW_LAYER_OUTER_L4; 1668 int ret; 1669 uint8_t next_proto = 0xFF; 1670 const uint64_t l2_vlan = (MLX5_FLOW_LAYER_L2 | 1671 MLX5_FLOW_LAYER_OUTER_VLAN | 1672 MLX5_FLOW_LAYER_INNER_VLAN); 1673 1674 if ((last_item & l2_vlan) && ether_type && 1675 ether_type != RTE_ETHER_TYPE_IPV6) 1676 return rte_flow_error_set(error, EINVAL, 1677 RTE_FLOW_ERROR_TYPE_ITEM, item, 1678 "IPv6 cannot follow L2/VLAN layer " 1679 "which ether type is not IPv6"); 1680 if (item_flags & MLX5_FLOW_LAYER_IPV6_ENCAP) { 1681 if (mask && spec) 1682 next_proto = mask->hdr.proto & spec->hdr.proto; 1683 if (next_proto == IPPROTO_IPIP || next_proto == IPPROTO_IPV6) 1684 return rte_flow_error_set(error, EINVAL, 1685 RTE_FLOW_ERROR_TYPE_ITEM, 1686 item, 1687 "multiple tunnel " 1688 "not supported"); 1689 } 1690 if (item_flags & MLX5_FLOW_LAYER_IPIP) 1691 return rte_flow_error_set(error, EINVAL, 1692 RTE_FLOW_ERROR_TYPE_ITEM, item, 1693 "wrong tunnel type - IPv4 specified " 1694 "but IPv6 item provided"); 1695 if (item_flags & l3m) 1696 return rte_flow_error_set(error, ENOTSUP, 1697 RTE_FLOW_ERROR_TYPE_ITEM, item, 1698 "multiple L3 layers not supported"); 1699 else if (item_flags & l4m) 1700 return rte_flow_error_set(error, EINVAL, 1701 RTE_FLOW_ERROR_TYPE_ITEM, item, 1702 "L3 cannot follow an L4 layer."); 1703 else if ((item_flags & MLX5_FLOW_LAYER_NVGRE) && 1704 !(item_flags & MLX5_FLOW_LAYER_INNER_L2)) 1705 return rte_flow_error_set(error, EINVAL, 1706 RTE_FLOW_ERROR_TYPE_ITEM, item, 1707 "L3 cannot follow an NVGRE layer."); 1708 if (!mask) 1709 mask = &rte_flow_item_ipv6_mask; 1710 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask, 1711 acc_mask ? (const uint8_t *)acc_mask 1712 : (const uint8_t *)&nic_mask, 1713 sizeof(struct rte_flow_item_ipv6), 1714 error); 1715 if (ret < 0) 1716 return ret; 1717 return 0; 1718 } 1719 1720 /** 1721 * Validate UDP item. 1722 * 1723 * @param[in] item 1724 * Item specification. 1725 * @param[in] item_flags 1726 * Bit-fields that holds the items detected until now. 1727 * @param[in] target_protocol 1728 * The next protocol in the previous item. 1729 * @param[in] flow_mask 1730 * mlx5 flow-specific (DV, verbs, etc.) supported header fields mask. 1731 * @param[out] error 1732 * Pointer to error structure. 1733 * 1734 * @return 1735 * 0 on success, a negative errno value otherwise and rte_errno is set. 1736 */ 1737 int 1738 mlx5_flow_validate_item_udp(const struct rte_flow_item *item, 1739 uint64_t item_flags, 1740 uint8_t target_protocol, 1741 struct rte_flow_error *error) 1742 { 1743 const struct rte_flow_item_udp *mask = item->mask; 1744 const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL); 1745 const uint64_t l3m = tunnel ? MLX5_FLOW_LAYER_INNER_L3 : 1746 MLX5_FLOW_LAYER_OUTER_L3; 1747 const uint64_t l4m = tunnel ? MLX5_FLOW_LAYER_INNER_L4 : 1748 MLX5_FLOW_LAYER_OUTER_L4; 1749 int ret; 1750 1751 if (target_protocol != 0xff && target_protocol != IPPROTO_UDP) 1752 return rte_flow_error_set(error, EINVAL, 1753 RTE_FLOW_ERROR_TYPE_ITEM, item, 1754 "protocol filtering not compatible" 1755 " with UDP layer"); 1756 if (!(item_flags & l3m)) 1757 return rte_flow_error_set(error, EINVAL, 1758 RTE_FLOW_ERROR_TYPE_ITEM, item, 1759 "L3 is mandatory to filter on L4"); 1760 if (item_flags & l4m) 1761 return rte_flow_error_set(error, EINVAL, 1762 RTE_FLOW_ERROR_TYPE_ITEM, item, 1763 "multiple L4 layers not supported"); 1764 if (!mask) 1765 mask = &rte_flow_item_udp_mask; 1766 ret = mlx5_flow_item_acceptable 1767 (item, (const uint8_t *)mask, 1768 (const uint8_t *)&rte_flow_item_udp_mask, 1769 sizeof(struct rte_flow_item_udp), error); 1770 if (ret < 0) 1771 return ret; 1772 return 0; 1773 } 1774 1775 /** 1776 * Validate TCP item. 1777 * 1778 * @param[in] item 1779 * Item specification. 1780 * @param[in] item_flags 1781 * Bit-fields that holds the items detected until now. 1782 * @param[in] target_protocol 1783 * The next protocol in the previous item. 1784 * @param[out] error 1785 * Pointer to error structure. 1786 * 1787 * @return 1788 * 0 on success, a negative errno value otherwise and rte_errno is set. 1789 */ 1790 int 1791 mlx5_flow_validate_item_tcp(const struct rte_flow_item *item, 1792 uint64_t item_flags, 1793 uint8_t target_protocol, 1794 const struct rte_flow_item_tcp *flow_mask, 1795 struct rte_flow_error *error) 1796 { 1797 const struct rte_flow_item_tcp *mask = item->mask; 1798 const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL); 1799 const uint64_t l3m = tunnel ? MLX5_FLOW_LAYER_INNER_L3 : 1800 MLX5_FLOW_LAYER_OUTER_L3; 1801 const uint64_t l4m = tunnel ? MLX5_FLOW_LAYER_INNER_L4 : 1802 MLX5_FLOW_LAYER_OUTER_L4; 1803 int ret; 1804 1805 MLX5_ASSERT(flow_mask); 1806 if (target_protocol != 0xff && target_protocol != IPPROTO_TCP) 1807 return rte_flow_error_set(error, EINVAL, 1808 RTE_FLOW_ERROR_TYPE_ITEM, item, 1809 "protocol filtering not compatible" 1810 " with TCP layer"); 1811 if (!(item_flags & l3m)) 1812 return rte_flow_error_set(error, EINVAL, 1813 RTE_FLOW_ERROR_TYPE_ITEM, item, 1814 "L3 is mandatory to filter on L4"); 1815 if (item_flags & l4m) 1816 return rte_flow_error_set(error, EINVAL, 1817 RTE_FLOW_ERROR_TYPE_ITEM, item, 1818 "multiple L4 layers not supported"); 1819 if (!mask) 1820 mask = &rte_flow_item_tcp_mask; 1821 ret = mlx5_flow_item_acceptable 1822 (item, (const uint8_t *)mask, 1823 (const uint8_t *)flow_mask, 1824 sizeof(struct rte_flow_item_tcp), error); 1825 if (ret < 0) 1826 return ret; 1827 return 0; 1828 } 1829 1830 /** 1831 * Validate VXLAN item. 1832 * 1833 * @param[in] item 1834 * Item specification. 1835 * @param[in] item_flags 1836 * Bit-fields that holds the items detected until now. 1837 * @param[in] target_protocol 1838 * The next protocol in the previous item. 1839 * @param[out] error 1840 * Pointer to error structure. 1841 * 1842 * @return 1843 * 0 on success, a negative errno value otherwise and rte_errno is set. 1844 */ 1845 int 1846 mlx5_flow_validate_item_vxlan(const struct rte_flow_item *item, 1847 uint64_t item_flags, 1848 struct rte_flow_error *error) 1849 { 1850 const struct rte_flow_item_vxlan *spec = item->spec; 1851 const struct rte_flow_item_vxlan *mask = item->mask; 1852 int ret; 1853 union vni { 1854 uint32_t vlan_id; 1855 uint8_t vni[4]; 1856 } id = { .vlan_id = 0, }; 1857 1858 1859 if (item_flags & MLX5_FLOW_LAYER_TUNNEL) 1860 return rte_flow_error_set(error, ENOTSUP, 1861 RTE_FLOW_ERROR_TYPE_ITEM, item, 1862 "multiple tunnel layers not" 1863 " supported"); 1864 /* 1865 * Verify only UDPv4 is present as defined in 1866 * https://tools.ietf.org/html/rfc7348 1867 */ 1868 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_UDP)) 1869 return rte_flow_error_set(error, EINVAL, 1870 RTE_FLOW_ERROR_TYPE_ITEM, item, 1871 "no outer UDP layer found"); 1872 if (!mask) 1873 mask = &rte_flow_item_vxlan_mask; 1874 ret = mlx5_flow_item_acceptable 1875 (item, (const uint8_t *)mask, 1876 (const uint8_t *)&rte_flow_item_vxlan_mask, 1877 sizeof(struct rte_flow_item_vxlan), 1878 error); 1879 if (ret < 0) 1880 return ret; 1881 if (spec) { 1882 memcpy(&id.vni[1], spec->vni, 3); 1883 memcpy(&id.vni[1], mask->vni, 3); 1884 } 1885 if (!(item_flags & MLX5_FLOW_LAYER_OUTER)) 1886 return rte_flow_error_set(error, ENOTSUP, 1887 RTE_FLOW_ERROR_TYPE_ITEM, item, 1888 "VXLAN tunnel must be fully defined"); 1889 return 0; 1890 } 1891 1892 /** 1893 * Validate VXLAN_GPE item. 1894 * 1895 * @param[in] item 1896 * Item specification. 1897 * @param[in] item_flags 1898 * Bit-fields that holds the items detected until now. 1899 * @param[in] priv 1900 * Pointer to the private data structure. 1901 * @param[in] target_protocol 1902 * The next protocol in the previous item. 1903 * @param[out] error 1904 * Pointer to error structure. 1905 * 1906 * @return 1907 * 0 on success, a negative errno value otherwise and rte_errno is set. 1908 */ 1909 int 1910 mlx5_flow_validate_item_vxlan_gpe(const struct rte_flow_item *item, 1911 uint64_t item_flags, 1912 struct rte_eth_dev *dev, 1913 struct rte_flow_error *error) 1914 { 1915 struct mlx5_priv *priv = dev->data->dev_private; 1916 const struct rte_flow_item_vxlan_gpe *spec = item->spec; 1917 const struct rte_flow_item_vxlan_gpe *mask = item->mask; 1918 int ret; 1919 union vni { 1920 uint32_t vlan_id; 1921 uint8_t vni[4]; 1922 } id = { .vlan_id = 0, }; 1923 1924 if (!priv->config.l3_vxlan_en) 1925 return rte_flow_error_set(error, ENOTSUP, 1926 RTE_FLOW_ERROR_TYPE_ITEM, item, 1927 "L3 VXLAN is not enabled by device" 1928 " parameter and/or not configured in" 1929 " firmware"); 1930 if (item_flags & MLX5_FLOW_LAYER_TUNNEL) 1931 return rte_flow_error_set(error, ENOTSUP, 1932 RTE_FLOW_ERROR_TYPE_ITEM, item, 1933 "multiple tunnel layers not" 1934 " supported"); 1935 /* 1936 * Verify only UDPv4 is present as defined in 1937 * https://tools.ietf.org/html/rfc7348 1938 */ 1939 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_UDP)) 1940 return rte_flow_error_set(error, EINVAL, 1941 RTE_FLOW_ERROR_TYPE_ITEM, item, 1942 "no outer UDP layer found"); 1943 if (!mask) 1944 mask = &rte_flow_item_vxlan_gpe_mask; 1945 ret = mlx5_flow_item_acceptable 1946 (item, (const uint8_t *)mask, 1947 (const uint8_t *)&rte_flow_item_vxlan_gpe_mask, 1948 sizeof(struct rte_flow_item_vxlan_gpe), 1949 error); 1950 if (ret < 0) 1951 return ret; 1952 if (spec) { 1953 if (spec->protocol) 1954 return rte_flow_error_set(error, ENOTSUP, 1955 RTE_FLOW_ERROR_TYPE_ITEM, 1956 item, 1957 "VxLAN-GPE protocol" 1958 " not supported"); 1959 memcpy(&id.vni[1], spec->vni, 3); 1960 memcpy(&id.vni[1], mask->vni, 3); 1961 } 1962 if (!(item_flags & MLX5_FLOW_LAYER_OUTER)) 1963 return rte_flow_error_set(error, ENOTSUP, 1964 RTE_FLOW_ERROR_TYPE_ITEM, item, 1965 "VXLAN-GPE tunnel must be fully" 1966 " defined"); 1967 return 0; 1968 } 1969 /** 1970 * Validate GRE Key item. 1971 * 1972 * @param[in] item 1973 * Item specification. 1974 * @param[in] item_flags 1975 * Bit flags to mark detected items. 1976 * @param[in] gre_item 1977 * Pointer to gre_item 1978 * @param[out] error 1979 * Pointer to error structure. 1980 * 1981 * @return 1982 * 0 on success, a negative errno value otherwise and rte_errno is set. 1983 */ 1984 int 1985 mlx5_flow_validate_item_gre_key(const struct rte_flow_item *item, 1986 uint64_t item_flags, 1987 const struct rte_flow_item *gre_item, 1988 struct rte_flow_error *error) 1989 { 1990 const rte_be32_t *mask = item->mask; 1991 int ret = 0; 1992 rte_be32_t gre_key_default_mask = RTE_BE32(UINT32_MAX); 1993 const struct rte_flow_item_gre *gre_spec; 1994 const struct rte_flow_item_gre *gre_mask; 1995 1996 if (item_flags & MLX5_FLOW_LAYER_GRE_KEY) 1997 return rte_flow_error_set(error, ENOTSUP, 1998 RTE_FLOW_ERROR_TYPE_ITEM, item, 1999 "Multiple GRE key not support"); 2000 if (!(item_flags & MLX5_FLOW_LAYER_GRE)) 2001 return rte_flow_error_set(error, ENOTSUP, 2002 RTE_FLOW_ERROR_TYPE_ITEM, item, 2003 "No preceding GRE header"); 2004 if (item_flags & MLX5_FLOW_LAYER_INNER) 2005 return rte_flow_error_set(error, ENOTSUP, 2006 RTE_FLOW_ERROR_TYPE_ITEM, item, 2007 "GRE key following a wrong item"); 2008 gre_mask = gre_item->mask; 2009 if (!gre_mask) 2010 gre_mask = &rte_flow_item_gre_mask; 2011 gre_spec = gre_item->spec; 2012 if (gre_spec && (gre_mask->c_rsvd0_ver & RTE_BE16(0x2000)) && 2013 !(gre_spec->c_rsvd0_ver & RTE_BE16(0x2000))) 2014 return rte_flow_error_set(error, EINVAL, 2015 RTE_FLOW_ERROR_TYPE_ITEM, item, 2016 "Key bit must be on"); 2017 2018 if (!mask) 2019 mask = &gre_key_default_mask; 2020 ret = mlx5_flow_item_acceptable 2021 (item, (const uint8_t *)mask, 2022 (const uint8_t *)&gre_key_default_mask, 2023 sizeof(rte_be32_t), error); 2024 return ret; 2025 } 2026 2027 /** 2028 * Validate GRE item. 2029 * 2030 * @param[in] item 2031 * Item specification. 2032 * @param[in] item_flags 2033 * Bit flags to mark detected items. 2034 * @param[in] target_protocol 2035 * The next protocol in the previous item. 2036 * @param[out] error 2037 * Pointer to error structure. 2038 * 2039 * @return 2040 * 0 on success, a negative errno value otherwise and rte_errno is set. 2041 */ 2042 int 2043 mlx5_flow_validate_item_gre(const struct rte_flow_item *item, 2044 uint64_t item_flags, 2045 uint8_t target_protocol, 2046 struct rte_flow_error *error) 2047 { 2048 const struct rte_flow_item_gre *spec __rte_unused = item->spec; 2049 const struct rte_flow_item_gre *mask = item->mask; 2050 int ret; 2051 const struct rte_flow_item_gre nic_mask = { 2052 .c_rsvd0_ver = RTE_BE16(0xB000), 2053 .protocol = RTE_BE16(UINT16_MAX), 2054 }; 2055 2056 if (target_protocol != 0xff && target_protocol != IPPROTO_GRE) 2057 return rte_flow_error_set(error, EINVAL, 2058 RTE_FLOW_ERROR_TYPE_ITEM, item, 2059 "protocol filtering not compatible" 2060 " with this GRE layer"); 2061 if (item_flags & MLX5_FLOW_LAYER_TUNNEL) 2062 return rte_flow_error_set(error, ENOTSUP, 2063 RTE_FLOW_ERROR_TYPE_ITEM, item, 2064 "multiple tunnel layers not" 2065 " supported"); 2066 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L3)) 2067 return rte_flow_error_set(error, ENOTSUP, 2068 RTE_FLOW_ERROR_TYPE_ITEM, item, 2069 "L3 Layer is missing"); 2070 if (!mask) 2071 mask = &rte_flow_item_gre_mask; 2072 ret = mlx5_flow_item_acceptable 2073 (item, (const uint8_t *)mask, 2074 (const uint8_t *)&nic_mask, 2075 sizeof(struct rte_flow_item_gre), error); 2076 if (ret < 0) 2077 return ret; 2078 #ifndef HAVE_MLX5DV_DR 2079 #ifndef HAVE_IBV_DEVICE_MPLS_SUPPORT 2080 if (spec && (spec->protocol & mask->protocol)) 2081 return rte_flow_error_set(error, ENOTSUP, 2082 RTE_FLOW_ERROR_TYPE_ITEM, item, 2083 "without MPLS support the" 2084 " specification cannot be used for" 2085 " filtering"); 2086 #endif 2087 #endif 2088 return 0; 2089 } 2090 2091 /** 2092 * Validate Geneve item. 2093 * 2094 * @param[in] item 2095 * Item specification. 2096 * @param[in] itemFlags 2097 * Bit-fields that holds the items detected until now. 2098 * @param[in] enPriv 2099 * Pointer to the private data structure. 2100 * @param[out] error 2101 * Pointer to error structure. 2102 * 2103 * @return 2104 * 0 on success, a negative errno value otherwise and rte_errno is set. 2105 */ 2106 2107 int 2108 mlx5_flow_validate_item_geneve(const struct rte_flow_item *item, 2109 uint64_t item_flags, 2110 struct rte_eth_dev *dev, 2111 struct rte_flow_error *error) 2112 { 2113 struct mlx5_priv *priv = dev->data->dev_private; 2114 const struct rte_flow_item_geneve *spec = item->spec; 2115 const struct rte_flow_item_geneve *mask = item->mask; 2116 int ret; 2117 uint16_t gbhdr; 2118 uint8_t opt_len = priv->config.hca_attr.geneve_max_opt_len ? 2119 MLX5_GENEVE_OPT_LEN_1 : MLX5_GENEVE_OPT_LEN_0; 2120 const struct rte_flow_item_geneve nic_mask = { 2121 .ver_opt_len_o_c_rsvd0 = RTE_BE16(0x3f80), 2122 .vni = "\xff\xff\xff", 2123 .protocol = RTE_BE16(UINT16_MAX), 2124 }; 2125 2126 if (!priv->config.hca_attr.tunnel_stateless_geneve_rx) 2127 return rte_flow_error_set(error, ENOTSUP, 2128 RTE_FLOW_ERROR_TYPE_ITEM, item, 2129 "L3 Geneve is not enabled by device" 2130 " parameter and/or not configured in" 2131 " firmware"); 2132 if (item_flags & MLX5_FLOW_LAYER_TUNNEL) 2133 return rte_flow_error_set(error, ENOTSUP, 2134 RTE_FLOW_ERROR_TYPE_ITEM, item, 2135 "multiple tunnel layers not" 2136 " supported"); 2137 /* 2138 * Verify only UDPv4 is present as defined in 2139 * https://tools.ietf.org/html/rfc7348 2140 */ 2141 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_UDP)) 2142 return rte_flow_error_set(error, EINVAL, 2143 RTE_FLOW_ERROR_TYPE_ITEM, item, 2144 "no outer UDP layer found"); 2145 if (!mask) 2146 mask = &rte_flow_item_geneve_mask; 2147 ret = mlx5_flow_item_acceptable 2148 (item, (const uint8_t *)mask, 2149 (const uint8_t *)&nic_mask, 2150 sizeof(struct rte_flow_item_geneve), error); 2151 if (ret) 2152 return ret; 2153 if (spec) { 2154 gbhdr = rte_be_to_cpu_16(spec->ver_opt_len_o_c_rsvd0); 2155 if (MLX5_GENEVE_VER_VAL(gbhdr) || 2156 MLX5_GENEVE_CRITO_VAL(gbhdr) || 2157 MLX5_GENEVE_RSVD_VAL(gbhdr) || spec->rsvd1) 2158 return rte_flow_error_set(error, ENOTSUP, 2159 RTE_FLOW_ERROR_TYPE_ITEM, 2160 item, 2161 "Geneve protocol unsupported" 2162 " fields are being used"); 2163 if (MLX5_GENEVE_OPTLEN_VAL(gbhdr) > opt_len) 2164 return rte_flow_error_set 2165 (error, ENOTSUP, 2166 RTE_FLOW_ERROR_TYPE_ITEM, 2167 item, 2168 "Unsupported Geneve options length"); 2169 } 2170 if (!(item_flags & MLX5_FLOW_LAYER_OUTER)) 2171 return rte_flow_error_set 2172 (error, ENOTSUP, 2173 RTE_FLOW_ERROR_TYPE_ITEM, item, 2174 "Geneve tunnel must be fully defined"); 2175 return 0; 2176 } 2177 2178 /** 2179 * Validate MPLS item. 2180 * 2181 * @param[in] dev 2182 * Pointer to the rte_eth_dev structure. 2183 * @param[in] item 2184 * Item specification. 2185 * @param[in] item_flags 2186 * Bit-fields that holds the items detected until now. 2187 * @param[in] prev_layer 2188 * The protocol layer indicated in previous item. 2189 * @param[out] error 2190 * Pointer to error structure. 2191 * 2192 * @return 2193 * 0 on success, a negative errno value otherwise and rte_errno is set. 2194 */ 2195 int 2196 mlx5_flow_validate_item_mpls(struct rte_eth_dev *dev __rte_unused, 2197 const struct rte_flow_item *item __rte_unused, 2198 uint64_t item_flags __rte_unused, 2199 uint64_t prev_layer __rte_unused, 2200 struct rte_flow_error *error) 2201 { 2202 #ifdef HAVE_IBV_DEVICE_MPLS_SUPPORT 2203 const struct rte_flow_item_mpls *mask = item->mask; 2204 struct mlx5_priv *priv = dev->data->dev_private; 2205 int ret; 2206 2207 if (!priv->config.mpls_en) 2208 return rte_flow_error_set(error, ENOTSUP, 2209 RTE_FLOW_ERROR_TYPE_ITEM, item, 2210 "MPLS not supported or" 2211 " disabled in firmware" 2212 " configuration."); 2213 /* MPLS over IP, UDP, GRE is allowed */ 2214 if (!(prev_layer & (MLX5_FLOW_LAYER_OUTER_L3 | 2215 MLX5_FLOW_LAYER_OUTER_L4_UDP | 2216 MLX5_FLOW_LAYER_GRE))) 2217 return rte_flow_error_set(error, EINVAL, 2218 RTE_FLOW_ERROR_TYPE_ITEM, item, 2219 "protocol filtering not compatible" 2220 " with MPLS layer"); 2221 /* Multi-tunnel isn't allowed but MPLS over GRE is an exception. */ 2222 if ((item_flags & MLX5_FLOW_LAYER_TUNNEL) && 2223 !(item_flags & MLX5_FLOW_LAYER_GRE)) 2224 return rte_flow_error_set(error, ENOTSUP, 2225 RTE_FLOW_ERROR_TYPE_ITEM, item, 2226 "multiple tunnel layers not" 2227 " supported"); 2228 if (!mask) 2229 mask = &rte_flow_item_mpls_mask; 2230 ret = mlx5_flow_item_acceptable 2231 (item, (const uint8_t *)mask, 2232 (const uint8_t *)&rte_flow_item_mpls_mask, 2233 sizeof(struct rte_flow_item_mpls), error); 2234 if (ret < 0) 2235 return ret; 2236 return 0; 2237 #endif 2238 return rte_flow_error_set(error, ENOTSUP, 2239 RTE_FLOW_ERROR_TYPE_ITEM, item, 2240 "MPLS is not supported by Verbs, please" 2241 " update."); 2242 } 2243 2244 /** 2245 * Validate NVGRE item. 2246 * 2247 * @param[in] item 2248 * Item specification. 2249 * @param[in] item_flags 2250 * Bit flags to mark detected items. 2251 * @param[in] target_protocol 2252 * The next protocol in the previous item. 2253 * @param[out] error 2254 * Pointer to error structure. 2255 * 2256 * @return 2257 * 0 on success, a negative errno value otherwise and rte_errno is set. 2258 */ 2259 int 2260 mlx5_flow_validate_item_nvgre(const struct rte_flow_item *item, 2261 uint64_t item_flags, 2262 uint8_t target_protocol, 2263 struct rte_flow_error *error) 2264 { 2265 const struct rte_flow_item_nvgre *mask = item->mask; 2266 int ret; 2267 2268 if (target_protocol != 0xff && target_protocol != IPPROTO_GRE) 2269 return rte_flow_error_set(error, EINVAL, 2270 RTE_FLOW_ERROR_TYPE_ITEM, item, 2271 "protocol filtering not compatible" 2272 " with this GRE layer"); 2273 if (item_flags & MLX5_FLOW_LAYER_TUNNEL) 2274 return rte_flow_error_set(error, ENOTSUP, 2275 RTE_FLOW_ERROR_TYPE_ITEM, item, 2276 "multiple tunnel layers not" 2277 " supported"); 2278 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L3)) 2279 return rte_flow_error_set(error, ENOTSUP, 2280 RTE_FLOW_ERROR_TYPE_ITEM, item, 2281 "L3 Layer is missing"); 2282 if (!mask) 2283 mask = &rte_flow_item_nvgre_mask; 2284 ret = mlx5_flow_item_acceptable 2285 (item, (const uint8_t *)mask, 2286 (const uint8_t *)&rte_flow_item_nvgre_mask, 2287 sizeof(struct rte_flow_item_nvgre), error); 2288 if (ret < 0) 2289 return ret; 2290 return 0; 2291 } 2292 2293 /* Allocate unique ID for the split Q/RSS subflows. */ 2294 static uint32_t 2295 flow_qrss_get_id(struct rte_eth_dev *dev) 2296 { 2297 struct mlx5_priv *priv = dev->data->dev_private; 2298 uint32_t qrss_id, ret; 2299 2300 ret = mlx5_flow_id_get(priv->qrss_id_pool, &qrss_id); 2301 if (ret) 2302 return 0; 2303 MLX5_ASSERT(qrss_id); 2304 return qrss_id; 2305 } 2306 2307 /* Free unique ID for the split Q/RSS subflows. */ 2308 static void 2309 flow_qrss_free_id(struct rte_eth_dev *dev, uint32_t qrss_id) 2310 { 2311 struct mlx5_priv *priv = dev->data->dev_private; 2312 2313 if (qrss_id) 2314 mlx5_flow_id_release(priv->qrss_id_pool, qrss_id); 2315 } 2316 2317 /** 2318 * Release resource related QUEUE/RSS action split. 2319 * 2320 * @param dev 2321 * Pointer to Ethernet device. 2322 * @param flow 2323 * Flow to release id's from. 2324 */ 2325 static void 2326 flow_mreg_split_qrss_release(struct rte_eth_dev *dev, 2327 struct rte_flow *flow) 2328 { 2329 struct mlx5_priv *priv = dev->data->dev_private; 2330 uint32_t handle_idx; 2331 struct mlx5_flow_handle *dev_handle; 2332 2333 SILIST_FOREACH(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW], flow->dev_handles, 2334 handle_idx, dev_handle, next) 2335 if (dev_handle->split_flow_id) 2336 flow_qrss_free_id(dev, dev_handle->split_flow_id); 2337 } 2338 2339 static int 2340 flow_null_validate(struct rte_eth_dev *dev __rte_unused, 2341 const struct rte_flow_attr *attr __rte_unused, 2342 const struct rte_flow_item items[] __rte_unused, 2343 const struct rte_flow_action actions[] __rte_unused, 2344 bool external __rte_unused, 2345 struct rte_flow_error *error) 2346 { 2347 return rte_flow_error_set(error, ENOTSUP, 2348 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, NULL); 2349 } 2350 2351 static struct mlx5_flow * 2352 flow_null_prepare(struct rte_eth_dev *dev __rte_unused, 2353 const struct rte_flow_attr *attr __rte_unused, 2354 const struct rte_flow_item items[] __rte_unused, 2355 const struct rte_flow_action actions[] __rte_unused, 2356 struct rte_flow_error *error) 2357 { 2358 rte_flow_error_set(error, ENOTSUP, 2359 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, NULL); 2360 return NULL; 2361 } 2362 2363 static int 2364 flow_null_translate(struct rte_eth_dev *dev __rte_unused, 2365 struct mlx5_flow *dev_flow __rte_unused, 2366 const struct rte_flow_attr *attr __rte_unused, 2367 const struct rte_flow_item items[] __rte_unused, 2368 const struct rte_flow_action actions[] __rte_unused, 2369 struct rte_flow_error *error) 2370 { 2371 return rte_flow_error_set(error, ENOTSUP, 2372 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, NULL); 2373 } 2374 2375 static int 2376 flow_null_apply(struct rte_eth_dev *dev __rte_unused, 2377 struct rte_flow *flow __rte_unused, 2378 struct rte_flow_error *error) 2379 { 2380 return rte_flow_error_set(error, ENOTSUP, 2381 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, NULL); 2382 } 2383 2384 static void 2385 flow_null_remove(struct rte_eth_dev *dev __rte_unused, 2386 struct rte_flow *flow __rte_unused) 2387 { 2388 } 2389 2390 static void 2391 flow_null_destroy(struct rte_eth_dev *dev __rte_unused, 2392 struct rte_flow *flow __rte_unused) 2393 { 2394 } 2395 2396 static int 2397 flow_null_query(struct rte_eth_dev *dev __rte_unused, 2398 struct rte_flow *flow __rte_unused, 2399 const struct rte_flow_action *actions __rte_unused, 2400 void *data __rte_unused, 2401 struct rte_flow_error *error) 2402 { 2403 return rte_flow_error_set(error, ENOTSUP, 2404 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, NULL); 2405 } 2406 2407 /* Void driver to protect from null pointer reference. */ 2408 const struct mlx5_flow_driver_ops mlx5_flow_null_drv_ops = { 2409 .validate = flow_null_validate, 2410 .prepare = flow_null_prepare, 2411 .translate = flow_null_translate, 2412 .apply = flow_null_apply, 2413 .remove = flow_null_remove, 2414 .destroy = flow_null_destroy, 2415 .query = flow_null_query, 2416 }; 2417 2418 /** 2419 * Select flow driver type according to flow attributes and device 2420 * configuration. 2421 * 2422 * @param[in] dev 2423 * Pointer to the dev structure. 2424 * @param[in] attr 2425 * Pointer to the flow attributes. 2426 * 2427 * @return 2428 * flow driver type, MLX5_FLOW_TYPE_MAX otherwise. 2429 */ 2430 static enum mlx5_flow_drv_type 2431 flow_get_drv_type(struct rte_eth_dev *dev, const struct rte_flow_attr *attr) 2432 { 2433 struct mlx5_priv *priv = dev->data->dev_private; 2434 enum mlx5_flow_drv_type type = MLX5_FLOW_TYPE_MAX; 2435 2436 if (attr->transfer && priv->config.dv_esw_en) 2437 type = MLX5_FLOW_TYPE_DV; 2438 if (!attr->transfer) 2439 type = priv->config.dv_flow_en ? MLX5_FLOW_TYPE_DV : 2440 MLX5_FLOW_TYPE_VERBS; 2441 return type; 2442 } 2443 2444 #define flow_get_drv_ops(type) flow_drv_ops[type] 2445 2446 /** 2447 * Flow driver validation API. This abstracts calling driver specific functions. 2448 * The type of flow driver is determined according to flow attributes. 2449 * 2450 * @param[in] dev 2451 * Pointer to the dev structure. 2452 * @param[in] attr 2453 * Pointer to the flow attributes. 2454 * @param[in] items 2455 * Pointer to the list of items. 2456 * @param[in] actions 2457 * Pointer to the list of actions. 2458 * @param[in] external 2459 * This flow rule is created by request external to PMD. 2460 * @param[out] error 2461 * Pointer to the error structure. 2462 * 2463 * @return 2464 * 0 on success, a negative errno value otherwise and rte_errno is set. 2465 */ 2466 static inline int 2467 flow_drv_validate(struct rte_eth_dev *dev, 2468 const struct rte_flow_attr *attr, 2469 const struct rte_flow_item items[], 2470 const struct rte_flow_action actions[], 2471 bool external, struct rte_flow_error *error) 2472 { 2473 const struct mlx5_flow_driver_ops *fops; 2474 enum mlx5_flow_drv_type type = flow_get_drv_type(dev, attr); 2475 2476 fops = flow_get_drv_ops(type); 2477 return fops->validate(dev, attr, items, actions, external, error); 2478 } 2479 2480 /** 2481 * Flow driver preparation API. This abstracts calling driver specific 2482 * functions. Parent flow (rte_flow) should have driver type (drv_type). It 2483 * calculates the size of memory required for device flow, allocates the memory, 2484 * initializes the device flow and returns the pointer. 2485 * 2486 * @note 2487 * This function initializes device flow structure such as dv or verbs in 2488 * struct mlx5_flow. However, it is caller's responsibility to initialize the 2489 * rest. For example, adding returning device flow to flow->dev_flow list and 2490 * setting backward reference to the flow should be done out of this function. 2491 * layers field is not filled either. 2492 * 2493 * @param[in] dev 2494 * Pointer to the dev structure. 2495 * @param[in] attr 2496 * Pointer to the flow attributes. 2497 * @param[in] items 2498 * Pointer to the list of items. 2499 * @param[in] actions 2500 * Pointer to the list of actions. 2501 * @param[out] error 2502 * Pointer to the error structure. 2503 * 2504 * @return 2505 * Pointer to device flow on success, otherwise NULL and rte_errno is set. 2506 */ 2507 static inline struct mlx5_flow * 2508 flow_drv_prepare(struct rte_eth_dev *dev, 2509 const struct rte_flow *flow, 2510 const struct rte_flow_attr *attr, 2511 const struct rte_flow_item items[], 2512 const struct rte_flow_action actions[], 2513 struct rte_flow_error *error) 2514 { 2515 const struct mlx5_flow_driver_ops *fops; 2516 enum mlx5_flow_drv_type type = flow->drv_type; 2517 2518 MLX5_ASSERT(type > MLX5_FLOW_TYPE_MIN && type < MLX5_FLOW_TYPE_MAX); 2519 fops = flow_get_drv_ops(type); 2520 return fops->prepare(dev, attr, items, actions, error); 2521 } 2522 2523 /** 2524 * Flow driver translation API. This abstracts calling driver specific 2525 * functions. Parent flow (rte_flow) should have driver type (drv_type). It 2526 * translates a generic flow into a driver flow. flow_drv_prepare() must 2527 * precede. 2528 * 2529 * @note 2530 * dev_flow->layers could be filled as a result of parsing during translation 2531 * if needed by flow_drv_apply(). dev_flow->flow->actions can also be filled 2532 * if necessary. As a flow can have multiple dev_flows by RSS flow expansion, 2533 * flow->actions could be overwritten even though all the expanded dev_flows 2534 * have the same actions. 2535 * 2536 * @param[in] dev 2537 * Pointer to the rte dev structure. 2538 * @param[in, out] dev_flow 2539 * Pointer to the mlx5 flow. 2540 * @param[in] attr 2541 * Pointer to the flow attributes. 2542 * @param[in] items 2543 * Pointer to the list of items. 2544 * @param[in] actions 2545 * Pointer to the list of actions. 2546 * @param[out] error 2547 * Pointer to the error structure. 2548 * 2549 * @return 2550 * 0 on success, a negative errno value otherwise and rte_errno is set. 2551 */ 2552 static inline int 2553 flow_drv_translate(struct rte_eth_dev *dev, struct mlx5_flow *dev_flow, 2554 const struct rte_flow_attr *attr, 2555 const struct rte_flow_item items[], 2556 const struct rte_flow_action actions[], 2557 struct rte_flow_error *error) 2558 { 2559 const struct mlx5_flow_driver_ops *fops; 2560 enum mlx5_flow_drv_type type = dev_flow->flow->drv_type; 2561 2562 MLX5_ASSERT(type > MLX5_FLOW_TYPE_MIN && type < MLX5_FLOW_TYPE_MAX); 2563 fops = flow_get_drv_ops(type); 2564 return fops->translate(dev, dev_flow, attr, items, actions, error); 2565 } 2566 2567 /** 2568 * Flow driver apply API. This abstracts calling driver specific functions. 2569 * Parent flow (rte_flow) should have driver type (drv_type). It applies 2570 * translated driver flows on to device. flow_drv_translate() must precede. 2571 * 2572 * @param[in] dev 2573 * Pointer to Ethernet device structure. 2574 * @param[in, out] flow 2575 * Pointer to flow structure. 2576 * @param[out] error 2577 * Pointer to error structure. 2578 * 2579 * @return 2580 * 0 on success, a negative errno value otherwise and rte_errno is set. 2581 */ 2582 static inline int 2583 flow_drv_apply(struct rte_eth_dev *dev, struct rte_flow *flow, 2584 struct rte_flow_error *error) 2585 { 2586 const struct mlx5_flow_driver_ops *fops; 2587 enum mlx5_flow_drv_type type = flow->drv_type; 2588 2589 MLX5_ASSERT(type > MLX5_FLOW_TYPE_MIN && type < MLX5_FLOW_TYPE_MAX); 2590 fops = flow_get_drv_ops(type); 2591 return fops->apply(dev, flow, error); 2592 } 2593 2594 /** 2595 * Flow driver remove API. This abstracts calling driver specific functions. 2596 * Parent flow (rte_flow) should have driver type (drv_type). It removes a flow 2597 * on device. All the resources of the flow should be freed by calling 2598 * flow_drv_destroy(). 2599 * 2600 * @param[in] dev 2601 * Pointer to Ethernet device. 2602 * @param[in, out] flow 2603 * Pointer to flow structure. 2604 */ 2605 static inline void 2606 flow_drv_remove(struct rte_eth_dev *dev, struct rte_flow *flow) 2607 { 2608 const struct mlx5_flow_driver_ops *fops; 2609 enum mlx5_flow_drv_type type = flow->drv_type; 2610 2611 MLX5_ASSERT(type > MLX5_FLOW_TYPE_MIN && type < MLX5_FLOW_TYPE_MAX); 2612 fops = flow_get_drv_ops(type); 2613 fops->remove(dev, flow); 2614 } 2615 2616 /** 2617 * Flow driver destroy API. This abstracts calling driver specific functions. 2618 * Parent flow (rte_flow) should have driver type (drv_type). It removes a flow 2619 * on device and releases resources of the flow. 2620 * 2621 * @param[in] dev 2622 * Pointer to Ethernet device. 2623 * @param[in, out] flow 2624 * Pointer to flow structure. 2625 */ 2626 static inline void 2627 flow_drv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow) 2628 { 2629 const struct mlx5_flow_driver_ops *fops; 2630 enum mlx5_flow_drv_type type = flow->drv_type; 2631 2632 flow_mreg_split_qrss_release(dev, flow); 2633 MLX5_ASSERT(type > MLX5_FLOW_TYPE_MIN && type < MLX5_FLOW_TYPE_MAX); 2634 fops = flow_get_drv_ops(type); 2635 fops->destroy(dev, flow); 2636 } 2637 2638 /** 2639 * Validate a flow supported by the NIC. 2640 * 2641 * @see rte_flow_validate() 2642 * @see rte_flow_ops 2643 */ 2644 int 2645 mlx5_flow_validate(struct rte_eth_dev *dev, 2646 const struct rte_flow_attr *attr, 2647 const struct rte_flow_item items[], 2648 const struct rte_flow_action actions[], 2649 struct rte_flow_error *error) 2650 { 2651 int ret; 2652 2653 ret = flow_drv_validate(dev, attr, items, actions, true, error); 2654 if (ret < 0) 2655 return ret; 2656 return 0; 2657 } 2658 2659 /** 2660 * Get RSS action from the action list. 2661 * 2662 * @param[in] actions 2663 * Pointer to the list of actions. 2664 * 2665 * @return 2666 * Pointer to the RSS action if exist, else return NULL. 2667 */ 2668 static const struct rte_flow_action_rss* 2669 flow_get_rss_action(const struct rte_flow_action actions[]) 2670 { 2671 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) { 2672 switch (actions->type) { 2673 case RTE_FLOW_ACTION_TYPE_RSS: 2674 return (const struct rte_flow_action_rss *) 2675 actions->conf; 2676 default: 2677 break; 2678 } 2679 } 2680 return NULL; 2681 } 2682 2683 static unsigned int 2684 find_graph_root(const struct rte_flow_item pattern[], uint32_t rss_level) 2685 { 2686 const struct rte_flow_item *item; 2687 unsigned int has_vlan = 0; 2688 2689 for (item = pattern; item->type != RTE_FLOW_ITEM_TYPE_END; item++) { 2690 if (item->type == RTE_FLOW_ITEM_TYPE_VLAN) { 2691 has_vlan = 1; 2692 break; 2693 } 2694 } 2695 if (has_vlan) 2696 return rss_level < 2 ? MLX5_EXPANSION_ROOT_ETH_VLAN : 2697 MLX5_EXPANSION_ROOT_OUTER_ETH_VLAN; 2698 return rss_level < 2 ? MLX5_EXPANSION_ROOT : 2699 MLX5_EXPANSION_ROOT_OUTER; 2700 } 2701 2702 /** 2703 * Get layer flags from the prefix flow. 2704 * 2705 * Some flows may be split to several subflows, the prefix subflow gets the 2706 * match items and the suffix sub flow gets the actions. 2707 * Some actions need the user defined match item flags to get the detail for 2708 * the action. 2709 * This function helps the suffix flow to get the item layer flags from prefix 2710 * subflow. 2711 * 2712 * @param[in] dev_flow 2713 * Pointer the created preifx subflow. 2714 * 2715 * @return 2716 * The layers get from prefix subflow. 2717 */ 2718 static inline uint64_t 2719 flow_get_prefix_layer_flags(struct mlx5_flow *dev_flow) 2720 { 2721 uint64_t layers = 0; 2722 2723 /* 2724 * Layers bits could be localization, but usually the compiler will 2725 * help to do the optimization work for source code. 2726 * If no decap actions, use the layers directly. 2727 */ 2728 if (!(dev_flow->act_flags & MLX5_FLOW_ACTION_DECAP)) 2729 return dev_flow->handle->layers; 2730 /* Convert L3 layers with decap action. */ 2731 if (dev_flow->handle->layers & MLX5_FLOW_LAYER_INNER_L3_IPV4) 2732 layers |= MLX5_FLOW_LAYER_OUTER_L3_IPV4; 2733 else if (dev_flow->handle->layers & MLX5_FLOW_LAYER_INNER_L3_IPV6) 2734 layers |= MLX5_FLOW_LAYER_OUTER_L3_IPV6; 2735 /* Convert L4 layers with decap action. */ 2736 if (dev_flow->handle->layers & MLX5_FLOW_LAYER_INNER_L4_TCP) 2737 layers |= MLX5_FLOW_LAYER_OUTER_L4_TCP; 2738 else if (dev_flow->handle->layers & MLX5_FLOW_LAYER_INNER_L4_UDP) 2739 layers |= MLX5_FLOW_LAYER_OUTER_L4_UDP; 2740 return layers; 2741 } 2742 2743 /** 2744 * Get metadata split action information. 2745 * 2746 * @param[in] actions 2747 * Pointer to the list of actions. 2748 * @param[out] qrss 2749 * Pointer to the return pointer. 2750 * @param[out] qrss_type 2751 * Pointer to the action type to return. RTE_FLOW_ACTION_TYPE_END is returned 2752 * if no QUEUE/RSS is found. 2753 * @param[out] encap_idx 2754 * Pointer to the index of the encap action if exists, otherwise the last 2755 * action index. 2756 * 2757 * @return 2758 * Total number of actions. 2759 */ 2760 static int 2761 flow_parse_metadata_split_actions_info(const struct rte_flow_action actions[], 2762 const struct rte_flow_action **qrss, 2763 int *encap_idx) 2764 { 2765 const struct rte_flow_action_raw_encap *raw_encap; 2766 int actions_n = 0; 2767 int raw_decap_idx = -1; 2768 2769 *encap_idx = -1; 2770 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) { 2771 switch (actions->type) { 2772 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP: 2773 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP: 2774 *encap_idx = actions_n; 2775 break; 2776 case RTE_FLOW_ACTION_TYPE_RAW_DECAP: 2777 raw_decap_idx = actions_n; 2778 break; 2779 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP: 2780 raw_encap = actions->conf; 2781 if (raw_encap->size > MLX5_ENCAPSULATION_DECISION_SIZE) 2782 *encap_idx = raw_decap_idx != -1 ? 2783 raw_decap_idx : actions_n; 2784 break; 2785 case RTE_FLOW_ACTION_TYPE_QUEUE: 2786 case RTE_FLOW_ACTION_TYPE_RSS: 2787 *qrss = actions; 2788 break; 2789 default: 2790 break; 2791 } 2792 actions_n++; 2793 } 2794 if (*encap_idx == -1) 2795 *encap_idx = actions_n; 2796 /* Count RTE_FLOW_ACTION_TYPE_END. */ 2797 return actions_n + 1; 2798 } 2799 2800 /** 2801 * Check meter action from the action list. 2802 * 2803 * @param[in] actions 2804 * Pointer to the list of actions. 2805 * @param[out] mtr 2806 * Pointer to the meter exist flag. 2807 * 2808 * @return 2809 * Total number of actions. 2810 */ 2811 static int 2812 flow_check_meter_action(const struct rte_flow_action actions[], uint32_t *mtr) 2813 { 2814 int actions_n = 0; 2815 2816 MLX5_ASSERT(mtr); 2817 *mtr = 0; 2818 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) { 2819 switch (actions->type) { 2820 case RTE_FLOW_ACTION_TYPE_METER: 2821 *mtr = 1; 2822 break; 2823 default: 2824 break; 2825 } 2826 actions_n++; 2827 } 2828 /* Count RTE_FLOW_ACTION_TYPE_END. */ 2829 return actions_n + 1; 2830 } 2831 2832 /** 2833 * Check if the flow should be splited due to hairpin. 2834 * The reason for the split is that in current HW we can't 2835 * support encap on Rx, so if a flow have encap we move it 2836 * to Tx. 2837 * 2838 * @param dev 2839 * Pointer to Ethernet device. 2840 * @param[in] attr 2841 * Flow rule attributes. 2842 * @param[in] actions 2843 * Associated actions (list terminated by the END action). 2844 * 2845 * @return 2846 * > 0 the number of actions and the flow should be split, 2847 * 0 when no split required. 2848 */ 2849 static int 2850 flow_check_hairpin_split(struct rte_eth_dev *dev, 2851 const struct rte_flow_attr *attr, 2852 const struct rte_flow_action actions[]) 2853 { 2854 int queue_action = 0; 2855 int action_n = 0; 2856 int encap = 0; 2857 const struct rte_flow_action_queue *queue; 2858 const struct rte_flow_action_rss *rss; 2859 const struct rte_flow_action_raw_encap *raw_encap; 2860 2861 if (!attr->ingress) 2862 return 0; 2863 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) { 2864 switch (actions->type) { 2865 case RTE_FLOW_ACTION_TYPE_QUEUE: 2866 queue = actions->conf; 2867 if (queue == NULL) 2868 return 0; 2869 if (mlx5_rxq_get_type(dev, queue->index) != 2870 MLX5_RXQ_TYPE_HAIRPIN) 2871 return 0; 2872 queue_action = 1; 2873 action_n++; 2874 break; 2875 case RTE_FLOW_ACTION_TYPE_RSS: 2876 rss = actions->conf; 2877 if (rss == NULL || rss->queue_num == 0) 2878 return 0; 2879 if (mlx5_rxq_get_type(dev, rss->queue[0]) != 2880 MLX5_RXQ_TYPE_HAIRPIN) 2881 return 0; 2882 queue_action = 1; 2883 action_n++; 2884 break; 2885 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP: 2886 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP: 2887 encap = 1; 2888 action_n++; 2889 break; 2890 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP: 2891 raw_encap = actions->conf; 2892 if (raw_encap->size > 2893 (sizeof(struct rte_flow_item_eth) + 2894 sizeof(struct rte_flow_item_ipv4))) 2895 encap = 1; 2896 action_n++; 2897 break; 2898 default: 2899 action_n++; 2900 break; 2901 } 2902 } 2903 if (encap == 1 && queue_action) 2904 return action_n; 2905 return 0; 2906 } 2907 2908 /* Declare flow create/destroy prototype in advance. */ 2909 static uint32_t 2910 flow_list_create(struct rte_eth_dev *dev, uint32_t *list, 2911 const struct rte_flow_attr *attr, 2912 const struct rte_flow_item items[], 2913 const struct rte_flow_action actions[], 2914 bool external, struct rte_flow_error *error); 2915 2916 static void 2917 flow_list_destroy(struct rte_eth_dev *dev, uint32_t *list, 2918 uint32_t flow_idx); 2919 2920 /** 2921 * Add a flow of copying flow metadata registers in RX_CP_TBL. 2922 * 2923 * As mark_id is unique, if there's already a registered flow for the mark_id, 2924 * return by increasing the reference counter of the resource. Otherwise, create 2925 * the resource (mcp_res) and flow. 2926 * 2927 * Flow looks like, 2928 * - If ingress port is ANY and reg_c[1] is mark_id, 2929 * flow_tag := mark_id, reg_b := reg_c[0] and jump to RX_ACT_TBL. 2930 * 2931 * For default flow (zero mark_id), flow is like, 2932 * - If ingress port is ANY, 2933 * reg_b := reg_c[0] and jump to RX_ACT_TBL. 2934 * 2935 * @param dev 2936 * Pointer to Ethernet device. 2937 * @param mark_id 2938 * ID of MARK action, zero means default flow for META. 2939 * @param[out] error 2940 * Perform verbose error reporting if not NULL. 2941 * 2942 * @return 2943 * Associated resource on success, NULL otherwise and rte_errno is set. 2944 */ 2945 static struct mlx5_flow_mreg_copy_resource * 2946 flow_mreg_add_copy_action(struct rte_eth_dev *dev, uint32_t mark_id, 2947 struct rte_flow_error *error) 2948 { 2949 struct mlx5_priv *priv = dev->data->dev_private; 2950 struct rte_flow_attr attr = { 2951 .group = MLX5_FLOW_MREG_CP_TABLE_GROUP, 2952 .ingress = 1, 2953 }; 2954 struct mlx5_rte_flow_item_tag tag_spec = { 2955 .data = mark_id, 2956 }; 2957 struct rte_flow_item items[] = { 2958 [1] = { .type = RTE_FLOW_ITEM_TYPE_END, }, 2959 }; 2960 struct rte_flow_action_mark ftag = { 2961 .id = mark_id, 2962 }; 2963 struct mlx5_flow_action_copy_mreg cp_mreg = { 2964 .dst = REG_B, 2965 .src = 0, 2966 }; 2967 struct rte_flow_action_jump jump = { 2968 .group = MLX5_FLOW_MREG_ACT_TABLE_GROUP, 2969 }; 2970 struct rte_flow_action actions[] = { 2971 [3] = { .type = RTE_FLOW_ACTION_TYPE_END, }, 2972 }; 2973 struct mlx5_flow_mreg_copy_resource *mcp_res; 2974 uint32_t idx = 0; 2975 int ret; 2976 2977 /* Fill the register fileds in the flow. */ 2978 ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error); 2979 if (ret < 0) 2980 return NULL; 2981 tag_spec.id = ret; 2982 ret = mlx5_flow_get_reg_id(dev, MLX5_METADATA_RX, 0, error); 2983 if (ret < 0) 2984 return NULL; 2985 cp_mreg.src = ret; 2986 /* Check if already registered. */ 2987 MLX5_ASSERT(priv->mreg_cp_tbl); 2988 mcp_res = (void *)mlx5_hlist_lookup(priv->mreg_cp_tbl, mark_id); 2989 if (mcp_res) { 2990 /* For non-default rule. */ 2991 if (mark_id != MLX5_DEFAULT_COPY_ID) 2992 mcp_res->refcnt++; 2993 MLX5_ASSERT(mark_id != MLX5_DEFAULT_COPY_ID || 2994 mcp_res->refcnt == 1); 2995 return mcp_res; 2996 } 2997 /* Provide the full width of FLAG specific value. */ 2998 if (mark_id == (priv->sh->dv_regc0_mask & MLX5_FLOW_MARK_DEFAULT)) 2999 tag_spec.data = MLX5_FLOW_MARK_DEFAULT; 3000 /* Build a new flow. */ 3001 if (mark_id != MLX5_DEFAULT_COPY_ID) { 3002 items[0] = (struct rte_flow_item){ 3003 .type = MLX5_RTE_FLOW_ITEM_TYPE_TAG, 3004 .spec = &tag_spec, 3005 }; 3006 items[1] = (struct rte_flow_item){ 3007 .type = RTE_FLOW_ITEM_TYPE_END, 3008 }; 3009 actions[0] = (struct rte_flow_action){ 3010 .type = MLX5_RTE_FLOW_ACTION_TYPE_MARK, 3011 .conf = &ftag, 3012 }; 3013 actions[1] = (struct rte_flow_action){ 3014 .type = MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG, 3015 .conf = &cp_mreg, 3016 }; 3017 actions[2] = (struct rte_flow_action){ 3018 .type = RTE_FLOW_ACTION_TYPE_JUMP, 3019 .conf = &jump, 3020 }; 3021 actions[3] = (struct rte_flow_action){ 3022 .type = RTE_FLOW_ACTION_TYPE_END, 3023 }; 3024 } else { 3025 /* Default rule, wildcard match. */ 3026 attr.priority = MLX5_FLOW_PRIO_RSVD; 3027 items[0] = (struct rte_flow_item){ 3028 .type = RTE_FLOW_ITEM_TYPE_END, 3029 }; 3030 actions[0] = (struct rte_flow_action){ 3031 .type = MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG, 3032 .conf = &cp_mreg, 3033 }; 3034 actions[1] = (struct rte_flow_action){ 3035 .type = RTE_FLOW_ACTION_TYPE_JUMP, 3036 .conf = &jump, 3037 }; 3038 actions[2] = (struct rte_flow_action){ 3039 .type = RTE_FLOW_ACTION_TYPE_END, 3040 }; 3041 } 3042 /* Build a new entry. */ 3043 mcp_res = mlx5_ipool_zmalloc(priv->sh->ipool[MLX5_IPOOL_MCP], &idx); 3044 if (!mcp_res) { 3045 rte_errno = ENOMEM; 3046 return NULL; 3047 } 3048 mcp_res->idx = idx; 3049 /* 3050 * The copy Flows are not included in any list. There 3051 * ones are referenced from other Flows and can not 3052 * be applied, removed, deleted in ardbitrary order 3053 * by list traversing. 3054 */ 3055 mcp_res->rix_flow = flow_list_create(dev, NULL, &attr, items, 3056 actions, false, error); 3057 if (!mcp_res->rix_flow) 3058 goto error; 3059 mcp_res->refcnt++; 3060 mcp_res->hlist_ent.key = mark_id; 3061 ret = mlx5_hlist_insert(priv->mreg_cp_tbl, 3062 &mcp_res->hlist_ent); 3063 MLX5_ASSERT(!ret); 3064 if (ret) 3065 goto error; 3066 return mcp_res; 3067 error: 3068 if (mcp_res->rix_flow) 3069 flow_list_destroy(dev, NULL, mcp_res->rix_flow); 3070 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_MCP], mcp_res->idx); 3071 return NULL; 3072 } 3073 3074 /** 3075 * Release flow in RX_CP_TBL. 3076 * 3077 * @param dev 3078 * Pointer to Ethernet device. 3079 * @flow 3080 * Parent flow for wich copying is provided. 3081 */ 3082 static void 3083 flow_mreg_del_copy_action(struct rte_eth_dev *dev, 3084 struct rte_flow *flow) 3085 { 3086 struct mlx5_flow_mreg_copy_resource *mcp_res; 3087 struct mlx5_priv *priv = dev->data->dev_private; 3088 3089 if (!flow->rix_mreg_copy) 3090 return; 3091 mcp_res = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_MCP], 3092 flow->rix_mreg_copy); 3093 if (!mcp_res || !priv->mreg_cp_tbl) 3094 return; 3095 if (flow->copy_applied) { 3096 MLX5_ASSERT(mcp_res->appcnt); 3097 flow->copy_applied = 0; 3098 --mcp_res->appcnt; 3099 if (!mcp_res->appcnt) { 3100 struct rte_flow *mcp_flow = mlx5_ipool_get 3101 (priv->sh->ipool[MLX5_IPOOL_RTE_FLOW], 3102 mcp_res->rix_flow); 3103 3104 if (mcp_flow) 3105 flow_drv_remove(dev, mcp_flow); 3106 } 3107 } 3108 /* 3109 * We do not check availability of metadata registers here, 3110 * because copy resources are not allocated in this case. 3111 */ 3112 if (--mcp_res->refcnt) 3113 return; 3114 MLX5_ASSERT(mcp_res->rix_flow); 3115 flow_list_destroy(dev, NULL, mcp_res->rix_flow); 3116 mlx5_hlist_remove(priv->mreg_cp_tbl, &mcp_res->hlist_ent); 3117 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_MCP], mcp_res->idx); 3118 flow->rix_mreg_copy = 0; 3119 } 3120 3121 /** 3122 * Start flow in RX_CP_TBL. 3123 * 3124 * @param dev 3125 * Pointer to Ethernet device. 3126 * @flow 3127 * Parent flow for wich copying is provided. 3128 * 3129 * @return 3130 * 0 on success, a negative errno value otherwise and rte_errno is set. 3131 */ 3132 static int 3133 flow_mreg_start_copy_action(struct rte_eth_dev *dev, 3134 struct rte_flow *flow) 3135 { 3136 struct mlx5_flow_mreg_copy_resource *mcp_res; 3137 struct mlx5_priv *priv = dev->data->dev_private; 3138 int ret; 3139 3140 if (!flow->rix_mreg_copy || flow->copy_applied) 3141 return 0; 3142 mcp_res = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_MCP], 3143 flow->rix_mreg_copy); 3144 if (!mcp_res) 3145 return 0; 3146 if (!mcp_res->appcnt) { 3147 struct rte_flow *mcp_flow = mlx5_ipool_get 3148 (priv->sh->ipool[MLX5_IPOOL_RTE_FLOW], 3149 mcp_res->rix_flow); 3150 3151 if (mcp_flow) { 3152 ret = flow_drv_apply(dev, mcp_flow, NULL); 3153 if (ret) 3154 return ret; 3155 } 3156 } 3157 ++mcp_res->appcnt; 3158 flow->copy_applied = 1; 3159 return 0; 3160 } 3161 3162 /** 3163 * Stop flow in RX_CP_TBL. 3164 * 3165 * @param dev 3166 * Pointer to Ethernet device. 3167 * @flow 3168 * Parent flow for wich copying is provided. 3169 */ 3170 static void 3171 flow_mreg_stop_copy_action(struct rte_eth_dev *dev, 3172 struct rte_flow *flow) 3173 { 3174 struct mlx5_flow_mreg_copy_resource *mcp_res; 3175 struct mlx5_priv *priv = dev->data->dev_private; 3176 3177 if (!flow->rix_mreg_copy || !flow->copy_applied) 3178 return; 3179 mcp_res = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_MCP], 3180 flow->rix_mreg_copy); 3181 if (!mcp_res) 3182 return; 3183 MLX5_ASSERT(mcp_res->appcnt); 3184 --mcp_res->appcnt; 3185 flow->copy_applied = 0; 3186 if (!mcp_res->appcnt) { 3187 struct rte_flow *mcp_flow = mlx5_ipool_get 3188 (priv->sh->ipool[MLX5_IPOOL_RTE_FLOW], 3189 mcp_res->rix_flow); 3190 3191 if (mcp_flow) 3192 flow_drv_remove(dev, mcp_flow); 3193 } 3194 } 3195 3196 /** 3197 * Remove the default copy action from RX_CP_TBL. 3198 * 3199 * @param dev 3200 * Pointer to Ethernet device. 3201 */ 3202 static void 3203 flow_mreg_del_default_copy_action(struct rte_eth_dev *dev) 3204 { 3205 struct mlx5_flow_mreg_copy_resource *mcp_res; 3206 struct mlx5_priv *priv = dev->data->dev_private; 3207 3208 /* Check if default flow is registered. */ 3209 if (!priv->mreg_cp_tbl) 3210 return; 3211 mcp_res = (void *)mlx5_hlist_lookup(priv->mreg_cp_tbl, 3212 MLX5_DEFAULT_COPY_ID); 3213 if (!mcp_res) 3214 return; 3215 MLX5_ASSERT(mcp_res->rix_flow); 3216 flow_list_destroy(dev, NULL, mcp_res->rix_flow); 3217 mlx5_hlist_remove(priv->mreg_cp_tbl, &mcp_res->hlist_ent); 3218 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_MCP], mcp_res->idx); 3219 } 3220 3221 /** 3222 * Add the default copy action in in RX_CP_TBL. 3223 * 3224 * @param dev 3225 * Pointer to Ethernet device. 3226 * @param[out] error 3227 * Perform verbose error reporting if not NULL. 3228 * 3229 * @return 3230 * 0 for success, negative value otherwise and rte_errno is set. 3231 */ 3232 static int 3233 flow_mreg_add_default_copy_action(struct rte_eth_dev *dev, 3234 struct rte_flow_error *error) 3235 { 3236 struct mlx5_priv *priv = dev->data->dev_private; 3237 struct mlx5_flow_mreg_copy_resource *mcp_res; 3238 3239 /* Check whether extensive metadata feature is engaged. */ 3240 if (!priv->config.dv_flow_en || 3241 priv->config.dv_xmeta_en == MLX5_XMETA_MODE_LEGACY || 3242 !mlx5_flow_ext_mreg_supported(dev) || 3243 !priv->sh->dv_regc0_mask) 3244 return 0; 3245 mcp_res = flow_mreg_add_copy_action(dev, MLX5_DEFAULT_COPY_ID, error); 3246 if (!mcp_res) 3247 return -rte_errno; 3248 return 0; 3249 } 3250 3251 /** 3252 * Add a flow of copying flow metadata registers in RX_CP_TBL. 3253 * 3254 * All the flow having Q/RSS action should be split by 3255 * flow_mreg_split_qrss_prep() to pass by RX_CP_TBL. A flow in the RX_CP_TBL 3256 * performs the following, 3257 * - CQE->flow_tag := reg_c[1] (MARK) 3258 * - CQE->flow_table_metadata (reg_b) := reg_c[0] (META) 3259 * As CQE's flow_tag is not a register, it can't be simply copied from reg_c[1] 3260 * but there should be a flow per each MARK ID set by MARK action. 3261 * 3262 * For the aforementioned reason, if there's a MARK action in flow's action 3263 * list, a corresponding flow should be added to the RX_CP_TBL in order to copy 3264 * the MARK ID to CQE's flow_tag like, 3265 * - If reg_c[1] is mark_id, 3266 * flow_tag := mark_id, reg_b := reg_c[0] and jump to RX_ACT_TBL. 3267 * 3268 * For SET_META action which stores value in reg_c[0], as the destination is 3269 * also a flow metadata register (reg_b), adding a default flow is enough. Zero 3270 * MARK ID means the default flow. The default flow looks like, 3271 * - For all flow, reg_b := reg_c[0] and jump to RX_ACT_TBL. 3272 * 3273 * @param dev 3274 * Pointer to Ethernet device. 3275 * @param flow 3276 * Pointer to flow structure. 3277 * @param[in] actions 3278 * Pointer to the list of actions. 3279 * @param[out] error 3280 * Perform verbose error reporting if not NULL. 3281 * 3282 * @return 3283 * 0 on success, negative value otherwise and rte_errno is set. 3284 */ 3285 static int 3286 flow_mreg_update_copy_table(struct rte_eth_dev *dev, 3287 struct rte_flow *flow, 3288 const struct rte_flow_action *actions, 3289 struct rte_flow_error *error) 3290 { 3291 struct mlx5_priv *priv = dev->data->dev_private; 3292 struct mlx5_dev_config *config = &priv->config; 3293 struct mlx5_flow_mreg_copy_resource *mcp_res; 3294 const struct rte_flow_action_mark *mark; 3295 3296 /* Check whether extensive metadata feature is engaged. */ 3297 if (!config->dv_flow_en || 3298 config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY || 3299 !mlx5_flow_ext_mreg_supported(dev) || 3300 !priv->sh->dv_regc0_mask) 3301 return 0; 3302 /* Find MARK action. */ 3303 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) { 3304 switch (actions->type) { 3305 case RTE_FLOW_ACTION_TYPE_FLAG: 3306 mcp_res = flow_mreg_add_copy_action 3307 (dev, MLX5_FLOW_MARK_DEFAULT, error); 3308 if (!mcp_res) 3309 return -rte_errno; 3310 flow->rix_mreg_copy = mcp_res->idx; 3311 if (dev->data->dev_started) { 3312 mcp_res->appcnt++; 3313 flow->copy_applied = 1; 3314 } 3315 return 0; 3316 case RTE_FLOW_ACTION_TYPE_MARK: 3317 mark = (const struct rte_flow_action_mark *) 3318 actions->conf; 3319 mcp_res = 3320 flow_mreg_add_copy_action(dev, mark->id, error); 3321 if (!mcp_res) 3322 return -rte_errno; 3323 flow->rix_mreg_copy = mcp_res->idx; 3324 if (dev->data->dev_started) { 3325 mcp_res->appcnt++; 3326 flow->copy_applied = 1; 3327 } 3328 return 0; 3329 default: 3330 break; 3331 } 3332 } 3333 return 0; 3334 } 3335 3336 #define MLX5_MAX_SPLIT_ACTIONS 24 3337 #define MLX5_MAX_SPLIT_ITEMS 24 3338 3339 /** 3340 * Split the hairpin flow. 3341 * Since HW can't support encap on Rx we move the encap to Tx. 3342 * If the count action is after the encap then we also 3343 * move the count action. in this case the count will also measure 3344 * the outer bytes. 3345 * 3346 * @param dev 3347 * Pointer to Ethernet device. 3348 * @param[in] actions 3349 * Associated actions (list terminated by the END action). 3350 * @param[out] actions_rx 3351 * Rx flow actions. 3352 * @param[out] actions_tx 3353 * Tx flow actions.. 3354 * @param[out] pattern_tx 3355 * The pattern items for the Tx flow. 3356 * @param[out] flow_id 3357 * The flow ID connected to this flow. 3358 * 3359 * @return 3360 * 0 on success. 3361 */ 3362 static int 3363 flow_hairpin_split(struct rte_eth_dev *dev, 3364 const struct rte_flow_action actions[], 3365 struct rte_flow_action actions_rx[], 3366 struct rte_flow_action actions_tx[], 3367 struct rte_flow_item pattern_tx[], 3368 uint32_t *flow_id) 3369 { 3370 struct mlx5_priv *priv = dev->data->dev_private; 3371 const struct rte_flow_action_raw_encap *raw_encap; 3372 const struct rte_flow_action_raw_decap *raw_decap; 3373 struct mlx5_rte_flow_action_set_tag *set_tag; 3374 struct rte_flow_action *tag_action; 3375 struct mlx5_rte_flow_item_tag *tag_item; 3376 struct rte_flow_item *item; 3377 char *addr; 3378 int encap = 0; 3379 3380 mlx5_flow_id_get(priv->sh->flow_id_pool, flow_id); 3381 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) { 3382 switch (actions->type) { 3383 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP: 3384 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP: 3385 rte_memcpy(actions_tx, actions, 3386 sizeof(struct rte_flow_action)); 3387 actions_tx++; 3388 break; 3389 case RTE_FLOW_ACTION_TYPE_COUNT: 3390 if (encap) { 3391 rte_memcpy(actions_tx, actions, 3392 sizeof(struct rte_flow_action)); 3393 actions_tx++; 3394 } else { 3395 rte_memcpy(actions_rx, actions, 3396 sizeof(struct rte_flow_action)); 3397 actions_rx++; 3398 } 3399 break; 3400 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP: 3401 raw_encap = actions->conf; 3402 if (raw_encap->size > 3403 (sizeof(struct rte_flow_item_eth) + 3404 sizeof(struct rte_flow_item_ipv4))) { 3405 memcpy(actions_tx, actions, 3406 sizeof(struct rte_flow_action)); 3407 actions_tx++; 3408 encap = 1; 3409 } else { 3410 rte_memcpy(actions_rx, actions, 3411 sizeof(struct rte_flow_action)); 3412 actions_rx++; 3413 } 3414 break; 3415 case RTE_FLOW_ACTION_TYPE_RAW_DECAP: 3416 raw_decap = actions->conf; 3417 if (raw_decap->size < 3418 (sizeof(struct rte_flow_item_eth) + 3419 sizeof(struct rte_flow_item_ipv4))) { 3420 memcpy(actions_tx, actions, 3421 sizeof(struct rte_flow_action)); 3422 actions_tx++; 3423 } else { 3424 rte_memcpy(actions_rx, actions, 3425 sizeof(struct rte_flow_action)); 3426 actions_rx++; 3427 } 3428 break; 3429 default: 3430 rte_memcpy(actions_rx, actions, 3431 sizeof(struct rte_flow_action)); 3432 actions_rx++; 3433 break; 3434 } 3435 } 3436 /* Add set meta action and end action for the Rx flow. */ 3437 tag_action = actions_rx; 3438 tag_action->type = MLX5_RTE_FLOW_ACTION_TYPE_TAG; 3439 actions_rx++; 3440 rte_memcpy(actions_rx, actions, sizeof(struct rte_flow_action)); 3441 actions_rx++; 3442 set_tag = (void *)actions_rx; 3443 set_tag->id = mlx5_flow_get_reg_id(dev, MLX5_HAIRPIN_RX, 0, NULL); 3444 MLX5_ASSERT(set_tag->id > REG_NONE); 3445 set_tag->data = *flow_id; 3446 tag_action->conf = set_tag; 3447 /* Create Tx item list. */ 3448 rte_memcpy(actions_tx, actions, sizeof(struct rte_flow_action)); 3449 addr = (void *)&pattern_tx[2]; 3450 item = pattern_tx; 3451 item->type = MLX5_RTE_FLOW_ITEM_TYPE_TAG; 3452 tag_item = (void *)addr; 3453 tag_item->data = *flow_id; 3454 tag_item->id = mlx5_flow_get_reg_id(dev, MLX5_HAIRPIN_TX, 0, NULL); 3455 MLX5_ASSERT(set_tag->id > REG_NONE); 3456 item->spec = tag_item; 3457 addr += sizeof(struct mlx5_rte_flow_item_tag); 3458 tag_item = (void *)addr; 3459 tag_item->data = UINT32_MAX; 3460 tag_item->id = UINT16_MAX; 3461 item->mask = tag_item; 3462 addr += sizeof(struct mlx5_rte_flow_item_tag); 3463 item->last = NULL; 3464 item++; 3465 item->type = RTE_FLOW_ITEM_TYPE_END; 3466 return 0; 3467 } 3468 3469 /** 3470 * The last stage of splitting chain, just creates the subflow 3471 * without any modification. 3472 * 3473 * @param[in] dev 3474 * Pointer to Ethernet device. 3475 * @param[in] flow 3476 * Parent flow structure pointer. 3477 * @param[in, out] sub_flow 3478 * Pointer to return the created subflow, may be NULL. 3479 * @param[in] prefix_layers 3480 * Prefix subflow layers, may be 0. 3481 * @param[in] attr 3482 * Flow rule attributes. 3483 * @param[in] items 3484 * Pattern specification (list terminated by the END pattern item). 3485 * @param[in] actions 3486 * Associated actions (list terminated by the END action). 3487 * @param[in] external 3488 * This flow rule is created by request external to PMD. 3489 * @param[out] error 3490 * Perform verbose error reporting if not NULL. 3491 * @return 3492 * 0 on success, negative value otherwise 3493 */ 3494 static int 3495 flow_create_split_inner(struct rte_eth_dev *dev, 3496 struct rte_flow *flow, 3497 struct mlx5_flow **sub_flow, 3498 uint64_t prefix_layers, 3499 const struct rte_flow_attr *attr, 3500 const struct rte_flow_item items[], 3501 const struct rte_flow_action actions[], 3502 bool external, struct rte_flow_error *error) 3503 { 3504 struct mlx5_flow *dev_flow; 3505 3506 dev_flow = flow_drv_prepare(dev, flow, attr, items, actions, error); 3507 if (!dev_flow) 3508 return -rte_errno; 3509 dev_flow->flow = flow; 3510 dev_flow->external = external; 3511 /* Subflow object was created, we must include one in the list. */ 3512 SILIST_INSERT(&flow->dev_handles, dev_flow->handle_idx, 3513 dev_flow->handle, next); 3514 /* 3515 * If dev_flow is as one of the suffix flow, some actions in suffix 3516 * flow may need some user defined item layer flags. 3517 */ 3518 if (prefix_layers) 3519 dev_flow->handle->layers = prefix_layers; 3520 if (sub_flow) 3521 *sub_flow = dev_flow; 3522 return flow_drv_translate(dev, dev_flow, attr, items, actions, error); 3523 } 3524 3525 /** 3526 * Split the meter flow. 3527 * 3528 * As meter flow will split to three sub flow, other than meter 3529 * action, the other actions make sense to only meter accepts 3530 * the packet. If it need to be dropped, no other additional 3531 * actions should be take. 3532 * 3533 * One kind of special action which decapsulates the L3 tunnel 3534 * header will be in the prefix sub flow, as not to take the 3535 * L3 tunnel header into account. 3536 * 3537 * @param dev 3538 * Pointer to Ethernet device. 3539 * @param[in] items 3540 * Pattern specification (list terminated by the END pattern item). 3541 * @param[out] sfx_items 3542 * Suffix flow match items (list terminated by the END pattern item). 3543 * @param[in] actions 3544 * Associated actions (list terminated by the END action). 3545 * @param[out] actions_sfx 3546 * Suffix flow actions. 3547 * @param[out] actions_pre 3548 * Prefix flow actions. 3549 * @param[out] pattern_sfx 3550 * The pattern items for the suffix flow. 3551 * @param[out] tag_sfx 3552 * Pointer to suffix flow tag. 3553 * 3554 * @return 3555 * 0 on success. 3556 */ 3557 static int 3558 flow_meter_split_prep(struct rte_eth_dev *dev, 3559 const struct rte_flow_item items[], 3560 struct rte_flow_item sfx_items[], 3561 const struct rte_flow_action actions[], 3562 struct rte_flow_action actions_sfx[], 3563 struct rte_flow_action actions_pre[]) 3564 { 3565 struct rte_flow_action *tag_action = NULL; 3566 struct rte_flow_item *tag_item; 3567 struct mlx5_rte_flow_action_set_tag *set_tag; 3568 struct rte_flow_error error; 3569 const struct rte_flow_action_raw_encap *raw_encap; 3570 const struct rte_flow_action_raw_decap *raw_decap; 3571 struct mlx5_rte_flow_item_tag *tag_spec; 3572 struct mlx5_rte_flow_item_tag *tag_mask; 3573 uint32_t tag_id; 3574 bool copy_vlan = false; 3575 3576 /* Prepare the actions for prefix and suffix flow. */ 3577 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) { 3578 struct rte_flow_action **action_cur = NULL; 3579 3580 switch (actions->type) { 3581 case RTE_FLOW_ACTION_TYPE_METER: 3582 /* Add the extra tag action first. */ 3583 tag_action = actions_pre; 3584 tag_action->type = MLX5_RTE_FLOW_ACTION_TYPE_TAG; 3585 actions_pre++; 3586 action_cur = &actions_pre; 3587 break; 3588 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP: 3589 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP: 3590 action_cur = &actions_pre; 3591 break; 3592 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP: 3593 raw_encap = actions->conf; 3594 if (raw_encap->size < MLX5_ENCAPSULATION_DECISION_SIZE) 3595 action_cur = &actions_pre; 3596 break; 3597 case RTE_FLOW_ACTION_TYPE_RAW_DECAP: 3598 raw_decap = actions->conf; 3599 if (raw_decap->size > MLX5_ENCAPSULATION_DECISION_SIZE) 3600 action_cur = &actions_pre; 3601 break; 3602 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN: 3603 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID: 3604 copy_vlan = true; 3605 break; 3606 default: 3607 break; 3608 } 3609 if (!action_cur) 3610 action_cur = &actions_sfx; 3611 memcpy(*action_cur, actions, sizeof(struct rte_flow_action)); 3612 (*action_cur)++; 3613 } 3614 /* Add end action to the actions. */ 3615 actions_sfx->type = RTE_FLOW_ACTION_TYPE_END; 3616 actions_pre->type = RTE_FLOW_ACTION_TYPE_END; 3617 actions_pre++; 3618 /* Set the tag. */ 3619 set_tag = (void *)actions_pre; 3620 set_tag->id = mlx5_flow_get_reg_id(dev, MLX5_MTR_SFX, 0, &error); 3621 /* 3622 * Get the id from the qrss_pool to make qrss share the id with meter. 3623 */ 3624 tag_id = flow_qrss_get_id(dev); 3625 set_tag->data = tag_id << MLX5_MTR_COLOR_BITS; 3626 assert(tag_action); 3627 tag_action->conf = set_tag; 3628 /* Prepare the suffix subflow items. */ 3629 tag_item = sfx_items++; 3630 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) { 3631 int item_type = items->type; 3632 3633 switch (item_type) { 3634 case RTE_FLOW_ITEM_TYPE_PORT_ID: 3635 memcpy(sfx_items, items, sizeof(*sfx_items)); 3636 sfx_items++; 3637 break; 3638 case RTE_FLOW_ITEM_TYPE_VLAN: 3639 if (copy_vlan) { 3640 memcpy(sfx_items, items, sizeof(*sfx_items)); 3641 /* 3642 * Convert to internal match item, it is used 3643 * for vlan push and set vid. 3644 */ 3645 sfx_items->type = MLX5_RTE_FLOW_ITEM_TYPE_VLAN; 3646 sfx_items++; 3647 } 3648 break; 3649 default: 3650 break; 3651 } 3652 } 3653 sfx_items->type = RTE_FLOW_ITEM_TYPE_END; 3654 sfx_items++; 3655 tag_spec = (struct mlx5_rte_flow_item_tag *)sfx_items; 3656 tag_spec->data = tag_id << MLX5_MTR_COLOR_BITS; 3657 tag_spec->id = mlx5_flow_get_reg_id(dev, MLX5_MTR_SFX, 0, &error); 3658 tag_mask = tag_spec + 1; 3659 tag_mask->data = 0xffffff00; 3660 tag_item->type = MLX5_RTE_FLOW_ITEM_TYPE_TAG; 3661 tag_item->spec = tag_spec; 3662 tag_item->last = NULL; 3663 tag_item->mask = tag_mask; 3664 return tag_id; 3665 } 3666 3667 /** 3668 * Split action list having QUEUE/RSS for metadata register copy. 3669 * 3670 * Once Q/RSS action is detected in user's action list, the flow action 3671 * should be split in order to copy metadata registers, which will happen in 3672 * RX_CP_TBL like, 3673 * - CQE->flow_tag := reg_c[1] (MARK) 3674 * - CQE->flow_table_metadata (reg_b) := reg_c[0] (META) 3675 * The Q/RSS action will be performed on RX_ACT_TBL after passing by RX_CP_TBL. 3676 * This is because the last action of each flow must be a terminal action 3677 * (QUEUE, RSS or DROP). 3678 * 3679 * Flow ID must be allocated to identify actions in the RX_ACT_TBL and it is 3680 * stored and kept in the mlx5_flow structure per each sub_flow. 3681 * 3682 * The Q/RSS action is replaced with, 3683 * - SET_TAG, setting the allocated flow ID to reg_c[2]. 3684 * And the following JUMP action is added at the end, 3685 * - JUMP, to RX_CP_TBL. 3686 * 3687 * A flow to perform remained Q/RSS action will be created in RX_ACT_TBL by 3688 * flow_create_split_metadata() routine. The flow will look like, 3689 * - If flow ID matches (reg_c[2]), perform Q/RSS. 3690 * 3691 * @param dev 3692 * Pointer to Ethernet device. 3693 * @param[out] split_actions 3694 * Pointer to store split actions to jump to CP_TBL. 3695 * @param[in] actions 3696 * Pointer to the list of original flow actions. 3697 * @param[in] qrss 3698 * Pointer to the Q/RSS action. 3699 * @param[in] actions_n 3700 * Number of original actions. 3701 * @param[out] error 3702 * Perform verbose error reporting if not NULL. 3703 * 3704 * @return 3705 * non-zero unique flow_id on success, otherwise 0 and 3706 * error/rte_error are set. 3707 */ 3708 static uint32_t 3709 flow_mreg_split_qrss_prep(struct rte_eth_dev *dev, 3710 struct rte_flow_action *split_actions, 3711 const struct rte_flow_action *actions, 3712 const struct rte_flow_action *qrss, 3713 int actions_n, struct rte_flow_error *error) 3714 { 3715 struct mlx5_rte_flow_action_set_tag *set_tag; 3716 struct rte_flow_action_jump *jump; 3717 const int qrss_idx = qrss - actions; 3718 uint32_t flow_id = 0; 3719 int ret = 0; 3720 3721 /* 3722 * Given actions will be split 3723 * - Replace QUEUE/RSS action with SET_TAG to set flow ID. 3724 * - Add jump to mreg CP_TBL. 3725 * As a result, there will be one more action. 3726 */ 3727 ++actions_n; 3728 memcpy(split_actions, actions, sizeof(*split_actions) * actions_n); 3729 set_tag = (void *)(split_actions + actions_n); 3730 /* 3731 * If tag action is not set to void(it means we are not the meter 3732 * suffix flow), add the tag action. Since meter suffix flow already 3733 * has the tag added. 3734 */ 3735 if (split_actions[qrss_idx].type != RTE_FLOW_ACTION_TYPE_VOID) { 3736 /* 3737 * Allocate the new subflow ID. This one is unique within 3738 * device and not shared with representors. Otherwise, 3739 * we would have to resolve multi-thread access synch 3740 * issue. Each flow on the shared device is appended 3741 * with source vport identifier, so the resulting 3742 * flows will be unique in the shared (by master and 3743 * representors) domain even if they have coinciding 3744 * IDs. 3745 */ 3746 flow_id = flow_qrss_get_id(dev); 3747 if (!flow_id) 3748 return rte_flow_error_set(error, ENOMEM, 3749 RTE_FLOW_ERROR_TYPE_ACTION, 3750 NULL, "can't allocate id " 3751 "for split Q/RSS subflow"); 3752 /* Internal SET_TAG action to set flow ID. */ 3753 *set_tag = (struct mlx5_rte_flow_action_set_tag){ 3754 .data = flow_id, 3755 }; 3756 ret = mlx5_flow_get_reg_id(dev, MLX5_COPY_MARK, 0, error); 3757 if (ret < 0) 3758 return ret; 3759 set_tag->id = ret; 3760 /* Construct new actions array. */ 3761 /* Replace QUEUE/RSS action. */ 3762 split_actions[qrss_idx] = (struct rte_flow_action){ 3763 .type = MLX5_RTE_FLOW_ACTION_TYPE_TAG, 3764 .conf = set_tag, 3765 }; 3766 } 3767 /* JUMP action to jump to mreg copy table (CP_TBL). */ 3768 jump = (void *)(set_tag + 1); 3769 *jump = (struct rte_flow_action_jump){ 3770 .group = MLX5_FLOW_MREG_CP_TABLE_GROUP, 3771 }; 3772 split_actions[actions_n - 2] = (struct rte_flow_action){ 3773 .type = RTE_FLOW_ACTION_TYPE_JUMP, 3774 .conf = jump, 3775 }; 3776 split_actions[actions_n - 1] = (struct rte_flow_action){ 3777 .type = RTE_FLOW_ACTION_TYPE_END, 3778 }; 3779 return flow_id; 3780 } 3781 3782 /** 3783 * Extend the given action list for Tx metadata copy. 3784 * 3785 * Copy the given action list to the ext_actions and add flow metadata register 3786 * copy action in order to copy reg_a set by WQE to reg_c[0]. 3787 * 3788 * @param[out] ext_actions 3789 * Pointer to the extended action list. 3790 * @param[in] actions 3791 * Pointer to the list of actions. 3792 * @param[in] actions_n 3793 * Number of actions in the list. 3794 * @param[out] error 3795 * Perform verbose error reporting if not NULL. 3796 * @param[in] encap_idx 3797 * The encap action inndex. 3798 * 3799 * @return 3800 * 0 on success, negative value otherwise 3801 */ 3802 static int 3803 flow_mreg_tx_copy_prep(struct rte_eth_dev *dev, 3804 struct rte_flow_action *ext_actions, 3805 const struct rte_flow_action *actions, 3806 int actions_n, struct rte_flow_error *error, 3807 int encap_idx) 3808 { 3809 struct mlx5_flow_action_copy_mreg *cp_mreg = 3810 (struct mlx5_flow_action_copy_mreg *) 3811 (ext_actions + actions_n + 1); 3812 int ret; 3813 3814 ret = mlx5_flow_get_reg_id(dev, MLX5_METADATA_RX, 0, error); 3815 if (ret < 0) 3816 return ret; 3817 cp_mreg->dst = ret; 3818 ret = mlx5_flow_get_reg_id(dev, MLX5_METADATA_TX, 0, error); 3819 if (ret < 0) 3820 return ret; 3821 cp_mreg->src = ret; 3822 if (encap_idx != 0) 3823 memcpy(ext_actions, actions, sizeof(*ext_actions) * encap_idx); 3824 if (encap_idx == actions_n - 1) { 3825 ext_actions[actions_n - 1] = (struct rte_flow_action){ 3826 .type = MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG, 3827 .conf = cp_mreg, 3828 }; 3829 ext_actions[actions_n] = (struct rte_flow_action){ 3830 .type = RTE_FLOW_ACTION_TYPE_END, 3831 }; 3832 } else { 3833 ext_actions[encap_idx] = (struct rte_flow_action){ 3834 .type = MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG, 3835 .conf = cp_mreg, 3836 }; 3837 memcpy(ext_actions + encap_idx + 1, actions + encap_idx, 3838 sizeof(*ext_actions) * (actions_n - encap_idx)); 3839 } 3840 return 0; 3841 } 3842 3843 /** 3844 * The splitting for metadata feature. 3845 * 3846 * - Q/RSS action on NIC Rx should be split in order to pass by 3847 * the mreg copy table (RX_CP_TBL) and then it jumps to the 3848 * action table (RX_ACT_TBL) which has the split Q/RSS action. 3849 * 3850 * - All the actions on NIC Tx should have a mreg copy action to 3851 * copy reg_a from WQE to reg_c[0]. 3852 * 3853 * @param dev 3854 * Pointer to Ethernet device. 3855 * @param[in] flow 3856 * Parent flow structure pointer. 3857 * @param[in] prefix_layers 3858 * Prefix flow layer flags. 3859 * @param[in] attr 3860 * Flow rule attributes. 3861 * @param[in] items 3862 * Pattern specification (list terminated by the END pattern item). 3863 * @param[in] actions 3864 * Associated actions (list terminated by the END action). 3865 * @param[in] external 3866 * This flow rule is created by request external to PMD. 3867 * @param[out] error 3868 * Perform verbose error reporting if not NULL. 3869 * @return 3870 * 0 on success, negative value otherwise 3871 */ 3872 static int 3873 flow_create_split_metadata(struct rte_eth_dev *dev, 3874 struct rte_flow *flow, 3875 uint64_t prefix_layers, 3876 const struct rte_flow_attr *attr, 3877 const struct rte_flow_item items[], 3878 const struct rte_flow_action actions[], 3879 bool external, struct rte_flow_error *error) 3880 { 3881 struct mlx5_priv *priv = dev->data->dev_private; 3882 struct mlx5_dev_config *config = &priv->config; 3883 const struct rte_flow_action *qrss = NULL; 3884 struct rte_flow_action *ext_actions = NULL; 3885 struct mlx5_flow *dev_flow = NULL; 3886 uint32_t qrss_id = 0; 3887 int mtr_sfx = 0; 3888 size_t act_size; 3889 int actions_n; 3890 int encap_idx; 3891 int ret; 3892 3893 /* Check whether extensive metadata feature is engaged. */ 3894 if (!config->dv_flow_en || 3895 config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY || 3896 !mlx5_flow_ext_mreg_supported(dev)) 3897 return flow_create_split_inner(dev, flow, NULL, prefix_layers, 3898 attr, items, actions, external, 3899 error); 3900 actions_n = flow_parse_metadata_split_actions_info(actions, &qrss, 3901 &encap_idx); 3902 if (qrss) { 3903 /* Exclude hairpin flows from splitting. */ 3904 if (qrss->type == RTE_FLOW_ACTION_TYPE_QUEUE) { 3905 const struct rte_flow_action_queue *queue; 3906 3907 queue = qrss->conf; 3908 if (mlx5_rxq_get_type(dev, queue->index) == 3909 MLX5_RXQ_TYPE_HAIRPIN) 3910 qrss = NULL; 3911 } else if (qrss->type == RTE_FLOW_ACTION_TYPE_RSS) { 3912 const struct rte_flow_action_rss *rss; 3913 3914 rss = qrss->conf; 3915 if (mlx5_rxq_get_type(dev, rss->queue[0]) == 3916 MLX5_RXQ_TYPE_HAIRPIN) 3917 qrss = NULL; 3918 } 3919 } 3920 if (qrss) { 3921 /* Check if it is in meter suffix table. */ 3922 mtr_sfx = attr->group == (attr->transfer ? 3923 (MLX5_FLOW_TABLE_LEVEL_SUFFIX - 1) : 3924 MLX5_FLOW_TABLE_LEVEL_SUFFIX); 3925 /* 3926 * Q/RSS action on NIC Rx should be split in order to pass by 3927 * the mreg copy table (RX_CP_TBL) and then it jumps to the 3928 * action table (RX_ACT_TBL) which has the split Q/RSS action. 3929 */ 3930 act_size = sizeof(struct rte_flow_action) * (actions_n + 1) + 3931 sizeof(struct rte_flow_action_set_tag) + 3932 sizeof(struct rte_flow_action_jump); 3933 ext_actions = rte_zmalloc(__func__, act_size, 0); 3934 if (!ext_actions) 3935 return rte_flow_error_set(error, ENOMEM, 3936 RTE_FLOW_ERROR_TYPE_ACTION, 3937 NULL, "no memory to split " 3938 "metadata flow"); 3939 /* 3940 * If we are the suffix flow of meter, tag already exist. 3941 * Set the tag action to void. 3942 */ 3943 if (mtr_sfx) 3944 ext_actions[qrss - actions].type = 3945 RTE_FLOW_ACTION_TYPE_VOID; 3946 else 3947 ext_actions[qrss - actions].type = 3948 MLX5_RTE_FLOW_ACTION_TYPE_TAG; 3949 /* 3950 * Create the new actions list with removed Q/RSS action 3951 * and appended set tag and jump to register copy table 3952 * (RX_CP_TBL). We should preallocate unique tag ID here 3953 * in advance, because it is needed for set tag action. 3954 */ 3955 qrss_id = flow_mreg_split_qrss_prep(dev, ext_actions, actions, 3956 qrss, actions_n, error); 3957 if (!mtr_sfx && !qrss_id) { 3958 ret = -rte_errno; 3959 goto exit; 3960 } 3961 } else if (attr->egress && !attr->transfer) { 3962 /* 3963 * All the actions on NIC Tx should have a metadata register 3964 * copy action to copy reg_a from WQE to reg_c[meta] 3965 */ 3966 act_size = sizeof(struct rte_flow_action) * (actions_n + 1) + 3967 sizeof(struct mlx5_flow_action_copy_mreg); 3968 ext_actions = rte_zmalloc(__func__, act_size, 0); 3969 if (!ext_actions) 3970 return rte_flow_error_set(error, ENOMEM, 3971 RTE_FLOW_ERROR_TYPE_ACTION, 3972 NULL, "no memory to split " 3973 "metadata flow"); 3974 /* Create the action list appended with copy register. */ 3975 ret = flow_mreg_tx_copy_prep(dev, ext_actions, actions, 3976 actions_n, error, encap_idx); 3977 if (ret < 0) 3978 goto exit; 3979 } 3980 /* Add the unmodified original or prefix subflow. */ 3981 ret = flow_create_split_inner(dev, flow, &dev_flow, prefix_layers, attr, 3982 items, ext_actions ? ext_actions : 3983 actions, external, error); 3984 if (ret < 0) 3985 goto exit; 3986 MLX5_ASSERT(dev_flow); 3987 if (qrss) { 3988 const struct rte_flow_attr q_attr = { 3989 .group = MLX5_FLOW_MREG_ACT_TABLE_GROUP, 3990 .ingress = 1, 3991 }; 3992 /* Internal PMD action to set register. */ 3993 struct mlx5_rte_flow_item_tag q_tag_spec = { 3994 .data = qrss_id, 3995 .id = 0, 3996 }; 3997 struct rte_flow_item q_items[] = { 3998 { 3999 .type = MLX5_RTE_FLOW_ITEM_TYPE_TAG, 4000 .spec = &q_tag_spec, 4001 .last = NULL, 4002 .mask = NULL, 4003 }, 4004 { 4005 .type = RTE_FLOW_ITEM_TYPE_END, 4006 }, 4007 }; 4008 struct rte_flow_action q_actions[] = { 4009 { 4010 .type = qrss->type, 4011 .conf = qrss->conf, 4012 }, 4013 { 4014 .type = RTE_FLOW_ACTION_TYPE_END, 4015 }, 4016 }; 4017 uint64_t layers = flow_get_prefix_layer_flags(dev_flow); 4018 4019 /* 4020 * Configure the tag item only if there is no meter subflow. 4021 * Since tag is already marked in the meter suffix subflow 4022 * we can just use the meter suffix items as is. 4023 */ 4024 if (qrss_id) { 4025 /* Not meter subflow. */ 4026 MLX5_ASSERT(!mtr_sfx); 4027 /* 4028 * Put unique id in prefix flow due to it is destroyed 4029 * after suffix flow and id will be freed after there 4030 * is no actual flows with this id and identifier 4031 * reallocation becomes possible (for example, for 4032 * other flows in other threads). 4033 */ 4034 dev_flow->handle->split_flow_id = qrss_id; 4035 ret = mlx5_flow_get_reg_id(dev, MLX5_COPY_MARK, 0, 4036 error); 4037 if (ret < 0) 4038 goto exit; 4039 q_tag_spec.id = ret; 4040 } 4041 dev_flow = NULL; 4042 /* Add suffix subflow to execute Q/RSS. */ 4043 ret = flow_create_split_inner(dev, flow, &dev_flow, layers, 4044 &q_attr, mtr_sfx ? items : 4045 q_items, q_actions, 4046 external, error); 4047 if (ret < 0) 4048 goto exit; 4049 /* qrss ID should be freed if failed. */ 4050 qrss_id = 0; 4051 MLX5_ASSERT(dev_flow); 4052 } 4053 4054 exit: 4055 /* 4056 * We do not destroy the partially created sub_flows in case of error. 4057 * These ones are included into parent flow list and will be destroyed 4058 * by flow_drv_destroy. 4059 */ 4060 flow_qrss_free_id(dev, qrss_id); 4061 rte_free(ext_actions); 4062 return ret; 4063 } 4064 4065 /** 4066 * The splitting for meter feature. 4067 * 4068 * - The meter flow will be split to two flows as prefix and 4069 * suffix flow. The packets make sense only it pass the prefix 4070 * meter action. 4071 * 4072 * - Reg_C_5 is used for the packet to match betweend prefix and 4073 * suffix flow. 4074 * 4075 * @param dev 4076 * Pointer to Ethernet device. 4077 * @param[in] flow 4078 * Parent flow structure pointer. 4079 * @param[in] attr 4080 * Flow rule attributes. 4081 * @param[in] items 4082 * Pattern specification (list terminated by the END pattern item). 4083 * @param[in] actions 4084 * Associated actions (list terminated by the END action). 4085 * @param[in] external 4086 * This flow rule is created by request external to PMD. 4087 * @param[out] error 4088 * Perform verbose error reporting if not NULL. 4089 * @return 4090 * 0 on success, negative value otherwise 4091 */ 4092 static int 4093 flow_create_split_meter(struct rte_eth_dev *dev, 4094 struct rte_flow *flow, 4095 const struct rte_flow_attr *attr, 4096 const struct rte_flow_item items[], 4097 const struct rte_flow_action actions[], 4098 bool external, struct rte_flow_error *error) 4099 { 4100 struct mlx5_priv *priv = dev->data->dev_private; 4101 struct rte_flow_action *sfx_actions = NULL; 4102 struct rte_flow_action *pre_actions = NULL; 4103 struct rte_flow_item *sfx_items = NULL; 4104 struct mlx5_flow *dev_flow = NULL; 4105 struct rte_flow_attr sfx_attr = *attr; 4106 uint32_t mtr = 0; 4107 uint32_t mtr_tag_id = 0; 4108 size_t act_size; 4109 size_t item_size; 4110 int actions_n = 0; 4111 int ret; 4112 4113 if (priv->mtr_en) 4114 actions_n = flow_check_meter_action(actions, &mtr); 4115 if (mtr) { 4116 /* The five prefix actions: meter, decap, encap, tag, end. */ 4117 act_size = sizeof(struct rte_flow_action) * (actions_n + 5) + 4118 sizeof(struct mlx5_rte_flow_action_set_tag); 4119 /* tag, vlan, port id, end. */ 4120 #define METER_SUFFIX_ITEM 4 4121 item_size = sizeof(struct rte_flow_item) * METER_SUFFIX_ITEM + 4122 sizeof(struct mlx5_rte_flow_item_tag) * 2; 4123 sfx_actions = rte_zmalloc(__func__, (act_size + item_size), 0); 4124 if (!sfx_actions) 4125 return rte_flow_error_set(error, ENOMEM, 4126 RTE_FLOW_ERROR_TYPE_ACTION, 4127 NULL, "no memory to split " 4128 "meter flow"); 4129 sfx_items = (struct rte_flow_item *)((char *)sfx_actions + 4130 act_size); 4131 pre_actions = sfx_actions + actions_n; 4132 mtr_tag_id = flow_meter_split_prep(dev, items, sfx_items, 4133 actions, sfx_actions, 4134 pre_actions); 4135 if (!mtr_tag_id) { 4136 ret = -rte_errno; 4137 goto exit; 4138 } 4139 /* Add the prefix subflow. */ 4140 ret = flow_create_split_inner(dev, flow, &dev_flow, 0, attr, 4141 items, pre_actions, external, 4142 error); 4143 if (ret) { 4144 ret = -rte_errno; 4145 goto exit; 4146 } 4147 dev_flow->handle->split_flow_id = mtr_tag_id; 4148 /* Setting the sfx group atrr. */ 4149 sfx_attr.group = sfx_attr.transfer ? 4150 (MLX5_FLOW_TABLE_LEVEL_SUFFIX - 1) : 4151 MLX5_FLOW_TABLE_LEVEL_SUFFIX; 4152 } 4153 /* Add the prefix subflow. */ 4154 ret = flow_create_split_metadata(dev, flow, dev_flow ? 4155 flow_get_prefix_layer_flags(dev_flow) : 4156 0, &sfx_attr, 4157 sfx_items ? sfx_items : items, 4158 sfx_actions ? sfx_actions : actions, 4159 external, error); 4160 exit: 4161 if (sfx_actions) 4162 rte_free(sfx_actions); 4163 return ret; 4164 } 4165 4166 /** 4167 * Split the flow to subflow set. The splitters might be linked 4168 * in the chain, like this: 4169 * flow_create_split_outer() calls: 4170 * flow_create_split_meter() calls: 4171 * flow_create_split_metadata(meter_subflow_0) calls: 4172 * flow_create_split_inner(metadata_subflow_0) 4173 * flow_create_split_inner(metadata_subflow_1) 4174 * flow_create_split_inner(metadata_subflow_2) 4175 * flow_create_split_metadata(meter_subflow_1) calls: 4176 * flow_create_split_inner(metadata_subflow_0) 4177 * flow_create_split_inner(metadata_subflow_1) 4178 * flow_create_split_inner(metadata_subflow_2) 4179 * 4180 * This provide flexible way to add new levels of flow splitting. 4181 * The all of successfully created subflows are included to the 4182 * parent flow dev_flow list. 4183 * 4184 * @param dev 4185 * Pointer to Ethernet device. 4186 * @param[in] flow 4187 * Parent flow structure pointer. 4188 * @param[in] attr 4189 * Flow rule attributes. 4190 * @param[in] items 4191 * Pattern specification (list terminated by the END pattern item). 4192 * @param[in] actions 4193 * Associated actions (list terminated by the END action). 4194 * @param[in] external 4195 * This flow rule is created by request external to PMD. 4196 * @param[out] error 4197 * Perform verbose error reporting if not NULL. 4198 * @return 4199 * 0 on success, negative value otherwise 4200 */ 4201 static int 4202 flow_create_split_outer(struct rte_eth_dev *dev, 4203 struct rte_flow *flow, 4204 const struct rte_flow_attr *attr, 4205 const struct rte_flow_item items[], 4206 const struct rte_flow_action actions[], 4207 bool external, struct rte_flow_error *error) 4208 { 4209 int ret; 4210 4211 ret = flow_create_split_meter(dev, flow, attr, items, 4212 actions, external, error); 4213 MLX5_ASSERT(ret <= 0); 4214 return ret; 4215 } 4216 4217 /** 4218 * Create a flow and add it to @p list. 4219 * 4220 * @param dev 4221 * Pointer to Ethernet device. 4222 * @param list 4223 * Pointer to a TAILQ flow list. If this parameter NULL, 4224 * no list insertion occurred, flow is just created, 4225 * this is caller's responsibility to track the 4226 * created flow. 4227 * @param[in] attr 4228 * Flow rule attributes. 4229 * @param[in] items 4230 * Pattern specification (list terminated by the END pattern item). 4231 * @param[in] actions 4232 * Associated actions (list terminated by the END action). 4233 * @param[in] external 4234 * This flow rule is created by request external to PMD. 4235 * @param[out] error 4236 * Perform verbose error reporting if not NULL. 4237 * 4238 * @return 4239 * A flow index on success, 0 otherwise and rte_errno is set. 4240 */ 4241 static uint32_t 4242 flow_list_create(struct rte_eth_dev *dev, uint32_t *list, 4243 const struct rte_flow_attr *attr, 4244 const struct rte_flow_item items[], 4245 const struct rte_flow_action actions[], 4246 bool external, struct rte_flow_error *error) 4247 { 4248 struct mlx5_priv *priv = dev->data->dev_private; 4249 struct rte_flow *flow = NULL; 4250 struct mlx5_flow *dev_flow; 4251 const struct rte_flow_action_rss *rss; 4252 union { 4253 struct rte_flow_expand_rss buf; 4254 uint8_t buffer[2048]; 4255 } expand_buffer; 4256 union { 4257 struct rte_flow_action actions[MLX5_MAX_SPLIT_ACTIONS]; 4258 uint8_t buffer[2048]; 4259 } actions_rx; 4260 union { 4261 struct rte_flow_action actions[MLX5_MAX_SPLIT_ACTIONS]; 4262 uint8_t buffer[2048]; 4263 } actions_hairpin_tx; 4264 union { 4265 struct rte_flow_item items[MLX5_MAX_SPLIT_ITEMS]; 4266 uint8_t buffer[2048]; 4267 } items_tx; 4268 struct rte_flow_expand_rss *buf = &expand_buffer.buf; 4269 struct mlx5_flow_rss_desc *rss_desc = &((struct mlx5_flow_rss_desc *) 4270 priv->rss_desc)[!!priv->flow_idx]; 4271 const struct rte_flow_action *p_actions_rx = actions; 4272 uint32_t i; 4273 uint32_t idx = 0; 4274 int hairpin_flow = 0; 4275 uint32_t hairpin_id = 0; 4276 struct rte_flow_attr attr_tx = { .priority = 0 }; 4277 int ret = flow_drv_validate(dev, attr, items, p_actions_rx, external, 4278 error); 4279 4280 if (ret < 0) 4281 return 0; 4282 hairpin_flow = flow_check_hairpin_split(dev, attr, actions); 4283 if (hairpin_flow > 0) { 4284 if (hairpin_flow > MLX5_MAX_SPLIT_ACTIONS) { 4285 rte_errno = EINVAL; 4286 return 0; 4287 } 4288 flow_hairpin_split(dev, actions, actions_rx.actions, 4289 actions_hairpin_tx.actions, items_tx.items, 4290 &hairpin_id); 4291 p_actions_rx = actions_rx.actions; 4292 } 4293 flow = mlx5_ipool_zmalloc(priv->sh->ipool[MLX5_IPOOL_RTE_FLOW], &idx); 4294 if (!flow) { 4295 rte_errno = ENOMEM; 4296 goto error_before_flow; 4297 } 4298 flow->drv_type = flow_get_drv_type(dev, attr); 4299 if (hairpin_id != 0) 4300 flow->hairpin_flow_id = hairpin_id; 4301 MLX5_ASSERT(flow->drv_type > MLX5_FLOW_TYPE_MIN && 4302 flow->drv_type < MLX5_FLOW_TYPE_MAX); 4303 memset(rss_desc, 0, sizeof(*rss_desc)); 4304 rss = flow_get_rss_action(p_actions_rx); 4305 if (rss) { 4306 /* 4307 * The following information is required by 4308 * mlx5_flow_hashfields_adjust() in advance. 4309 */ 4310 rss_desc->level = rss->level; 4311 /* RSS type 0 indicates default RSS type (ETH_RSS_IP). */ 4312 rss_desc->types = !rss->types ? ETH_RSS_IP : rss->types; 4313 } 4314 flow->dev_handles = 0; 4315 if (rss && rss->types) { 4316 unsigned int graph_root; 4317 4318 graph_root = find_graph_root(items, rss->level); 4319 ret = rte_flow_expand_rss(buf, sizeof(expand_buffer.buffer), 4320 items, rss->types, 4321 mlx5_support_expansion, 4322 graph_root); 4323 MLX5_ASSERT(ret > 0 && 4324 (unsigned int)ret < sizeof(expand_buffer.buffer)); 4325 } else { 4326 buf->entries = 1; 4327 buf->entry[0].pattern = (void *)(uintptr_t)items; 4328 } 4329 /* 4330 * Record the start index when there is a nested call. All sub-flows 4331 * need to be translated before another calling. 4332 * No need to use ping-pong buffer to save memory here. 4333 */ 4334 if (priv->flow_idx) { 4335 MLX5_ASSERT(!priv->flow_nested_idx); 4336 priv->flow_nested_idx = priv->flow_idx; 4337 } 4338 for (i = 0; i < buf->entries; ++i) { 4339 /* 4340 * The splitter may create multiple dev_flows, 4341 * depending on configuration. In the simplest 4342 * case it just creates unmodified original flow. 4343 */ 4344 ret = flow_create_split_outer(dev, flow, attr, 4345 buf->entry[i].pattern, 4346 p_actions_rx, external, 4347 error); 4348 if (ret < 0) 4349 goto error; 4350 } 4351 /* Create the tx flow. */ 4352 if (hairpin_flow) { 4353 attr_tx.group = MLX5_HAIRPIN_TX_TABLE; 4354 attr_tx.ingress = 0; 4355 attr_tx.egress = 1; 4356 dev_flow = flow_drv_prepare(dev, flow, &attr_tx, items_tx.items, 4357 actions_hairpin_tx.actions, error); 4358 if (!dev_flow) 4359 goto error; 4360 dev_flow->flow = flow; 4361 dev_flow->external = 0; 4362 SILIST_INSERT(&flow->dev_handles, dev_flow->handle_idx, 4363 dev_flow->handle, next); 4364 ret = flow_drv_translate(dev, dev_flow, &attr_tx, 4365 items_tx.items, 4366 actions_hairpin_tx.actions, error); 4367 if (ret < 0) 4368 goto error; 4369 } 4370 /* 4371 * Update the metadata register copy table. If extensive 4372 * metadata feature is enabled and registers are supported 4373 * we might create the extra rte_flow for each unique 4374 * MARK/FLAG action ID. 4375 * 4376 * The table is updated for ingress Flows only, because 4377 * the egress Flows belong to the different device and 4378 * copy table should be updated in peer NIC Rx domain. 4379 */ 4380 if (attr->ingress && 4381 (external || attr->group != MLX5_FLOW_MREG_CP_TABLE_GROUP)) { 4382 ret = flow_mreg_update_copy_table(dev, flow, actions, error); 4383 if (ret) 4384 goto error; 4385 } 4386 /* 4387 * If the flow is external (from application) OR device is started, then 4388 * the flow will be applied immediately. 4389 */ 4390 if (external || dev->data->dev_started) { 4391 ret = flow_drv_apply(dev, flow, error); 4392 if (ret < 0) 4393 goto error; 4394 } 4395 if (list) 4396 ILIST_INSERT(priv->sh->ipool[MLX5_IPOOL_RTE_FLOW], list, idx, 4397 flow, next); 4398 flow_rxq_flags_set(dev, flow); 4399 /* Nested flow creation index recovery. */ 4400 priv->flow_idx = priv->flow_nested_idx; 4401 if (priv->flow_nested_idx) 4402 priv->flow_nested_idx = 0; 4403 return idx; 4404 error: 4405 MLX5_ASSERT(flow); 4406 ret = rte_errno; /* Save rte_errno before cleanup. */ 4407 flow_mreg_del_copy_action(dev, flow); 4408 flow_drv_destroy(dev, flow); 4409 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_RTE_FLOW], idx); 4410 rte_errno = ret; /* Restore rte_errno. */ 4411 error_before_flow: 4412 ret = rte_errno; 4413 if (hairpin_id) 4414 mlx5_flow_id_release(priv->sh->flow_id_pool, 4415 hairpin_id); 4416 rte_errno = ret; 4417 priv->flow_idx = priv->flow_nested_idx; 4418 if (priv->flow_nested_idx) 4419 priv->flow_nested_idx = 0; 4420 return 0; 4421 } 4422 4423 /** 4424 * Create a dedicated flow rule on e-switch table 0 (root table), to direct all 4425 * incoming packets to table 1. 4426 * 4427 * Other flow rules, requested for group n, will be created in 4428 * e-switch table n+1. 4429 * Jump action to e-switch group n will be created to group n+1. 4430 * 4431 * Used when working in switchdev mode, to utilise advantages of table 1 4432 * and above. 4433 * 4434 * @param dev 4435 * Pointer to Ethernet device. 4436 * 4437 * @return 4438 * Pointer to flow on success, NULL otherwise and rte_errno is set. 4439 */ 4440 struct rte_flow * 4441 mlx5_flow_create_esw_table_zero_flow(struct rte_eth_dev *dev) 4442 { 4443 const struct rte_flow_attr attr = { 4444 .group = 0, 4445 .priority = 0, 4446 .ingress = 1, 4447 .egress = 0, 4448 .transfer = 1, 4449 }; 4450 const struct rte_flow_item pattern = { 4451 .type = RTE_FLOW_ITEM_TYPE_END, 4452 }; 4453 struct rte_flow_action_jump jump = { 4454 .group = 1, 4455 }; 4456 const struct rte_flow_action actions[] = { 4457 { 4458 .type = RTE_FLOW_ACTION_TYPE_JUMP, 4459 .conf = &jump, 4460 }, 4461 { 4462 .type = RTE_FLOW_ACTION_TYPE_END, 4463 }, 4464 }; 4465 struct mlx5_priv *priv = dev->data->dev_private; 4466 struct rte_flow_error error; 4467 4468 return (void *)(uintptr_t)flow_list_create(dev, &priv->ctrl_flows, 4469 &attr, &pattern, 4470 actions, false, &error); 4471 } 4472 4473 /** 4474 * Create a flow. 4475 * 4476 * @see rte_flow_create() 4477 * @see rte_flow_ops 4478 */ 4479 struct rte_flow * 4480 mlx5_flow_create(struct rte_eth_dev *dev, 4481 const struct rte_flow_attr *attr, 4482 const struct rte_flow_item items[], 4483 const struct rte_flow_action actions[], 4484 struct rte_flow_error *error) 4485 { 4486 struct mlx5_priv *priv = dev->data->dev_private; 4487 4488 /* 4489 * If the device is not started yet, it is not allowed to created a 4490 * flow from application. PMD default flows and traffic control flows 4491 * are not affected. 4492 */ 4493 if (unlikely(!dev->data->dev_started)) { 4494 rte_errno = ENODEV; 4495 DRV_LOG(DEBUG, "port %u is not started when " 4496 "inserting a flow", dev->data->port_id); 4497 return NULL; 4498 } 4499 return (void *)(uintptr_t)flow_list_create(dev, &priv->flows, 4500 attr, items, actions, true, error); 4501 } 4502 4503 /** 4504 * Destroy a flow in a list. 4505 * 4506 * @param dev 4507 * Pointer to Ethernet device. 4508 * @param list 4509 * Pointer to the Indexed flow list. If this parameter NULL, 4510 * there is no flow removal from the list. Be noted that as 4511 * flow is add to the indexed list, memory of the indexed 4512 * list points to maybe changed as flow destroyed. 4513 * @param[in] flow_idx 4514 * Index of flow to destroy. 4515 */ 4516 static void 4517 flow_list_destroy(struct rte_eth_dev *dev, uint32_t *list, 4518 uint32_t flow_idx) 4519 { 4520 struct mlx5_priv *priv = dev->data->dev_private; 4521 struct mlx5_fdir_flow *priv_fdir_flow = NULL; 4522 struct rte_flow *flow = mlx5_ipool_get(priv->sh->ipool 4523 [MLX5_IPOOL_RTE_FLOW], flow_idx); 4524 4525 if (!flow) 4526 return; 4527 /* 4528 * Update RX queue flags only if port is started, otherwise it is 4529 * already clean. 4530 */ 4531 if (dev->data->dev_started) 4532 flow_rxq_flags_trim(dev, flow); 4533 if (flow->hairpin_flow_id) 4534 mlx5_flow_id_release(priv->sh->flow_id_pool, 4535 flow->hairpin_flow_id); 4536 flow_drv_destroy(dev, flow); 4537 if (list) 4538 ILIST_REMOVE(priv->sh->ipool[MLX5_IPOOL_RTE_FLOW], list, 4539 flow_idx, flow, next); 4540 flow_mreg_del_copy_action(dev, flow); 4541 if (flow->fdir) { 4542 LIST_FOREACH(priv_fdir_flow, &priv->fdir_flows, next) { 4543 if (priv_fdir_flow->rix_flow == flow_idx) 4544 break; 4545 } 4546 if (priv_fdir_flow) { 4547 LIST_REMOVE(priv_fdir_flow, next); 4548 rte_free(priv_fdir_flow->fdir); 4549 rte_free(priv_fdir_flow); 4550 } 4551 } 4552 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_RTE_FLOW], flow_idx); 4553 } 4554 4555 /** 4556 * Destroy all flows. 4557 * 4558 * @param dev 4559 * Pointer to Ethernet device. 4560 * @param list 4561 * Pointer to the Indexed flow list. 4562 * @param active 4563 * If flushing is called avtively. 4564 */ 4565 void 4566 mlx5_flow_list_flush(struct rte_eth_dev *dev, uint32_t *list, bool active) 4567 { 4568 uint32_t num_flushed = 0; 4569 4570 while (*list) { 4571 flow_list_destroy(dev, list, *list); 4572 num_flushed++; 4573 } 4574 if (active) { 4575 DRV_LOG(INFO, "port %u: %u flows flushed before stopping", 4576 dev->data->port_id, num_flushed); 4577 } 4578 } 4579 4580 /** 4581 * Remove all flows. 4582 * 4583 * @param dev 4584 * Pointer to Ethernet device. 4585 * @param list 4586 * Pointer to the Indexed flow list. 4587 */ 4588 void 4589 mlx5_flow_stop(struct rte_eth_dev *dev, uint32_t *list) 4590 { 4591 struct mlx5_priv *priv = dev->data->dev_private; 4592 struct rte_flow *flow = NULL; 4593 uint32_t idx; 4594 4595 ILIST_FOREACH(priv->sh->ipool[MLX5_IPOOL_RTE_FLOW], *list, idx, 4596 flow, next) { 4597 flow_drv_remove(dev, flow); 4598 flow_mreg_stop_copy_action(dev, flow); 4599 } 4600 flow_mreg_del_default_copy_action(dev); 4601 flow_rxq_flags_clear(dev); 4602 } 4603 4604 /** 4605 * Add all flows. 4606 * 4607 * @param dev 4608 * Pointer to Ethernet device. 4609 * @param list 4610 * Pointer to the Indexed flow list. 4611 * 4612 * @return 4613 * 0 on success, a negative errno value otherwise and rte_errno is set. 4614 */ 4615 int 4616 mlx5_flow_start(struct rte_eth_dev *dev, uint32_t *list) 4617 { 4618 struct mlx5_priv *priv = dev->data->dev_private; 4619 struct rte_flow *flow = NULL; 4620 struct rte_flow_error error; 4621 uint32_t idx; 4622 int ret = 0; 4623 4624 /* Make sure default copy action (reg_c[0] -> reg_b) is created. */ 4625 ret = flow_mreg_add_default_copy_action(dev, &error); 4626 if (ret < 0) 4627 return -rte_errno; 4628 /* Apply Flows created by application. */ 4629 ILIST_FOREACH(priv->sh->ipool[MLX5_IPOOL_RTE_FLOW], *list, idx, 4630 flow, next) { 4631 ret = flow_mreg_start_copy_action(dev, flow); 4632 if (ret < 0) 4633 goto error; 4634 ret = flow_drv_apply(dev, flow, &error); 4635 if (ret < 0) 4636 goto error; 4637 flow_rxq_flags_set(dev, flow); 4638 } 4639 return 0; 4640 error: 4641 ret = rte_errno; /* Save rte_errno before cleanup. */ 4642 mlx5_flow_stop(dev, list); 4643 rte_errno = ret; /* Restore rte_errno. */ 4644 return -rte_errno; 4645 } 4646 4647 /** 4648 * Stop all default actions for flows. 4649 * 4650 * @param dev 4651 * Pointer to Ethernet device. 4652 */ 4653 void 4654 mlx5_flow_stop_default(struct rte_eth_dev *dev) 4655 { 4656 flow_mreg_del_default_copy_action(dev); 4657 } 4658 4659 /** 4660 * Start all default actions for flows. 4661 * 4662 * @param dev 4663 * Pointer to Ethernet device. 4664 * @return 4665 * 0 on success, a negative errno value otherwise and rte_errno is set. 4666 */ 4667 int 4668 mlx5_flow_start_default(struct rte_eth_dev *dev) 4669 { 4670 struct rte_flow_error error; 4671 4672 /* Make sure default copy action (reg_c[0] -> reg_b) is created. */ 4673 return flow_mreg_add_default_copy_action(dev, &error); 4674 } 4675 4676 /** 4677 * Allocate intermediate resources for flow creation. 4678 * 4679 * @param dev 4680 * Pointer to Ethernet device. 4681 */ 4682 void 4683 mlx5_flow_alloc_intermediate(struct rte_eth_dev *dev) 4684 { 4685 struct mlx5_priv *priv = dev->data->dev_private; 4686 4687 if (!priv->inter_flows) { 4688 priv->inter_flows = rte_calloc(__func__, 1, 4689 MLX5_NUM_MAX_DEV_FLOWS * 4690 sizeof(struct mlx5_flow) + 4691 (sizeof(struct mlx5_flow_rss_desc) + 4692 sizeof(uint16_t) * UINT16_MAX) * 2, 0); 4693 if (!priv->inter_flows) { 4694 DRV_LOG(ERR, "can't allocate intermediate memory."); 4695 return; 4696 } 4697 } 4698 priv->rss_desc = &((struct mlx5_flow *)priv->inter_flows) 4699 [MLX5_NUM_MAX_DEV_FLOWS]; 4700 /* Reset the index. */ 4701 priv->flow_idx = 0; 4702 priv->flow_nested_idx = 0; 4703 } 4704 4705 /** 4706 * Free intermediate resources for flows. 4707 * 4708 * @param dev 4709 * Pointer to Ethernet device. 4710 */ 4711 void 4712 mlx5_flow_free_intermediate(struct rte_eth_dev *dev) 4713 { 4714 struct mlx5_priv *priv = dev->data->dev_private; 4715 4716 rte_free(priv->inter_flows); 4717 priv->inter_flows = NULL; 4718 } 4719 4720 /** 4721 * Verify the flow list is empty 4722 * 4723 * @param dev 4724 * Pointer to Ethernet device. 4725 * 4726 * @return the number of flows not released. 4727 */ 4728 int 4729 mlx5_flow_verify(struct rte_eth_dev *dev) 4730 { 4731 struct mlx5_priv *priv = dev->data->dev_private; 4732 struct rte_flow *flow; 4733 uint32_t idx; 4734 int ret = 0; 4735 4736 ILIST_FOREACH(priv->sh->ipool[MLX5_IPOOL_RTE_FLOW], priv->flows, idx, 4737 flow, next) { 4738 DRV_LOG(DEBUG, "port %u flow %p still referenced", 4739 dev->data->port_id, (void *)flow); 4740 ++ret; 4741 } 4742 return ret; 4743 } 4744 4745 /** 4746 * Enable default hairpin egress flow. 4747 * 4748 * @param dev 4749 * Pointer to Ethernet device. 4750 * @param queue 4751 * The queue index. 4752 * 4753 * @return 4754 * 0 on success, a negative errno value otherwise and rte_errno is set. 4755 */ 4756 int 4757 mlx5_ctrl_flow_source_queue(struct rte_eth_dev *dev, 4758 uint32_t queue) 4759 { 4760 struct mlx5_priv *priv = dev->data->dev_private; 4761 const struct rte_flow_attr attr = { 4762 .egress = 1, 4763 .priority = 0, 4764 }; 4765 struct mlx5_rte_flow_item_tx_queue queue_spec = { 4766 .queue = queue, 4767 }; 4768 struct mlx5_rte_flow_item_tx_queue queue_mask = { 4769 .queue = UINT32_MAX, 4770 }; 4771 struct rte_flow_item items[] = { 4772 { 4773 .type = MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE, 4774 .spec = &queue_spec, 4775 .last = NULL, 4776 .mask = &queue_mask, 4777 }, 4778 { 4779 .type = RTE_FLOW_ITEM_TYPE_END, 4780 }, 4781 }; 4782 struct rte_flow_action_jump jump = { 4783 .group = MLX5_HAIRPIN_TX_TABLE, 4784 }; 4785 struct rte_flow_action actions[2]; 4786 uint32_t flow_idx; 4787 struct rte_flow_error error; 4788 4789 actions[0].type = RTE_FLOW_ACTION_TYPE_JUMP; 4790 actions[0].conf = &jump; 4791 actions[1].type = RTE_FLOW_ACTION_TYPE_END; 4792 flow_idx = flow_list_create(dev, &priv->ctrl_flows, 4793 &attr, items, actions, false, &error); 4794 if (!flow_idx) { 4795 DRV_LOG(DEBUG, 4796 "Failed to create ctrl flow: rte_errno(%d)," 4797 " type(%d), message(%s)", 4798 rte_errno, error.type, 4799 error.message ? error.message : " (no stated reason)"); 4800 return -rte_errno; 4801 } 4802 return 0; 4803 } 4804 4805 /** 4806 * Enable a control flow configured from the control plane. 4807 * 4808 * @param dev 4809 * Pointer to Ethernet device. 4810 * @param eth_spec 4811 * An Ethernet flow spec to apply. 4812 * @param eth_mask 4813 * An Ethernet flow mask to apply. 4814 * @param vlan_spec 4815 * A VLAN flow spec to apply. 4816 * @param vlan_mask 4817 * A VLAN flow mask to apply. 4818 * 4819 * @return 4820 * 0 on success, a negative errno value otherwise and rte_errno is set. 4821 */ 4822 int 4823 mlx5_ctrl_flow_vlan(struct rte_eth_dev *dev, 4824 struct rte_flow_item_eth *eth_spec, 4825 struct rte_flow_item_eth *eth_mask, 4826 struct rte_flow_item_vlan *vlan_spec, 4827 struct rte_flow_item_vlan *vlan_mask) 4828 { 4829 struct mlx5_priv *priv = dev->data->dev_private; 4830 const struct rte_flow_attr attr = { 4831 .ingress = 1, 4832 .priority = MLX5_FLOW_PRIO_RSVD, 4833 }; 4834 struct rte_flow_item items[] = { 4835 { 4836 .type = RTE_FLOW_ITEM_TYPE_ETH, 4837 .spec = eth_spec, 4838 .last = NULL, 4839 .mask = eth_mask, 4840 }, 4841 { 4842 .type = (vlan_spec) ? RTE_FLOW_ITEM_TYPE_VLAN : 4843 RTE_FLOW_ITEM_TYPE_END, 4844 .spec = vlan_spec, 4845 .last = NULL, 4846 .mask = vlan_mask, 4847 }, 4848 { 4849 .type = RTE_FLOW_ITEM_TYPE_END, 4850 }, 4851 }; 4852 uint16_t queue[priv->reta_idx_n]; 4853 struct rte_flow_action_rss action_rss = { 4854 .func = RTE_ETH_HASH_FUNCTION_DEFAULT, 4855 .level = 0, 4856 .types = priv->rss_conf.rss_hf, 4857 .key_len = priv->rss_conf.rss_key_len, 4858 .queue_num = priv->reta_idx_n, 4859 .key = priv->rss_conf.rss_key, 4860 .queue = queue, 4861 }; 4862 struct rte_flow_action actions[] = { 4863 { 4864 .type = RTE_FLOW_ACTION_TYPE_RSS, 4865 .conf = &action_rss, 4866 }, 4867 { 4868 .type = RTE_FLOW_ACTION_TYPE_END, 4869 }, 4870 }; 4871 uint32_t flow_idx; 4872 struct rte_flow_error error; 4873 unsigned int i; 4874 4875 if (!priv->reta_idx_n || !priv->rxqs_n) { 4876 return 0; 4877 } 4878 for (i = 0; i != priv->reta_idx_n; ++i) 4879 queue[i] = (*priv->reta_idx)[i]; 4880 flow_idx = flow_list_create(dev, &priv->ctrl_flows, 4881 &attr, items, actions, false, &error); 4882 if (!flow_idx) 4883 return -rte_errno; 4884 return 0; 4885 } 4886 4887 /** 4888 * Enable a flow control configured from the control plane. 4889 * 4890 * @param dev 4891 * Pointer to Ethernet device. 4892 * @param eth_spec 4893 * An Ethernet flow spec to apply. 4894 * @param eth_mask 4895 * An Ethernet flow mask to apply. 4896 * 4897 * @return 4898 * 0 on success, a negative errno value otherwise and rte_errno is set. 4899 */ 4900 int 4901 mlx5_ctrl_flow(struct rte_eth_dev *dev, 4902 struct rte_flow_item_eth *eth_spec, 4903 struct rte_flow_item_eth *eth_mask) 4904 { 4905 return mlx5_ctrl_flow_vlan(dev, eth_spec, eth_mask, NULL, NULL); 4906 } 4907 4908 /** 4909 * Destroy a flow. 4910 * 4911 * @see rte_flow_destroy() 4912 * @see rte_flow_ops 4913 */ 4914 int 4915 mlx5_flow_destroy(struct rte_eth_dev *dev, 4916 struct rte_flow *flow, 4917 struct rte_flow_error *error __rte_unused) 4918 { 4919 struct mlx5_priv *priv = dev->data->dev_private; 4920 4921 flow_list_destroy(dev, &priv->flows, (uintptr_t)(void *)flow); 4922 return 0; 4923 } 4924 4925 /** 4926 * Destroy all flows. 4927 * 4928 * @see rte_flow_flush() 4929 * @see rte_flow_ops 4930 */ 4931 int 4932 mlx5_flow_flush(struct rte_eth_dev *dev, 4933 struct rte_flow_error *error __rte_unused) 4934 { 4935 struct mlx5_priv *priv = dev->data->dev_private; 4936 4937 mlx5_flow_list_flush(dev, &priv->flows, false); 4938 return 0; 4939 } 4940 4941 /** 4942 * Isolated mode. 4943 * 4944 * @see rte_flow_isolate() 4945 * @see rte_flow_ops 4946 */ 4947 int 4948 mlx5_flow_isolate(struct rte_eth_dev *dev, 4949 int enable, 4950 struct rte_flow_error *error) 4951 { 4952 struct mlx5_priv *priv = dev->data->dev_private; 4953 4954 if (dev->data->dev_started) { 4955 rte_flow_error_set(error, EBUSY, 4956 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, 4957 NULL, 4958 "port must be stopped first"); 4959 return -rte_errno; 4960 } 4961 priv->isolated = !!enable; 4962 if (enable) 4963 dev->dev_ops = &mlx5_dev_ops_isolate; 4964 else 4965 dev->dev_ops = &mlx5_dev_ops; 4966 return 0; 4967 } 4968 4969 /** 4970 * Query a flow. 4971 * 4972 * @see rte_flow_query() 4973 * @see rte_flow_ops 4974 */ 4975 static int 4976 flow_drv_query(struct rte_eth_dev *dev, 4977 uint32_t flow_idx, 4978 const struct rte_flow_action *actions, 4979 void *data, 4980 struct rte_flow_error *error) 4981 { 4982 struct mlx5_priv *priv = dev->data->dev_private; 4983 const struct mlx5_flow_driver_ops *fops; 4984 struct rte_flow *flow = mlx5_ipool_get(priv->sh->ipool 4985 [MLX5_IPOOL_RTE_FLOW], 4986 flow_idx); 4987 enum mlx5_flow_drv_type ftype; 4988 4989 if (!flow) { 4990 return rte_flow_error_set(error, ENOENT, 4991 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, 4992 NULL, 4993 "invalid flow handle"); 4994 } 4995 ftype = flow->drv_type; 4996 MLX5_ASSERT(ftype > MLX5_FLOW_TYPE_MIN && ftype < MLX5_FLOW_TYPE_MAX); 4997 fops = flow_get_drv_ops(ftype); 4998 4999 return fops->query(dev, flow, actions, data, error); 5000 } 5001 5002 /** 5003 * Query a flow. 5004 * 5005 * @see rte_flow_query() 5006 * @see rte_flow_ops 5007 */ 5008 int 5009 mlx5_flow_query(struct rte_eth_dev *dev, 5010 struct rte_flow *flow, 5011 const struct rte_flow_action *actions, 5012 void *data, 5013 struct rte_flow_error *error) 5014 { 5015 int ret; 5016 5017 ret = flow_drv_query(dev, (uintptr_t)(void *)flow, actions, data, 5018 error); 5019 if (ret < 0) 5020 return ret; 5021 return 0; 5022 } 5023 5024 /** 5025 * Convert a flow director filter to a generic flow. 5026 * 5027 * @param dev 5028 * Pointer to Ethernet device. 5029 * @param fdir_filter 5030 * Flow director filter to add. 5031 * @param attributes 5032 * Generic flow parameters structure. 5033 * 5034 * @return 5035 * 0 on success, a negative errno value otherwise and rte_errno is set. 5036 */ 5037 static int 5038 flow_fdir_filter_convert(struct rte_eth_dev *dev, 5039 const struct rte_eth_fdir_filter *fdir_filter, 5040 struct mlx5_fdir *attributes) 5041 { 5042 struct mlx5_priv *priv = dev->data->dev_private; 5043 const struct rte_eth_fdir_input *input = &fdir_filter->input; 5044 const struct rte_eth_fdir_masks *mask = 5045 &dev->data->dev_conf.fdir_conf.mask; 5046 5047 /* Validate queue number. */ 5048 if (fdir_filter->action.rx_queue >= priv->rxqs_n) { 5049 DRV_LOG(ERR, "port %u invalid queue number %d", 5050 dev->data->port_id, fdir_filter->action.rx_queue); 5051 rte_errno = EINVAL; 5052 return -rte_errno; 5053 } 5054 attributes->attr.ingress = 1; 5055 attributes->items[0] = (struct rte_flow_item) { 5056 .type = RTE_FLOW_ITEM_TYPE_ETH, 5057 .spec = &attributes->l2, 5058 .mask = &attributes->l2_mask, 5059 }; 5060 switch (fdir_filter->action.behavior) { 5061 case RTE_ETH_FDIR_ACCEPT: 5062 attributes->actions[0] = (struct rte_flow_action){ 5063 .type = RTE_FLOW_ACTION_TYPE_QUEUE, 5064 .conf = &attributes->queue, 5065 }; 5066 break; 5067 case RTE_ETH_FDIR_REJECT: 5068 attributes->actions[0] = (struct rte_flow_action){ 5069 .type = RTE_FLOW_ACTION_TYPE_DROP, 5070 }; 5071 break; 5072 default: 5073 DRV_LOG(ERR, "port %u invalid behavior %d", 5074 dev->data->port_id, 5075 fdir_filter->action.behavior); 5076 rte_errno = ENOTSUP; 5077 return -rte_errno; 5078 } 5079 attributes->queue.index = fdir_filter->action.rx_queue; 5080 /* Handle L3. */ 5081 switch (fdir_filter->input.flow_type) { 5082 case RTE_ETH_FLOW_NONFRAG_IPV4_UDP: 5083 case RTE_ETH_FLOW_NONFRAG_IPV4_TCP: 5084 case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER: 5085 attributes->l3.ipv4.hdr = (struct rte_ipv4_hdr){ 5086 .src_addr = input->flow.ip4_flow.src_ip, 5087 .dst_addr = input->flow.ip4_flow.dst_ip, 5088 .time_to_live = input->flow.ip4_flow.ttl, 5089 .type_of_service = input->flow.ip4_flow.tos, 5090 }; 5091 attributes->l3_mask.ipv4.hdr = (struct rte_ipv4_hdr){ 5092 .src_addr = mask->ipv4_mask.src_ip, 5093 .dst_addr = mask->ipv4_mask.dst_ip, 5094 .time_to_live = mask->ipv4_mask.ttl, 5095 .type_of_service = mask->ipv4_mask.tos, 5096 .next_proto_id = mask->ipv4_mask.proto, 5097 }; 5098 attributes->items[1] = (struct rte_flow_item){ 5099 .type = RTE_FLOW_ITEM_TYPE_IPV4, 5100 .spec = &attributes->l3, 5101 .mask = &attributes->l3_mask, 5102 }; 5103 break; 5104 case RTE_ETH_FLOW_NONFRAG_IPV6_UDP: 5105 case RTE_ETH_FLOW_NONFRAG_IPV6_TCP: 5106 case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER: 5107 attributes->l3.ipv6.hdr = (struct rte_ipv6_hdr){ 5108 .hop_limits = input->flow.ipv6_flow.hop_limits, 5109 .proto = input->flow.ipv6_flow.proto, 5110 }; 5111 5112 memcpy(attributes->l3.ipv6.hdr.src_addr, 5113 input->flow.ipv6_flow.src_ip, 5114 RTE_DIM(attributes->l3.ipv6.hdr.src_addr)); 5115 memcpy(attributes->l3.ipv6.hdr.dst_addr, 5116 input->flow.ipv6_flow.dst_ip, 5117 RTE_DIM(attributes->l3.ipv6.hdr.src_addr)); 5118 memcpy(attributes->l3_mask.ipv6.hdr.src_addr, 5119 mask->ipv6_mask.src_ip, 5120 RTE_DIM(attributes->l3_mask.ipv6.hdr.src_addr)); 5121 memcpy(attributes->l3_mask.ipv6.hdr.dst_addr, 5122 mask->ipv6_mask.dst_ip, 5123 RTE_DIM(attributes->l3_mask.ipv6.hdr.src_addr)); 5124 attributes->items[1] = (struct rte_flow_item){ 5125 .type = RTE_FLOW_ITEM_TYPE_IPV6, 5126 .spec = &attributes->l3, 5127 .mask = &attributes->l3_mask, 5128 }; 5129 break; 5130 default: 5131 DRV_LOG(ERR, "port %u invalid flow type%d", 5132 dev->data->port_id, fdir_filter->input.flow_type); 5133 rte_errno = ENOTSUP; 5134 return -rte_errno; 5135 } 5136 /* Handle L4. */ 5137 switch (fdir_filter->input.flow_type) { 5138 case RTE_ETH_FLOW_NONFRAG_IPV4_UDP: 5139 attributes->l4.udp.hdr = (struct rte_udp_hdr){ 5140 .src_port = input->flow.udp4_flow.src_port, 5141 .dst_port = input->flow.udp4_flow.dst_port, 5142 }; 5143 attributes->l4_mask.udp.hdr = (struct rte_udp_hdr){ 5144 .src_port = mask->src_port_mask, 5145 .dst_port = mask->dst_port_mask, 5146 }; 5147 attributes->items[2] = (struct rte_flow_item){ 5148 .type = RTE_FLOW_ITEM_TYPE_UDP, 5149 .spec = &attributes->l4, 5150 .mask = &attributes->l4_mask, 5151 }; 5152 break; 5153 case RTE_ETH_FLOW_NONFRAG_IPV4_TCP: 5154 attributes->l4.tcp.hdr = (struct rte_tcp_hdr){ 5155 .src_port = input->flow.tcp4_flow.src_port, 5156 .dst_port = input->flow.tcp4_flow.dst_port, 5157 }; 5158 attributes->l4_mask.tcp.hdr = (struct rte_tcp_hdr){ 5159 .src_port = mask->src_port_mask, 5160 .dst_port = mask->dst_port_mask, 5161 }; 5162 attributes->items[2] = (struct rte_flow_item){ 5163 .type = RTE_FLOW_ITEM_TYPE_TCP, 5164 .spec = &attributes->l4, 5165 .mask = &attributes->l4_mask, 5166 }; 5167 break; 5168 case RTE_ETH_FLOW_NONFRAG_IPV6_UDP: 5169 attributes->l4.udp.hdr = (struct rte_udp_hdr){ 5170 .src_port = input->flow.udp6_flow.src_port, 5171 .dst_port = input->flow.udp6_flow.dst_port, 5172 }; 5173 attributes->l4_mask.udp.hdr = (struct rte_udp_hdr){ 5174 .src_port = mask->src_port_mask, 5175 .dst_port = mask->dst_port_mask, 5176 }; 5177 attributes->items[2] = (struct rte_flow_item){ 5178 .type = RTE_FLOW_ITEM_TYPE_UDP, 5179 .spec = &attributes->l4, 5180 .mask = &attributes->l4_mask, 5181 }; 5182 break; 5183 case RTE_ETH_FLOW_NONFRAG_IPV6_TCP: 5184 attributes->l4.tcp.hdr = (struct rte_tcp_hdr){ 5185 .src_port = input->flow.tcp6_flow.src_port, 5186 .dst_port = input->flow.tcp6_flow.dst_port, 5187 }; 5188 attributes->l4_mask.tcp.hdr = (struct rte_tcp_hdr){ 5189 .src_port = mask->src_port_mask, 5190 .dst_port = mask->dst_port_mask, 5191 }; 5192 attributes->items[2] = (struct rte_flow_item){ 5193 .type = RTE_FLOW_ITEM_TYPE_TCP, 5194 .spec = &attributes->l4, 5195 .mask = &attributes->l4_mask, 5196 }; 5197 break; 5198 case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER: 5199 case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER: 5200 break; 5201 default: 5202 DRV_LOG(ERR, "port %u invalid flow type%d", 5203 dev->data->port_id, fdir_filter->input.flow_type); 5204 rte_errno = ENOTSUP; 5205 return -rte_errno; 5206 } 5207 return 0; 5208 } 5209 5210 #define FLOW_FDIR_CMP(f1, f2, fld) \ 5211 memcmp(&(f1)->fld, &(f2)->fld, sizeof(f1->fld)) 5212 5213 /** 5214 * Compare two FDIR flows. If items and actions are identical, the two flows are 5215 * regarded as same. 5216 * 5217 * @param dev 5218 * Pointer to Ethernet device. 5219 * @param f1 5220 * FDIR flow to compare. 5221 * @param f2 5222 * FDIR flow to compare. 5223 * 5224 * @return 5225 * Zero on match, 1 otherwise. 5226 */ 5227 static int 5228 flow_fdir_cmp(const struct mlx5_fdir *f1, const struct mlx5_fdir *f2) 5229 { 5230 if (FLOW_FDIR_CMP(f1, f2, attr) || 5231 FLOW_FDIR_CMP(f1, f2, l2) || 5232 FLOW_FDIR_CMP(f1, f2, l2_mask) || 5233 FLOW_FDIR_CMP(f1, f2, l3) || 5234 FLOW_FDIR_CMP(f1, f2, l3_mask) || 5235 FLOW_FDIR_CMP(f1, f2, l4) || 5236 FLOW_FDIR_CMP(f1, f2, l4_mask) || 5237 FLOW_FDIR_CMP(f1, f2, actions[0].type)) 5238 return 1; 5239 if (f1->actions[0].type == RTE_FLOW_ACTION_TYPE_QUEUE && 5240 FLOW_FDIR_CMP(f1, f2, queue)) 5241 return 1; 5242 return 0; 5243 } 5244 5245 /** 5246 * Search device flow list to find out a matched FDIR flow. 5247 * 5248 * @param dev 5249 * Pointer to Ethernet device. 5250 * @param fdir_flow 5251 * FDIR flow to lookup. 5252 * 5253 * @return 5254 * Index of flow if found, 0 otherwise. 5255 */ 5256 static uint32_t 5257 flow_fdir_filter_lookup(struct rte_eth_dev *dev, struct mlx5_fdir *fdir_flow) 5258 { 5259 struct mlx5_priv *priv = dev->data->dev_private; 5260 uint32_t flow_idx = 0; 5261 struct mlx5_fdir_flow *priv_fdir_flow = NULL; 5262 5263 MLX5_ASSERT(fdir_flow); 5264 LIST_FOREACH(priv_fdir_flow, &priv->fdir_flows, next) { 5265 if (!flow_fdir_cmp(priv_fdir_flow->fdir, fdir_flow)) { 5266 DRV_LOG(DEBUG, "port %u found FDIR flow %u", 5267 dev->data->port_id, flow_idx); 5268 flow_idx = priv_fdir_flow->rix_flow; 5269 break; 5270 } 5271 } 5272 return flow_idx; 5273 } 5274 5275 /** 5276 * Add new flow director filter and store it in list. 5277 * 5278 * @param dev 5279 * Pointer to Ethernet device. 5280 * @param fdir_filter 5281 * Flow director filter to add. 5282 * 5283 * @return 5284 * 0 on success, a negative errno value otherwise and rte_errno is set. 5285 */ 5286 static int 5287 flow_fdir_filter_add(struct rte_eth_dev *dev, 5288 const struct rte_eth_fdir_filter *fdir_filter) 5289 { 5290 struct mlx5_priv *priv = dev->data->dev_private; 5291 struct mlx5_fdir *fdir_flow; 5292 struct rte_flow *flow; 5293 struct mlx5_fdir_flow *priv_fdir_flow = NULL; 5294 uint32_t flow_idx; 5295 int ret; 5296 5297 fdir_flow = rte_zmalloc(__func__, sizeof(*fdir_flow), 0); 5298 if (!fdir_flow) { 5299 rte_errno = ENOMEM; 5300 return -rte_errno; 5301 } 5302 ret = flow_fdir_filter_convert(dev, fdir_filter, fdir_flow); 5303 if (ret) 5304 goto error; 5305 flow_idx = flow_fdir_filter_lookup(dev, fdir_flow); 5306 if (flow_idx) { 5307 rte_errno = EEXIST; 5308 goto error; 5309 } 5310 priv_fdir_flow = rte_zmalloc(__func__, sizeof(struct mlx5_fdir_flow), 5311 0); 5312 if (!priv_fdir_flow) { 5313 rte_errno = ENOMEM; 5314 goto error; 5315 } 5316 flow_idx = flow_list_create(dev, &priv->flows, &fdir_flow->attr, 5317 fdir_flow->items, fdir_flow->actions, true, 5318 NULL); 5319 flow = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_RTE_FLOW], flow_idx); 5320 if (!flow) 5321 goto error; 5322 flow->fdir = 1; 5323 priv_fdir_flow->fdir = fdir_flow; 5324 priv_fdir_flow->rix_flow = flow_idx; 5325 LIST_INSERT_HEAD(&priv->fdir_flows, priv_fdir_flow, next); 5326 DRV_LOG(DEBUG, "port %u created FDIR flow %p", 5327 dev->data->port_id, (void *)flow); 5328 return 0; 5329 error: 5330 rte_free(priv_fdir_flow); 5331 rte_free(fdir_flow); 5332 return -rte_errno; 5333 } 5334 5335 /** 5336 * Delete specific filter. 5337 * 5338 * @param dev 5339 * Pointer to Ethernet device. 5340 * @param fdir_filter 5341 * Filter to be deleted. 5342 * 5343 * @return 5344 * 0 on success, a negative errno value otherwise and rte_errno is set. 5345 */ 5346 static int 5347 flow_fdir_filter_delete(struct rte_eth_dev *dev, 5348 const struct rte_eth_fdir_filter *fdir_filter) 5349 { 5350 struct mlx5_priv *priv = dev->data->dev_private; 5351 uint32_t flow_idx; 5352 struct mlx5_fdir fdir_flow = { 5353 .attr.group = 0, 5354 }; 5355 struct mlx5_fdir_flow *priv_fdir_flow = NULL; 5356 int ret; 5357 5358 ret = flow_fdir_filter_convert(dev, fdir_filter, &fdir_flow); 5359 if (ret) 5360 return -rte_errno; 5361 LIST_FOREACH(priv_fdir_flow, &priv->fdir_flows, next) { 5362 /* Find the fdir in priv list */ 5363 if (!flow_fdir_cmp(priv_fdir_flow->fdir, &fdir_flow)) 5364 break; 5365 } 5366 if (!priv_fdir_flow) 5367 return 0; 5368 LIST_REMOVE(priv_fdir_flow, next); 5369 flow_idx = priv_fdir_flow->rix_flow; 5370 flow_list_destroy(dev, &priv->flows, flow_idx); 5371 rte_free(priv_fdir_flow->fdir); 5372 rte_free(priv_fdir_flow); 5373 DRV_LOG(DEBUG, "port %u deleted FDIR flow %u", 5374 dev->data->port_id, flow_idx); 5375 return 0; 5376 } 5377 5378 /** 5379 * Update queue for specific filter. 5380 * 5381 * @param dev 5382 * Pointer to Ethernet device. 5383 * @param fdir_filter 5384 * Filter to be updated. 5385 * 5386 * @return 5387 * 0 on success, a negative errno value otherwise and rte_errno is set. 5388 */ 5389 static int 5390 flow_fdir_filter_update(struct rte_eth_dev *dev, 5391 const struct rte_eth_fdir_filter *fdir_filter) 5392 { 5393 int ret; 5394 5395 ret = flow_fdir_filter_delete(dev, fdir_filter); 5396 if (ret) 5397 return ret; 5398 return flow_fdir_filter_add(dev, fdir_filter); 5399 } 5400 5401 /** 5402 * Flush all filters. 5403 * 5404 * @param dev 5405 * Pointer to Ethernet device. 5406 */ 5407 static void 5408 flow_fdir_filter_flush(struct rte_eth_dev *dev) 5409 { 5410 struct mlx5_priv *priv = dev->data->dev_private; 5411 struct mlx5_fdir_flow *priv_fdir_flow = NULL; 5412 5413 while (!LIST_EMPTY(&priv->fdir_flows)) { 5414 priv_fdir_flow = LIST_FIRST(&priv->fdir_flows); 5415 LIST_REMOVE(priv_fdir_flow, next); 5416 flow_list_destroy(dev, &priv->flows, priv_fdir_flow->rix_flow); 5417 rte_free(priv_fdir_flow->fdir); 5418 rte_free(priv_fdir_flow); 5419 } 5420 } 5421 5422 /** 5423 * Get flow director information. 5424 * 5425 * @param dev 5426 * Pointer to Ethernet device. 5427 * @param[out] fdir_info 5428 * Resulting flow director information. 5429 */ 5430 static void 5431 flow_fdir_info_get(struct rte_eth_dev *dev, struct rte_eth_fdir_info *fdir_info) 5432 { 5433 struct rte_eth_fdir_masks *mask = 5434 &dev->data->dev_conf.fdir_conf.mask; 5435 5436 fdir_info->mode = dev->data->dev_conf.fdir_conf.mode; 5437 fdir_info->guarant_spc = 0; 5438 rte_memcpy(&fdir_info->mask, mask, sizeof(fdir_info->mask)); 5439 fdir_info->max_flexpayload = 0; 5440 fdir_info->flow_types_mask[0] = 0; 5441 fdir_info->flex_payload_unit = 0; 5442 fdir_info->max_flex_payload_segment_num = 0; 5443 fdir_info->flex_payload_limit = 0; 5444 memset(&fdir_info->flex_conf, 0, sizeof(fdir_info->flex_conf)); 5445 } 5446 5447 /** 5448 * Deal with flow director operations. 5449 * 5450 * @param dev 5451 * Pointer to Ethernet device. 5452 * @param filter_op 5453 * Operation to perform. 5454 * @param arg 5455 * Pointer to operation-specific structure. 5456 * 5457 * @return 5458 * 0 on success, a negative errno value otherwise and rte_errno is set. 5459 */ 5460 static int 5461 flow_fdir_ctrl_func(struct rte_eth_dev *dev, enum rte_filter_op filter_op, 5462 void *arg) 5463 { 5464 enum rte_fdir_mode fdir_mode = 5465 dev->data->dev_conf.fdir_conf.mode; 5466 5467 if (filter_op == RTE_ETH_FILTER_NOP) 5468 return 0; 5469 if (fdir_mode != RTE_FDIR_MODE_PERFECT && 5470 fdir_mode != RTE_FDIR_MODE_PERFECT_MAC_VLAN) { 5471 DRV_LOG(ERR, "port %u flow director mode %d not supported", 5472 dev->data->port_id, fdir_mode); 5473 rte_errno = EINVAL; 5474 return -rte_errno; 5475 } 5476 switch (filter_op) { 5477 case RTE_ETH_FILTER_ADD: 5478 return flow_fdir_filter_add(dev, arg); 5479 case RTE_ETH_FILTER_UPDATE: 5480 return flow_fdir_filter_update(dev, arg); 5481 case RTE_ETH_FILTER_DELETE: 5482 return flow_fdir_filter_delete(dev, arg); 5483 case RTE_ETH_FILTER_FLUSH: 5484 flow_fdir_filter_flush(dev); 5485 break; 5486 case RTE_ETH_FILTER_INFO: 5487 flow_fdir_info_get(dev, arg); 5488 break; 5489 default: 5490 DRV_LOG(DEBUG, "port %u unknown operation %u", 5491 dev->data->port_id, filter_op); 5492 rte_errno = EINVAL; 5493 return -rte_errno; 5494 } 5495 return 0; 5496 } 5497 5498 /** 5499 * Manage filter operations. 5500 * 5501 * @param dev 5502 * Pointer to Ethernet device structure. 5503 * @param filter_type 5504 * Filter type. 5505 * @param filter_op 5506 * Operation to perform. 5507 * @param arg 5508 * Pointer to operation-specific structure. 5509 * 5510 * @return 5511 * 0 on success, a negative errno value otherwise and rte_errno is set. 5512 */ 5513 int 5514 mlx5_dev_filter_ctrl(struct rte_eth_dev *dev, 5515 enum rte_filter_type filter_type, 5516 enum rte_filter_op filter_op, 5517 void *arg) 5518 { 5519 switch (filter_type) { 5520 case RTE_ETH_FILTER_GENERIC: 5521 if (filter_op != RTE_ETH_FILTER_GET) { 5522 rte_errno = EINVAL; 5523 return -rte_errno; 5524 } 5525 *(const void **)arg = &mlx5_flow_ops; 5526 return 0; 5527 case RTE_ETH_FILTER_FDIR: 5528 return flow_fdir_ctrl_func(dev, filter_op, arg); 5529 default: 5530 DRV_LOG(ERR, "port %u filter type (%d) not supported", 5531 dev->data->port_id, filter_type); 5532 rte_errno = ENOTSUP; 5533 return -rte_errno; 5534 } 5535 return 0; 5536 } 5537 5538 /** 5539 * Create the needed meter and suffix tables. 5540 * 5541 * @param[in] dev 5542 * Pointer to Ethernet device. 5543 * @param[in] fm 5544 * Pointer to the flow meter. 5545 * 5546 * @return 5547 * Pointer to table set on success, NULL otherwise. 5548 */ 5549 struct mlx5_meter_domains_infos * 5550 mlx5_flow_create_mtr_tbls(struct rte_eth_dev *dev, 5551 const struct mlx5_flow_meter *fm) 5552 { 5553 const struct mlx5_flow_driver_ops *fops; 5554 5555 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_DV); 5556 return fops->create_mtr_tbls(dev, fm); 5557 } 5558 5559 /** 5560 * Destroy the meter table set. 5561 * 5562 * @param[in] dev 5563 * Pointer to Ethernet device. 5564 * @param[in] tbl 5565 * Pointer to the meter table set. 5566 * 5567 * @return 5568 * 0 on success. 5569 */ 5570 int 5571 mlx5_flow_destroy_mtr_tbls(struct rte_eth_dev *dev, 5572 struct mlx5_meter_domains_infos *tbls) 5573 { 5574 const struct mlx5_flow_driver_ops *fops; 5575 5576 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_DV); 5577 return fops->destroy_mtr_tbls(dev, tbls); 5578 } 5579 5580 /** 5581 * Create policer rules. 5582 * 5583 * @param[in] dev 5584 * Pointer to Ethernet device. 5585 * @param[in] fm 5586 * Pointer to flow meter structure. 5587 * @param[in] attr 5588 * Pointer to flow attributes. 5589 * 5590 * @return 5591 * 0 on success, -1 otherwise. 5592 */ 5593 int 5594 mlx5_flow_create_policer_rules(struct rte_eth_dev *dev, 5595 struct mlx5_flow_meter *fm, 5596 const struct rte_flow_attr *attr) 5597 { 5598 const struct mlx5_flow_driver_ops *fops; 5599 5600 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_DV); 5601 return fops->create_policer_rules(dev, fm, attr); 5602 } 5603 5604 /** 5605 * Destroy policer rules. 5606 * 5607 * @param[in] fm 5608 * Pointer to flow meter structure. 5609 * @param[in] attr 5610 * Pointer to flow attributes. 5611 * 5612 * @return 5613 * 0 on success, -1 otherwise. 5614 */ 5615 int 5616 mlx5_flow_destroy_policer_rules(struct rte_eth_dev *dev, 5617 struct mlx5_flow_meter *fm, 5618 const struct rte_flow_attr *attr) 5619 { 5620 const struct mlx5_flow_driver_ops *fops; 5621 5622 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_DV); 5623 return fops->destroy_policer_rules(dev, fm, attr); 5624 } 5625 5626 /** 5627 * Allocate a counter. 5628 * 5629 * @param[in] dev 5630 * Pointer to Ethernet device structure. 5631 * 5632 * @return 5633 * Index to allocated counter on success, 0 otherwise. 5634 */ 5635 uint32_t 5636 mlx5_counter_alloc(struct rte_eth_dev *dev) 5637 { 5638 const struct mlx5_flow_driver_ops *fops; 5639 struct rte_flow_attr attr = { .transfer = 0 }; 5640 5641 if (flow_get_drv_type(dev, &attr) == MLX5_FLOW_TYPE_DV) { 5642 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_DV); 5643 return fops->counter_alloc(dev); 5644 } 5645 DRV_LOG(ERR, 5646 "port %u counter allocate is not supported.", 5647 dev->data->port_id); 5648 return 0; 5649 } 5650 5651 /** 5652 * Free a counter. 5653 * 5654 * @param[in] dev 5655 * Pointer to Ethernet device structure. 5656 * @param[in] cnt 5657 * Index to counter to be free. 5658 */ 5659 void 5660 mlx5_counter_free(struct rte_eth_dev *dev, uint32_t cnt) 5661 { 5662 const struct mlx5_flow_driver_ops *fops; 5663 struct rte_flow_attr attr = { .transfer = 0 }; 5664 5665 if (flow_get_drv_type(dev, &attr) == MLX5_FLOW_TYPE_DV) { 5666 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_DV); 5667 fops->counter_free(dev, cnt); 5668 return; 5669 } 5670 DRV_LOG(ERR, 5671 "port %u counter free is not supported.", 5672 dev->data->port_id); 5673 } 5674 5675 /** 5676 * Query counter statistics. 5677 * 5678 * @param[in] dev 5679 * Pointer to Ethernet device structure. 5680 * @param[in] cnt 5681 * Index to counter to query. 5682 * @param[in] clear 5683 * Set to clear counter statistics. 5684 * @param[out] pkts 5685 * The counter hits packets number to save. 5686 * @param[out] bytes 5687 * The counter hits bytes number to save. 5688 * 5689 * @return 5690 * 0 on success, a negative errno value otherwise. 5691 */ 5692 int 5693 mlx5_counter_query(struct rte_eth_dev *dev, uint32_t cnt, 5694 bool clear, uint64_t *pkts, uint64_t *bytes) 5695 { 5696 const struct mlx5_flow_driver_ops *fops; 5697 struct rte_flow_attr attr = { .transfer = 0 }; 5698 5699 if (flow_get_drv_type(dev, &attr) == MLX5_FLOW_TYPE_DV) { 5700 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_DV); 5701 return fops->counter_query(dev, cnt, clear, pkts, bytes); 5702 } 5703 DRV_LOG(ERR, 5704 "port %u counter query is not supported.", 5705 dev->data->port_id); 5706 return -ENOTSUP; 5707 } 5708 5709 #define MLX5_POOL_QUERY_FREQ_US 1000000 5710 5711 /** 5712 * Set the periodic procedure for triggering asynchronous batch queries for all 5713 * the counter pools. 5714 * 5715 * @param[in] sh 5716 * Pointer to mlx5_ibv_shared object. 5717 */ 5718 void 5719 mlx5_set_query_alarm(struct mlx5_ibv_shared *sh) 5720 { 5721 struct mlx5_pools_container *cont = MLX5_CNT_CONTAINER(sh, 0, 0); 5722 uint32_t pools_n = rte_atomic16_read(&cont->n_valid); 5723 uint32_t us; 5724 5725 cont = MLX5_CNT_CONTAINER(sh, 1, 0); 5726 pools_n += rte_atomic16_read(&cont->n_valid); 5727 us = MLX5_POOL_QUERY_FREQ_US / pools_n; 5728 DRV_LOG(DEBUG, "Set alarm for %u pools each %u us", pools_n, us); 5729 if (rte_eal_alarm_set(us, mlx5_flow_query_alarm, sh)) { 5730 sh->cmng.query_thread_on = 0; 5731 DRV_LOG(ERR, "Cannot reinitialize query alarm"); 5732 } else { 5733 sh->cmng.query_thread_on = 1; 5734 } 5735 } 5736 5737 /** 5738 * The periodic procedure for triggering asynchronous batch queries for all the 5739 * counter pools. This function is probably called by the host thread. 5740 * 5741 * @param[in] arg 5742 * The parameter for the alarm process. 5743 */ 5744 void 5745 mlx5_flow_query_alarm(void *arg) 5746 { 5747 struct mlx5_ibv_shared *sh = arg; 5748 struct mlx5_devx_obj *dcs; 5749 uint16_t offset; 5750 int ret; 5751 uint8_t batch = sh->cmng.batch; 5752 uint16_t pool_index = sh->cmng.pool_index; 5753 struct mlx5_pools_container *cont; 5754 struct mlx5_pools_container *mcont; 5755 struct mlx5_flow_counter_pool *pool; 5756 5757 if (sh->cmng.pending_queries >= MLX5_MAX_PENDING_QUERIES) 5758 goto set_alarm; 5759 next_container: 5760 cont = MLX5_CNT_CONTAINER(sh, batch, 1); 5761 mcont = MLX5_CNT_CONTAINER(sh, batch, 0); 5762 /* Check if resize was done and need to flip a container. */ 5763 if (cont != mcont) { 5764 if (cont->pools) { 5765 /* Clean the old container. */ 5766 rte_free(cont->pools); 5767 memset(cont, 0, sizeof(*cont)); 5768 } 5769 rte_cio_wmb(); 5770 /* Flip the host container. */ 5771 sh->cmng.mhi[batch] ^= (uint8_t)2; 5772 cont = mcont; 5773 } 5774 if (!cont->pools) { 5775 /* 2 empty containers case is unexpected. */ 5776 if (unlikely(batch != sh->cmng.batch)) 5777 goto set_alarm; 5778 batch ^= 0x1; 5779 pool_index = 0; 5780 goto next_container; 5781 } 5782 pool = cont->pools[pool_index]; 5783 if (pool->raw_hw) 5784 /* There is a pool query in progress. */ 5785 goto set_alarm; 5786 pool->raw_hw = 5787 LIST_FIRST(&sh->cmng.free_stat_raws); 5788 if (!pool->raw_hw) 5789 /* No free counter statistics raw memory. */ 5790 goto set_alarm; 5791 dcs = (struct mlx5_devx_obj *)(uintptr_t)rte_atomic64_read 5792 (&pool->a64_dcs); 5793 offset = batch ? 0 : dcs->id % MLX5_COUNTERS_PER_POOL; 5794 /* 5795 * Identify the counters released between query trigger and query 5796 * handle more effiecntly. The counter released in this gap period 5797 * should wait for a new round of query as the new arrived packets 5798 * will not be taken into account. 5799 */ 5800 rte_atomic64_add(&pool->start_query_gen, 1); 5801 ret = mlx5_devx_cmd_flow_counter_query(dcs, 0, MLX5_COUNTERS_PER_POOL - 5802 offset, NULL, NULL, 5803 pool->raw_hw->mem_mng->dm->id, 5804 (void *)(uintptr_t) 5805 (pool->raw_hw->data + offset), 5806 sh->devx_comp, 5807 (uint64_t)(uintptr_t)pool); 5808 if (ret) { 5809 rte_atomic64_sub(&pool->start_query_gen, 1); 5810 DRV_LOG(ERR, "Failed to trigger asynchronous query for dcs ID" 5811 " %d", pool->min_dcs->id); 5812 pool->raw_hw = NULL; 5813 goto set_alarm; 5814 } 5815 pool->raw_hw->min_dcs_id = dcs->id; 5816 LIST_REMOVE(pool->raw_hw, next); 5817 sh->cmng.pending_queries++; 5818 pool_index++; 5819 if (pool_index >= rte_atomic16_read(&cont->n_valid)) { 5820 batch ^= 0x1; 5821 pool_index = 0; 5822 } 5823 set_alarm: 5824 sh->cmng.batch = batch; 5825 sh->cmng.pool_index = pool_index; 5826 mlx5_set_query_alarm(sh); 5827 } 5828 5829 /** 5830 * Handler for the HW respond about ready values from an asynchronous batch 5831 * query. This function is probably called by the host thread. 5832 * 5833 * @param[in] sh 5834 * The pointer to the shared IB device context. 5835 * @param[in] async_id 5836 * The Devx async ID. 5837 * @param[in] status 5838 * The status of the completion. 5839 */ 5840 void 5841 mlx5_flow_async_pool_query_handle(struct mlx5_ibv_shared *sh, 5842 uint64_t async_id, int status) 5843 { 5844 struct mlx5_flow_counter_pool *pool = 5845 (struct mlx5_flow_counter_pool *)(uintptr_t)async_id; 5846 struct mlx5_counter_stats_raw *raw_to_free; 5847 5848 if (unlikely(status)) { 5849 rte_atomic64_sub(&pool->start_query_gen, 1); 5850 raw_to_free = pool->raw_hw; 5851 } else { 5852 raw_to_free = pool->raw; 5853 rte_spinlock_lock(&pool->sl); 5854 pool->raw = pool->raw_hw; 5855 rte_spinlock_unlock(&pool->sl); 5856 MLX5_ASSERT(rte_atomic64_read(&pool->end_query_gen) + 1 == 5857 rte_atomic64_read(&pool->start_query_gen)); 5858 rte_atomic64_set(&pool->end_query_gen, 5859 rte_atomic64_read(&pool->start_query_gen)); 5860 /* Be sure the new raw counters data is updated in memory. */ 5861 rte_cio_wmb(); 5862 } 5863 LIST_INSERT_HEAD(&sh->cmng.free_stat_raws, raw_to_free, next); 5864 pool->raw_hw = NULL; 5865 sh->cmng.pending_queries--; 5866 } 5867 5868 /** 5869 * Translate the rte_flow group index to HW table value. 5870 * 5871 * @param[in] attributes 5872 * Pointer to flow attributes 5873 * @param[in] external 5874 * Value is part of flow rule created by request external to PMD. 5875 * @param[in] group 5876 * rte_flow group index value. 5877 * @param[out] fdb_def_rule 5878 * Whether fdb jump to table 1 is configured. 5879 * @param[out] table 5880 * HW table value. 5881 * @param[out] error 5882 * Pointer to error structure. 5883 * 5884 * @return 5885 * 0 on success, a negative errno value otherwise and rte_errno is set. 5886 */ 5887 int 5888 mlx5_flow_group_to_table(const struct rte_flow_attr *attributes, bool external, 5889 uint32_t group, bool fdb_def_rule, uint32_t *table, 5890 struct rte_flow_error *error) 5891 { 5892 if (attributes->transfer && external && fdb_def_rule) { 5893 if (group == UINT32_MAX) 5894 return rte_flow_error_set 5895 (error, EINVAL, 5896 RTE_FLOW_ERROR_TYPE_ATTR_GROUP, 5897 NULL, 5898 "group index not supported"); 5899 *table = group + 1; 5900 } else { 5901 *table = group; 5902 } 5903 return 0; 5904 } 5905 5906 /** 5907 * Discover availability of metadata reg_c's. 5908 * 5909 * Iteratively use test flows to check availability. 5910 * 5911 * @param[in] dev 5912 * Pointer to the Ethernet device structure. 5913 * 5914 * @return 5915 * 0 on success, a negative errno value otherwise and rte_errno is set. 5916 */ 5917 int 5918 mlx5_flow_discover_mreg_c(struct rte_eth_dev *dev) 5919 { 5920 struct mlx5_priv *priv = dev->data->dev_private; 5921 struct mlx5_dev_config *config = &priv->config; 5922 enum modify_reg idx; 5923 int n = 0; 5924 5925 /* reg_c[0] and reg_c[1] are reserved. */ 5926 config->flow_mreg_c[n++] = REG_C_0; 5927 config->flow_mreg_c[n++] = REG_C_1; 5928 /* Discover availability of other reg_c's. */ 5929 for (idx = REG_C_2; idx <= REG_C_7; ++idx) { 5930 struct rte_flow_attr attr = { 5931 .group = MLX5_FLOW_MREG_CP_TABLE_GROUP, 5932 .priority = MLX5_FLOW_PRIO_RSVD, 5933 .ingress = 1, 5934 }; 5935 struct rte_flow_item items[] = { 5936 [0] = { 5937 .type = RTE_FLOW_ITEM_TYPE_END, 5938 }, 5939 }; 5940 struct rte_flow_action actions[] = { 5941 [0] = { 5942 .type = MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG, 5943 .conf = &(struct mlx5_flow_action_copy_mreg){ 5944 .src = REG_C_1, 5945 .dst = idx, 5946 }, 5947 }, 5948 [1] = { 5949 .type = RTE_FLOW_ACTION_TYPE_JUMP, 5950 .conf = &(struct rte_flow_action_jump){ 5951 .group = MLX5_FLOW_MREG_ACT_TABLE_GROUP, 5952 }, 5953 }, 5954 [2] = { 5955 .type = RTE_FLOW_ACTION_TYPE_END, 5956 }, 5957 }; 5958 uint32_t flow_idx; 5959 struct rte_flow *flow; 5960 struct rte_flow_error error; 5961 5962 if (!config->dv_flow_en) 5963 break; 5964 /* Create internal flow, validation skips copy action. */ 5965 flow_idx = flow_list_create(dev, NULL, &attr, items, 5966 actions, false, &error); 5967 flow = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_RTE_FLOW], 5968 flow_idx); 5969 if (!flow) 5970 continue; 5971 if (dev->data->dev_started || !flow_drv_apply(dev, flow, NULL)) 5972 config->flow_mreg_c[n++] = idx; 5973 flow_list_destroy(dev, NULL, flow_idx); 5974 } 5975 for (; n < MLX5_MREG_C_NUM; ++n) 5976 config->flow_mreg_c[n] = REG_NONE; 5977 return 0; 5978 } 5979 5980 /** 5981 * Dump flow raw hw data to file 5982 * 5983 * @param[in] dev 5984 * The pointer to Ethernet device. 5985 * @param[in] file 5986 * A pointer to a file for output. 5987 * @param[out] error 5988 * Perform verbose error reporting if not NULL. PMDs initialize this 5989 * structure in case of error only. 5990 * @return 5991 * 0 on success, a nagative value otherwise. 5992 */ 5993 int 5994 mlx5_flow_dev_dump(struct rte_eth_dev *dev, 5995 FILE *file, 5996 struct rte_flow_error *error __rte_unused) 5997 { 5998 struct mlx5_priv *priv = dev->data->dev_private; 5999 struct mlx5_ibv_shared *sh = priv->sh; 6000 6001 return mlx5_devx_cmd_flow_dump(sh->fdb_domain, sh->rx_domain, 6002 sh->tx_domain, file); 6003 } 6004